From 740f67b11277304a9b4173a56d8cb8925507e776 Mon Sep 17 00:00:00 2001 From: strongtz Date: Thu, 4 Mar 2021 18:30:06 +0800 Subject: [PATCH] Add source to build DSDT (in the future) In the future, we are going to build DSDT using iasl from source in the build.sh script. Device specific configuration will be added in subdir. (eg. sdm845Pkg/AcpiTables/fajita/*.asl) --- sdm845Pkg/AcpiTables/common/HoyaSmmu.asl | 158 + .../AcpiTables/common/HoyaSmmu_resources.asl | 121 + sdm845Pkg/AcpiTables/common/Pep_lpi.asl | 617 +++ sdm845Pkg/AcpiTables/common/Qdss.asl | 451 ++ sdm845Pkg/AcpiTables/common/abd.asl | 26 + sdm845Pkg/AcpiTables/common/adsprpc.asl | 27 + sdm845Pkg/AcpiTables/common/backlightcfg.asl | 39 + sdm845Pkg/AcpiTables/common/backlightcfg2.asl | 18 + sdm845Pkg/AcpiTables/common/bam.asl | 143 + sdm845Pkg/AcpiTables/common/buses.asl | 680 +++ sdm845Pkg/AcpiTables/common/cbsp_mproc.asl | 64 + .../AcpiTables/common/corebsp_resources.asl | 4153 +++++++++++++++++ .../common/corebsp_wa_resources.asl | 242 + .../common/corebsp_wp_resources.asl | 13 + .../AcpiTables/common/crypto_resources.asl | 495 ++ .../AcpiTables/common/cust_dsdt_common.asl | 1 + .../common/cust_wcnss_resources.asl | 10 + .../AcpiTables/common/cust_win_mproc.asl | 34 + sdm845Pkg/AcpiTables/common/display.asl | 638 +++ sdm845Pkg/AcpiTables/common/display2.asl | 389 ++ sdm845Pkg/AcpiTables/common/displayext.asl | 49 + sdm845Pkg/AcpiTables/common/dsdt_common.asl | 187 + sdm845Pkg/AcpiTables/common/gps.asl | 20 + sdm845Pkg/AcpiTables/common/gsi.asl | 35 + sdm845Pkg/AcpiTables/common/ipa.asl | 44 + sdm845Pkg/AcpiTables/common/ipa_resources.asl | 74 + .../AcpiTables/common/msft_resources.asl | 25 + sdm845Pkg/AcpiTables/common/nfc.asl | 174 + sdm845Pkg/AcpiTables/common/oem_resources.asl | 25 + sdm845Pkg/AcpiTables/common/pcie.asl | 995 ++++ sdm845Pkg/AcpiTables/common/pcie1.asl | 1237 +++++ .../AcpiTables/common/pcie_resources.asl | 404 ++ sdm845Pkg/AcpiTables/common/pep_common.asl | 537 +++ sdm845Pkg/AcpiTables/common/pep_cprh.asl | 608 +++ .../AcpiTables/common/pep_dbgSettings.asl | 434 ++ sdm845Pkg/AcpiTables/common/pep_dcvscfg.asl | 194 + sdm845Pkg/AcpiTables/common/pep_dvreg.asl | 101 + sdm845Pkg/AcpiTables/common/pep_idle.asl | 1242 +++++ sdm845Pkg/AcpiTables/common/pep_libPCU.asl | 28 + sdm845Pkg/AcpiTables/common/pep_libPdc.asl | 61 + sdm845Pkg/AcpiTables/common/pep_lmh.asl | 32 + sdm845Pkg/AcpiTables/common/pep_resources.asl | 108 + sdm845Pkg/AcpiTables/common/pep_tsens.asl | 233 + .../AcpiTables/common/pep_vddresources.asl | 50 + sdm845Pkg/AcpiTables/common/pmic_batt.asl | 496 ++ sdm845Pkg/AcpiTables/common/pmic_core.asl | 268 ++ sdm845Pkg/AcpiTables/common/qcdb.asl | 8 + sdm845Pkg/AcpiTables/common/qcgpio.asl | 44 + sdm845Pkg/AcpiTables/common/qcsp.asl | 12 + sdm845Pkg/AcpiTables/common/qdss_qpmda.asl | 442 ++ .../AcpiTables/common/qdss_remote_etm.asl | 49 + .../AcpiTables/common/qdss_replicator.asl | 49 + .../AcpiTables/common/qdss_resources.asl | 175 + sdm845Pkg/AcpiTables/common/qdss_tgu.asl | 47 + sdm845Pkg/AcpiTables/common/qdss_tmc.asl | 52 + .../AcpiTables/common/qdss_verifyclocks.asl | 59 + sdm845Pkg/AcpiTables/common/qgpi.asl | 250 + sdm845Pkg/AcpiTables/common/qwpp.asl | 25 + sdm845Pkg/AcpiTables/common/rfs.asl | 49 + sdm845Pkg/AcpiTables/common/sar_manager.asl | 11 + sdm845Pkg/AcpiTables/common/slimbus.asl | 52 + sdm845Pkg/AcpiTables/common/spmi.asl | 22 + sdm845Pkg/AcpiTables/common/spmi_conf.asl | 27 + sdm845Pkg/AcpiTables/common/ssm.asl | 14 + .../AcpiTables/common/ssm_ce_resources.asl | 78 + .../AcpiTables/common/subsys_resources.asl | 494 ++ sdm845Pkg/AcpiTables/common/syscache.asl | 24 + .../AcpiTables/common/testbam_resources.asl | 40 + sdm845Pkg/AcpiTables/common/thz.asl | 558 +++ sdm845Pkg/AcpiTables/common/tmm_resources.asl | 296 ++ sdm845Pkg/AcpiTables/common/ufs.asl | 44 + sdm845Pkg/AcpiTables/common/usb.asl | 953 ++++ sdm845Pkg/AcpiTables/common/wcnss_bt.asl | 53 + sdm845Pkg/AcpiTables/common/wcnss_fm.asl | 27 + .../AcpiTables/common/wcnss_resources.asl | 385 ++ sdm845Pkg/AcpiTables/common/wcnss_wlan.asl | 82 + sdm845Pkg/AcpiTables/common/win_mproc.asl | 359 ++ 77 files changed, 20760 insertions(+) create mode 100644 sdm845Pkg/AcpiTables/common/HoyaSmmu.asl create mode 100644 sdm845Pkg/AcpiTables/common/HoyaSmmu_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/Pep_lpi.asl create mode 100644 sdm845Pkg/AcpiTables/common/Qdss.asl create mode 100644 sdm845Pkg/AcpiTables/common/abd.asl create mode 100644 sdm845Pkg/AcpiTables/common/adsprpc.asl create mode 100644 sdm845Pkg/AcpiTables/common/backlightcfg.asl create mode 100644 sdm845Pkg/AcpiTables/common/backlightcfg2.asl create mode 100644 sdm845Pkg/AcpiTables/common/bam.asl create mode 100644 sdm845Pkg/AcpiTables/common/buses.asl create mode 100644 sdm845Pkg/AcpiTables/common/cbsp_mproc.asl create mode 100644 sdm845Pkg/AcpiTables/common/corebsp_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/corebsp_wa_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/corebsp_wp_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/crypto_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/cust_dsdt_common.asl create mode 100644 sdm845Pkg/AcpiTables/common/cust_wcnss_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/cust_win_mproc.asl create mode 100644 sdm845Pkg/AcpiTables/common/display.asl create mode 100644 sdm845Pkg/AcpiTables/common/display2.asl create mode 100644 sdm845Pkg/AcpiTables/common/displayext.asl create mode 100644 sdm845Pkg/AcpiTables/common/dsdt_common.asl create mode 100644 sdm845Pkg/AcpiTables/common/gps.asl create mode 100644 sdm845Pkg/AcpiTables/common/gsi.asl create mode 100644 sdm845Pkg/AcpiTables/common/ipa.asl create mode 100644 sdm845Pkg/AcpiTables/common/ipa_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/msft_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/nfc.asl create mode 100644 sdm845Pkg/AcpiTables/common/oem_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/pcie.asl create mode 100644 sdm845Pkg/AcpiTables/common/pcie1.asl create mode 100644 sdm845Pkg/AcpiTables/common/pcie_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_common.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_cprh.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_dbgSettings.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_dcvscfg.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_dvreg.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_idle.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_libPCU.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_libPdc.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_lmh.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_tsens.asl create mode 100644 sdm845Pkg/AcpiTables/common/pep_vddresources.asl create mode 100644 sdm845Pkg/AcpiTables/common/pmic_batt.asl create mode 100644 sdm845Pkg/AcpiTables/common/pmic_core.asl create mode 100644 sdm845Pkg/AcpiTables/common/qcdb.asl create mode 100644 sdm845Pkg/AcpiTables/common/qcgpio.asl create mode 100644 sdm845Pkg/AcpiTables/common/qcsp.asl create mode 100644 sdm845Pkg/AcpiTables/common/qdss_qpmda.asl create mode 100644 sdm845Pkg/AcpiTables/common/qdss_remote_etm.asl create mode 100644 sdm845Pkg/AcpiTables/common/qdss_replicator.asl create mode 100644 sdm845Pkg/AcpiTables/common/qdss_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/qdss_tgu.asl create mode 100644 sdm845Pkg/AcpiTables/common/qdss_tmc.asl create mode 100644 sdm845Pkg/AcpiTables/common/qdss_verifyclocks.asl create mode 100644 sdm845Pkg/AcpiTables/common/qgpi.asl create mode 100644 sdm845Pkg/AcpiTables/common/qwpp.asl create mode 100644 sdm845Pkg/AcpiTables/common/rfs.asl create mode 100644 sdm845Pkg/AcpiTables/common/sar_manager.asl create mode 100644 sdm845Pkg/AcpiTables/common/slimbus.asl create mode 100644 sdm845Pkg/AcpiTables/common/spmi.asl create mode 100644 sdm845Pkg/AcpiTables/common/spmi_conf.asl create mode 100644 sdm845Pkg/AcpiTables/common/ssm.asl create mode 100644 sdm845Pkg/AcpiTables/common/ssm_ce_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/subsys_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/syscache.asl create mode 100644 sdm845Pkg/AcpiTables/common/testbam_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/thz.asl create mode 100644 sdm845Pkg/AcpiTables/common/tmm_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/ufs.asl create mode 100644 sdm845Pkg/AcpiTables/common/usb.asl create mode 100644 sdm845Pkg/AcpiTables/common/wcnss_bt.asl create mode 100644 sdm845Pkg/AcpiTables/common/wcnss_fm.asl create mode 100644 sdm845Pkg/AcpiTables/common/wcnss_resources.asl create mode 100644 sdm845Pkg/AcpiTables/common/wcnss_wlan.asl create mode 100644 sdm845Pkg/AcpiTables/common/win_mproc.asl diff --git a/sdm845Pkg/AcpiTables/common/HoyaSmmu.asl b/sdm845Pkg/AcpiTables/common/HoyaSmmu.asl new file mode 100644 index 0000000..97c1bb5 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/HoyaSmmu.asl @@ -0,0 +1,158 @@ + + + // + // SMMU Driver + // + // SMT vector diagram: \\brewmp4\public\Istari\ + // + // Need to change Device Name in resorce file + // Currently Marking CP-P, CP-NP as CP_Pixel only need to add these VM + // to SMMU driver and need to update + + Device (MMU0) + { + // ATCU + + Name (_HID, "HID_MMU0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + Name (_DEP, Package () + { + \_SB_.MMU1 + }) + + + Method (_CRS, 0x0, NotSerialized) + { + Return (ResourceTemplate () + { + // a-TCU register address space + Memory32Fixed (ReadWrite, 0x15000000, 0x7FFB8) + // TLBI HW SPINLOCK BASE ADDRESS + Memory32Fixed (ReadWrite, 0x1F46000, 0x4) + // a-TCU: there is one interrupt for each CB handled by HLOS clients (only non-secure CBs) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {128} // CB 0 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {129} // CB 1 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {130} // CB 2 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {131} // CB 3 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {132} // CB 4 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {133} // CB 5 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {134} // CB 6 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {135} // CB 7 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {136} // CB 8 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {137} // CB 9 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {138} // CB 10 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {139} // CB 11 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {140} // CB 12 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {141} // CB 13 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {142} // CB 14 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {143} // CB 15 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {144} // CB 16 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {145} // CB 17 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {146} // CB 18 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {147} // CB 19 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {148} // CB 20 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {149} // CB 21 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {150} // CB 22 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {213} // CB 23 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {214} // CB 24 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {215} // CB 25 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {216} // CB 26 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {217} // CB 27 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {218} // CB 28 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {219} // CB 29 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {220} // CB 30 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {221} // CB 31 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {222} // CB 32 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {223} // CB 33 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {224} // CB 34 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {347} // CB 35 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {348} // CB 36 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {349} // CB 37 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {350} // CB 38 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {351} // CB 39 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {352} // CB 40 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {353} // CB 41 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {354} // CB 42 + + + + + + // Not used for mapping + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {355} // CB 43 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {356} // CB 44 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {357} // CB 45 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {358} // CB 46 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {359} // CB 47 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {360} // CB 48 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {361} // CB 49 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {362} // CB 50 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {363} // CB 51 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {364} // CB 52 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {365} // CB 53 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {366} // CB 54 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {367} // CB 55 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {368} // CB 56 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {369} // CB 57 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {370} // CB 58 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {371} // CB 59 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {372} // CB 60 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {373} // CB 61 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {374} // CB 62 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {375} // CB 63 + }) + } + } + + Device (MMU1) + { + // This is the SMMU for Oxili/GFX + + Name (_HID, "HID_MMU0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + Name (_DEP, Package() + { + \_SB_.PEP0 + }) + + // When testing on 8960, delete the _CRS method. This will cause + // the driver to use a chunk of RAM. + + Method (_CRS, 0x0, NotSerialized) + { + Return (ResourceTemplate () + { + //g-TCU register address space + Memory32Fixed (ReadWrite, 0x05040000, 0x10000) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {396} // CB 0 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {397} // CB 1 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {398} // CB 2 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {399} // CB 3 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {400} // CB 4 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {401} // CB 5 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {402} // CB 6 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {403} // CB 7 + }) + } + } + + + Device (IMM0) + { + // ATCU + + Name (_HID, "HID_IMMU") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + } + + Device (IMM1) + { + // This is the SMMU for Oxili/GFX + + Name (_HID, "HID_IMMU") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + } diff --git a/sdm845Pkg/AcpiTables/common/HoyaSmmu_resources.asl b/sdm845Pkg/AcpiTables/common/HoyaSmmu_resources.asl new file mode 100644 index 0000000..b26c820 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/HoyaSmmu_resources.asl @@ -0,0 +1,121 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by SMMU driver. +// +// +// +//=========================================================================== +Scope(\_SB.PEP0){ + // SMMU + Method(SMMD){ + Return(SMMC) + } + Name(SMMC, + Package(){ + + // SMMU MNOC Resources + Package(){ + "DEVICE", + "\\_SB.MMU0", + //-------------------------------------------------------------------------------------- + // Component 0 - + //-------------------------------------------------------------------------------------- + // + Package(){ + "COMPONENT", + 0, + Package(){ + "FSTATE", + 0, + + // Action: 1 == ENABLE + // + // Domain Name Action + // ---------------- ------ + // Package() { "FOOTSWITCH", Package() { "gcc_hlos1_vote_mmu_tcu_gds", 1, },}, + + // Action: 1 == ENABLE + // MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST + // + // Clock Name Action + // -------------------- ------ + Package() { "CLOCK", Package() { "gcc_hlos1_vote_mmu_tcu_clk", 1 }} + + }, + Package(){ + "FSTATE", + 1, + + // Action: 2 == DISABLE + // MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST + // + // Clock Name Action + // -------------------- ------ + Package() { "CLOCK", Package() { "gcc_hlos1_vote_mmu_tcu_clk", 2 }}, + + // Action: 2 == DISABLE + // + // Domain Name Action + // ---------------- ------ + // Package() { "FOOTSWITCH", Package() { "gcc_hlos1_vote_mmu_tcu_gds", 2, },}, + + }, + }, + }, + + // A5x/GFX SMMU Resources + Package(){ + "DEVICE", + "\\_SB.MMU1", + //-------------------------------------------------------------------------------------- + // Component 0 - + //-------------------------------------------------------------------------------------- + // + Package(){ + "COMPONENT", + 0, + Package(){ + "FSTATE", + 0, + + // Vote for the frequencies we need otherwise these clocks may not be configured properly + + // Action: 1 == ENABLE + // + // Domain Name Action + // ---------------- ------ + Package() { "FOOTSWITCH", Package() { "gcc_hlos1_vote_gpu_smmu_gds", 1 }}, + + // Action: 1 == ENABLE + // MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST + // + // Clock Name Action + // -------------------- ------ + Package() { "CLOCK", Package() { "gcc_hlos1_vote_gpu_smmu_clk", 1 }}, + + }, + Package(){ + "FSTATE", + 1, + + // Action: 2 == DISABLE + // MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST + // + // Clock Name Action + // -------------------- ------ + Package() { "CLOCK", Package() { "gcc_hlos1_vote_gpu_smmu_clk", 2 }}, + + + // Action: 2 == DISABLE + // + // Domain Name Action + // ---------------- ------ + Package() { "FOOTSWITCH", Package() { "gcc_hlos1_vote_gpu_smmu_gds", 2 }}, + + }, + }, + }, + }) +} + diff --git a/sdm845Pkg/AcpiTables/common/Pep_lpi.asl b/sdm845Pkg/AcpiTables/common/Pep_lpi.asl new file mode 100644 index 0000000..89f441b --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/Pep_lpi.asl @@ -0,0 +1,617 @@ + +Device (SYSM) { + Name (_HID, "ACPI0010") + Name (_UID, 0x100000) + Name (_LPI, Package() { + 0, // Version + 0x1000000, // Level ID + 2, // Count + + // State F1 - Cx retention + AOSS Sleep + Package () { + 9500, // Min residency (us) + 6000, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0x20, // Arch context last flags + 0x20 For Debugger Transistion by PEP. + 0, // Residency counter frequency + 0, // Enabled parent state + 0x3300, // Integer entry method E2+F1 + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "platform.F1" // Name + }, + // State F2 - Cx collapse + AOSS Sleep + LLC deactivate + Package () { + 10000, // Min residency (us) + 6600, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0x20, // Arch context last flags + 0x20 For Debugger Transistion by PEP. + 0, // Residency counter frequency + 0, // Enabled parent state + 0xC300, // Integer entry method E2+F2 + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "platform.F2" // Name + } + }) // End of _LPI + + Device (CLUS) { + Name (_HID, "ACPI0010") + Name (_UID, 0x10) + Name (_LPI, Package() { + 0, // Version + 0x1000000, + 2, // Count + + // State 0: D2 + Package () { + 5900, // Min residency (us) + 3000, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + 0x20, // Integer entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "L3Cluster.D2" // Name + }, + // State 1: D4 + Package () { + 6000, // Min residency (us) + 3300, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Till F2) + 0x40, // Integer entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "L3Cluster.D4" // Name + }, + + }) // End of _LPI + + + Device (CPU0) // Kyro Silver CPU0 < SYSM.APSS.CPU0 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x0) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C1" // Name + }, + // C2 + Package () { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C2" // Name + }, + // C3 + Package () { + 5000, // Min residency (us) + 500, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C3" // Name + }, + // C4 + Package () { + 5100, // Min residency (us) + 550, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C4" // Name + }, + + }) // End of _LPI + } // End of CPU0 + + Device (CPU1) // Kyro Silver CPU1 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x1) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C1" // Name + }, + // C2 + Package () { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C2" // Name + }, + // C3 + Package () { + 5000, // Min residency (us) + 500, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C3" // Name + }, + // C4 + Package () { + 5100, // Min residency (us) + 550, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C4" // Name + }, + + }) // End of _LPI + } // End of CPU1 + + Device (CPU2) // Kyro Silver CPU2 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x2) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C1" // Name + }, + // C2 + Package () { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C2" // Name + }, + // C3 + Package () { + 5000, // Min residency (us) + 500, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C3" // Name + }, + // C4 + Package () { + 5100, // Min residency (us) + 550, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C4" // Name + }, + + }) // End of _LPI + } // End of CPU2 + + Device (CPU3) // Kyro Silver CPU3 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x3) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C1" // Name + }, + // C2 + Package () { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C2" // Name + }, + // C3 + Package () { + 5000, // Min residency (us) + 500, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C3" // Name + }, + // C4 + Package () { + 5100, // Min residency (us) + 550, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C4" // Name + }, + + }) // End of _LPI + } // End of CPU3 + + Device (CPU4) // Kyro Gold CPU0 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x4) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C1" // Name + }, + // C2 + Package () { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C2" // Name + }, + // C3 + Package () { + 1000, // Min residency (us) + 650, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C3" // Name + }, + // C4 + Package () { + 1500, // Min residency (us) + 1100, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C4" // Name + }, + + }) // End of _LPI + } // End of CPU4 + + Device (CPU5) // Kyro Gold CPU1 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x5) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C1" // Name + }, + // C2 + Package () { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C2" // Name + }, + // C3 + Package () { + 1000, // Min residency (us) + 650, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C3" // Name + }, + // C4 + Package () { + 1500, // Min residency (us) + 1100, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C4" // Name + }, + }) // End of _LPI + } // End of CPU5 + + Device (CPU6) // Kyro Gold CPU2 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x6) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C1" // Name + }, + // C2 + Package () { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C2" // Name + }, + // C3 + Package () { + 1000, // Min residency (us) + 650, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C3" // Name + }, + // C4 + Package () { + 1500, // Min residency (us) + 1100, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000004 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C4" // Name + }, + }) // End of _LPI + } // End of CPU6 + + Device (CPU7) // Kyro Gold CPU3 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x7) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold3.C1" // Name + }, + // C2 + Package () { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold3.C2" // Name + }, + // C3 + Package () { + 1000, // Min residency (us) + 650, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold3.C3" // Name + }, + // C4 + Package () { + 1500, // Min residency (us) + 1100, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000004 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold3.C4" // Name + }, + }) // End of _LPI + } // End of CPU7 + } // End of CLUS +} // End of SYSM \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/Qdss.asl b/sdm845Pkg/AcpiTables/common/Qdss.asl new file mode 100644 index 0000000..5fd0253 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/Qdss.asl @@ -0,0 +1,451 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by qdss driver. +// +// +//=========================================================================== + +// +// QDSS device +// +Device (QDSS) +{ + Name (_DEP, Package () { \_SB_.PEP0 }) + + Name (_HID, "HID_QDSS") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Return + ( + ResourceTemplate () + { + // Software uses QDSSETRIRQCTRL to set a byte count threshold for a counter that counts + // the number of bytes of trace data the ETR has moved on its AXI interface. When the + // threshold is reached an IRQ is fired. + // reference : http://ipcatalog.qualcomm.com/irqs/chip/53/map/438 + //qdss_etrbytecnt_irq = SYS_apssQgicSPI[270] = 302 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {302} // The ETR byte counter interrupt + // reference : http://ipcatalog.qualcomm.com/memmap/chip/99/map/367#block=866956 + Memory32Fixed (ReadWrite, 0x06000000, 0x00049000) // The QDSS_QDSS address space + // reference : http://ipcatalog.qualcomm.com/memmap/chip/99/map/367 + Memory32Fixed (ReadWrite, 0x16000000, 0x1000000) // The QDSS_STM address 0x1000000 = 16777216d (~16MB) + // Following memory resource is required starting from 8994. In such case, QDSS driver expects + // OFF2 control method which defines register block offsets within this address space. + //reference : http://ipcatalog.qualcomm.com/swi/module/1385017 + Memory32Fixed (ReadWrite, 0x07000000, 0x00901000) // The QDSS_CPU address space. + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {67} // L3 fault interrupt + } + ) + } + + // The QBAL method returns QDSS Base Address Length as needed for configuring all QDSS registers. + // Reason for returning length through seperate method is BAM driver address range conflicts with QDSS adress range. + // Due to this OS does not enumerate QDSS driver if whole length defined in CRS method. + // QDSS cfg is of total 32MB address space. 0x06000000 - 0x06C2B000 is used to configure QDSS registers. See http://ipcatalog.qualcomm.com/memmap/chip/53/map/307#block=871326 + Method (QBAL) + { + Return (0x0C2B000) + } + Method (XULC) + { + Return (0x2) + } + + Method (XUPC) + { + Return (0x8) + } + + Method (X3LN) + { + Return (0x1) + } + METHOD (CPID) + { + Return (\_SB_.SOID) + } + + // The CHPD method returns a 32-bit value that allows us to tweak things on + // a chip-by-chip basis. Goal is not to use this, but it's handy during + // bring up. + + Method (CHPD) + { + Return (0x00000000) + } + + // The PSIL method returns a boolean value to indicate platform is a Pre-silicon or real SOC. + // Value 1 if we are using Pre-silicon platform for validation. + // Value 0 if we are using real SOC platform. + // If this method is not present, driver assumes the platform as a real SOC (default value 0). + Method (PSIL) + { + Return (0) + } + + // The PWRV method returns the version of the power model that is in use by + // this chip. If 0 (or this method is missing), the QDSS driver will use + // the default F-state-only power model. If 1, the QDSS driver will use the + // F-state-and-P-state model. + + Method (PWRV) + { + Return (0x1) + } + + // The ETMV method returns value indicating how to program the ETM registers that is in use by + // this SoC. Following version numbers are in sync with QDSS_ETM_VER_ENUM as defined in + // halqdss_ptm.h . + // If 0 (or this method is missing), the QDSS driver will use the default way of + // writing/reading ETM registers, eg. co-processor commands. This version works for cortex (8974). + // If 1, the QDSS driver will use the memory map model. This version works for A7 (8x26). + // When co-processor command is used, PEP driver needs to save/restore the register values + // across power collapse; With memory map model, PEP driver needs to keep QDSS clocks on + // during power collapse (This is not ideal, and it is being discussed with ARM). + // If 4, the Apps CPU supports ETMv4. + + Method (ETMV) + { + Return (0x4) + } + + // The OFFS method returns the offset and size of each register block + // within the QDSS_QDSS address space. This also returns the type of register block + // the block types can be 0 - nonCTI; 1 - CTI + // Block name as defined here has to exist in QdssDeviceOffsets.h; in future we will + // do this differently, but for now, this is an implicit contract. + // Block Type: 0 -NORMAL_BLOCK, + // 1 -CTI_BLOCK, + // 2 -ETM_BLOCK, + // 3 -FUNNEL_BLOCK, + // Address Base: Since now some projects' qdss has some base address spaces for block + // pls refer :Method _CRS and put the block's base address space into "Address Base" area. + // references: + // http://ipcatalog.qualcomm.com/memmap/chip/99/map/367#block=993378 + // http://sew-napali.runq-sd-a-sm.qualcomm.com/prj/qct/chips/napali/sandiego/docs/SWI/HTML/latest_2.0/napali.index.html + + Method (OFFS) + { + Return + ( + Package () + { + // { "Block Name", Offset, Size, Block Type, Address Base }, + Package () { "CSR", 0x00001000, 0x00001000, 0x0, 0x06000000}, //QDSS Coresight CSR Slave + Package () { "STM", 0x00002000, 0x00001000, 0x0, 0x06000000}, + Package () { "QATB_FUNNEL", 0x00005000, 0x00001000, 0x3, 0x06000000}, // QDSS QATB Funnel + Package () { "TGU", 0x0000E000, 0x00001000, 0x0, 0x06000000}, + Package () { "CTI0", 0x00010000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI1", 0x00011000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI2", 0x00012000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI3", 0x00013000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI4", 0x00014000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI5", 0x00015000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI6", 0x00016000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI7", 0x00017000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI8", 0x00018000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI9", 0x00019000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI10", 0x0001A000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI11", 0x0001B000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI12", 0x0001C000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI13", 0x0001D000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI14", 0x0001E000, 0x00001000, 0x1, 0x06000000}, + Package () { "CTI15", 0x0001F000, 0x00001000, 0x1, 0x06000000}, + Package () { "TPIU", 0x00040000, 0x00001000, 0x0, 0x06000000}, + Package () { "IN_FUN0", 0x00041000, 0x00001000, 0x3, 0x06000000}, // QDSS FUN_IN0 + Package () { "IN_FUN1", 0x00042000, 0x00001000, 0x3, 0x06000000}, // QDSS FUN_IN1 + Package () { "IN_FUN2", 0x00043000, 0x00001000, 0x3, 0x06000000}, // QDSS FUN_IN2 + Package () { "MERG_FUN", 0x00045000, 0x00001000, 0x3, 0x06000000}, // QDSS Merg_Fun + Package () { "ETR", 0x00048000, 0x00001000, 0x0, 0x06000000}, + Package () { "MSS_QATBFUN", 0x00832000, 0x00001000, 0x3, 0x06000000}, // Modem DL Funnel + Package () { "LPASS_QATBFUN", 0x00845000, 0x00001000, 0x3, 0x06000000}, // LPASS DL Funnel + Package () { "TURING_QATBFUN", 0x00861000, 0x00001000, 0x3, 0x06000000}, // Turing DL Funnel + Package () { "SPSS_QATBFUN", 0x00883000, 0x00001000, 0x3, 0x06000000}, // Secure Processor DL Funnel + Package () { "GPU_FUN", 0x00943000, 0x00001000, 0x3, 0x06000000}, + Package () { "GPU_QATBFUN", 0x00944000, 0x00001000, 0x3, 0x06000000}, // GPU DL Funnel + Package () { "WCSS_FUN", 0x0099E000, 0x00001000, 0x3, 0x06000000}, // WCSS Funnel + Package () { "DLST_QATBFUN", 0x009C1000, 0x00001000, 0x3, 0x06000000}, // DL South Funnel + Package () { "DL0_QATBFUNNEL", 0x009E2000, 0x00001000, 0x3, 0x06000000}, // DDR_0 DL Funnel + Package () { "DL1_QATBFUNNEL", 0x009E7000, 0x00001000, 0x3, 0x06000000}, // DDR_1 DL Funnel + Package () { "SWAO_CTI0", 0x00B04000, 0x00001000, 0x1, 0x06000000}, + Package () { "SWAO_CTI1", 0x00B05000, 0x00001000, 0x1, 0x06000000}, + Package () { "SWAO_CTI2", 0x00B06000, 0x00001000, 0x1, 0x06000000}, + Package () { "SWAO_CTI3", 0x00B07000, 0x00001000, 0x1, 0x06000000}, + Package () { "SWAO_FUN0", 0x00B08000, 0x00001000, 0x3, 0x06000000}, // AOSS Funnel + Package () { "SWAO_CSR", 0x00B0E000, 0x00001000, 0x0, 0x06000000}, + Package () { "SSC_FUN0", 0x00B14000, 0x00001000, 0x3, 0x06000000}, // SSC Funnel + Package () { "DLMM_QATBFUN", 0x00C0B000, 0x00001000, 0x3, 0x06000000}, // DL MM Funnel + + // reference: http://ipcatalog.qualcomm.com/swi/module/1279554 + // ETM_0 to ETM_3 blocks QDSS_APSS_APSS_SILVER_APB_APSS_SILVER_APB_A53_APB. + // ETM_4 to ETM_7 blocks QDSS_APSS_APSS_GOLD_APB_APSS_GOLD_APB_A53_APB. + Package () { "ETM_0", 0x00440000, 0x00001000, 0x2, 0x07000000}, // 0x07440000 QDSS_APSS_APSS_SILVER_APB_APSS_SILVER_APB_A53_APB + Package () { "ETM_1", 0x00540000, 0x00001000, 0x2, 0x07000000}, // 0x07540000 QDSS_APSS_APSS_SILVER_APB_APSS_SILVER_APB_A53_APB + Package () { "ETM_2", 0x00640000, 0x00001000, 0x2, 0x07000000}, // 0x07640000 QDSS_APSS_APSS_SILVER_APB_APSS_SILVER_APB_A53_APB + Package () { "ETM_3", 0x00740000, 0x00001000, 0x2, 0x07000000}, // 0x07740000 QDSS_APSS_APSS_SILVER_APB_APSS_SILVER_APB_A53_APB + Package () { "ETM_4", 0x00040000, 0x00001000, 0x2, 0x07000000}, // 0x07040000 QDSS_APSS_APSS_GOLD_APB_APSS_GOLD_APB_A53_APB + Package () { "ETM_5", 0x00140000, 0x00001000, 0x2, 0x07000000}, // 0x07140000 QDSS_APSS_APSS_GOLD_APB_APSS_GOLD_APB_A53_APB + Package () { "ETM_6", 0x00240000, 0x00001000, 0x2, 0x07000000}, // 0x07240000 QDSS_APSS_APSS_GOLD_APB_APSS_GOLD_APB_A53_APB + Package () { "ETM_7", 0x00340000, 0x00001000, 0x2, 0x07000000}, // 0x07340000 QDSS_APSS_APSS_GOLD_APB_APSS_GOLD_APB_A53_APB + + Package () { "CPU_FUN0", 0x00800000, 0x00001000, 0x3, 0x07000000}, // APSS CPU trace funnel, QDSS_APSS_FUN_ATB_FUN_ATB_CXATBFUNNEL_128W8SP + Package () { "CPU_FUN1", 0x00810000, 0x00001000, 0x3, 0x07000000}, // APSS Top Funnel, QDSS_APSS_FUN_FUN_CXATBFUNNEL_128W8SP + + Package () { "APSS_CTI0", 0x008E0000, 0x00001000, 0x1, 0x07000000}, + Package () { "APSS_CTI1", 0x008F0000, 0x00001000, 0x1, 0x07000000}, + Package () { "APSS_CTI2", 0x00900000, 0x00001000, 0x1, 0x07000000}, + } + ) + } + + // The S2FP (Source To Funnel Port) method maps a source to the funnel and port. + // references: + // https://sharepoint.qualcomm.com/qct/DHW/Projects/Napali/Documents/Design/debug/SOC%20DEBUG/Napali_ATB_Structure.xlsx + // https://sharepoint.qualcomm.com/qct/DHW/Projects/Napali/Documents/Design/debug/SOC%20DEBUG/Napali_ATB_APB_TS_Infrastructure.vsd + Method (S2FP) + { + Return + ( + Package () + { + Package () + { + "STM", + Package () { "MERG_FUN", 0 }, + Package () { "IN_FUN0", 7 }, + }, + Package () + { + "ETM", + Package () { "MERG_FUN", 2 }, + Package () { "IN_FUN2", 5 }, + Package () { "CPU_FUN1", 0 }, // top funnel APSS PWR CPU0 ATB + Package () { "CPU_FUN0", 0 }, // trace funnel APSS PWR CPU0 ATB + Package () { "CPU_FUN0", 1 }, // trace funnel APSS PWR CPU1 ATB + Package () { "CPU_FUN0", 2 }, // trace funnel APSS PWR CPU2 ATB + Package () { "CPU_FUN0", 3 }, // trace funnel APSS PWR CPU3 ATB + Package () { "CPU_FUN0", 4 }, // trace funnel APSS PERF CPU4 ATB + Package () { "CPU_FUN0", 5 }, // trace funnel APSS PERF CPU5 ATB + Package () { "CPU_FUN0", 6 }, // trace funnel APSS PERF CPU6 ATB + Package () { "CPU_FUN0", 7 }, // trace funnel APSS PERF CPU7 ATB + Package () { "CPU_FUN1", 1 }, // top funnel APSS GNoC (CCI) ATB + }, + Package () + { + "BUS", + Package () { "MERG_FUN", 0 }, + Package () { "IN_FUN0", 6 }, + Package () { "QATB_FUNNEL", 2 }, + Package () { "GPU_QATBFUN", 1 }, // GPU DL VBIF ATB + Package () { "QATB_FUNNEL", 3 }, + Package () { "DLMM_QATBFUN", 2 }, // MMNoC ATB + Package () { "DLMM_QATBFUN", 3 }, // Venus ATB + Package () { "DLMM_QATBFUN", 4 }, // MDSS MDP ATB + Package () { "DLMM_QATBFUN", 5 }, // MDSS NRT ATB + Package () { "DLMM_QATBFUN", 6 }, // TITAN ATB + Package () { "DLMM_QATBFUN", 7 }, // Cam NoC ATB + + Package () { "QATB_FUNNEL", 4 }, + Package () { "DL0_QATBFUNNEL", 1 }, // DDR DL_0 LLC0 ATB + Package () { "DL0_QATBFUNNEL", 2 }, // DDR DL_0 LLC1 ATB + Package () { "DL0_QATBFUNNEL", 3 }, // DDR DL_0 LLC2 ATB + Package () { "DL0_QATBFUNNEL", 4 }, // DDR DL_0 LLC3 ATB + Package () { "DL0_QATBFUNNEL", 5 }, // DDR DL_0 CH0 CABO ATB + Package () { "DL0_QATBFUNNEL", 6 }, // DDR DL_0 CH1 CABO ATB + Package () { "DL0_QATBFUNNEL", 7 }, // DDR DL_1 QATB + + Package () { "DL1_QATBFUNNEL", 0 }, // DDR DL_1 CH2 CABO ATB + Package () { "DL1_QATBFUNNEL", 1 }, // DDR DL_1 CH3 CABO ATB + Package () { "DL1_QATBFUNNEL", 2 }, // DDR DL_1 Mem NoC ATB + + Package () { "QATB_FUNNEL", 5 }, + Package () { "DLST_QATBFUN", 1 }, // A1NoC ATB + Package () { "WCSS_FUN", 0 }, + Package () { "DLST_QATBFUN", 2 }, // WCSS NoC ATB + + Package () { "QATB_FUNNEL", 6 }, + Package () { "LPASS_QATBFUN", 1 }, // LPASS DL Q6 ATB + + Package () { "QATB_FUNNEL", 7 }, + Package () { "TURING_QATBFUN", 1 }, // Turing DL Q6 ATB + Package () { "IN_FUN0", 2 }, // System NoC ATB + + Package () { "IN_FUN0", 3 }, + Package () { "SPSS_QATBFUN", 2 }, // Secure Processor NoC ATB + + Package () { "IN_FUN0", 5 }, // A2NoC ATB + + Package () { "MERG_FUN", 1 }, + Package () { "IN_FUN1", 2 }, // NAV ATB + + Package () { "MERG_FUN", 2 }, + Package () { "IN_FUN2", 0 }, // Modem Q6 ATB + + Package () { "IN_FUN2", 1 }, + Package () { "SWAO_FUN0", 1 }, // AOSS AOP ITM ATB + + Package () { "SWAO_FUN0", 6 }, + Package () { "SSC_FUN0", 1 }, // SSC STM ATB + Package () { "SSC_FUN0", 3 }, // SSC SDC ITM ATB + Package () { "SSC_FUN0", 4 }, // SSC NOC + + Package () { "IN_FUN2", 5 }, + Package () { "CPU_FUN1", 3 }, // DBG_UI ATB + Package () { "CPU_FUN1", 4 }, // HWE DL ATB + Package () { "CPU_FUN1", 5 }, // LLM Silver Cluster ATB + Package () { "CPU_FUN1", 6 }, // LLM Gold Cluster ATB + }, + Package () + { + "GFX", + Package () { "MERG_FUN", 2 }, + Package () { "IN_FUN2", 6 }, // GPU + + Package () { "MERG_FUN", 0 }, + Package () { "IN_FUN0", 6 }, + Package () { "QATB_FUNNEL", 2 }, + Package () { "GPU_QATBFUN", 1 }, // GPU DL VBIF ATB + }, + Package () + { + "MODEMQ6ETM", + Package () { "MERG_FUN", 2 }, + Package () { "IN_FUN2", 0 }, // Modem Q6 ATB + }, + Package () + { + "QDSS", + Package () { "MERG_FUN", 0 }, + Package () { "IN_FUN0", 6 }, + Package () { "QATB_FUNNEL", 0 }, // VSENSE TPDM, DCC TPDM, PRNG TPDM, QM TPDM, PIMEM TPDM, QDSS internal DSB TPDM + + Package () { "GPU_QATBFUN", 0 }, // GPU DL VBIF ATB + + Package () { "DLMM_QATBFUN", 1 }, // DL MM QATB TPDM + + Package () { "DL0_QATBFUNNEL", 0 }, // DDR DL_0 QATB TPDM + + Package () { "LPASS_QATBFUN", 0 }, // LPASS DL QATB TPDM + + Package () { "TURING_QATBFUN", 0 }, // Turing DL QATB TPDM + + }, + Package () + { + "APSS", + Package () { "MERG_FUN", 2 }, + Package () { "IN_FUN2", 5 }, + Package () { "CPU_FUN1", 0 }, // APSS Top Funnel + Package () { "CPU_FUN1", 1 }, + Package () { "CPU_FUN1", 2 }, + Package () { "CPU_FUN1", 3 }, + Package () { "CPU_FUN1", 4 }, + Package () { "CPU_FUN1", 5 }, + Package () { "CPU_FUN1", 6 }, + Package () { "CPU_FUN0", 0 }, // APSS CPU Trace Funnel + Package () { "CPU_FUN0", 1 }, + Package () { "CPU_FUN0", 2 }, + Package () { "CPU_FUN0", 3 }, + Package () { "CPU_FUN0", 4 }, + Package () { "CPU_FUN0", 5 }, + Package () { "CPU_FUN0", 6 }, + Package () { "CPU_FUN0", 7 }, + }, + Package () + { + "MSS", // Modem RFFE TPDM / TPDA ATB + Package () { "MERG_FUN", 2 }, + Package () { "IN_FUN2", 2 }, + Package () { "MSS_QATBFUN", 1 }, // Modem DL Funnel + }, + Package () + { + "NAV", // NAV ATB + Package () { "MERG_FUN", 1 }, + Package () { "IN_FUN1", 2 }, + }, + Package () + { + "OLC", // APSS OLC (LMH) TPDM / TPDA ATB + Package () { "MERG_FUN", 2 }, + Package () { "IN_FUN2", 5 }, + Package () { "CPU_FUN1", 2 }, // APSS Top Funnel + }, + Package () + { + "SP", // Secure Processor TPDM ATB + Package () { "MERG_FUN", 0 }, + Package () { "IN_FUN0", 3 }, + Package () { "SPSS_QATBFUN", 0 }, // Secure Processor DL Funnel + }, + Package () + { + "SWAO", // AOSS TPDM 0 ATB, AOSS TPDM 1 ATB + Package () { "MERG_FUN", 2 }, + Package () { "IN_FUN2", 1 }, + Package () { "SWAO_FUN0", 7 }, // AOSS Funnel + }, + Package () + { + "LLMGOLD", // LLM Gold Cluster ATB + Package () { "MERG_FUN", 2 }, + Package () { "IN_FUN2", 5 }, + Package () { "CPU_FUN1", 6 }, // APSS Top Funnel + }, + Package () + { + "LLMSILVER", // LLM Silver Cluster ATB + Package () { "MERG_FUN", 2 }, + Package () { "IN_FUN2", 5 }, + Package () { "CPU_FUN1", 5 }, // APSS Top Funnel + }, + Package () + { + "MSSDL", // Modem DL HWE TPDM ATB + Package () { "MERG_FUN", 2 }, + Package () { "IN_FUN2", 2 }, + Package () { "MSS_QATBFUN", 0 }, // Modem DL Funnel + }, + } + ) + } + + // The HWEV method holds the base addresses and the sizes of the subsystems + // muxes that are needed to be turned on for collecting the hardware events + // from the corresponding subsystems. + // "Address" and "Length" are used to validate if address from QTF is in range + // "Set" value must match the enum QDSS_HWEVT_PSTATES_ENUM defined in qdssPower.h + // 0xFF means this mux block has the clock already turned on and doesnt need p-state + // It takes values in increments of 2 as in {0,2,4,6,8,... ,etc} + // "Qdss-Csr" - 1 if it is a Qdss CSR register block or 0 if it is a subsystem block + // reference : + // "\\char\tools\Installers\QTF\hwe_db_do_not_export\850_hw_event.xml" timestamp : Mon Feb 06 18:34:45 2017 + Method (HWEV) + { + Return + ( + Package () + { + // Address, Length, Set, Qdss-Csr + Package () { 0x06001020, 0x10, 0x0, 1}, // QDSS_CS_QDSSCSR_STMEXTHWCTLn - GLOBAL SYS MUX base address + Package () { 0x010BA020, 0x80, 0x0, 0}, + } + ) + } +} + +// Inclusion for enabling QDSS QPMDA ACPI +Include("qdss_qpmda.asl") +// Inclusion for enabling QDSS ETB/ETF and ETR ACPI +Include("qdss_tmc.asl") +// Inclusion for enabling QDSS Replicator ACPI +Include("qdss_replicator.asl") +// Inclusion for enabling QDSS TGU ACPI +Include("qdss_tgu.asl") +// Inclusion for enabling QDSS REMOTE ETM ACPI +Include("qdss_remote_etm.asl") +Include("qdss_verifyclocks.asl") diff --git a/sdm845Pkg/AcpiTables/common/abd.asl b/sdm845Pkg/AcpiTables/common/abd.asl new file mode 100644 index 0000000..68a4815 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/abd.asl @@ -0,0 +1,26 @@ +// +// This file contains ASL Bridge Device definitions +// + +// +// ASL Bridge Device +// +Device (ABD) +{ + Name (_DEP, Package(0x1) + { + \_SB_.PEP0 + }) + Name (_HID, "HID_ABD") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + OperationRegion(ROP1, GenericSerialBus, 0x00000000, 0x100) + Name(AVBL, Zero) + Method(_REG, 0x2, NotSerialized) + { + If(Lequal(Arg0, 0x9)) + { + Store(Arg1, AVBL) + } + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/adsprpc.asl b/sdm845Pkg/AcpiTables/common/adsprpc.asl new file mode 100644 index 0000000..f603dcc --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/adsprpc.asl @@ -0,0 +1,27 @@ + +// +// ADSP RPC Driver +// +Device (ARPC) +{ + Name (_DEP, Package(0x3) + { + \_SB_.MMU0, + \_SB_.GLNK, + \_SB_.SCM0 + }) + Name (_HID, "HID_fastRPC_driver_to_make_RPC_from_apps_to_ADSP") + Alias(\_SB.PSUB, _SUB) +} +// ARPD AUDIO Daemon Driver +Device (ARPD) +{ + Name (_DEP, Package(0x2) + { + \_SB_.ADSP, + \_SB_.ARPC + }) + Name (_HID, "HID_ARPD") + Alias(\_SB.PSUB, _SUB) +} + diff --git a/sdm845Pkg/AcpiTables/common/backlightcfg.asl b/sdm845Pkg/AcpiTables/common/backlightcfg.asl new file mode 100644 index 0000000..597d30e --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/backlightcfg.asl @@ -0,0 +1,39 @@ +/// +// BLCP Method - Backlight control packet method, returns a +// command buffer for a specific backlight level +// +// Input Parameters +// Backlight level - Integer from 0% to 100% +// +// Output Parameters +// +// Packet format: +// +--32bits--+-----variable (8bit alignment)--+ +// | Header | Packet payload | +// +----------+--------------------------------+ +// +// For DSI Command packets, payload data must be in this format +// +// +-- 8 bits-+----variable (8bit alignment)----+ +// | Cmd Type | Packet Data | +// +----------+---------------------------------+ +// +// For I2C Command packets, payload data must be in this format +// +// +-- 16 bits-+----variable (8bit alignment)----+ +// | Address | Command Data | +// +-----------+---------------------------------+ +// +// All packets must follow with a DWORD header with 0x0 +// +Method (BLCP, 1, NotSerialized) { + + // Create Response buffer + Name(RBUF, Buffer(0x100){}) + + // Details to be populated by OEM based on the platform requirements + + // Return the packet data + Return(RBUF) +} + diff --git a/sdm845Pkg/AcpiTables/common/backlightcfg2.asl b/sdm845Pkg/AcpiTables/common/backlightcfg2.asl new file mode 100644 index 0000000..3120537 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/backlightcfg2.asl @@ -0,0 +1,18 @@ +// +// +// BLCP Method - Secondary display backlight control packet method, returns a +// command buffer for a specific backlight level +// +// Backlight configuration format is same as BLCP of primary panel in backlightcfg.asl +// +Method (BLC2, 1, NotSerialized) { + + // Create Response buffer + Name(RBUF, Buffer(0x100){}) + + // Details to be populated by OEM based on the platform requirements + + // Return the packet data + Return(RBUF) +} + diff --git a/sdm845Pkg/AcpiTables/common/bam.asl b/sdm845Pkg/AcpiTables/common/bam.asl new file mode 100644 index 0000000..575529a --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/bam.asl @@ -0,0 +1,143 @@ +// This file contains the Bus Access Modules (BAM) +// ACPI device definitions and pipe configurations +// + +// +// Device Map: +// 0x2401 - BAM +// +// List of Devices +// BAM1 - CRYPTO1 +// BAM5 - SLIMBUS1 +// BAM6 - SLIMBUS +// BAM7 - TSIF +// BAMD - USB3.0 secondary +// BAME - QDSS +// BAMF - USB3.0 primary +Device (BAM1) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // CRYPTO0 register address space + Memory32Fixed (ReadWrite, 0x1DC4000, 0x00024000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {304} + }) + Return (RBUF) + } +} + +Device (BAM5) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 5) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // AUD_SLIMBUS register address space + Memory32Fixed (ReadWrite, 0x17184000, 0x00032000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {196} + }) + Return (RBUF) + } +} + + +Device (BAM6) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 6) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // QCA_SLIMBUS register address space + Memory32Fixed (ReadWrite, 0x17204000, 0x00026000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {324} + }) + Return (RBUF) + } +} + +Device (BAM7) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 7) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // TSIF register address space + Memory32Fixed (ReadWrite, 0x08884000, 0x00023000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {154} + }) + Return (RBUF) + } +} + +Device (BAMD) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 13) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // USB30 sec register address space + Memory32Fixed (ReadWrite, 0xA904000, 0x00017000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {169} + }) + Return (RBUF) + } +} + +Device (BAME) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 14) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // QDSS register address space + Memory32Fixed (ReadWrite, 0x6064000, 0x00015000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {199} + }) + Return (RBUF) + } +} + +Device (BAMF) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 15) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // USB30 PRI register address space + Memory32Fixed (ReadWrite, 0x0A704000, 0x00017000) + + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {164} + }) + Return (RBUF) + } +} + diff --git a/sdm845Pkg/AcpiTables/common/buses.asl b/sdm845Pkg/AcpiTables/common/buses.asl new file mode 100644 index 0000000..df38213 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/buses.asl @@ -0,0 +1,680 @@ +// +// +// Please note that not all the SE engine instances (I2C/SPI/UART) from below asl file can be used directly by icluding in the client ACPI, +// The corresponding Access Control needs to be enabled from TZ side to get the SE/usecase working End 2 End. +// +// + +// +// QUPV3_ID0_SE7 (attached to BT SOC) +// +Device (UAR7) +{ + Name (_HID, "HID_UART") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 7) + Name (_DEP, Package() { \_SB_.PEP0 }) + Name (_CCA, 0) + + Method (_CRS) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0x00898000, 0x0004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {639} + GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {48} // UART RX, + }) + Return (RBUF) + } + + Method (_STA) + { + Return (0x0B) + } +} + +// +// QUPV3_ID1_SE2 (UART Debug port) +// + Device (UARD) + { + Name (_HID, "HID_UART") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 10) + Name (_DEP, Package() { \_SB_.PEP0 }) + Name (_CCA, 0) + + Method (_CRS) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0x00A84000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {386} + GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {5} // UART RX + }) + Return (RBUF) + } + } + +// +// I2C4 - "Core I2C Bus" +// +Device (I2C4) +{ + Name (_HID, "HID_I2C") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 4) + Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0088C000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {636} + }) + Return (RBUF) + } +} + +// +// I2C5 - "Core I2C Bus" +// +Device (I2C6) +{ + Name (_HID, "HID_I2C") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 6) + Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x894000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {638} + }) + Return (RBUF) + } +} + +// +// I2C11 - "Core I2C Bus" +// +Device (IC11) +{ + Name (_HID, "HID_I2C") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 11) + Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00A88000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {387} + }) + Return (RBUF) + } +} + + +// +// I2C15 - "Core I2C Bus" +// +//Device (IC15) +//{ +// Name (_HID, "HID_I2C") +// Name (_UID, 15) +// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) +// Name (_CCA, 0) + +// Method (_CRS, 0x0, NotSerialized) +// { +// Name (RBUF, ResourceTemplate () +// { +// Memory32Fixed (ReadWrite, 0x00A98000, 0x00004000) +// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {391} +// }) +// Return (RBUF) +// } +//} + + +//SPI9 - EPM + +Device (SPI9) +{ + Name (_HID, "HID_SPI") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 9) + Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP1}) + Name (_CCA, 0) + + Method (_CRS) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0xA80000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {385} + }) + Return (RBUF) + } +} + +// +// PEP resources for buses +// +Scope(\_SB_.PEP0) +{ + Method(BSMD) + { + Return(BSRC) + } + + Method(PQMD) + { + If (LLess(\_SB.SIDV,0x00020000)) + { + Return(DFS1) + } + Else + { + Return(DFS2) + } + } + + Name(BSRC, Package() + { + // "\\_SB.UAR7" + Package() + { + "DEVICE", "\\_SB.UAR7", + + Package() + { + "COMPONENT", 0, // UART resources + + Package() + { + "FSTATE", 0, // enable UART clocks + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 1}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 1400000000,1666}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 148000000, 50000000}}, + }, + + Package() + { + "FSTATE", 1, // disable UART clocks + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 2}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 0, 0}}, + }, + + Package() + { + "PSTATE", 0, // enable GPIOs + Package(){"TLMMGPIO", Package(){ 45, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 46, 0, 1, 0, 0, 0 }}, + Package(){"TLMMGPIO", Package(){ 47, 0, 1, 0, 0, 0 }}, + Package(){"TLMMGPIO", Package(){ 48, 0, 1, 0, 1, 0 }}, + }, + + Package() + { + "PSTATE", 1, // disable GPIOs + Package(){"TLMMGPIO", Package(){ 45, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 46, 0, 1, 0, 0, 0 }}, + Package(){"TLMMGPIO", Package(){ 47, 0, 1, 0, 0, 0 }}, + Package(){"TLMMGPIO", Package(){ 48, 0, 1, 0, 1, 0 }}, + }, + + Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 7372800, 4}}}, + Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 14745600, 4}}}, + Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 29491200, 4}}}, + Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 32000000, 4}}}, + Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 48000000, 4}}}, + Package(){"PSTATE", 7, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 64000000, 4}}}, + Package(){"PSTATE", 8, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 80000000, 4}}}, + Package(){"PSTATE", 9, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 96000000, 4}}}, + Package(){"PSTATE", 10, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,102400000, 4}}}, + Package(){"PSTATE", 11, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,112000000, 4}}}, + Package(){"PSTATE", 12, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,117964800, 4}}}, + Package(){"PSTATE", 13, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,128000000, 4}}}, + }, + + Package() + { + "COMPONENT", 1, // DMA resources + Package(){"FSTATE", 0}, // enable DMA clocks + Package(){"FSTATE", 1}, // disable DMA clocks + }, + }, + + // "\\_SB.UARD" + Package() + { + "DEVICE", 0x2, //Debug device + "\\_SB.UARD", + + Package() + { + "COMPONENT", 0, // UART resources + + Package() + { + "FSTATE", 0, // enable UART clocks + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk",3, 7372800, 4}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 1}}, + + Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000, 50000000}}, + }, + + Package() + { + "FSTATE", 1, // disable UART clocks + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 2}}, + + Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0}}, + }, + + Package() + { + "PSTATE", 0, // enable GPIOs + Package(){"TLMMGPIO", Package(){ 5, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 4, 0, 1, 0, 0, 0 }}, + }, + + Package() + { + "PSTATE", 1, // disable GPIOs + Package(){"TLMMGPIO", Package(){ 5, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 4, 0, 1, 0, 0, 0 }}, + }, + + Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 7372800, 4}}}, + Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 14745600, 4}}}, + Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 29491200, 4}}}, + Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 32000000, 4}}}, + Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 48000000, 4}}}, + Package(){"PSTATE", 7, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 64000000, 4}}}, + Package(){"PSTATE", 8, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 80000000, 4}}}, + Package(){"PSTATE", 9, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 96000000, 4}}}, + Package(){"PSTATE", 10, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,102400000, 4}}}, + Package(){"PSTATE", 11, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,112000000, 4}}}, + Package(){"PSTATE", 12, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,117964800, 4}}}, + Package(){"PSTATE", 13, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,128000000, 4}}}, + }, + + Package() + { + "COMPONENT", 1, // DMA resources + Package(){"FSTATE", 0}, // enable DMA clocks + Package(){"FSTATE", 1}, // disable DMA clocks + }, + }, + + // "\\_SB.I2C4" + Package() + { + "DEVICE", + "\\_SB.I2C4", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s3_clk",8,19200000, 4}}, + + Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 1400000000,1666}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 148000000, 50000000}}, + + // Configure SDA and then SCL + package() {"TLMMGPIO", package() {41, 1, 1, 1, 3, 0}}, + package() {"TLMMGPIO", package() {42, 1, 1, 1, 3, 0}}, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s3_clk",2}}, + + Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 0, 0 }}, + Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 0, 0 }}, + + // Configure SCL and then SDA + package() { "TLMMGPIO", package() {41, 0, 0, 0, 3, 0}}, + package() { "TLMMGPIO", package() {42, 0, 0, 0, 3, 0}}, + }, + }, + + // "\\_SB.I2C6" + Package() + { + "DEVICE", + "\\_SB.I2C6", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s5_clk",8,19200000, 4}}, + + Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 1400000000,1666}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 148000000, 50000000}}, + + // Configure SDA and then SCL + package() {"TLMMGPIO", package() {85, 1, 1, 1, 3, 0}}, + package() {"TLMMGPIO", package() {86, 1, 1, 1, 3, 0}}, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s5_clk",2}}, + + Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 0, 0 }}, + Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 0, 0 }}, + + // Configure SCL and then SDA + package() { "TLMMGPIO", package() {85, 0, 0, 0, 3, 0}}, + package() { "TLMMGPIO", package() {86, 0, 0, 0, 3, 0}}, + }, + }, + + // "\\_SB.IC11" + Package() + { + "DEVICE", + "\\_SB.IC11", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + + }, + Package() + { + "DSTATE", + 0x0, // D0 state + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s2_clk",8,19200000, 4}}, + + Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}}, + Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000}}, + + // Configure SDA and then SCL + package() {"TLMMGPIO", package() {55, 1, 1, 1, 3, 0}}, + package() {"TLMMGPIO", package() {56, 1, 1, 1, 3, 0}}, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s2_clk",2}}, + + Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0 }}, + Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0 }}, + + // Configure SCL and then SDA + package() { "TLMMGPIO", package() {55, 0, 0, 0, 3, 0}}, + package() { "TLMMGPIO", package() {56, 0, 0, 0, 3, 0}}, + }, + }, + + // "\\_SB.IC15" + //Package() + //{ + //"DEVICE", + //"\\_SB.IC15", + //Package() + //{ + //"COMPONENT", + //0x0, // Component 0. + //Package() + //{ + //"FSTATE", + //0x0, // f0 state + //}, + //}, + //Package() + //{ + //"DSTATE", + //0x0, // D0 state + //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}}, + //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}}, + //Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",8,19200000, 4}}, + //Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666 }}, + //Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000 }}, + + // Configure SDA and then SCL + //package() {"TLMMGPIO", package() {33, 1, 1, 1, 3, 0}}, + //package() {"TLMMGPIO", package() {34, 1, 1, 1, 3, 0}}, + //}, + //Package() + //{ + //"DSTATE", + //0x1, // D1 state + //}, + //Package() + //{ + //"DSTATE", + //0x2, // D2 state + //}, + //Package() + //{ + //"DSTATE", + //0x3, // D3 state + //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}}, + //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}}, + //Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",2}}, + //Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0 }}, + //Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0 }}, + + // Configure SCL and then SDA + //package() { "TLMMGPIO", package() {33, 0, 0, 0, 3, 0}}, + // package() { "TLMMGPIO", package() {34, 0, 0, 0, 3, 0}}, + //}, + //}, + }) + + Name(DFS1, Package() + { + Package() + { + "DEVICE", "\\_SB.SPI9", + + Package() + { + "COMPONENT", 0, + + Package() {"FSTATE", 0}, + + Package(){"PSTATE", 0, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 19200000, 3}}}, + Package(){"PSTATE", 1, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 32000000, 3}}}, + Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 38400000, 3}}}, + Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 48000000, 3}}}, + Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 64000000, 3}}}, + Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 96000000, 3}}}, + Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 100000000, 3}}}, + }, + + Package() + { + "DSTATE", 0, // enable clocks, enable GPIOs + + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",1}}, + + Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}}, + Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000}}, + + Package(){"TLMMGPIO", Package(){ 65, 1, 2, 0, 1, 0}}, // MISO + Package(){"TLMMGPIO", Package(){ 66, 1, 2, 1, 1, 0}}, // MOSI + Package(){"TLMMGPIO", Package(){ 67, 1, 2, 1, 1, 0}}, // CLK + Package(){"TLMMGPIO", Package(){ 68, 1, 2, 1, 1, 0}}, // CS + }, + + Package() {"DSTATE", 1,}, + Package() {"DSTATE", 2,}, + + Package() + { + "DSTATE", 3, // disable clocks, disable GPIOs + + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",2}}, + + Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0}}, + + Package(){"TLMMGPIO", Package(){ 65, 0, 2, 0, 1, 0}}, // MOSI + Package(){"TLMMGPIO", Package(){ 66, 0, 2, 0, 1, 0}}, // MISO + Package(){"TLMMGPIO", Package(){ 67, 0, 2, 0, 1, 0}}, // CS + Package(){"TLMMGPIO", Package(){ 68, 0, 2, 0, 1, 0}}, // CLK + }, + }, + }) + + Name(DFS2, Package() + { + Package() + { + "DEVICE", "\\_SB.SPI9", + + Package() + { + "COMPONENT", 0, + + Package() {"FSTATE", 0}, + + Package(){"PSTATE", 0, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 19200000, 3}}}, + Package(){"PSTATE", 1, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 32000000, 3}}}, + Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 48000000, 3}}}, + Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 64000000, 3}}}, + Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 96000000, 3}}}, + Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 100000000, 3}}}, + Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 120000000, 3}}}, + }, + + Package() + { + "DSTATE", 0, // enable clocks, enable GPIOs + + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",1}}, + + Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}}, + Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000}}, + + + Package(){"TLMMGPIO", Package(){ 65, 1, 2, 0, 1, 0}}, // MISO + Package(){"TLMMGPIO", Package(){ 66, 1, 2, 1, 1, 0}}, // MOSI + Package(){"TLMMGPIO", Package(){ 67, 1, 2, 1, 1, 0}}, // CLK + Package(){"TLMMGPIO", Package(){ 68, 1, 2, 1, 1, 0}}, // CS + }, + + Package() {"DSTATE", 1,}, + Package() {"DSTATE", 2,}, + + Package() + { + "DSTATE", 3, // disable clocks, disable GPIOs + + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",2}}, + + Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0}}, + + Package(){"TLMMGPIO", Package(){ 65, 0, 2, 0, 1, 0}}, // MOSI + Package(){"TLMMGPIO", Package(){ 66, 0, 2, 0, 1, 0}}, // MISO + Package(){"TLMMGPIO", Package(){ 67, 0, 2, 0, 1, 0}}, // CS + Package(){"TLMMGPIO", Package(){ 68, 0, 2, 0, 1, 0}}, // CLK + }, + }, + }) +} + diff --git a/sdm845Pkg/AcpiTables/common/cbsp_mproc.asl b/sdm845Pkg/AcpiTables/common/cbsp_mproc.asl new file mode 100644 index 0000000..10ec8aa --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/cbsp_mproc.asl @@ -0,0 +1,64 @@ +// +// Core-BSP MPROC Drivers (IPC Router & GLINK) +// + +// +// IPC Router +// +Device (IPC0) +{ + Name (_DEP, Package(0x1) + { + \_SB_.GLNK + }) + Name (_HID, "HID_IPC0") + Alias(\_SB.PSUB, _SUB) +} + +// +// GLINK +// +// Order of incoming and outgoing interrupts depend on the number of interrupts mentioned in INTR method +Device (GLNK) +{ + Name (_DEP, Package(0x1) + { + \_SB_.RPEN + }) + Name (_HID, "HID_GLNK") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + + // Inbound SMP2P interrupt from Modem (SYS_apssQgicSPI(451)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {483} + + // Inbound SMP2P interrupt from ADSP (SYS_apssQgicSPI[158]): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {190} + + // Inbound SMP2P interrupt from SSC (SYS_apssQgicSPI(172)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {204} + + // Inbound SMP2P interrupt from CDSP (SYS_apssQgicSPI(576)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {608} + + // Inbound SMEM XPORT interrupt from Modem (SYS_apssQgicSPI(449)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {481} + + // Inbound SMEM XPORT interrupt from ADSP (SYS_apssQgicSPI[156]): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {188} + + // Inbound SMEM XPORT interrupt from SSC (SYS_apssQgicSPI(170)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {202} + + // Inbound SMEM XPORT interrupt from CDSP (SYS_apssQgicSPI(574)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {606} + + }) + Return (RBUF) + } + +} diff --git a/sdm845Pkg/AcpiTables/common/corebsp_resources.asl b/sdm845Pkg/AcpiTables/common/corebsp_resources.asl new file mode 100644 index 0000000..2b924c3 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/corebsp_resources.asl @@ -0,0 +1,4153 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by core BSP drivers. +// +// +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + + Method(BPMD) + { + Return(BPCC) + } + + Method(LPMD) + { + Return(LPCC) + } + + Name(BPCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.UFS0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + Package() { "PSTATE_ADJUST", Package() { 0, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 0 } }, + }, + Package() + { + "FSTATE", + 0x1, // f1 state + Package() { "PSTATE_ADJUST", Package() { 2, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 0, 1 } }, + }, + + Package() + { + "PSTATE_SET", + 0x0, + + Package() + { + "PSTATE", + 0x0, + Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 1 }}, + }, + Package() + { + "PSTATE", + 0x1, + Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 2 }}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x1, + + Package() + { + "PSTATE", + 0x0, + + Package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 8, 200000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 8, 150000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 8, 300000000, 2}}, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_mem_clkref_en", 1,}}, + }, + Package() + { + "PSTATE", + 0x1, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 2,}}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x2, + + Package() + { + "PSTATE", + 0x0, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 900000000, 900000000}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 299000000, 0}}, + }, + Package() + { + "PSTATE", + 0x1, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 0, 0}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + + Package() {"PSTATE_ADJUST", Package() { 2, 0 } }, + + Package() {"PSTATE_ADJUST", Package() { 0, 0 } }, + + // Vcc supply = L20 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO20_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq supply = L2 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO2_A", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq2 supply = S4 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_SMPS4_A", + 2, // Voltage Regulator type = SMPS + 1800000, // 1.8V + 1, // Force enable from software + 0, // Power mode - AUTO + 0, // head room voltage + }, + }, + + // PHY VDDA supply: L26 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO26_A", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // VDDA_UFS_CORE supply: L1 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO1_A", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"DELAY", package() { 35 }}, + + Package() {"PSTATE_ADJUST", Package() { 1, 0 } }, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() {"PSTATE_ADJUST", Package() { 1, 1 } }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO1_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO26_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO20_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"PSTATE_ADJUST", Package() { 0, 1 } }, + + Package() {"PSTATE_ADJUST", Package() { 2, 1 } }, + }, + }, + Package() + { + "DEVICE", + "\\_SB.SDC2", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + + Package() + { + "PSTATE_SET", + 0x0, + + // + // Contract with SDBUS for card frequencies + // + // P-State Note + // -------- ----- + // 0 - 19 Reserved (Legacy) + // 20 Reset to 3.3v signal voltage (max fixed at 2.95v) + // 21 1.8v signal voltage (max fixed at 1.85v) + Package(){"PSTATE", 0, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 1, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 2, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 3, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 4, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 5, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 6, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 7, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 8, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 9, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 11, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 12, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 13, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 14, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 15, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 16, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 17, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 18, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 19, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 20, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO21_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO13_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO21_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO13_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + Package(){"PSTATE", 21, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO13_A", // VREG ID + 1, // Voltage Regulator type = LDO + 1850000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + Package(){"PSTATE", 22, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO21_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO13_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + Package(){"PSTATE", 23, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO21_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO13_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + }, + + // P-state set 1: APPS Clock frequencies + // 0: Disable + // 1: 20 MHz (SVS2) + // 2: 100 MHz (SVS) + // 3: 201.5 MHz (Nominal) + Package() + { + "PSTATE_SET", + 0x1, + + Package() + { + "PSTATE", + 0x0, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 2}}, + }, + Package() + { + "PSTATE", + 0x1, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 20000000, 2}}, + }, + Package() + { + "PSTATE", + 0x2, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 100000000, 2}}, + }, + Package() + { + "PSTATE", + 0x3, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 201500000, 2}}, + }, + }, + + // P-state set 2: Bus Bandwidth requests + // P0: IB = 400 MBps, AB = 200 MBps + // P1: IB = 200 MBps, AB = 100 MBps + // P2: IB = 40 MBps, AB = 20 MBps + // P3: IB = 0 MBps, AB = 0 MBps + Package() + { + "PSTATE_SET", + 0x2, + + Package() + { + "PSTATE", + 0x0, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 400000000, 200000000}}, + }, + + Package() + { + "PSTATE", + 0x1, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 200000000, 100000000}}, + }, + + Package() + { + "PSTATE", + 0x2, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 40000000, 20000000}}, + }, + + Package() + { + "PSTATE", + 0x3, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + }, + + // P-state set 3: MSFT P-states + // P0: Clk = 200 MHz, IB = 400 MBps, AB = 200 MBps + // P1: Clk = 100 MHz, IB = 200 MBps, AB = 100 MBps + // P2: Clk = 20 MHz, IB = 40 MBps, AB = 20 MBps + Package() + { + "PSTATE_SET", + 0x3, + + Package() + { + "PSTATE", + 0x0, + Package() { "PSTATE_ADJUST", Package() { 1, 3 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 0 } }, + }, + Package() + { + "PSTATE", + 0x1, + Package() { "PSTATE_ADJUST", Package() { 1, 2 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 1 } }, + }, + Package() + { + "PSTATE", + 0x2, + Package() { "PSTATE_ADJUST", Package() { 1, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 2 } }, + }, + }, + + + // P-state set 4: AHB clock + Package() + { + "PSTATE_SET", + 0x4, + + Package() + { + "PSTATE", + 0x0, + package() {"CLOCK", package() {"gcc_sdcc2_ahb_clk", 1,}}, // AHB freq should be 100 MHz + }, + Package() + { + "PSTATE", + 0x1, + package() {"CLOCK", package() {"gcc_sdcc2_ahb_clk", 2}}, + }, + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + + Package() {"PSTATE_ADJUST", Package () { 0, 22 }}, + package() {"TLMMPORT", package() { 0x99A000, 0x7FFF, 0x1FE4 }}, + Package() {"PSTATE_ADJUST", Package() { 2, 0 }}, + Package() {"PSTATE_ADJUST", Package() { 4, 0 }}, + Package() {"PSTATE_ADJUST", Package() { 1, 3 }}, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() {"PSTATE_ADJUST", Package() { 1, 0 }}, + Package() {"PSTATE_ADJUST", Package() { 4, 1 }}, + Package() {"PSTATE_ADJUST", Package() { 2, 3 }}, + package() {"TLMMPORT", package() { 0x99A000, 0x7FFF, 0xA00 }}, + Package() {"PSTATE_ADJUST", Package () { 0, 23 }}, + }, + }, + /////////////////////////////////////////////////////////////////////////////////////// + + Package() + { + "DEVICE", + "\\_SB.ADSP.SLM1", + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + Package() + { + "DEVICE", + "\\_SB.ADSP.SLM2", + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + ///////////////////////////////////////////////////////////////////////////////////// + }) + + Name(LPCC, + package () + { + Package() + { + "DEVICE", + "\\_SB.UCP0", + Package() + { + "COMPONENT",0, //Component 0: USB HS Rails for Charger Detection + Package(){"FSTATE", 0 }, //Dummy F-State, required for P-State operation + Package() + { + "PSTATE", 0, // P0 state - Component ON + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + }, + Package() + { + "PSTATE", 1, // P1 state - Component OFF + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + //Enable vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 0} + }, + + }, + }, + //D states + package() { + "DSTATE", 0x0, // D0 state + }, + package() { + "DSTATE", 0x1, // D1 state + }, + package() { + "DSTATE", 0x2, // D2 state + }, + package() { + "DSTATE", 0x3, // D3 state + }, + }, + + //PMIC Type-C Controller + //Component 0: USB HS rails for Automiatic Port Source Detection (APSD) + Package() + { + "DEVICE", + "\\_SB.PTCC", + Package() + { + "COMPONENT",0, //Component 0: USB HS Rails for Charger Detection + Package(){"FSTATE", 0 }, //Dummy F-State, required for P-State operation + Package() + { + "PSTATE", 0, // P0 state - Component ON + // LDO 24: ON, 3.075V, LDO 12: ON, 1.8V + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 1, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 1, // SW Power Mode = NPM + 0, // Head Room + }, + }, + }, + Package() + { + "PSTATE", 1, // P1 state - Component OFF + // LDO 24 & LDO 12 : OFF + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @0v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 0, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @0v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 0, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + }, + //D states + package() { + "DSTATE", 0x0, // D0 state + }, + package() { + "DSTATE", 0x1, // D1 state + }, + package() { + "DSTATE", 0x2, // D2 state + }, + package() { + "DSTATE", 0x3, // D3 state + }, + }, //End PMIC Type-C Controller + Package() + { + "DEVICE", + "\\_SB.URS0", + Package() + { + "COMPONENT", + Zero, + Package() {"FSTATE", 0}, + Package() {"PSTATE", 0}, + Package() {"PSTATE", 1} + }, + Package() {"DSTATE", 0 }, + Package() {"DSTATE", 1 }, + Package() {"DSTATE", 2 }, + Package() {"DSTATE", 3 } + }, + + + //USB SS/HS1 core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.URS0.USB0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Now Enable all the clocks + + //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps //LowSVS + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact) + //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact) + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact) + //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact) + 0 // AB=0 MBps + } + }, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() + { + "CLOCK", + package() { "gcc_usb3_prim_phy_aux_clk", 2} + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + // Disable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0 v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for USB0 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB0 + // + //************************* USB3.0 SS/HS0 core (Peripheral Stack) **************************** + // + package() + { + "DEVICE", + "\\_SB.URS0.UFN0", + package() + { + "COMPONENT", + 0x0, + // F-State placeholders + package() + { + "FSTATE", + 0x0, + }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + + package() + { // PERIPH D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @ 3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + + }, + package() + { + // PERIPH D1: Not supported by USBFN driver + "DSTATE", //USB SS+HS suspend state + 0x1, + }, + package() + { // PERIPH D2 + "DSTATE", //USB DCP/HVDCP charger state + 0x2, + + // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable ; + package() {"CLOCK", package() { "gcc_usb30_prim_master_clk", 2 } }, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + //Disable gcc_usb3_prim_phy_aux_clk + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + package() {1, "/arc/client/rail_cx", 256} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { + // PERIPH D3 + "DSTATE", + 0x3, // Detach State + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + // Disable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for UFN0 (peripheral) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End UFN0 + + //USB Primary Core (Host Stack) Standalone + Package() + { + "DEVICE", + "\\_SB.USB0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Now Enable all the clocks + + //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps //LowSVS + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact) + //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact) + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact) + //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact) + 0 // AB=0 MBps + } + }, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() + { + "CLOCK", + package() { "gcc_usb3_prim_phy_aux_clk", 2} + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + // Disable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0 v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for USB0 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB0 + + //USB secondary core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.USB1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Now Enable all the clocks + + //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps //LowSVS + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact) + //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact) + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact) + //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact) + 0 // AB=0 MBps + } + }, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() + { + "CLOCK", + package() { "gcc_usb3_sec_phy_aux_clk", 2} + }, + + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + // Disable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0 v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for USB1 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB1 + + Package() + { + "DEVICE", + "\\_SB.URS1", + Package() + { + "COMPONENT", + Zero, + Package() {"FSTATE", 0}, + Package() + { + "PSTATE", + 0, // P0 -Disable Vbus + package() + { + "PMICGPIO", + Package() + { + "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", + 1, // PMI8998 + 9, // GPIO #10: USBOTG_VBUS_EN + 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS + 0, // PM_GPIO_VIN0 + 0, // EN_AND_SOURCE_SEL, 1: LOW + 1, // PM_GPIO_OUT_BUFFER_LOW + 4, // PM_GPIO_I_SOURCE_PULL_DOWN_10uA + }, + }, + }, + Package() + { + "PSTATE", + 1, // P1 - Enable Vbus + package() + { + "PMICGPIO", + Package() + { + "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", + 1, // PMI8998 + 9, // GPIO #10: USBOTG_VBUS_EN + 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS + 0, // PM_GPIO_VIN0 + 1, // EN_AND_SOURCE_SEL, 1: HIGH + 3, // PM_GPIO_OUT_BUFFER_HIGH + 5, // PM_GPIO_I_SOURCE_PULL_NO_PULL + }, + }, + } + }, + Package() {"DSTATE", 0 }, + Package() {"DSTATE", 1 }, + Package() {"DSTATE", 2 }, + Package() {"DSTATE", 3 } + }, + + + //USB secondary core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.URS1.USB1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Now Enable all the clocks + + //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps //LowSVS + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact) + //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact) + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact) + //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact) + 0 // AB=0 MBps + } + }, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() + { + "CLOCK", + package() { "gcc_usb3_sec_phy_aux_clk", 2} + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + // Disable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0 v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for USB1 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB1 + + //************************* USB3.0 SS/HS0 core (Peripheral Secondary Stack) **************************** + // + package() + { + "DEVICE", + "\\_SB.URS1.UFN1", + package() + { + "COMPONENT", + 0x0, + // F-State placeholders + package() + { + "FSTATE", + 0x0, + }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + + package() + { // PERIPH D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @ 3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + + }, + package() + { + // PERIPH D1: Not supported by USBFN driver + "DSTATE", //USB SS+HS suspend state + 0x1, + }, + package() + { // PERIPH D2 + "DSTATE", //USB DCP/HVDCP charger state + 0x2, + + // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable ; + package() {"CLOCK", package() { "gcc_usb30_sec_master_clk", 2 } }, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + //Disable gcc_usb3_sec_phy_aux_clk + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + package() {1, "/arc/client/rail_cx", 256} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { + // PERIPH D3 + "DSTATE", + 0x3, // Detach State + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + // Disable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for UFN1 (peripheral) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End UFN1 + }) +} diff --git a/sdm845Pkg/AcpiTables/common/corebsp_wa_resources.asl b/sdm845Pkg/AcpiTables/common/corebsp_wa_resources.asl new file mode 100644 index 0000000..f183918 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/corebsp_wa_resources.asl @@ -0,0 +1,242 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by core BSP drivers. +// +// +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + Method(LPMD) + { + Return(LPCC) + } + + Name(LPCC, + Package () + { + //Need to put under external Cfg package + //Touch + // Package() + // { + // "DEVICE", + // "\\_SB.TSC0", + // Package() + // { + // "COMPONENT", + // 0x0, // Component 0. + // Package() + // { + // "FSTATE", + // 0x0, // f0 state + // }, + + // Package() + // { + // "FSTATE", + // 0x1, // f1 state + // }, + + // }, + // Package() + // { + // "DSTATE", + // 0x0, // D0 state + + // package() + // { + // "PMICVREGVOTE", // PMICVREGVOTE resource + // package() + // { + // "PPP_RESOURCE_ID_SMPS3_A", + // 2, // Voltage Regulator type = SMPS + // 1800000, // 1.8V + // 2000000, // 2000 mA -> 2A + // 1, // Force enable from s/w + // 0, // Disable pin control enable + // 0, // Power mode - AUTO + // 0, // Disable pin control power mode + // 0, // Bypass allowed - default + // 5, // Frequency - 3.20 MHz + // 0, // Freq reason - none + // 0, // Quiet Mode - disable + // 0, // Corner Mode - none + // 0, // head room voltage + // }, + // }, + + + // package() + // { + // "TLMMGPIO", // TLMMGPIO Resource Enabling HID/I2C firmware on Touch Controller + // package() + // { + // 57, // PIN number + // 0, // State = active + // 0, // Function select = GPIO + // 1, // direction = Output + // 0, // Pull value = No Pull + // 0, // Drive Strength = 2mA + // }, + // }, + + + + // // START mxT1386E in RESET + // package() + // { + // "TLMMGPIO", // TLMMGPIO resource Touch RESET + // package() + // { + // 60, // PIN number + // 0, // State = inactive + // 0, // Function select = GPIO + // 1, // direction = Output + // 0, // Pull value = No Pull + // 0, // Drive Strength = 2mA + // }, + // }, + + // // Enable POWER to mxT1664S using LDO 22 + // package() + // { + // "PMICVREGVOTE", // PMICVREGVOTE resource + // package() + // { + // "PPP_RESOURCE_ID_LDO22_A", // VREG ID + // 1, // Voltage Regulator type = LDO + // 3000000, // 3.00V. Voltage is in micro volts on 8960 + // 300000, // 300 mA Peak current in microamps + // 1, // force enable from software + // 0, // disable pin control enable + // 1, // power mode - Normal Power Mode + // 0, // power mode pin control - disable + // 0, // bypass mode allowed + // 0, // head room voltage + // }, + // }, + + + // // WAIT for AVdd & DVdd to stabilize + // package() + // { + // "DELAY", // Delay resource + // package() + // { + // 2, // 2 Millisec delay + // }, + // }, + // // Take mxT1664S out of RESET + // package() + // { + // "TLMMGPIO", // TLMMGPIO resource Touch RESET + // package() + // { + // 60, // PIN number + // 1, // State = active + // 0, // Function select = GPIO + // 1, // direction = Output + // 0, // Pull value = No Pull + // 0, // Drive Strength = 2mA + // }, + // }, + // // WAIT for mxT1386E to be READY for I2C communication + // package() + // { + // "DELAY", // Delay resource + // package() + // { + // 100, // 100 Millisec delay + // }, + // }, + + + + // }, //End of D0 + + // Package() + // { + // "DSTATE", + // 0x3, // D3 state + + // // Turn OFF POWER to mxT1664S + // package() + // { + // "PMICVREGVOTE", // PMICVREGVOTE resource + // package() + // { + // "PPP_RESOURCE_ID_LDO22_A", + // 1, // Voltage Regulator type = LDO + // 0, // Voltage (uV) + // 0, // Peak current (uA) + // 0, // force disable from software + // 0, // disable pin control enable + // 0, // power mode - Low Power Mode + // 0, // power mode pin control - disable + // 0, // bypass mode allowed + // 0, // head room voltage + // }, + // }, + + // //Drive SMPS3A to low power mode + // package() + // { + // "PMICVREGVOTE", // PMICVREGVOTE resource + // package() + // { + // "PPP_RESOURCE_ID_SMPS3_A", + // 2, // Voltage Regulator type = SMPS + // 0, // 0V + // 0, // 0 mA + // 1, // Force enable from s/w + // 0, // Disable pin control enable + // 0, // Power mode - AUTO + // 0, // Disable pin control power mode + // 0, // Bypass allowed - default + // 5, // Frequency - 3.20 MHz + // 0, // Freq reason - none + // 0, // Quiet Mode - disable + // 0, // Corner Mode - none + // 0, // head room voltage + // }, + // }, + + + // //Drive Firmware Selection line to low power mode + // package() + // { + // "TLMMGPIO", // TLMMGPIO Resource Selecting HID/I2C firmware on Touch Controller + // package() + // { + // 57, // PIN number + // 0, // State = Inactive + // 0, // Function select = GPIO + // 0, // direction = Input + // 1, // Pull value = Pull Down + // 0, // Drive Strength = 2mA + // }, + // }, + // //Drive Reset line in low power mode + // package() + // { + // "TLMMGPIO", // TLMMGPIO resource Touch RESET + // package() + // { + // 60, // PIN number + // 0, // State = inactive + // 0, // Function select = GPIO + // 0, // direction = Output + // 1, // Pull value = Pull Down + // 0, // Drive Strength = 2mA + // }, + // }, + + // }, + // }, + ///////////////////////////////////////////////////////////////////////////////////// + }) + +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/corebsp_wp_resources.asl b/sdm845Pkg/AcpiTables/common/corebsp_wp_resources.asl new file mode 100644 index 0000000..32e7523 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/corebsp_wp_resources.asl @@ -0,0 +1,13 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by core BSP drivers. +// +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + +} diff --git a/sdm845Pkg/AcpiTables/common/crypto_resources.asl b/sdm845Pkg/AcpiTables/common/crypto_resources.asl new file mode 100644 index 0000000..55d029c --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/crypto_resources.asl @@ -0,0 +1,495 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by pep drivers. +// +// +//=========================================================================== + + + +Scope(\_SB_.PEP0) +{ + + // CRYPTO + Method(CRMD) + { + Return(CRCC) + } + + + Name(CRCC, + Package () + { + //Device QsecureMSM Data + Package() + { + "DEVICE", + "\\_SB.QBCC", + + Package() + { + "COMPONENT", + 0x0, // Component 0. PRNG + Package() + { + "FSTATE", + 0x0, // f0 state + + //package() {"REQUIRED_RESOURCE", package() { 1, "/clk/pnoc" , 100000}}, // 100MHz + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PRNG", 800000000, 0}}, + // Earlier the clock request was 100MHz. Replacing it with BUSARB: 800MB/s is requested because the bus width is 8 bytes, so one 8-byte transfer occurs per clock. + + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_prng_ahb_clk", // Clock name + 1, // Enable + 0, // na + 1, // Match, at least + } + }, + }, + Package() + { + "FSTATE", + 0x1, // f1 state + //package() {"REQUIRED_RESOURCE", package() { 1, "/clk/pnoc" , 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PRNG", 0, 0}}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_prng_ahb_clk", // Clock name + 2, // Disable + 0, // na + 1, // Match, at least + } + }, + }, + }, + + Package() + { + "COMPONENT", + 0x1, // Component 1. Dedicated Crypto (CRYPTO1 - ce2) + Package() + { + "FSTATE", + 0x0, // f0 state + //package() {"REQUIRED_RESOURCE", package() { 1, "/clk/snoc", 0xffffffff}}, + //package() {"REQUIRED_RESOURCE", package() { 1, "/clk/cnoc", 0xffffffff}}, + //package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE1", "ICBID_SLAVE_EBI1", 200000000, 200000000}}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce2_ahb_clk", // Clock name + 1, // 1: Enable + 0, // Freq: NA + 1, // Match: 1, at least + } + }, + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce2_axi_clk", // Clock name + 1, // 1: Enable + 0, // Freq: NA + 1, // Match: 1, at least + } + }, + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce2_clk", // Clock name + 1, // 1: Enable + 0, // Freq: NA + 1, // Match: 1, at least + } + }, + + //Attach with Pstate 0 (Highest Power) + package(){"PSTATE_ADJUST", Package () { 0, 0 }}, + }, + + Package() + { + "FSTATE", + 0x1, // f1 state + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/snoc", 0x0}}, + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/cnoc", 0x0}}, + + //Attach with Pstate 3 (Remove bandwidth vote) + package(){"PSTATE_ADJUST", Package () { 0, 3 }}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce2_ahb_clk", // Clock name + 2, // Disable + 0, // na + 1, // Match: At Least + } + }, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce2_axi_clk", // Clock name + 2, // Disable + 0, // na + 1, // Match: At Least + } + }, + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce2_clk", // Clock name + 2, // Disable + 0, // na + 1, // Match: At Least + } + }, + }, + + Package() + { + "PSTATE", + 0x0, // P0 state + //Highest power state , vote for max possible frequency, Device should already be in F0, before reaching this state + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE1", "ICBID_SLAVE_EBI1", 200000000, 200000000}}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce2_clk", // Clock name + 3, // 3: Set + 171430000, // Freq: 171.43 Mhz (Turbo/Nominal) + 1, // Match: 1, at least + } + }, + }, + Package() + { + "PSTATE", + 0x1, // P1 state + //Low power state , vote for less frequency, Device should already be in F0, before reaching this state + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE1", "ICBID_SLAVE_EBI1", 100000000, 100000000}}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce2_clk", // Clock name + 3, // 3: Set + 85710000, // Freq: 85.71 Mhz (SVS) + 1, // Match: 1, at least + } + }, + }, + Package() + { + "PSTATE", + 0x2, // P2 state + //Lower power state , vote for least possible frequency, Device should already be in F0, before reaching this state + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE1", "ICBID_SLAVE_EBI1", 50000000, 50000000}}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce2_clk", // Clock name + 3, // 3: Set + 42860000, // Freq: 42.86 Mhz (SVS2) + 1, // Match: 1, at least + } + }, + }, + Package() + { + "PSTATE", + 0x3, // P3 state + //Off power state , remove bandwidth votes. Device should transition to this state before going to F1 + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE1", "ICBID_SLAVE_EBI1", 0, 0}}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce2_clk", // Clock name + 3, // 3: Set + 42860000, // Freq: 42.86 Mhz (SVS2) + 1, // Match: 1, at least + } + }, + }, + }, + + Package() + { + "COMPONENT", + 0x2, // Component 2. Shared Crypto (CRYPTO0) + Package() + { + "FSTATE", + 0x0, // f0 state + + //skubair: New way to turn on/off clocks through NPA + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce1", 1 } }, + + //Attach with Pstate 0 (Highest Power) + package(){"PSTATE_ADJUST", Package () { 0, 0 }}, + }, + Package() + { + "FSTATE", + 0x1, // f1 state + + //Attach with Pstate 3 (Remove bandwidth vote) + package(){"PSTATE_ADJUST", Package () { 0, 3 }}, + + //skubair: New way to turn on/off clocks through NPA + //Removing below vote. Instead, setting the freq to 0 Hz in P3 + //package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce1", 0 } }, + }, + Package() + { + "PSTATE", + 0x0, // P0 state + //Highest power state , vote for max possible frequency, Device should already be in F0, before reaching this state + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE0", "ICBID_SLAVE_EBI1", 200000000, 200000000}}, + + //skubair: New way to turn on/off clocks through NPA + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce1", 171430 } }, + }, + Package() + { + "PSTATE", + 0x1, // P1 state + //Low power state , vote for less frequency, Device should already be in F0, before reaching this state + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE0", "ICBID_SLAVE_EBI1", 100000000, 100000000}}, + + //skubair: New way to turn on/off clocks through NPA + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce1", 85710 } }, + }, + Package() + { + "PSTATE", + 0x2, // P2 state + //Lower power state , vote for least possible frequency, Device should already be in F0, before reaching this state + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE0", "ICBID_SLAVE_EBI1", 50000000, 50000000}}, + + //skubair: New way to turn on/off clocks through NPA + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce1", 42860 } }, + }, + Package() + { + "PSTATE", + 0x3, // P3 state + //Off power state , remove bandwidth votes. Device should transition to this state before going to F1 + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE0", "ICBID_SLAVE_EBI1", 0, 0}}, + + //skubair: New way to turn on/off clocks through NPA + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce1", 0 } }, + }, + }, + + Package() + { + "COMPONENT", + 0x3, // Component 3. Dedicated Crypto (CRYPTO2) + Package() + { + "FSTATE", + 0x0, // f0 state + //package() {"REQUIRED_RESOURCE", package() { 1, "/clk/snoc", 0xffffffff}}, + //package() {"REQUIRED_RESOURCE", package() { 1, "/clk/cnoc", 0xffffffff}}, + //package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE2", "ICBID_SLAVE_EBI1", 200000000, 200000000}}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce3_ahb_clk", // Clock name + 1, // 1: Enable + 0, // Freq: NA + 1, // Match: 1, at least + } + }, + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce3_axi_clk", // Clock name + 1, // 1: Enable + 0, // Freq: NA + 1, // Match: 1, at least + } + }, + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce3_clk", // Clock name + 1, // 1: Enable + 0, // Freq: NA + 1, // Match: 1, at least + } + }, + + //Attach with Pstate 0 (Highest Power) + package(){"PSTATE_ADJUST", Package () { 0, 0 }}, + }, + + Package() + { + "FSTATE", + 0x1, // f1 state + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/snoc", 0x0}}, + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/cnoc", 0x0}}, + + //Attach with Pstate 3 (Remove bandwidth vote) + package(){"PSTATE_ADJUST", Package () { 0, 3 }}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce3_ahb_clk", // Clock name + 2, // Disable + 0, // na + 1, // Match: At Least + } + }, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce3_axi_clk", // Clock name + 2, // Disable + 0, // na + 1, // Match: At Least + } + }, + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce3_clk", // Clock name + 2, // Disable + 0, // na + 1, // Match: At Least + } + }, + }, + + Package() + { + "PSTATE", + 0x0, // P0 state + //Highest power state , vote for max possible frequency, Device should already be in F0, before reaching this state + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE2", "ICBID_SLAVE_EBI1", 200000000, 200000000}}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce3_clk", // Clock name + 3, // 3: Set + 171430000, // Freq: 171.43 Mhz (Turbo/Nominal) + 1, // Match: At Least + } + }, + }, + Package() + { + "PSTATE", + 0x1, // P1 state + //Low power state , vote for less frequency, Device should already be in F0, before reaching this state + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE2", "ICBID_SLAVE_EBI1", 100000000, 100000000}}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce3_clk", // Clock name + 3, // 3: Set + 85710000, // Freq: 85.71 Mhz (SVS) + 1, // Match: At Least + } + }, + }, + Package() + { + "PSTATE", + 0x2, // P2 state + //Lower power state , vote for least possible frequency, Device should already be in F0, before reaching this state + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE2", "ICBID_SLAVE_EBI1", 50000000, 50000000}}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce3_clk", // Clock name + 3, // 3: Set + 42860000, // Freq: 42.86 Mhz (SVS2) + 1, // Match: At Least + } + }, + }, + Package() + { + "PSTATE", + 0x3, // P3 state + //Off power state , remove bandwidth votes. Device should transition to this state before going to F1 + package() {"BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE2", "ICBID_SLAVE_EBI1", 0, 0}}, + + package() + { + "CLOCK", // Clock resource + package() + { + "gcc_ce3_clk", // Clock name + 3, // 3: Set + 42860000, // Freq: 42.86 Mhz (SVS2) + 1, // Match: At Least + } + }, + }, + }, + } + }) +} diff --git a/sdm845Pkg/AcpiTables/common/cust_dsdt_common.asl b/sdm845Pkg/AcpiTables/common/cust_dsdt_common.asl new file mode 100644 index 0000000..ab0c014 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/cust_dsdt_common.asl @@ -0,0 +1 @@ +// \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/cust_wcnss_resources.asl b/sdm845Pkg/AcpiTables/common/cust_wcnss_resources.asl new file mode 100644 index 0000000..c0e8862 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/cust_wcnss_resources.asl @@ -0,0 +1,10 @@ + +//customizable resource for wlan/bt/fm +// PEP resources for iHelium +// END iHelium + +// PEP resources for Bluetooth SOC +// END BTH0 + +// PEP resources for FM SOC +// END FM diff --git a/sdm845Pkg/AcpiTables/common/cust_win_mproc.asl b/sdm845Pkg/AcpiTables/common/cust_win_mproc.asl new file mode 100644 index 0000000..51c798a --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/cust_win_mproc.asl @@ -0,0 +1,34 @@ + +// +// MPROC Drivers (PIL Driver and Subsystem Drivers) +// + +Scope(\_SB.ADSP) +{ + +} + +Scope(\_SB.AMSS) +{ + +} + +Scope(\_SB.SCSS) +{ + +} + +Scope(\_SB.PILC) +{ + +} + +Scope(\_SB.CDI) +{ + +} + +Scope(\_SB.RPEN) +{ + +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/display.asl b/sdm845Pkg/AcpiTables/common/display.asl new file mode 100644 index 0000000..ffb00fc --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/display.asl @@ -0,0 +1,638 @@ +// +// This file contains the ACPI Extensions for Display Adapters +// +/// +// _ROM Method - Used to retrieve proprietary ROM data for primary panel +// +Method (_ROM, 3, NotSerialized) { + + // Include primary panel specific ROM data + Include("panelcfg.asl") + + //====================================================================================== + // Based on the panel Id(Arg2), store the buffer object into Local2 + // + // IMPORTANT: + // PCFG is buffer name for all default panel configurations + // All other dynamically detected panel configurations must not use this name + //====================================================================================== + Switch ( ToInteger (Arg2) ) + { + // Truly WQHD Dual DSI Command Mode + Case (0x008010) { + Store (PCFG, Local2) + } + // Truly WQHD Dual DSI Video Mode + Case (0x008011) { + Store (PCF1, Local2) + } + // Truly WQHD Single DSI DSC Command Mode + Case (0x008012) { + Store (PCF2, Local2) + } + // Truly WQHD Single DSI DSC Video Mode + Case (0x008013) { + Store (PCF3, Local2) + } + // 4k Dual DSC Sharp Command Mode + Case (0x00008000) { + Store (PCF4, Local2) + } + // 4k Dual DSC Sharp Video Mode + Case (0x00008056) { + Store (PCF5, Local2) + } + // All others + Default { + Store (PCFG, Local2) + } + } + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(Local2))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(Local2))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(Local2), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBuf + CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + Return(RBUF) +} + +// +// IGC method - panel inverse gamma correction table. +// +// The buffer contains inverse gamma correction data for 3 color components, each with 256 16-bit integers. +// The buffer size is 3*256*2 = 1536 bytes. +// each table entry is represend by a 16-bit integer and data format in the buffer is described below: +// +// +--- 16 bits ---+--- 16 bits ---+--- 16 bits ---+---------+--- 16 bits ---+ 0 +// | Red[0] | Red[1] | Red[2] | ... | Red[255] | +// +---------------+---------------+---------------+---------+---------------+ 512 +// | Green[0] | Green[1] | Green[2] | ... | Green[255] | +// +---------------+---------------+---------------+---------+---------------+ 1024 +// | Blue[0] | Blue[1] | Blue[2] | ... | Blue[255] | +// +---------------+---------------+---------------+---------+---------------+ 1536 +// +Method (PIGC, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the IGC buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Return the packet data + Return(RBUF) +} + + +// +// PCC method - panel color correction matrix +// +// Buffer format for HW which support 3X8 color correction matrix. +// +// The buffer contains color correction coefficients for 3 color components, each with 11 64-bit integers. +// The buffer size is 3*11*8 = 264 bytes. +// each coefficient in the matrix is represented by a long long integer (64-bit), and data format in the +// buffer is described below: +// +// +--64 bits--+--64 bits--+--------+--64 bits--+--64 bits--+--64 bits--+--64 bits--+ 0 +// | Red[0] | Red[1] | ... | Red[7] | 0 | 0 | 0 | +// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 88 +// | Green[0] | Green[1] | ... | Green[7] | 0 | 0 | 0 | +// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 176 +// | Blue[0] | Blue[1] | ... | Blue[7] | 0 | 0 | 0 | +// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 264 +// +// Buffer format for HW which support 3X11 color correction matrix. +// +// The buffer contains color correction coefficients for 3 color components, each with 11 64-bit integers. +// The buffer size is 3*11*8 = 264 bytes. +// each coefficient in the matrix is represented by a long long integer (64-bit), and data format in the +// buffer is described below: +// +// +--- 64 bits ---+--- 64 bits ---+--- 64 bits ---+-----------+--- 64 bits ---+ 0 +// | Red[0] | Red[1] | Red[2] | ... | Red[10] | +// +---------------+---------------+---------------+-----------+---------------+ 88 +// | Green[0] | Green[1] | Green[2] | ... | Green[10] | +// +---------------+---------------+---------------+-----------+---------------+ 176 +// | Blue[0] | Blue[1] | Blue[2] | ... | Blue[10] | +// +---------------+---------------+---------------+-----------+---------------+ 264 +// +Method (PPCC, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the PCC buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Return the packet data + Return(RBUF) +} + + +// +// PGC method - panel segment gamma correction table +// +// there're thee components and each with 16 gamma correction segments. Each segment is defined +// as below with parameters, and each parameter is represented by a 32-bit integer (DWORD): +// +// +--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--+ +// | enable | start | gain | offset | one gamma correction segment(16 bytes) +// +-----------+-----------+-----------+-----------+ +// +// +--- 16 bytes ---+--- 16 bytes ---+--- 16 bytes ---+-----------+--- 16 bytes ---+ 0 +// | red_seg[0] | red_seg[1] | red_seg[2] | ... | red_seg[15] | +// +----------------+----------------+----------------+-----------+----------------+ 256 +// | green_seg[0] | green_seg[1] | green_seg[2] | ... | green_seg[15] | +// +----------------+----------------+----------------+-----------+----------------+ 512 +// | blue_seg[0] | blue_seg[1] | blue_seg[2] | ... | blue_seg[15] | +// +----------------+----------------+----------------+-----------+----------------+ 768 +// +Method (PGCT, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the GCT buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Return the packet data + Return(RBUF) +} + + +// +// PLGC method - panel linear gamma correction table +// +// There are three color components, each color component has 1024 entries. each entry is 2 bytes. +// +// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+ 0 +// | red[0] | red[1] | red[2] | ... | red[1023] | +// +---------------+---------------+---------------+-----------+---------------+ 2048 +// | green[0] | green[1] | green[2] | ... | green[1023] | +// +---------------+---------------+---------------+-----------+---------------+ 4096 +// | blue[0] | blue[1] | blue[2] | ... | blue[1023] | +// +---------------+---------------+---------------+-----------+---------------+ 6144 +// +Method (PLGC, 3, NotSerialized) { + // Arg0 - Panel ID + // Arg1 - Data offset + // Arg2 - Data size + + // Based on the panel Id read the LGC buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (TBUF, Buffer() {0x0} ) + + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg1, Sizeof(TBUF))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg1, Local1) + } + + // Arg2 - Data size + // Ensure the size requested is less than 4k + If (LGreater(Arg2, 0x1000)) + { + Store(0x1000, Local2) + } + else + { + Store(Arg2, Local2) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local1, Local2), Sizeof(TBUF))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(TBUF), Local1, Local2); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBUF + CreateField(TBUF, Multiply(0x8, Local1), Multiply(0x8, Local2), RBUF) + + // Return the packet data + Return(RBUF) +} + + +// +// HSIC method - HSIC settings +// +// Hue, Saturation, Intensity, Contrast levels, the first parameter enable/disable HSIC control, +// followed by HSIC level values, each level ranges from -100 to 100, represented by a 32-bit integer: +// +// +--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--++ +// | Enable | Hue | Saturation| Intensity | Contrast | +// +-----------+-----------+-----------+-----------+-----------++ +// +// +Method (HSIC, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the HSIC buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Return the packet data + Return(RBUF) +} + + + +// +// PGMT - panel gamut mapping table for HW which support 9x9x9 gamut mapping: +// +// This method returns the gamut mapping table for a panel. +// +// There are three components. Each component has 8 tables and a total of 729 entries. +// Each value is represented by a 16-bit integer: +// +// Table ID Entries +// 0 125 +// 1 100 +// 2 80 +// 3 100 +// 4 100 +// 5 80 +// 6 64 +// 7 80 +// +// +----- 16 bits -----+----- 16 bits ------+----- 16 bits -----+-----------+----- 16 bits -------+ +// | red_comp[0][0] | red_comp[0][1] | red_comp[0][2] | ... | red_comp[7][79] | +// +-------------------+--------------------+-------------------+---------------------------------+ +// | green_comp[0][0] | green_comp[0][1] | green_comp[0][2] | ... | green_comp[7][79] | +// +-------------------+--------------------+-------------------+---------------------------------+ +// | blue_comp[0][0] | blue_comp[0][1] | blue_comp[0][2] | ... | blue_comp[7][79] | +// +-------------------+--------------------+-------------------+---------------------------------+ +// +Method (PGMT, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the GMT buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (TBUF, Buffer() {0x0} ) + + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(TBUF))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Arg1 - Data size + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(TBUF))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(TBUF), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBUF + CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + + // Return the packet data + Return(RBUF) +} + + + +// +// PWGM - panel gamut mapping data for HW which support 17x17x17 gamut mapping +// +// This data's header which has two fields: +// NumSamplesPerColorComponent: Number samples per color component in gamut mapping table. +// NumSegmentsPerColor : Number of segments per color component. +// NumSegmentsPerColor must equal 0 or NumSamplesPerColorComponent -1. +// +// This data also can have two tables, one is 3d table, one is segment table. +// Segment table is only required if NumSegmentsPerColor != 0. +// +// 3d table: There are three components. If number samples per component is N = NumSamplesPerColorComponent, +// total entries are NxNxN per component. Each value is represented by a 16-bit integer: +// Segment table: There are three components, table entries are uNumSegmentsPerColor per component, +// each entry is 32 bit value. +// +// Table data header: +// +--------- 32 bits ----------+------- 32 bits -----+ +// | NumSamplesPerColorComponent| NumSegmentsPerColor | +// +----------------------------+---------------------+ 8 bytes +// +// 3d table: +// +---- 16 bits ----+---- 16 bits ----+---- 16 bits ----+-------------+------- 16 bits -----------+ 8 +// | red_comp[0] | red_comp[1] | red_comp[2] | ... | red_comp[N x N x N - 1 ] | +// +-----------------+-----------------+-----------------+-------------+---------------------------+ NxNxNx2 + 8 +// | green_comp[0] | green_comp[1] | green_comp[2] | ... | green_comp[N x N x N - 1] | +// +-----------------+-----------------+-----------------+-------------+---------------------------+ 2xNxNxNx2 + 8 +// | blue_comp[0] | blue_comp[1] | blue_comp[2] | ... | blue_comp[N x N x N - 1] | +// +-----------------+-----------------+-----------------+-------------+---------------------------+ 3xNxNxNx2 + 8 +// +// Segment table: ( if NumSegmentsPerColor = 0, there is no segment table). +// +----- 32 bits ------+----- 32 bits ------+------ 32 bits -----+-------------+-------- 32 bits -------+ 3xNxNxNx2 + 8 +// | sg_red_comp[[0] | sg_red_comp[1] | sg_red_comp[2] | ... | sg_red_comp[N-2] | +// +--------------------+--------------------+--------------------+-------------+------------------------+ (N-1)x4 + 3xNxNxNx2 + 8 +// | sg_green_comp[0] | sg_ green_comp[1] | sg_ green_comp[2] | ... | sg_green_comp[N-2] | +// +--------------------+--------------------+--------------------+-------------+------------------------+ 2x(N-1)x4 + 3xNxNxNx2 + 8 +// | sg_ blue_comp[0] | sg_ blue_comp[1] | sg_ blue_comp[2] | ... | sg_ blue_comp[N-2] | +// +--------------------+--------------------+------------------- +-------------+------------------------+ 3x(N-1)x4 + 3xNxNxNx2 + 8 +// +// Maximum size = 3 x(17 - 1) x 4 + 3 x 17 x 17 x 17 x 2 + 8 = 29678 bytes. +// +Method (PWGM, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the WGM buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (TBUF, Buffer() {0x0} ) + + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(TBUF))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Arg1 - Data size + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(TBUF))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(TBUF), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBUF + CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + + // Return the packet data + Return(RBUF) +} + + + +// +// PGRT - panel gamma response table +// +// This method returns the Gamma response table for a panel. +// The table is given in 2 arrays, one representing the x axis or grayscale and other +// representing the y axis or luminance. +// +// The table is given in a 256 entries array, where the first entry value represents +// the luminance (Y) achieved when displaying black on the screen (shade value is 0 +// for all R, G and B) and the last entry represents the luminance (Y) achieved when +// displaying white on the screen (shade value is 255 for all R, G and B). +// +// The array must be 256 entries. +// +// The range of each entry must be from 0 to 0xffff +// +// Values are least significant byte first. E.g. {0x01, 0x00} represents 0x1 and +// {0x02, 0x01} represents 0x0102 +// +// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+ +// | Y[0] | Y[1] | Y[2] | ... | Y[255] | +// +---------------+---------------+---------------+-----------+---------------+ +Method (PGRT, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the GRT buffer and return the data + + // If nothing specified return NULL + + Name (RBUF, Buffer() {0x0}) + + // Return the packet data + Return(RBUF) +} + + +// +// PBRT - panel backlight response table +// +// This method returns the Backlight response table for a panel. +// The table is given in a 256 entries array, where the first entry value represents +// the backlight level (BL) to achieve 0 luminance and the last entry represents +// the highest backlight level to achieve the maximum desired luminance. +// In other words, this array serves as a map from luminance to backlight levels, +// where the index is the desired luminance level and the value (or output) is +// the backlight level to be sent to the hardware (backlight controller). +// +// The array must be 256 entries. +// +// The range of each entry must be from 0 to 0xffff +// +// Values are least significant byte first. E.g. {0x01, 0x00} represents 0x1 and +// {0x02, 0x01} represents 0x0102 +// +// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+ +// | BL[0] | BL[1] | BL[2] | ... | BL[255] | +// +---------------+---------------+---------------+-----------+---------------+ +Method (PBRT, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the BRT buffer and return the data + + // If nothing specified return NULL + + Name (RBUF, Buffer() {0x0}) + + // Return the packet data + Return(RBUF) +} + +// +// PBRC - panel backlight response curve for CABL +// +// This method returns the Backlight response curve for a panel used specifically for CABL algorithm. +// The curve is represented in a maximum 1024 x 2 elements array, where the first entry in each row +// will be backlight level and next entry will be correponding luminance value. In other words, +// this array serves as a map from backlight to luminance levels. + +// First row will be number of control points in the backlight curve. Maximum number of points allowed is 1024. +// Points on the backlight response curve has to be specified in increasing order i.e last control point will +// correspond for maximum backlight value and first control point will correspond for minimum backlight value. + +// The buffer must be of 4*(2*x + 1) bytes. where x < 1024 is number of control points. +// +// The range of each backlight or luminance value must be from 0 to 0xffff. ( 2 bytes each ) +// +// Values are least significant byte first. E.g. {0x01, 0x00} represents 0x1 and +// {0x02, 0x01} represents 0x0102. + +// Below is an example of Backlight Response curve consisting of 5 control points. + +// +----- 2 bytes -----------+----- 2 bytes ------+ +// | table_length | | +// +-------------------------+--------------------+ +// | BacklightLevel[0] | Luminance[0] | +// +-------------------------+--------------------+ +// | BacklightLevel[1] | Luminance[1] | +// +-------------------------+--------------------+ +// | BacklightLevel[2] | Luminance[2] | +// +-------------------------+--------------------+ +// | BacklightLevel[3] | Luminance[3] | +// +-------------------------+--------------------+ +// | BacklightLevel[4] | Luminance[4] | +// +-------------------------+--------------------+ +Method (PBRC, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the BRC buffer and return the data + + // If nothing specified return NULL + + Name (RBUF, Buffer() {0x00,0x00}) + + // Return the packet data + Return(RBUF) +} + +// +// DITH method - Dithering settings +// +// Dithering matrix could have following two formats: +// +// Format 1: +// +--1 byte--------+--1 byte--------+--1 byte--------+--1 byte--------+ +// | Element[0,0] | Element[0,1] | Element[0,2] | Element[0,3] | +// | Element[1,0] | Element[1,1] | Element[1,2] | Element[1,3] | +// | Element[2,0] | Element[2,1] | Element[2,2] | Element[2,3] | +// | Element[3,0] | Element[3,1] | Element[3,2] | Element[3,3] | +// | Bit Depth C2 | Bit Depth C1 | Bit Depth C0 | Reserved(0x0) | +// +----------------+----------------+----------------+----------------+ +// | Dithering mode (4 bytes) (0: not supported, 1:Spatial, 2:Temporal)| +// +----------------+----------------+----------------+----------------+ +// +// There is dithering mode in Format 1. +// +// Format 2: +// +// +--1 byte--------+--1 byte--------+--1 byte--------+--1 byte--------++ +// | Element[0,0] | Element[0,1] | Element[0,2] | Element[0,3] | +// | Element[1,0] | Element[1,1] | Element[1,2] | Element[1,3] | +// | Element[2,0] | Element[2,1] | Element[2,2] | Element[2,3] | +// | Element[3,0] | Element[3,1] | Element[3,2] | Element[3,3] | +// | Bit Depth C2 | Bit Depth C1 | Bit Depth C0 | Reserved(0x0) | +// +----------------+----------------+----------------+----------------+ +// +// There is no dithering mode in Format 2. Default dither mode: spatial. +// +Method (DITH, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the DITH buffer and return the data + + // If nothing specified return NULL + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Return the packet data + Return(RBUF) +} +// Include primary panel specific configuration for backlight control packets +// +Include("backlightcfg.asl") \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/display2.asl b/sdm845Pkg/AcpiTables/common/display2.asl new file mode 100644 index 0000000..d465fac --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/display2.asl @@ -0,0 +1,389 @@ +// +// This file contains the ACPI Extensions for Secondary Display Adapters +// + +// +// ROM2 Method - Used to retrieve proprietary ROM data for secondary panel +// +Method (ROM2, 3, NotSerialized) { + + // Include secondary panel specific ROM data + Include("panelcfg2.asl") + + //====================================================================================== + // Based on the panel Id(Arg2), store the buffer object into Local2 + // + // IMPORTANT: + // PCFG is buffer name for all default panel configurations + // All other dynamically detected panel configurations must not use this name + //====================================================================================== + Switch ( ToInteger (Arg2) ) + { + // Default case + Default { + Store (PCFG, Local2) + } + } + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(Local2))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(Local2))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(Local2), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBuf + CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + Return(RBUF) +} + +// +// IGC2 method - panel inverse gamma correction table. +// +// Secondary panel IGC2 configuration, format is same as IGCT of primary +// panel in display.asl +// +Method (IGC2, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the IGC buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Return the packet data + Return(RBUF) +} + + +// +// PCC2 method - panel color correction matrix +// Secondary panel PCC2 configuration, format is same as PPCC of primary +// panel in display.asl +// +Method (PCC2, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the PCC buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Return the packet data + Return(RBUF) +} + + +// +// GCT2 method - panel segment gamma correction table +// Secondary panel GCT2 configuration, format is same as PGCT of primary +// panel in display.asl +// +Method (GCT2, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the GCT buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Return the packet data + Return(RBUF) +} + + +// +// LGC2 method - panel linear gamma correction table +// Secondary panel LGC2 configuration, format is same as PLGC of primary +// panel in display.asl +// +Method (LGC2, 3, NotSerialized) { + + // Arg0 - Panel ID + // Arg1 - Data offset + // Arg2 - Data size + + // Based on the panel Id read the LGC buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (TBUF, Buffer() {0x0} ) + + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg1, Sizeof(TBUF))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg1, Local1) + } + + // Arg2 - Data size + // Ensure the size requested is less than 4k + If (LGreater(Arg2, 0x1000)) + { + Store(0x1000, Local2) + } + else + { + Store(Arg2, Local2) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local1, Local2), Sizeof(TBUF))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(TBUF), Local1, Local2); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBUF + CreateField(TBUF, Multiply(0x8, Local1), Multiply(0x8, Local2), RBUF) + + // Return the packet data + Return(RBUF) +} + + +// +// HSI2 method - HSIC settings +// Secondary panel HSI2 configuration, format is same as HSIC of primary +// panel in display.asl +// +Method (HSI2, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the HSIC buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Return the packet data + Return(RBUF) +} + + + +// +// GMT2 - panel gamut mapping table for HW which support 9x9x9 gamut mapping: +// Secondary panel GMT2 configuration, format is same as PGMT of primary +// panel in display.asl +// +Method (GMT2, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the GMT buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (TBUF, Buffer() {0x0} ) + + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(TBUF))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Arg1 - Data size + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(TBUF))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(TBUF), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBUF + CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + + // Return the packet data + Return(RBUF) +} + + + +// +// WGM2 - panel gamut mapping data for HW which support 17x17x17 gamut mapping +// Secondary panel WGM2 configuration, format is same as PWGM of primary +// panel in display.asl +// +Method (WGM2, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the WGM buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (TBUF, Buffer() {0x0} ) + + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(TBUF))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Arg1 - Data size + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(TBUF))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(TBUF), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBUF + CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + + // Return the packet data + Return(RBUF) +} + + + +// +// GRT2 - panel gamma response table +// Secondary panel GRT2 configuration, format is same as PGRT of primary +// panel in display.asl +// +Method (GRT2, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the GRT buffer and return the data + + // If nothing specified return NULL + + Name (RBUF, Buffer() {0x0}) + + // Return the packet data + Return(RBUF) +} + + +// +// BRT2 - panel backlight response table +// Secondary panel BRT2 configuration, format is same as PBRT of primary +// panel in display.asl +// +Method (BRT2, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the BRT buffer and return the data + + // If nothing specified return NULL + + Name (RBUF, Buffer() {0x0}) + + // Return the packet data + Return(RBUF) +} + +// +// DIT2 method - Dithering settings +// Secondary panel DIT2 configuration, format is same as DITH of primary +// panel in display.asl +// +Method (DIT2, 2, NotSerialized) { + // Arg0 - Panel ID + + // Arg1 - Data size + + // Based on the panel Id read the DITH buffer and return the data + + // If nothing specified return NULL + + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Return the packet data + Return(RBUF) +} +// Include secondary panel specific configuration for backlight control packets +// +Include("backlightcfg2.asl") \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/displayext.asl b/sdm845Pkg/AcpiTables/common/displayext.asl new file mode 100644 index 0000000..58406ba --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/displayext.asl @@ -0,0 +1,49 @@ +// +// This file contains the ACPI Extensions for External Display Adapters +// + +// +// ROE1 Method - Used to retrieve proprietary ROM data for External display +// +Method (ROE1, 3, NotSerialized) { + + // Include external panel specific ROM data + Include("panelcfgext.asl") + + // Store the panel configuration + Store (PCFG, Local2) + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(Local2))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(Local2))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(Local2), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBuf + CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + Return(RBUF) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/dsdt_common.asl b/sdm845Pkg/AcpiTables/common/dsdt_common.asl new file mode 100644 index 0000000..efccf71 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/dsdt_common.asl @@ -0,0 +1,187 @@ + +// To enable SOC revision based run time differentiation, uncomment following line +// and uncomment SSID method in ABD device. The original string is artificailly set as +// 16 characters, so there is enough room to hold SOC revision string. +// To adjust the number, the MAX_SOCID_LEN macro as defined in ABD device.h should be +// adjusted at the same time. + +Name(SOID, 0xffffffff) // Holds the Chip Id +Name(SIDS, "899800000000000") // Holds the Chip ID translated to a string +Name(SIDV, 0xffffffff) // Holds the Chip Version as (major<<16)|(minor&0xffff) +Name(SVMJ, 0xffff) // Holds the major Chip Version +Name(SVMI, 0xffff) // Holds the minor Chip Version +Name(SDFE, 0xffff) // Holds the Chip Family enum +Name(SFES, "899800000000000") // Holds the Chip Family translated to a string +Name(SIDM, 0xfffffffff) // Holds the Modem Support bit field +Name(SOSN, 0xaaaaaaaabbbbbbbb) +Name (RMTB, 0xaaaaaaaa) +Name (RMTX, 0xbbbbbbbb) +Name (RFMB, 0xcccccccc) +Name (RFMS, 0xdddddddd) +Name (RFAB, 0xeeeeeeee) +Name (RFAS, 0x77777777) +Name (TPMA, 0x11111111) // Holds whether TPM is seperate app or combined with Winsecapp +Name (TDTV, 0x6654504D) // Holds TPM type, by default it set to fTPM type +Name (TCMA, 0xDEADBEEF) // Holds TrEE Carveout Memory Address +Name (TCML, 0xBEEFDEAD) // Holds TrEE Carveout Memory Length +Name (SOSI, 0xdeadbeefffffffff) // Holds the base address of the SoCInfo shared memory region used by ChipInfoLib + +//Include("cust_dsdt_common.asl") + +//Audio Drivers +Include("audio.asl") + + // + // Storage - UFS/SD + // + Include("ufs.asl") + Include("sdc.asl") + + // + // ASL Bridge Device + // + Include("abd.asl") + + Name (ESNL, 20) // Exsoc name limit 20 characters + Name (DBFL, 23) // buffer Length, should be ESNL+3 + +// +// PMIC driver +// +Include("pmic_core.asl") + +// +// PMICTCC driver +// +Include("pmic_batt.asl") + + Include("pep.asl") + Include("bam.asl") + Include("buses.asl") + // MPROC Drivers (PIL Driver and Subsystem Drivers) + Include("win_mproc.asl") + Include("syscache.asl") + Include("HoyaSmmu.asl") + //Include("Ocmem.asl") + Include("graphics.asl") + //Include("OcmemTest.asl") + + Include("SCM.asl"); + + // + // SPMI driver + // + Include("spmi.asl") + + // + // TLMM controller. + // + Include("qcgpio.asl") + + Include("pcie.asl") + + Include("cbsp_mproc.asl") + +Include("adsprpc.asl") + + // + // RemoteFS + // + Include("rfs.asl") + + + // Test Drivers + Include("testdev.asl") + // + + // + // Qualcomm IPA + Include("ipa.asl") + + Include("gsi.asl") + + // +// Device (IPA) +// { +// // Indicates dependency on PEP +// Name (_DEP, Package () { \_SB_.PEP0 }) +// Name(_HID, "HID_IPA") +// Name (_UID, 0) +// } + + // + //Qualcomm DIAG Service + // + Device (QDIG) + { + Name (_DEP, Package(0x1) + { + \_SB_.GLNK + }) + Name (_HID, "HID_QDIG") + Alias(\_SB.PSUB, _SUB) + } + Include("qcdb.asl") + //Include("ssm.asl") + Include("Pep_lpi.asl") + + // + // QcRNG Driver (qcsecuremsm) + // + Device (QRNG) + { + Name (_DEP, Package(0x1) { + \_SB_.PEP0, + }) + Name (_HID, "HID_QRNG") + Name (_UID, 0) + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // PRNG_CFG_EE2_EE2_PRNG_SUB register address space + Memory32Fixed (ReadWrite, 0x00793000, 0x00001000) + }) + Return (RBUF) + } + } + + + // + // QCOM GPS + // + Include("gps.asl") + + // + // Qualcomm GPS driver + // + //Device (GPS) + //{ + // Name (_DEP, Package(0x1) + // { + // \_SB_.GLNK + // }) + // + // Name (_HID, "HID_GPS") + // Name (_CID, "ACPI\HID_GPS") + // Name (_UID, 0) + //} + +// Name (_HID, "QCOM_GPS") +// Name (_CID, "ACPI\QCOM_GPS") +// Name (_UID, 0) +// } + + // QDSS driver + Include("Qdss.asl") + +// QUPV3 GPI device node and resources +// +Include("qgpi.asl") + +Include("qwpp.asl") +//Include("nfc.asl") +// Disabling QCSP Changes +//Include("qcsp.asl") + +Include("sar_manager.asl") diff --git a/sdm845Pkg/AcpiTables/common/gps.asl b/sdm845Pkg/AcpiTables/common/gps.asl new file mode 100644 index 0000000..2a21ced --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/gps.asl @@ -0,0 +1,20 @@ +// +// This file contains the GPS ACPI device definitions. +// + + // + // Qualcomm GPS driver + // + Device (GPS) + { + Name (_DEP, Package(0x1) + { + \_SB_.GLNK + }) + + Name (_HID, "HID_GPS") + Alias(\_SB.PSUB, _SUB) + Name (_CID, "ACPI\QCOM24B4") + Name (_UID, 0) + } + diff --git a/sdm845Pkg/AcpiTables/common/gsi.asl b/sdm845Pkg/AcpiTables/common/gsi.asl new file mode 100644 index 0000000..aeb25da --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/gsi.asl @@ -0,0 +1,35 @@ +// +// This file contains the Generic Software Interface(GSI) +// ACPI device definitions. +// GSI is the interface used by IPA driver to talk to IPA HW and is intended +// as a replacement for BAM. +// + +// +// Device Map: +// GSI +// +// List of Devices + + +Device (GSI) +{ + // Indicates dependency on PEP + Name (_DEP, Package () { \_SB_.PEP0 }) + + Name(_HID, "HID_GSI") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // GSI_PHYSICAL_ADDRESS, GSI_MEM_SIZE + Memory32Fixed (ReadWrite, 0x1E00000, 0x30000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {464} + }) + Return (RBUF) + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/ipa.asl b/sdm845Pkg/AcpiTables/common/ipa.asl new file mode 100644 index 0000000..bf90a4b --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/ipa.asl @@ -0,0 +1,44 @@ +// +// This file contains the Bus Access Modules (BAM) +// ACPI device definitions and pipe configurations +// + +// +// Device Map: +// IPA +// +// List of Devices + + +Device (IPA) +{ + // Indicates dependency on PEP, RPE, SMEM, PIL, SMMU, GSI and GLINK + Name (_DEP, Package(0x6) + { + \_SB_.PEP0, + \_SB_.RPEN, + \_SB_.PILC, + \_SB_.MMU0, + \_SB_.GSI, + \_SB_.GLNK, + }) + + Name(_HID, "HID_IPA") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Return + ( + ResourceTemplate () + { + // IPA_PHYSICAL_ADDRESS, IPA_MEM_SIZE + Memory32Fixed (ReadWrite, 0x1E40000, 0x1FFFF) + + // IPA Interrupt for uC communication + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {343} + } + ) + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/ipa_resources.asl b/sdm845Pkg/AcpiTables/common/ipa_resources.asl new file mode 100644 index 0000000..99e72a7 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/ipa_resources.asl @@ -0,0 +1,74 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by ipa driver. +// +//=========================================================================== + +//=========================================================================== +// Implementation of function states for IPA driver. +// Present implementation has two function states F0 and F1. +// +// F0 = Full power mode. +// F1 = Low power mode. +// +// Resource being managed is /clk/ipa +//=========================================================================== + +Scope(\_SB.PEP0) +{ + Method(IPMD){ + Return(IPSC) + } + + Name(IPSC, + Package() + { + Package() + { + "DEVICE", + "\\_SB.IPA", + Package() + { + "COMPONENT", + 0x0, + Package() + { + "FSTATE", + 0x0, + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_IPA_CORE", // Master + "ICBID_SLAVE_IPA_CORE", // Slave + 37400, // IB= KHz ( map 37500 KHz needs to mapped to IB value ) + 0, // AB + "HLOS_DRV", // Optional: DRV Id + }, + }, + }, + Package() + { + "FSTATE", + 0x1, + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_IPA_CORE", // Master + "ICBID_SLAVE_IPA_CORE", // Slave + 0, // IB + 0, // AB + "HLOS_DRV", // Optional: DRV Id + }, + }, + }, + }, + }, + }) +} diff --git a/sdm845Pkg/AcpiTables/common/msft_resources.asl b/sdm845Pkg/AcpiTables/common/msft_resources.asl new file mode 100644 index 0000000..1e13490 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/msft_resources.asl @@ -0,0 +1,25 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by microsoft drivers. +// +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + + // MICROSOFT + + Method(MPMD) + { + Return(MPCC) + } + + + Name(MPCC, + Package () + { + }) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/nfc.asl b/sdm845Pkg/AcpiTables/common/nfc.asl new file mode 100644 index 0000000..46a117b --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/nfc.asl @@ -0,0 +1,174 @@ +// + +// +// NFC entry. +// +Device(NFCD) +{ + Name(_HID, "NXP1001") + Name(_CID, "ACPI\NXP1001") + Alias(\_SB.PSUB, _SUB) + Name(_CRS, ResourceTemplate() + { + I2CSerialBus(0x28, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.I2C4", 0, ResourceConsumer, , ) + GpioInt(Level, ActiveHigh, Exclusive, PullDefault, 0, "\\_SB.GIO0", 0, ResourceConsumer, , ) {63} + }) +// ESE SPI GPIO + Name(NFCS, ResourceTemplate() + { + GpioIO(Exclusive, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , ) {116} + }) +// NFCC VEN GPIO + Name(NFCP, ResourceTemplate() + { + GpioIO(Exclusive, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , ) {12} + }) + Scope(GIO0) + { + OperationRegion(NFPO, GeneralPurposeIO, Zero, One) + } + Field(\_SB_.GIO0.NFPO, ByteAcc, NoLock, Preserve) + { + Connection(\_SB_.NFCD.NFCP), + MGPE, 1 + } + Method(POON, 0x0, NotSerialized) + { + Store(One, MGPE) + } + Method(POOF, 0x0, NotSerialized) + { + Store(Zero, MGPE) + } +//NFCC FW DOWNLOAD GPIO + Name(NFCF, ResourceTemplate() + { + GpioIO(Exclusive, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , ) {62} // Download + }) + Scope(GIO0) + { + OperationRegion(NFFO, GeneralPurposeIO, Zero, One) + } + Field(\_SB_.GIO0.NFFO, ByteAcc, NoLock, Preserve) + { + Connection(\_SB_.NFCD.NFCF), + MGFE, 1 + } + Method(FWON, 0x0, NotSerialized) + { + Store(One, MGFE) + } + Method(FWOF, 0x0, NotSerialized) + { + Store(Zero, MGFE) + } + Method(_DSM, 0x4, NotSerialized) + { + Store("Method NFC _DSM begin", Debug) + If(LEqual(Arg0, Buffer(0x10) + { + 0xc4, 0xf6, 0xe7, 0xa2, 0x38, 0x96, 0x85, 0x44, 0x9f, 0x12, 0x6b, 0x4e, + 0x20, 0xb6, 0x0d, 0x63 + })) + { + If(LEqual(Arg2, Zero)) + { + Store("Method NFC _DSM QUERY", Debug) + If(LEqual(Arg1, One)) + { + \_SB_.NFCD.POOF() + Sleep(0x14) + Return(Buffer(One) + { + 0x0f + }) + } + } + If(LEqual(Arg2, 0x2)) + { + Store("Method NFC _DSM SETPOWERMODE", Debug) + If(LEqual(Arg3, One)) + { + \_SB_.NFCD.POON() + Sleep(0x14) + } + If(LEqual(Arg3, Zero)) + { + \_SB_.NFCD.POOF() + Sleep(0x14) + } + } + If(LEqual(Arg2, One)) + { + Store("Method NFC _DSM SETFWMODE", Debug) +// +// Set the firmware mode to ON. +// + If(LEqual(Arg3, One)) + { + \_SB_.NFCD.FWON() +// +// Provide any delay required by the controller before toggling the power GPIO line. +// + Sleep(0x14) + \_SB_.NFCD.POOF() + Sleep(0x14) + \_SB_.NFCD.POON() + Sleep(0x14) + } +// +// Set the firmware mode to OFF. +// + If(LEqual(Arg3, Zero)) + { + \_SB_.NFCD.FWOF() + Sleep(0x14) + \_SB_.NFCD.POOF() + Sleep(0x14) + \_SB_.NFCD.POON() + Sleep(0x14) + } + } + If(LEqual(Arg2, 0x3)) + { + Store("Method NFC _DSM EEPROM Config", Debug) + Return(Buffer(0x13) + { + 0x9c, 0x1f, 0x38, 0x19, 0xa8, 0xb9, 0x4b, 0xab, 0xa1, 0xba, 0xd0, 0x20, + 0x76, 0x88, 0x2a, 0xe0, 0x03, 0x01, 0x11 + }) + } + } + } +//PEP Proxy Support + Name(PGID, Buffer(10) {"\\_SB.NFCD"}) // Device ID buffer - PGID( Pep given ID ) + Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID( Pep given ID ) + CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE + // HIDDEN 1 BYTE ( SIZE ) + CreateByteField(DBUF, 2, DVAL ) // Packet value, 1 BYTES Device Status + CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES(160 Bits) + Method (_S1D, 0) { Return (3) } // S1 => D3 + Method (_S2D, 0) { Return (3) } // S2 => D3 + Method (_S3D, 0) { Return (3) } // S3 => D3 + + Method(_PS0, 0x0, NotSerialized) + { + Store(Buffer(ESNL){}, DEID) + Store(0, DVAL) + Store(PGID, DEID) + If(\_SB.ABD.AVBL) + { + Store(DBUF, \_SB.PEP0.FLD0) + } + } + Method(_PS3, 0x0, NotSerialized) + { + Store(Buffer(ESNL){}, DEID) + Store(3, DVAL) + Store(PGID, DEID) + If(\_SB.ABD.AVBL) + { + Store(DBUF, \_SB.PEP0.FLD0) + } + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/oem_resources.asl b/sdm845Pkg/AcpiTables/common/oem_resources.asl new file mode 100644 index 0000000..db1f209 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/oem_resources.asl @@ -0,0 +1,25 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by oem drivers. +// +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + + // OEM + Method(OPMD) + { + Return(OPCC) + } + + + Name(OPCC, + Package () + { + }) + +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/pcie.asl b/sdm845Pkg/AcpiTables/common/pcie.asl new file mode 100644 index 0000000..e7b922c --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pcie.asl @@ -0,0 +1,995 @@ +//PCIE asl + +// Unused Memory range +OperationRegion(CP00, SystemMemory, 0x13000000, 0x24) +Field(CP00, DWordAcc, NoLock, Preserve){ + MVIO, 32, //0x00 Address to cause Memory violation + MV01, 32, //0x04 Address to cause Memory violation + MV02, 32, //0x08 Address to cause Memory violation + MV03, 32, //0x0C Address to cause Memory violation + MV04, 32, //0x10 Address to cause Memory violation + MV11, 32, //0x14 Address to cause Memory violation + MV12, 32, //0x18 Address to cause Memory violation + MV13, 32, //0x1C Address to cause Memory violation + MV14, 32, //0x20 Address to cause Memory violation +} + +// PCIE_0_PCIE20_PARF +OperationRegion(CP01, SystemMemory, 0x01C00000, 0x1004) +Field(CP01, DWordAcc, NoLock, Preserve){ + PSC0, 32, //0x00 PCIE_0_PCIE20_PARF_SYS_CTRL + Offset(0x20), + PPC0, 32, //0x20 PCIE_0_PCIE20_PARF_PM_CTRL + PPS0, 32, //0x24 PCIE_0_PCIE20_PARF_PM_STTS + Offset(0x1b0), + PLT0, 32, //0x1b0 PCIE_0_PCIE20_PARF_LTSSM + Offset(0x358), + PSL0, 32, //0x358 PCIE20_PARF_SLV_ADDR_SPACE_SIZE + Offset(0x360), + WBL0, 32, //0x360 PCIE20_PARF_BLOCK_SLV_AXI_WR_BASE + WBH0, 32, //0x364 PCIE20_PARF_BLOCK_SLV_AXI_WR_BASE_HI + WLL0, 32, //0x368 PCIE20_PARF_BLOCK_SLV_AXI_WR_LIMIT + WLH0, 32, //0x36C PCIE20_PARF_BLOCK_SLV_AXI_WR_LIMIT_HI + RBL0, 32, //0x370 PCIE20_PARF_BLOCK_SLV_AXI_RD_BASE + RBH0, 32, //0x374 PCIE20_PARF_BLOCK_SLV_AXI_RD_BASE_HI + RLL0, 32, //0x378 PCIE20_PARF_BLOCK_SLV_AXI_RD_LIMIT + RLH0, 32, //0x37C PCIE20_PARF_BLOCK_SLV_AXI_RD_LIMIT_HI + PPEB, 32, //0x380 PCIE_0_PCIE20_PARF_ECAM_BASE + Offset(0x398), + WBL1, 32, //0x398 PCIE20_PARF_BLOCK_SLV_AXI_WR_BASE_2 + WBH1, 32, //0x39C PCIE20_PARF_BLOCK_SLV_AXI_WR_BASE_2_HI + WLL1, 32, //0x3A0 PCIE20_PARF_BLOCK_SLV_AXI_WR_LIMIT_2 + WLH1, 32, //0x3A4 PCIE20_PARF_BLOCK_SLV_AXI_WR_LIMIT_2_HI + RBL1, 32, //0x3A8 PCIE20_PARF_BLOCK_SLV_AXI_RD_BASE_2 + RBH1, 32, //0x3AC PCIE20_PARF_BLOCK_SLV_AXI_RD_BASE_2_HI + RLL1, 32, //0x3B0 PCIE20_PARF_BLOCK_SLV_AXI_RD_LIMIT_2 + RLH1, 32, //0x3B4 PCIE20_PARF_BLOCK_SLV_AXI_RD_LIMIT_2_HI + Offset(0x1000), + PDT0, 32, //0x1000 PCIE_0_PCIE20_PARF_DEVICE_TYPE +} + +// PCIE_0_QSERDES_COM_QSERDES_COM_PCIE_USB3_QMP_PLL +OperationRegion(CP02, SystemMemory, 0x01C06000, 0x188) +Field(CP02, DWordAcc, NoLock, Preserve){ + Offset (0x00C), + QCB1, 32, //0x00C QSERDES_COM_BG_TIMER + QSEC, 32, //0x010 QSERDES_COM_SSC_EN_CENTER + QAP1, 32, //0x014 QSERDES_COM_SSC_ADJ_PER1 + QAP2, 32, //0x018 QSERDES_COM_SSC_ADJ_PER2 + QSP1, 32, //0x01C QSERDES_COM_SSC_PER1 + QSP2, 32, //0x020 QSERDES_COM_SSC_PER2 + QSS1, 32, //0x024 QSERDES_COM_SSC_STEP_SIZE1 + QSS2, 32, //0x028 QSERDES_COM_SSC_STEP_SIZE2 + Offset (0x034), + QECE, 32, //0x034 QSERDES_COM_BIAS_EN_CLKBUFLR_EN + QCE1, 32, //0x038 QSERDES_COM_CLK_ENABLE1 + QSCC, 32, //0x03C QSERDES_COM_SYS_CLK_CTRL + QSBE, 32, //0x40 QSERDES_COM_SYSCLK_BUF_ENABLE + Offset (0x048), + QCPI, 32, //0x048 QSERDES_COM_PLL_IVCO + Offset (0x05C), + QCED, 32, //0x05C QSERDES_COM_CLK_EP_DIV + QCP0, 32, //0x060 QSERDES_COM_CP_CTRL_MODE0 + Offset (0x068), + QPR0, 32, //0x068 QSERDES_COM_PLL_RCTRL_MODE0 + Offset (0x070), + QPC0, 32, //0x070 QSERDES_COM_PLL_CCTRL_MODE0 + Offset (0x080), + QSES, 32, //0x080 QSERDES_COM_SYSCLK_EN_SEL + Offset (0x088), + QCRC, 32, //0x088 QSERDES_COM_RESETSM_CNTRL + Offset (0x090), + QCLC, 32, //0x090 QSERDES_COM_LOCK_CMP_EN + Offset (0x098), + QC1M, 32, //0x098 QSERDES_COM_LOCK_CMP1_MODE0 + QC2M, 32, //0x09C QSERDES_COM_LOCK_CMP2_MODE0 + QC3M, 32, //0x0A0 QSERDES_COM_LOCK_CMP3_MODE0 + Offset (0x0B0), + QSM0, 32, //0x0B0 QSERDES_COM_DEC_START_MODE0 + Offset (0x0B8), + QS1M, 32, //0x0B8 QSERDES_COM_DIV_FRAC_START1_MODE0 + QS2M, 32, //0x0BC QSERDES_COM_DIV_FRAC_START2_MODE0 + QS3M, 32, //0x0C0 QSERDES_COM_DIV_FRAC_START3_MODE0 + Offset (0x0D8), + QIG0, 32, //0x0D8 QSERDES_COM_INTEGLOOP_GAIN0_MODE0 + QIG1, 32, //0x0DC QSERDES_COM_INTEGLOOP_GAIN1_MODE0 + Offset (0x0F0), + QCVT, 32, //0x0F0 QSERDES_COM_VCO_TUNE_MAP + QVT1, 32, //0x0F4 QSERDES_COM_VCO_TUNE1_MODE0 + QVT2, 32, //0x0F8 QSERDES_COM_VCO_TUNE2_MODE0 + Offset (0x11C), + QTT1, 32, //0x11C QSERDES_COM_VCO_TUNE_TIMER1 + QTT2, 32, //0x120 QSERDES_COM_VCO_TUNE_TIMER2 + Offset (0x138), + QCCS, 32, //0x138 QSERDES_COM_CLK_SELECT + QCHS, 32, //0x13C QSERDES_COM_HSCLK_SEL + Offset (0x148), + QCD0, 32, //0x148 QSERDES_COM_CORECLK_DIV_MODE0 + Offset (0x154), + QCCN, 32, //0x154 QSERDES_COM_CORE_CLK_EN + Offset (0x15C), + QCCC, 32, //0x15C QSERDES_COM_CMN_CONFIG + Offset (0x164), + QMCS, 32, //0x164 QSERDES_COM_SVS_MODE_CLK_SEL + Offset (0x184), + QCCM, 32, //0x184 QSERDES_COM_CMN_MODE +} + +// PCIE_0_QSERDES_TX_QSERDES_TX_PCIE_USB3_QMP_TX +OperationRegion(CP03, SystemMemory, 0x01C06200, 0xA8) +Field(CP03, DWordAcc, NoLock, Preserve){ + Offset (0x044), + QTOT, 32, //0x044 QSERDES_TX_RES_CODE_LANE_OFFSET_TX + Offset (0x060), + QTDE, 32, //0x060 QSERDES_TX_HIGHZ_DRVR_EN + Offset (0x08C), + QTM1, 32, //0x08C QSERDES_TX_LANE_MODE_1 + Offset (0x0A4), + QTL2, 32, //0x0A4 QSERDES_TX_RCV_DETECT_LVL_2 +} + +// PCIE_0_QSERDES_RX_QSERDES_RX_PCIE_USB3_QMP_RX +OperationRegion(CP04, SystemMemory, 0x01C06400, 0x16C) +Field(CP04, DWordAcc, NoLock, Preserve){ + Offset (0x00C), + QRSH, 32, //0x00C QSERDES_RX_UCDR_SO_GAIN_HALF + Offset (0x014), + QRSG, 32, //0x014 QSERDES_RX_UCDR_SO_GAIN + Offset (0x034), + QRUS, 32, //0x034 QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE + Offset (0x03C), + QRFL, 32, //0x03C QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW + Offset (0x044), + QRPC, 32, //0x044 QSERDES_RX_UCDR_PI_CONTROLS + Offset (0x0D4), + QRC2, 32, //0x0D4 QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 + QRC3, 32, //0x0D8 QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 + QRC4, 32, //0x0DC QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 + Offset (0x0F8), + QRA1, 32, //0x0F8 QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 + QRA2, 32, //0x0FC QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 + Offset (0x100), + QRSE, 32, //0x100 QSERDES_RX_SIGDET_ENABLES + QRSC, 32, //0x104 QSERDES_RX_SIGDET_CNTRL + Offset (0x10C), + QRDC, 32, //0x10C QSERDES_RX_SIGDET_DEGLITCH_CNTRL + Offset (0x11C), + QRIM, 32, //0x11C QSERDES_RX_RX_INTERFACE_MODE + Offset (0x164), + QRM0, 32, //0x164 QSERDES_RX_RX_MODE_00 + QRM1, 32, //0x168 QSERDES_RX_RX_MODE_01 +} + +// PCIE_0_PCIE_USB3_PCS_MISC_PCIE_USB3_PCS_MISC_PCIE_USB3_PCS_MISC +OperationRegion(CP05, SystemMemory, 0x01C06600, 0x70) +Field(CP05, DWordAcc, NoLock, Preserve){ + Offset (0x02C), + PMDC, 32, //0x02C PCIE_PCS_MISC_OSC_DTCT_CONFIG2 + Offset (0x044), + PAC1, 32, //0x044 PCIE_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 + Offset (0x054), + PMC2, 32, //0x054 PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 + PMC3, 32, //0x058 PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG3 + PMC4, 32, //0x05C PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 + PMC5, 32, //0x060 PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 +} + +// PCIE_0_PCIE_USB3_PCS_PCIE_USB3_PCS_PCIE_USB3_PCS +OperationRegion(CP06, SystemMemory, 0x01C06800, 0x210) +Field(CP06, DWordAcc, NoLock, Preserve){ + PPSR, 32, //0x000 PCIE_PCS_SW_RESET + PPDC, 32, //0x004 PCIE_PCS_POWER_DOWN_CONTROL + PCST, 32, //0x008 PCIE_PCS_START_CONTROL + Offset (0x054), + PERD, 32, //0x054 PCIE_PCS_ENDPOINT_REFCLK_DRIVE + Offset (0x06C), + PSC4, 32, //0x06C PCIE_PCS_POWER_STATE_CONFIG4 + Offset (0x0A0), + PDTA, 32, //0x0A0 PCIE_PCS_PWRUP_RESET_DLY_TIME_AUXCLK + PLTA, 32, //0x0A4 PCIE_PCS_LP_WAKEUP_DLY_TIME_AUXCLK + PLCD, 32, //0x0A8 PCIE_PCS_PLL_LOCK_CHK_DLY_TIME + Offset (0x0C4), + PFC1, 32, //0x0C4 PCIE_PCS_FLL_CNTRL1 + PFC2, 32, //0x0C8 PCIE_PCS_FLL_CNTRL2 + PFVL, 32, //0x0CC PCIE_PCS_FLL_CNT_VAL_L + PFVH, 32, //0x0D0 PCIE_PCS_FLL_CNT_VAL_H_TOL + PFMC, 32, //0x0D4 PCIE_PCS_FLL_MAN_CODE + Offset (0x174), + PPPS, 32, //0x174 PCIE_PCS_PCS_STATUS + Offset (0x1A8), + PSDM, 32, //0x1A8 PCIE_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB + PODA, 32, //0x1AC PCIE_PCS_OSC_DTCT_ACTIONS + PPSC, 32, //0x1B0 PCIE_PCS_SIGDET_CNTRL + Offset (0x1D8), + PRSL, 32, //0x1D8 PCIE_PCS_RX_SIGDET_LVL + PDAL, 32, //0x1DC PCIE_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB + PDAM, 32, //0x1E0 PCIE_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB + Offset (0x20C), + PRC1, 32, //0x20C PCIE_PCS_REFGEN_REQ_CONFIG1 +} + +// PCIE_0_PCIE20_DBI +OperationRegion(CP07, SystemMemory, 0x60000000, 0x1000) +Field(CP07, DWordAcc, NoLock, Preserve){ + Offset(0x4), + SCR0, 32, //0x04 STATUS_COMMAND_REG + CRI0, 32, //0x08 TYPE1_CLASS_CODE_REV_ID_REG + Offset(0x10), + R0B0, 32, //0x10 PCIE_0_BAR0_REG + R0B1, 32, //0x14 PCIE_0_BAR1_REG + BNR0, 32, //0x18 PCIE_0_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG + Offset(0x7C), + LCA0, 32, //0x7C PCIE_0_LINK_CAPABILITIES_REG + LCS0, 32, //0x80 PCIE_0_LINK_CONTROL_LINK_STATUS_REG + Offset(0x88), + SLC0, 32, //0x88 SLOT_CAS + Offset(0xa0), + LC20, 32, //0xa0 PCIE_0_LINK_CONTROL2_LINK_STATUS2_REG + Offset(0x8bc), + CSW0, 32, // 0x8bc CS Write Access register + Offset(0x900), + IAV0, 32, //0x900 PCIE_0_IATU_VIEWPORT_REG + CR10, 32, //0x904 PCIE_0_PL_IATU_REGION_CTRL_REG_1_OUTBOUND_0 + CR20, 32, //0x908 PCIE_0_PL_IATU_REGION_CTRL_REG_2_OUTBOUND_0 + ILB0, 32, //0x90C PCIE_0_PL_IATU_LWR_BASE_ADDR_REG_OUTBOUND_0 + IUB0, 32, //0x910 PCIE_0_PL_IATU_UPPER_BASE_ADDR_REG_OUTBOUND_0 + ILR0, 32, //0x914 PCIE_0_PL_IATU_LIMIT_ADDR_REG_OUTBOUND_0 + ILT0, 32, //0x918 PCIE_0_PL_IATU_LWR_TARGET_ADDR_REG_OUTBOUND_0 + IUT0, 32, //0x91C PCIE_0_PL_IATU_UPPER_TARGET_ADDR_REG_OUTBOUND_0 + Offset(0xF24), + ESC0, 32, //0xF24 PCIE_0_PCIE20_ELBI_SYS_CTRL + EST0, 32, //0xF28 PCIE_0_PCIE20_ELBI_SYS_STTS + Offset(0xFC4), + ECS0, 32, //0xFC4 PCIE_0_PCIE20_ELBI_CS2_ENABLE +} + +// Setup PHY +Method(PPU0, 0x0, Serialized) { + Name(TOUT, Zero) + Store (0x04, PDT0) // PCIE20_PARF_DEVICE_TYPE + Store (0x01, PPDC) // PCIE_PCS_POWER_DOWN_CONTROL + Store (0x14, QECE) // QSERDES_COM_BIAS_EN_CLKBUFLR_EN + Store (0x30, QCCS) // QSERDES_COM_CLK_SELECT + Store (0x07, QCPI) // QSERDES_COM_PLL_IVCO + Store (0x06, QCCC) // QSERDES_COM_CMN_CONFIG + Store (0x01, QCLC) // QSERDES_COM_LOCK_CMP_EN + Store (0x20, QCRC) // QSERDES_COM_RESETSM_CNTRL + Store (0x00, QCVT) // QSERDES_COM_VCO_TUNE_MAP + Store (0x01, QVT2) // QSERDES_COM_VCO_TUNE2_MODE0 + Store (0xC9, QVT1) // QSERDES_COM_VCO_TUNE1_MODE0 + Store (0xFF, QTT1) // QSERDES_COM_VCO_TUNE_TIMER1 + Store (0x3F, QTT2) // QSERDES_COM_VCO_TUNE_TIMER2 + Store (0x01, QMCS) // QSERDES_COM_SVS_MODE_CLK_SEL + Store (0x00, QCCN) // QSERDES_COM_CORE_CLK_EN + Store (0x0A, QCD0) // QSERDES_COM_CORECLK_DIV_MODE0 + Store (0x19, QCED) // QSERDES_COM_CLK_EP_DIV + Store (0x90, QCE1) // QSERDES_COM_CLK_ENABLE1 + Store (0x82, QSM0) // QSERDES_COM_DEC_START_MODE0 + Store (0x02, QS3M) // QSERDES_COM_DIV_FRAC_START3_MODE0 + Store (0xEA, QS2M) // QSERDES_COM_DIV_FRAC_START2_MODE0 + Store (0xAB, QS1M) // QSERDES_COM_DIV_FRAC_START1_MODE0 + Store (0x00, QC3M) // QSERDES_COM_LOCK_CMP3_MODE0 + Store (0x0D, QC2M) // QSERDES_COM_LOCK_CMP2_MODE0 + Store (0x04, QC1M) // QSERDES_COM_LOCK_CMP1_MODE0 + Store (0x00, QCHS) // QSERDES_COM_HSCLK_SEL + Store (0x06, QCP0) // QSERDES_COM_CP_CTRL_MODE0 + Store (0x16, QPR0) // QSERDES_COM_PLL_RCTRL_MODE0 + Store (0x36, QPC0) // QSERDES_COM_PLL_CCTRL_MODE0 + Store (0x01, QCCM) // QSERDES_COM_CMN_MODE + Store (0x02, QSCC) // QSERDES_COM_SYS_CLK_CTRL + Store (0x06, QSBE) // QSERDES_COM_SYSCLK_BUF_ENABLE + Store (0x04, QSES) // QSERDES_COM_SYSCLK_EN_SEL + Store (0x00, QIG1) // QSERDES_COM_INTEGLOOP_GAIN1_MODE0 + Store (0x3F, QIG0) // QSERDES_COM_INTEGLOOP_GAIN0_MODE0 + Store (0x09, QCB1) // QSERDES_COM_BG_TIMER + Store (0x01, QSEC) // QSERDES_COM_SSC_EN_CENTER + Store (0x40, QSP1) // QSERDES_COM_SSC_PER1 + Store (0x01, QSP2) // QSERDES_COM_SSC_PER2 + Store (0x02, QAP1) // QSERDES_COM_SSC_ADJ_PER1 + Store (0x00, QAP2) // QSERDES_COM_SSC_ADJ_PER2 + Store (0x7E, QSS1) // QSERDES_COM_SSC_STEP_SIZE1 + Store (0x15, QSS2) // QSERDES_COM_SSC_STEP_SIZE2 + Store (0x02, QTOT) // QSERDES_TX_RES_CODE_LANE_OFFSET_TX + Store (0x12, QTL2) // QSERDES_TX_RCV_DETECT_LVL_2 + Store (0x10, QTDE) // QSERDES_TX_HIGHZ_DRVR_EN + Store (0x06, QTM1) // QSERDES_TX_LANE_MODE_1 + Store (0x03, QRSC) // QSERDES_RX_SIGDET_CNTRL + Store (0x10, QRSE) // QSERDES_RX_SIGDET_ENABLES + Store (0x14, QRDC) // QSERDES_RX_SIGDET_DEGLITCH_CNTRL + Store (0x0E, QRC2) // QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 + Store (0x04, QRC3) // QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 + Store (0x1A, QRC4) // QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 + Store (0x4B, QRUS) // QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE + Store (0x04, QRSG) // QSERDES_RX_UCDR_SO_GAIN + Store (0x04, QRSH) // QSERDES_RX_UCDR_SO_GAIN_HALF + Store (0x71, QRA1) // QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 + Store (0x59, QRM0) // QSERDES_RX_RX_MODE_00 + Store (0x59, QRM1) // QSERDES_RX_RX_MODE_01 + Store (0x80, QRA2) // QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 + Store (0x40, QRIM) // QSERDES_RX_RX_INTERFACE_MODE + Store (0x71, QRPC) // QSERDES_RX_UCDR_PI_CONTROLS + Store (0x40, QRFL) // QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW + Store (0x04, PERD) // PCIE_PCS_ENDPOINT_REFCLK_DRIVE + Store (0x52, PMDC) // PCIE_PCS_MISC_OSC_DTCT_CONFIG2 + Store (0x10, PMC2) // PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 + Store (0x1A, PMC4) // PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 + Store (0x06, PMC5) // PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 + Store (0x83, PFC2) // PCIE_PCS_FLL_CNTRL2 + Store (0x09, PFVL) // PCIE_PCS_FLL_CNT_VAL_L + Store (0xA2, PFVH) // PCIE_PCS_FLL_CNT_VAL_H_TOL + Store (0x40, PFMC) // PCIE_PCS_FLL_MAN_CODE + Store (0x02, PFC1) // PCIE_PCS_FLL_CNTRL1 + Store (0x00, PODA) // PCIE_PCS_OSC_DTCT_ACTIONS + Store (0x01, PDTA) // PCIE_PCS_PWRUP_RESET_DLY_TIME_AUXCLK + Store (0x00, PDAM) // PCIE_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB + Store (0x20, PDAL) // PCIE_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB + Store (0x00, PSDM) // PCIE_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB + Store (0x01, PLTA) // PCIE_PCS_LP_WAKEUP_DLY_TIME_AUXCLK + Store (0x73, PLCD) // PCIE_PCS_PLL_LOCK_CHK_DLY_TIME + Store (0xBB, PRSL) // PCIE_PCS_RX_SIGDET_LVL + Store (0x03, PPSC) // PCIE_PCS_SIGDET_CNTRL + Store (0x0D, PRC1) // PCIE_PCS_REFGEN_REQ_CONFIG1 + Store (0x00, PSC4) // PCIE_PCS_POWER_STATE_CONFIG4 + Store (0x00, PAC1) // PCIE_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 + + // Version 2 and Higher Changes + If (LGreaterEqual (\_SB.SIDV,0x00020000)) + { + //V1 and V2 PHY settings are same for PCI0 + } + + Store (0x03, PPDC) // PCIE_PCS_POWER_DOWN_CONTROL + Store (0x00, PPSR) // PCIE_PCS_SW_RESET + Store (0x03, PCST) // PCIE_PCS_START_CONTROL + + Store (PPPS, Local0) // PCIE_PCS_PCS_STATUS + // loop until HWIO_PCIE_PCS_PCS_STATUS_PHYSTATUS_BMSK is '0' + While(And (Local0 , 0x40)) + { + Sleep(1) + Increment(TOUT) + If (LEqual(TOUT, 0xF)) + { + Break + } + Store (PPPS, Local0) + } + + If(LEqual(TOUT, 0xF)) + { + //Timeout occurred after 15 ms, so return an error value + Return(One) + } + Else + { + // PHY Init success + Return(Zero) + } +} + +// Setup Link +Method(LTS0, 0x0, Serialized) { + Name(TOUT, Zero) + Store(LC20, Local0) ////PCIE_0_LINK_CONTROL2_LINK_STATUS2_REG + OR(Local0, 0x40, Local0) //set 3.5dB transmitter de-emphassis + Store(Local0, LC20) + Store (0x100, PLT0)// PCIE_0_PCIE20_PARF_PCIE20_PARF_LTSSM = 0x100 + Store (EST0, Local0)// PCIE20_ELBI_SYS_STTS + While(LNotEqual(And(Local0 , 0x400), 0x400))// check for HWIO_PCIE20_ELBI_SYS_STTS_XMLH_LINK_UP_BMSK + { + Sleep(1) + Increment(TOUT) + If (LEqual(TOUT, 0x96)) + { + Break + } + Store (EST0, Local0) + } + + If(LEqual(TOUT, 0x96)) + { + //Timeout occurred after 150 ms, so return an error value + Return(One) + } + Else + { + // LTSSM success + Return(Zero) + } +} + +// Setup iATU +Method(IAT0, 0x0, Serialized) { + Store (0x01, IAV0)// IATU_VIEWPORT_REG + Store (0x60100000, ILB0)// PL_IATU_LWR_BASE_ADDR_REG_OUTBOUND_0 + Store (0x00, IUB0)// PL_IATU_UPPER_BASE_ADDR_REG_OUTBOUND_0 + Store (0x601FFFFF, ILR0)// PL_IATU_LIMIT_ADDR_REG_OUTBOUND_0 + Store (0x01000000, ILT0 )// PL_IATU_LWR_TARGET_ADDR_REG_OUTBOUND_0 + Store (0x00, IUT0)// PL_IATU_UPPER_TARGET_ADDR_REG_OUTBOUND_0 + Store (0x04, CR10)// PL_IATU_REGION_CTRL_REG_1_OUTBOUND_0 + Store (0x80000000, CR20)// PL_IATU_REGION_CTRL_REG_2_OUTBOUND_0 + Store (0x010100, BNR0)// SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG +} + +// Rootport Ecam-Blocker Method +// Arg0 - Block Base Address +// Arg1 - Block Limit Address +Method(REB0, 0x2, Serialized) { + Store (PSC0, Local0) + // Disable ECAM Blocker Region-0 at 26th bit + AND (Local0, 0xFBFFFFFF, Local0) + Store (Local0, PSC0) + + // Configure Region Base and Limit + Store (Arg0, WBL0) + Store (0x00, WBH0) + Store (Arg1, WLL0) + Store (0x00, WLH0) + Store (Arg0, RBL0) + Store (0x00, RBH0) + Store (Arg1, RLL0) + Store (0x00, RLH0) + + Store (PSC0, Local0) + // Enable ECAM Blocker Region-0 at 26th bit + OR (Local0, 0x04000000, Local0) + Store (Local0, PSC0) +} + +// Endpoint Ecam-Blocker Method +// Arg0 - Block Base Address +// Arg1 - Block Limit Address +Method(EEB0, 0x2, Serialized) { + Store (PSC0, Local0) + // Disable ECAM Blocker Region-2 at 30th bit + AND (Local0, 0xBFFFFFFF, Local0) + Store (Local0, PSC0) + + // Configure Region Base and Limit + Store (Arg0, WBL1) + Store (0x00, WBH1) + Store (Arg1, WLL1) + Store (0x00, WLH1) + Store (Arg0, RBL1) + Store (0x00, RBH1) + Store (Arg1, RLL1) + Store (0x00, RLH1) + + Store (PSC0, Local0) + // Enable ECAM Blocker Region-2 at 30th bit + OR (Local0, 0x40000000, Local0) + Store (Local0, PSC0) +} + +// Configure the limit for PCIe0 RP ECAM blocker +Name(E0LT, 0x600FFFFF) + +// Setup Misc Configuration +Method(MSC0, 0x0, Serialized) { + // Memory Enable Compliance + Store (SCR0, Local0) + OR (Local0, 0x2, Local0) + Store (Local0, SCR0) + + // Writing Slave address space size as 16MB + Store (0x01000000, PSL0)// PCIE20_PARF_SLV_ADDR_SPACE_SIZE + + // Clear REQ_NOT_ENTER_L1 Field + Store(PPC0, Local0) + AND (Local0, 0xFFFFFFDF, Local0) + Store (Local0, PPC0) + + // Enable DBI_RO_WR_EN to access CS1 region + Store (0x01, CSW0) + + // Writing Link capability for enabling L1 and disabling L0s + Store(LCA0, Local0) + // Enable Optionality Compliance + OR(Local0, 0x00400000, Local0) + // Disable L0s + AND(Local0, 0xFFFFFBFF, Local0) + // Enable L1 + OR(Local0, 0x00000800, Local0) + Store(Local0 , LCA0) + + // Writing Bridge Class code + Store (CRI0, Local0) + AND (Local0, 0xFFFF, Local0) + OR (Local0, 0x06040000, Local0) + Store (Local0, CRI0) + + // Assert CS2 + Store (0x1, ECS0) + // Disable BAR0 and BAR1 + Store (0x0, R0B0) + Store (0x0, R0B1) + // De-Assert CS2 + Store (0x0, ECS0) + + // Disable DBI_RO_WR_EN to access CS1 region + Store (0x00, CSW0) + + // Store ECAM Base + Store (0x60000000, PPEB) + // Rootport Ecam-Blocker Method + REB0 (0x60001000, \_SB.E0LT) + // Endpoint Ecam-Blocker Method + EEB0 (0x60101000, 0x601FFFFF) +} + +Name(G0D3, Zero) +PowerResource(P0ON, 0x5, 0) { + Name (_DEP, Package(0x1) { + \_SB.GIO0 + }) + Method(_STA){Return(0)} + Method(_ON) { + If(G0D3) + { + Store(0x1, GP0B) + Sleep(1) + Store(0x0, GP0B) + + If(LEqual(\_SB.GIO0.GABL, 0x1)) + { + Store (0x01, \_SB.PCI0.MOD1) + Sleep(5) + Store (0x00, \_SB.PCI0.MOD2) + } + + Store (0x00, G0D3) + + // Setup PHY + if ( \_SB.PPU0() ) + { + // Method not returned 0x00, So handle the error + Store("PHY Init failed for Port 0", Debug) + // Store(0x0, MV01) + // This infinite loop would cause a bug check in Windows + While (One) + { + } + } + + Sleep(5) + If(LEqual(\_SB.GIO0.GABL, 0x1)) + { + Store (0x1, \_SB.PCI0.MOD2) + } + + // Setup the Link + If( \_SB.LTS0() ) + { + // Link training Failed!, block any potential access to Endpoint + // by extending the ECAM blocker region to hide the Endpoint + // config space + Store(0x601FFFFF, \_SB.E0LT) + } + Else + { + Store(0x600FFFFF, \_SB.E0LT) + } + + // Setup iATU + \_SB.IAT0() + + // Misc Configuration + \_SB.MSC0() + } + } + Method(_OFF) { + If(LEqual(G0D3, 0x0)) + { + BreakPoint + Name(PTO0, Zero) + Store(1,G0D3) + Store(PSC0 , Local0) + OR(Local0, 0x10, Local0) + Store(Local0, PSC0) + Store(ESC0, Local0) + OR(Local0, 0x10, Local0) + Store(Local0 , ESC0) + + Store (PPS0, Local0) + While(LNotEqual(And(Local0 , 0x20, Local0), 0x20)) + { + Sleep(10) + Add(PTO0, 0x1, PTO0) + If(LEqual(PTO0, 0xA)) + { + Break + } + Store (PPS0, Local0) + } + + If(LEqual(\_SB.GIO0.GABL, 0x1)) + { + Store (0x0, \_SB.PCI0.MOD2) + } + + // Power Down Sequence for Port PHY + Store(0x0, PPDC)// PCIE_PCS_POWER_DOWN_CONTROL + Store(0x0, PCST)// PCIE_PCS_START_CONTROL + } + } +} + +PowerResource(P0OF, 0x5, 0) { + Name (_DEP, Package(0x1) { + \_SB.GIO0 + }) + Method(_STA){Return(0)} + Method(_ON) { + + } + Method(_OFF) { + + } + Method(_RST, 0x0, NotSerialized) { + Store(0x1, GP0B) + Sleep(1) + Store(0x0, GP0B) + + If(LEqual(\_SB.GIO0.GABL, 0x1)) + { + Store (0x00, \_SB.PCI0.MOD1) + Sleep(1) + Store (0x01, \_SB.PCI0.MOD1) + Sleep(5) + Store (0x00, \_SB.PCI0.MOD2) + } + + Store (0x00, G0D3) + + // Setup PHY + if ( \_SB.PPU0() ) + { + // Method not returned 0x00, So handle the error + Store("PHY Init failed for Port 0", Debug) + // Store(0x0, MV03) + // This infinite loop would cause a bug check in Windows + While (One) + { + } + } + + Sleep(5) + If(LEqual(\_SB.GIO0.GABL, 0x1)) + { + Store (0x1, \_SB.PCI0.MOD2) + } + + // Setup the Link + If( \_SB.LTS0() ) + { + // Link training Failed!, block any potential access to Endpoint + // by extending the ECAM blocker region to hide the Endpoint + // config space + Store(0x601FFFFF, \_SB.E0LT) + } + Else + { + Store(0x600FFFFF, \_SB.E0LT) + } + + // Setup iATU + \_SB.IAT0() + + // Misc Configuration + \_SB.MSC0() + } +} + +Device (PCI0) { + Name (_DEP, Package(0x1) { + \_SB.PEP0 + }) + Name(_HID,EISAID("PNP0A08")) + Alias(\_SB.PSUB, _SUB) + Name(_CID,EISAID("PNP0A03")) + Name(_UID, 0x0) + Name(_SEG, 0x0) + Name(_BBN, 0x0) + Name(_PRT, Package(){ + Package(){0x0FFFF, 0, 0, 181}, // Slot 1, INTA + Package(){0x0FFFF, 1, 0, 182}, // Slot 1, INTB + Package(){0x0FFFF, 2, 0, 183}, // Slot 1, INTC + Package(){0x0FFFF, 3, 0, 184} // Slot 1, INTD + }) + + // On SDM850 CCA is NOT supported by default for GEN2 port + Method (_CCA, 0) + { + Return (Zero) + } + + //Wlan_11ad ACPI Enumeration + Include("wlan_11ad.asl") + + Method(_PSC) { + Return(Zero) + } + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // [PCIE_0_PCIE20_DBI + 2MB(ECAM_SIZE)] to [DBI_SIZE - 2MB(ECAM_SIZE) - 64KB IO Space] + Memory32Fixed (ReadWrite, 0x60200000, 0x00DF0000) + WordBusNumber (ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + , // Decode: PosDecode + 0, // AddressGranularity + 0, // AddressMinimum + 1, // AddressMaximum + 0, // AddressTranslation + 2) // RangeLength + }) + + Return (RBUF) + } + Name(SUPP, 0) + Name(CTRL, 0) + + Method(_DSW, 0x3, NotSerialized) { + + } + + Method(_OSC, 4) { + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + //No native hot plug support + //ASPM supported + //Clock PM supported + //MSI/MSI-X + + If(LNotEqual(And(SUPP, 0x16), 0x16)) + { + And(CTRL,0x1E) // Give control of everything to the OS + } + + And(CTRL,0x15,CTRL) + + If(LNotEqual(Arg1,One)) + { // Unknown revision + Or(CDW1,0x08,CDW1) + } + If(LNotEqual(CDW3,CTRL)) + { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } // Update DWORD3 in the buffer + + Store(CTRL,CDW3) + Return(Arg3) + } + Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + // + // Function 0: Return supported functions, based on revision + // + + case(0) + { + // revision 0: functions 1-9 are supported. + return (Buffer() {0xFF, 0x03}) + } + + // + // Function 1: For emulated ActiveBoth controllers, returns + // a package of controller-relative pin numbers. + // Each corresponding pin will have an initial + // polarity of ActiveHigh. + // + + case(1) + { + + Return (Package(2) { + Package(1){ + 1}, // Success + Package(3){ + 0,0x1,0x1}// Link Width supports x1??, PCI express card slot and WAKE# signal + + }) + } + case(2) + { + + Return (Package(1) { + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(3) + { + + Return (Package(1) { + 0}) //Random have to check , not implemented yet + + + } + case(4) // Not implemented yet + { + + Return (Package(2) { + Package(1){0}, + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(5) // PCI Boot Configuration + { + + Return (Package(1) { + 1 + }) + } + case(6) // Latency Scale and Value + { + + Return (Package(4) { + Package(1){0}, // Maximum Snoop Latency Scale + Package(1){0}, // Maximum Snoop Latency Value + Package(1){0}, // Maximum No-Snoop Latency Scale + Package(1){0} // Maximum No-Snoop Latency Value + + }) + } + case(7) // PCI Express Slot Parsing + { + + Return (Package(1) { + 1 + }) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + + default + { + // Functions 9+: not supported + } + + } + } + } + + Name(_S0W, 4) + + Name (GWLE, ResourceTemplate () //An existing GPIO Connection (to be used later) + { + GpioIo (Exclusive,PullNone,0,0, ,"\\_SB.GIO0", ,) {39} + }) + Name (GWLP, ResourceTemplate () //An existing GPIO Connection (to be used later) + { + GpioIo (Exclusive,PullNone,0,0, ,"\\_SB.GIO0", ,) {35} + }) + Scope(\_SB.GIO0) { + OperationRegion(WLEN, GeneralPurposeIO, 0, 1) // Note: Region is less than 8 pins long + OperationRegion(WLPR, GeneralPurposeIO, 0, 1) // Note: Region is less than 8 pins long + } + + Field(\_SB.GIO0.WLEN, ByteAcc, NoLock, Preserve) + { + Connection (\_SB.PCI0.GWLE), // Following fields will be accessed atomically + MOD1, 1 // WIFI_EN + } + Field(\_SB.GIO0.WLPR, ByteAcc, NoLock, Preserve) + { + Connection (\_SB.PCI0.GWLP), // Following fields will be accessed atomically + MOD2, 1 // PERST + } + + Name(_PR0, Package(){ + \_SB.P0ON + }) + Name(_PR3, Package(){ + \_SB.P0ON + }) + + // PCIe Root Port 1 + Device(RP1) { + Name(_ADR, 0x0) + + Name(_PR0, Package(){ + \_SB.P0OF + }) + Name(_PR3, Package(){ + \_SB.P0OF + }) + + Name(_PRR, Package(){ + \_SB.P0OF + }) + + Name(_S0W, 4) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + GpioInt(Edge, ActiveLow, ExclusiveAndWake, PullUp, 0, "\\_SB.GIO0", 0 , ResourceConsumer, , ) {37} + }) + Return (RBUF) + } + + Name (_DSD, Package () { + ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), + Package () { + Package (2) {"HotPlugSupportInD3", 1}, + } + }) + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + case(0) + { + // revision 0: functions 1-7 are not supported. + return (Buffer() {0x01, 0x03}) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + default + { + // Functions 1-7: not supported + } + } + } + } + } +} // End PCI0 + +Include("pcie1.asl") \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/pcie1.asl b/sdm845Pkg/AcpiTables/common/pcie1.asl new file mode 100644 index 0000000..fba09a1 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pcie1.asl @@ -0,0 +1,1237 @@ +//PCIE1 asl + +// PARF +OperationRegion(CP08, SystemMemory, 0x01C08000, 0x1004) +Field(CP08, DWordAcc, NoLock, Preserve){ + PSC1, 32, //0x00 PARF_SYS_CTRL + Offset(0x20), + PPC1, 32, //0x20 PARF_PM_CTRL + PPS1, 32, //0x24 PARF_PM_STTS + Offset(0x1b0), + PLT1, 32, //0x1b0 PARF_LTSSM + Offset(0x358), + PSL1, 32, //0x358 PARF_SLV_ADDR_SPACE_SIZE + Offset(0x360), + LBW0, 32, //0x360 PARF_BLOCK_SLV_AXI_WR_BASE + HBW0, 32, //0x364 PARF_BLOCK_SLV_AXI_WR_BASE_HI + LLW0, 32, //0x368 PARF_BLOCK_SLV_AXI_WR_LIMIT + HLW0, 32, //0x36C PARF_BLOCK_SLV_AXI_WR_LIMIT_HI + LBR0, 32, //0x370 PARF_BLOCK_SLV_AXI_RD_BASE + HBR0, 32, //0x374 PARF_BLOCK_SLV_AXI_RD_BASE_HI + LLR0, 32, //0x378 PARF_BLOCK_SLV_AXI_RD_LIMIT + HLR0, 32, //0x37C PARF_BLOCK_SLV_AXI_RD_LIMIT_HI + PEB1, 32, //0x380 PARF_ECAM_BASE + Offset(0x398), + LBW1, 32, //0x398 PARF_BLOCK_SLV_AXI_WR_BASE_2 + HBW1, 32, //0x39C PARF_BLOCK_SLV_AXI_WR_BASE_2_HI + LLW1, 32, //0x3A0 PARF_BLOCK_SLV_AXI_WR_LIMIT_2 + HLW1, 32, //0x3A4 PARF_BLOCK_SLV_AXI_WR_LIMIT_2_HI + LBR1, 32, //0x3A8 PARF_BLOCK_SLV_AXI_RD_BASE_2 + HBR1, 32, //0x3AC PARF_BLOCK_SLV_AXI_RD_BASE_2_HI + LLR1, 32, //0x3B0 PARF_BLOCK_SLV_AXI_RD_LIMIT_2 + HLR1, 32, //0x3B4 PARF_BLOCK_SLV_AXI_RD_LIMIT_2_HI + Offset(0x1000), + PDT1, 32, //0x1000 PARF_DEVICE_TYPE +} + +// PCIE_GEN3_QHP_COM_HP_PCIE_COM_REG_BASE +OperationRegion(CP09, SystemMemory, 0x01C0A000, 0x26C) +Field(CP09, DWordAcc, NoLock, Preserve){ + Offset (0x014), + HSEC, 32, //0x014 PCIE_GEN3_QHP_COM_SSC_EN_CENTER + HAP1, 32, //0x018 PCIE_GEN3_QHP_COM_SSC_ADJ_PER1 + HAP2, 32, //0x01C PCIE_GEN3_QHP_COM_SSC_ADJ_PER2 + HSP1, 32, //0x020 PCIE_GEN3_QHP_COM_SSC_PER1 + HSP2, 32, //0x024 PCIE_GEN3_QHP_COM_SSC_PER2 + HSS1, 32, //0x028 PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 + HSS2, 32, //0x02C PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 + Offset (0x034), + HSM1, 32, //0x034 PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 + HSM2, 32, //0x038 PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 + Offset (0x054), + HECE, 32, //0x054 PCIE_GEN3_QHP_COM_BIAS_EN_CLKBUFLR_EN + HCE1, 32, //0x058 PCIE_GEN3_QHP_COM_CLK_ENABLE1 + HSCC, 32, //0x05C PCIE_GEN3_COM_SYS_CLK_CTRL + HSBE, 32, //0x060 PCIE_GEN3_COM_SYSCLK_BUF_ENABLE + HPLE, 32, //0x064 PCIE_GEN3_QHP_COM_PLL_EN + HCPI, 32, //0x068 PCIE_GEN3_QHP_COM_PLL_IVCO + C1M0, 32, //0x06C PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 + C2M0, 32, //0x070 PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 + C3M0, 32, //0x074 PCIE_GEN3_QHP_COM_LOCK_CMP3_MODE0 + C1M1, 32, //0x078 PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 + C2M1, 32, //0x07C PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 + C3M1, 32, //0x080 PCIE_GEN3_QHP_COM_LOCK_CMP3_MODE1 + Offset (0x098), + BGTR, 32, //0x098 PCIE_GEN3_QHP_COM_BGV_TRIM + Offset (0x0B4), + HCM0, 32, //0x0B4 PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 + HCM1, 32, //0x0B8 PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 + Offset (0x0C0), + HPR0, 32, //0x0C0 PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 + HPR1, 32, //0x0C4 PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 + HPR2, 32, //0x0C8 PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE2 + HPC0, 32, //0x0CC PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 + HPC1, 32, //0x0D0 PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 + HPC2, 32, //0x0D4 PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE2 + Offset (0x0DC), + HSES, 32, //0x0DC PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL + Offset (0x0F0), + HRC2, 32, //0x0F0 PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 + Offset (0x0F8), + HCLC, 32, //0x0F8 PCIE_GEN3_QHP_COM_LOCK_CMP_EN + Offset (0x100), + HRM0, 32, //0x100 PCIE_GEN3_QHP_COM_DEC_START_MODE0 + Offset (0x108), + HRM1, 32, //0x108 PCIE_GEN3_QHP_COM_DEC_START_MODE1 + Offset (0x11C), + S1M0, 32, //0x11C PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 + S2M0, 32, //0x120 PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 + S3M0, 32, //0x124 PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 + S1M1, 32, //0x128 PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 + S2M1, 32, //0x12C PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 + S3M1, 32, //0x130 PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 + Offset (0x150), + G0M0, 32, //0x150 PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 + Offset (0x158), + G0M1, 32, //0x158 PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 + Offset (0x178), + HCVT, 32, //0x178 PCIE_GEN3_QHP_COM_VCO_TUNE_MAP + Offset (0x1C8), + BGCT, 32, //0x1C8 PCIE_GEN3_QHP_COM_BG_CTRL + HCCS, 32, //0x1CC PCIE_GEN3_QHP_COM_CLK_SELECT + HCHS, 32, //0x1D0 PCIE_GEN3_QHP_COM_HSCLK_SEL1 + Offset (0x1E0), + HCDV, 32, //0x1E0 PCIE_GEN3_QHP_COM_CORECLK_DIV + Offset (0x1E8), + HCCE, 32, //0x1E8 PCIE_GEN3_QHP_COM_CORE_CLK_EN + Offset (0x1F0), + HCCC, 32, //0x1F0 PCIE_GEN3_QHP_COM_CMN_CONFIG + Offset (0x1FC), + HMCS, 32, //0x1FC PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL + Offset (0x21C), + HDM1, 32, //0x21C PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 + Offset (0x224), + HCCM, 32, //0x224 PCIE_GEN3_QHP_COM_CMN_MODE + HVD1, 32, //0x228 PCIE_GEN3_QHP_COM_VREGCLK_DIV1 + HVD2, 32, //0x22C PCIE_GEN3_QHP_COM_VREGCLK_DIV2 +} + +// PCIE_GEN3_QHP_L0_HP_PCIE_LANE_REG_BASE +OperationRegion(CP10, SystemMemory, 0x01C0A800, 0x2F0) +Field(CP10, DWordAcc, NoLock, Preserve){ + Offset (0x00C), + L0C0, 32, //0x00C PCIE_GEN3_QHP_L0_DRVR_CTRL0 + L0C1, 32, //0x010 PCIE_GEN3_QHP_L0_DRVR_CTRL1 + L0C2, 32, //0x014 PCIE_GEN3_QHP_L0_DRVR_CTRL2 + Offset (0x018), + L0TE, 32, //0x018 PCIE_GEN3_QHP_L0_DRVR_TAP_EN + Offset (0x060), + L0BM, 32, //0x060 PCIE_GEN3_QHP_L0_TX_BAND_MODE + L0LM, 32, //0x060 PCIE_GEN3_QHP_L0_LANE_MODE + Offset (0x07C), + L0PR, 32, //0x07C PCIE_GEN3_QHP_L0_PARALLEL_RATE + Offset (0x0C0), + L0L0, 32, //0x0C0 PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 + L0L1, 32, //0x0C4 PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 + L0L2, 32, //0x0C8 PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 + Offset (0x0D0), + L0R1, 32, //0x0D0 PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 + L0R2, 32, //0x0D4 PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 + L0M0, 32, //0x0D8 PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 + L0M1, 32, //0x0DC PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 + L0M2, 32, //0x0E0 PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 + Offset (0x0FC), + L0CD, 32, //0x0FC PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE + L0VD, 32, //0x100 PCIE_GEN3_QHP_L0_VGA_THRESH_DFE + Offset (0x108), + L0X0, 32, //0x108 PCIE_GEN3_QHP_L0_RXENGINE_EN0 + Offset (0x114), + L0TT, 32, //0x114 PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME + L0OT, 32, //0x118 PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME + L0RT, 32, //0x11C PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME + L0ET, 32, //0x120 PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME + L0VG, 32, //0x124 PCIE_GEN3_QHP_L0_VGA_GAIN + L0DG, 32, //0x128 PCIE_GEN3_QHP_L0_DFE_GAIN + Offset (0x130), + L0EG, 32, //0x130 PCIE_GEN3_QHP_L0_EQ_GAIN + L0OG, 32, //0x134 PCIE_GEN3_QHP_L0_OFFSET_GAIN + L0PG, 32, //0x138 PCIE_GEN3_QHP_L0_PRE_GAIN + L0IN, 32, //0x13C PCIE_GEN3_QHP_L0_VGA_INITVAL + Offset (0x154), + L0EI, 32, //0x154 PCIE_GEN3_QHP_L0_EQ_INITVAL + Offset (0x160), + L0DI, 32, //0x160 PCIE_GEN3_QHP_L0_EDAC_INITVAL + Offset (0x168), + L0B0, 32, //0x168 PCIE_GEN3_QHP_L0_RXEQ_INITB0 + L0B1, 32, //0x16C PCIE_GEN3_QHP_L0_RXEQ_INITB1 + Offset (0x178), + L0T1, 32, //0x178 PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 + Offset (0x180), + L0RC, 32, //0x180 PCIE_GEN3_QHP_L0_RXEQ_CTRL + L0F0, 32, //0x184 PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 + L0F1, 32, //0x188 PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 + L0F2, 32, //0x18C PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 + L0S0, 32, //0x190 PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 + L0S1, 32, //0x194 PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 + L0S2, 32, //0x198 PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 + L0SC, 32, //0x19C PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG + Offset (0x1A4), + L0RB, 32, //0x1A4 PCIE_GEN3_QHP_L0_RX_BAND + Offset (0x1C0), + L0P0, 32, //0x1C0 PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 + L0P1, 32, //0x1C4 PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 + L0P2, 32, //0x1C8 PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 + Offset (0x230), + L0SE, 32, //0x230 PCIE_GEN3_QHP_L0_SIGDET_ENABLES + L0SN, 32, //0x234 PCIE_GEN3_QHP_L0_SIGDET_CNTRL + L0SD, 32, //0x238 PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL + Offset (0x2A4), + L0DC, 32, //0x2A4 PCIE_GEN3_QHP_L0_DCC_GAIN + L0ST, 32, //0x2A8 PCIE_GEN3_QHP_L0_RSM_START + L0RE, 32, //0x2AC PCIE_GEN3_QHP_L0_RX_EN_SIGNAL + L0PC, 32, //0x2B0 PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL + Offset (0x2B8), + L0N0, 32, //0x2B8 PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 + Offset (0x2C0), + L0ER, 32, //0x2C0 PCIE_GEN3_QHP_L0_TS0_TIMER + L0HI, 32, //0x2C4 PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE + Offset (0x2CC), + L0RR, 32, //0x2CC PCIE_GEN3_QHP_L0_RX_RESECODE_OFFSET +} + +// PCIE_GEN3_QHP_L1_HP_PCIE_LANE_REG_BASE +OperationRegion(CP11, SystemMemory, 0x01C0B000, 0x2F0) +Field(CP11, DWordAcc, NoLock, Preserve){ + Offset (0x00C), + L1C0, 32, //0x00C PCIE_GEN3_QHP_L1_DRVR_CTRL0 + L1C1, 32, //0x010 PCIE_GEN3_QHP_L1_DRVR_CTRL1 + L1C2, 32, //0x014 PCIE_GEN3_QHP_L1_DRVR_CTRL2 + Offset (0x018), + L1TE, 32, //0x018 PCIE_GEN3_QHP_L1_DRVR_TAP_EN + Offset (0x060), + L1BM, 32, //0x060 PCIE_GEN3_QHP_L1_TX_BAND_MODE + L1LM, 32, //0x060 PCIE_GEN3_QHP_L1_LANE_MODE + Offset (0x07C), + L1PR, 32, //0x07C PCIE_GEN3_QHP_L1_PARALLEL_RATE + Offset (0x0C0), + L1L0, 32, //0x0C0 PCIE_GEN3_QHP_L1_CML_CTRL_MODE0 + L1L1, 32, //0x0C4 PCIE_GEN3_QHP_L1_CML_CTRL_MODE1 + L1L2, 32, //0x0C8 PCIE_GEN3_QHP_L1_CML_CTRL_MODE2 + Offset (0x0D0), + L1R1, 32, //0x0D0 PCIE_GEN3_QHP_L1_PREAMP_CTRL_MODE1 + L1R2, 32, //0x0D4 PCIE_GEN3_QHP_L1_PREAMP_CTRL_MODE2 + L1M0, 32, //0x0D8 PCIE_GEN3_QHP_L1_MIXER_CTRL_MODE0 + L1M1, 32, //0x0DC PCIE_GEN3_QHP_L1_MIXER_CTRL_MODE1 + L1M2, 32, //0x0E0 PCIE_GEN3_QHP_L1_MIXER_CTRL_MODE2 + Offset (0x0FC), + L1CD, 32, //0x0FC PCIE_GEN3_QHP_L1_CTLE_THRESH_DFE + L1VD, 32, //0x100 PCIE_GEN3_QHP_L1_VGA_THRESH_DFE + Offset (0x108), + L1X0, 32, //0x108 PCIE_GEN3_QHP_L1_RXENGINE_EN0 + Offset (0x114), + L1TT, 32, //0x114 PCIE_GEN3_QHP_L1_CTLE_TRAIN_TIME + L1OT, 32, //0x118 PCIE_GEN3_QHP_L1_CTLE_DFE_OVRLP_TIME + L1RT, 32, //0x11C PCIE_GEN3_QHP_L1_DFE_REFRESH_TIME + L1ET, 32, //0x120 PCIE_GEN3_QHP_L1_DFE_ENABLE_TIME + L1VG, 32, //0x124 PCIE_GEN3_QHP_L1_VGA_GAIN + L1DG, 32, //0x128 PCIE_GEN3_QHP_L1_DFE_GAIN + Offset (0x130), + L1EG, 32, //0x130 PCIE_GEN3_QHP_L1_EQ_GAIN + L1OG, 32, //0x134 PCIE_GEN3_QHP_L1_OFFSET_GAIN + L1PG, 32, //0x138 PCIE_GEN3_QHP_L1_PRE_GAIN + L1IN, 32, //0x13C PCIE_GEN3_QHP_L1_VGA_INITVAL + Offset (0x154), + L1EI, 32, //0x154 PCIE_GEN3_QHP_L1_EQ_INITVAL + Offset (0x160), + L1DI, 32, //0x160 PCIE_GEN3_QHP_L1_EDAC_INITVAL + Offset (0x168), + L1B0, 32, //0x168 PCIE_GEN3_QHP_L1_RXEQ_INITB0 + L1B1, 32, //0x16C PCIE_GEN3_QHP_L1_RXEQ_INITB1 + Offset (0x178), + L1T1, 32, //0x178 PCIE_GEN3_QHP_L1_RCVRDONE_THRESH1 + Offset (0x180), + L1RC, 32, //0x180 PCIE_GEN3_QHP_L1_RXEQ_CTRL + L1F0, 32, //0x184 PCIE_GEN3_QHP_L1_UCDR_FO_GAIN_MODE0 + L1F1, 32, //0x188 PCIE_GEN3_QHP_L1_UCDR_FO_GAIN_MODE1 + L1F2, 32, //0x18C PCIE_GEN3_QHP_L1_UCDR_FO_GAIN_MODE2 + L1S0, 32, //0x190 PCIE_GEN3_QHP_L1_UCDR_SO_GAIN_MODE0 + L1S1, 32, //0x194 PCIE_GEN3_QHP_L1_UCDR_SO_GAIN_MODE1 + L1S2, 32, //0x198 PCIE_GEN3_QHP_L1_UCDR_SO_GAIN_MODE2 + L1SC, 32, //0x19C PCIE_GEN3_QHP_L1_UCDR_SO_CONFIG + Offset (0x1A4), + L1RB, 32, //0x1A4 PCIE_GEN3_QHP_L1_RX_BAND + Offset (0x1C0), + L1P0, 32, //0x1C0 PCIE_GEN3_QHP_L1_RX_RCVR_PATH1_MODE0 + L1P1, 32, //0x1C4 PCIE_GEN3_QHP_L1_RX_RCVR_PATH1_MODE1 + L1P2, 32, //0x1C8 PCIE_GEN3_QHP_L1_RX_RCVR_PATH1_MODE2 + Offset (0x230), + L1SE, 32, //0x230 PCIE_GEN3_QHP_L1_SIGDET_ENABLES + L1SN, 32, //0x234 PCIE_GEN3_QHP_L1_SIGDET_CNTRL + L1SD, 32, //0x238 PCIE_GEN3_QHP_L1_SIGDET_DEGLITCH_CNTRL + Offset (0x2A4), + L1DC, 32, //0x2A4 PCIE_GEN3_QHP_L1_DCC_GAIN + L1ST, 32, //0x2A8 PCIE_GEN3_QHP_L1_RSM_START + L1RE, 32, //0x2AC PCIE_GEN3_QHP_L1_RX_EN_SIGNAL + L1PC, 32, //0x2B0 PCIE_GEN3_QHP_L1_PSM_RX_EN_CAL + Offset (0x2B8), + L1N0, 32, //0x2B8 PCIE_GEN3_QHP_L1_RX_MISC_CNTRL0 + Offset (0x2C0), + L1ER, 32, //0x2C0 PCIE_GEN3_QHP_L1_TS0_TIMER + L1HI, 32, //0x2C4 PCIE_GEN3_QHP_L1_DLL_HIGHDATARATE + Offset (0x2CC), + L1RR, 32, //0x2CC PCIE_GEN3_QHP_L1_RX_RESECODE_OFFSET +} + +// PCIE_GEN3_HP_PCIE_PHY_HP_PCIE_PCS_REG_BASE +OperationRegion(CP12, SystemMemory, 0x01C0B800, 0x2DC) +Field(CP12, DWordAcc, NoLock, Preserve){ + Offset (0x000), + HPSR, 32, //0x000 PCIE_GEN3_HP_PCIE_PHY_SW_RESET + HPDC, 32, //0x004 PCIE_GEN3_HP_PCIE_PHY_POWER_DOWN_CONTROL + HSTC, 32, //0x008 PCIE_GEN3_HP_PCIE_PHY_START_CONTROL + Offset (0x02C), + HTM3, 32, //0x02C PCIE_GEN3_HP_PCIE_PHY_TXMGN_MAIN_V0_M3P5DB + Offset (0x040), + HTP3, 32, //0x040 PCIE_GEN3_HP_PCIE_PHY_TXMGN_POST_V0_M3P5DB + Offset (0x054), + HTM6, 32, //0x054 PCIE_GEN3_HP_PCIE_PHY_TXMGN_MAIN_V0_M6DB + Offset (0x068), + HTP6, 32, //0x068 PCIE_GEN3_HP_PCIE_PHY_TXMGN_POST_V0_M6DB + Offset (0x15C), + HPSG, 32, //0x15C PCIE_GEN3_HP_PCIE_PHY_POWER_STATE_CONFIG + Offset (0x16C), + HPG5, 32, //0x16C PCIE_GEN3_HP_PCIE_PHY_POWER_STATE_CONFIG5 + Offset (0x174), + HTRC, 32, //0x174 PCIE_GEN3_HP_PCIE_PHY_PCS_TX_RX_CONFIG + Offset (0x2AC), + HPST, 32, //0x2AC PCIE_GEN3_HP_PCIE_PHY_PCS_STATUS +} + +// PCIE_GEN3_PCIE20_DBI_REG_BASE +OperationRegion(CP13, SystemMemory, 0x40000000, 0x1000) +Field(CP13, DWordAcc, NoLock, Preserve){ + Offset(0x004), + SCR1, 32, //0x004 STATUS_COMMAND_REG + CRI1, 32, //0x008 TYPE1_CLASS_CODE_REV_ID_REG + Offset(0x010), + R1B0, 32, //0x010 BAR0_REG + R1B1, 32, //0x014 BAR1_REG + BNR1, 32, //0x018 SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG + Offset(0x07C), + LCA1, 32, //0x07C LINK_CAPABILITIES_REG + LCS1, 32, //0x080 LINK_CONTROL_LINK_STATUS_REG + SCA1, 32, //0x084 SLOT_CAP + Offset(0x088), + SLC1, 32, //0x088 SLOT_CAS + Offset(0x0A0), + LC21, 32, //0x0A0 LINK_CONTROL2_LINK_STATUS2_REG + Offset(0x154), + P1PR, 32, //0x154 PCIE PRESET + Offset(0x710), + GPLC, 32, //0x710 PCIE_GEN3_TYPE0_PORT_LINK_CTRL_REG + Offset(0x80C), + G32C, 32, //0x80C PCIE_GEN3_TYPE0_GEN2_CTRL_REG + Offset(0x8A8), + GEQC, 32, //0x8A8 PCIE_GEN3_TYPE0_GEN3_EQ_CONTROL_REG + GMDC, 32, //0x8AC PCIE_GEN3_GEN3_EQ_FB_MODE_DIR_CHANGE_REG + Offset(0x8BC), + CSW1, 32, //0x8BC PCIE_GEN3_MISC_CONTROL_1_REG + Offset(0x900), + IAV1, 32, //0x900 IATU_VIEWPORT_REG + CR11, 32, //0x904 PL_IATU_REGION_CTRL_REG_1_OUTBOUND_0 + CR21, 32, //0x908 PL_IATU_REGION_CTRL_REG_2_OUTBOUND_0 + ILB1, 32, //0x90C PL_IATU_LWR_BASE_ADDR_REG_OUTBOUND_0 + IUB1, 32, //0x910 PL_IATU_UPPER_BASE_ADDR_REG_OUTBOUND_0 + ILR1, 32, //0x914 PL_IATU_LIMIT_ADDR_REG_OUTBOUND_0 + ILT1, 32, //0x918 PL_IATU_LWR_TARGET_ADDR_REG_OUTBOUND_0 + IUT1, 32, //0x91C PL_IATU_UPPER_TARGET_ADDR_REG_OUTBOUND_0 + Offset(0xF24), + ESC1, 32, //0xF24 ELBI_SYS_CTRL + EST1, 32, //0xF28 ELBI_SYS_STTS + Offset(0xFC4), + ECS1, 32, //0xFC4 ELBI_CS2_ENABLE +} + +// TLMM_GPIO_CFG113 +OperationRegion(CP14, SystemMemory, 0x03971000, 0x10) +Field(CP14, DWordAcc, NoLock, Preserve){ + C113, 32, //0x00 TLMM_GPIO_CFGn + I113, 32, //0x04 TLMM_GPIO_IN_OUTn + N113, 32, //0x08 TLMM_GPIO_INTR_CFGn + S113, 32, //0x0c TLMM_GPIO_INTR_STATUSn +} + +// PCIE 0 GCC CLK CTRL REG +OperationRegion(CP15, SystemMemory, 0x16B000, 0x1020) +Field(CP15, DWordAcc, NoLock, Preserve){ + GP0B, 32, //0x0000 GCC_PCIE_0_BCR + Offset(0x101C), + G0PB, 32, //0x101C GCC_PCIE_0_PHY_BCR +} + +// PCIE 1 GCC CLK CTRL REG +OperationRegion(CP16, SystemMemory, 0x18D000, 0x1030) +Field(CP16, DWordAcc, NoLock, Preserve){ + GP1B, 32, //0x0000 GCC_PCIE_1_BCR + Offset(0x1014), + G1LB, 32, //0x1014 GCC_PCIE_1_LINK_DOWN_BCR + Offset(0x101C), + G1PB, 32, //0x101C GCC_PCIE_1_PHY_BCR + Offset(0x1020), + G1NB, 32, //0x1020 GCC_PCIE_1_NOCSR_COM_PHY_BCR +} + +// Setup PHY +Method(PPU1, 0x0, Serialized) { + Name(TOUT, Zero) + Store (0x04, PDT1) // PCIE_0_PCIE20_PARF_DEVICE_TYPE + Store (0x03, HPDC) // PCIE_GEN3_HP_PCIE_PHY_POWER_DOWN_CONTROL + Store (0x27, HSES) // PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL + Store (0x01, HSEC) // PCIE_GEN3_QHP_COM_SSC_EN_CENTER + Store (0x31, HSP1) // PCIE_GEN3_QHP_COM_SSC_PER1 + Store (0x01, HSP2) // PCIE_GEN3_QHP_COM_SSC_PER2 + Store (0xDE, HSS1) // PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 + Store (0x07, HSS2) // PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 + Store (0x4C, HSM1) // PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 + Store (0x06, HSM2) // PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 + Store (0x18, HECE) // PCIE_GEN3_QHP_COM_BIAS_EN_CLKBUFLR_EN + Store (0xB0, HCE1) // PCIE_GEN3_QHP_COM_CLK_ENABLE1 + Store (0x8C, C1M0) // PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 + Store (0x20, C2M0) // PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 + Store (0x14, C1M1) // PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 + Store (0x34, C2M1) // PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 + Store (0x06, HCM0) // PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 + Store (0x06, HCM1) // PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 + Store (0x16, HPR0) // PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 + Store (0x16, HPR1) // PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 + Store (0x36, HPC0) // PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 + Store (0x36, HPC1) // PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 + Store (0x05, HRC2) // PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 + Store (0x42, HCLC) // PCIE_GEN3_QHP_COM_LOCK_CMP_EN + Store (0x82, HRM0) // PCIE_GEN3_QHP_COM_DEC_START_MODE0 + Store (0x68, HRM1) // PCIE_GEN3_QHP_COM_DEC_START_MODE1 + Store (0x55, S1M0) // PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 + Store (0x55, S2M0) // PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 + Store (0x03, S3M0) // PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 + Store (0xAB, S1M1) // PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 + Store (0xAA, S2M1) // PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 + Store (0x02, S3M1) // PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 + Store (0x3F, G0M0) // PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 + Store (0x3F, G0M1) // PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 + Store (0x10, HCVT) // PCIE_GEN3_QHP_COM_VCO_TUNE_MAP + Store (0x04, HCCS) // PCIE_GEN3_QHP_COM_CLK_SELECT + Store (0x30, HCHS) // PCIE_GEN3_QHP_COM_HSCLK_SEL1 + Store (0x04, HCDV) // PCIE_GEN3_QHP_COM_CORECLK_DIV + Store (0x73, HCCE) // PCIE_GEN3_QHP_COM_CORE_CLK_EN + Store (0x1C, HCCC) // PCIE_GEN3_QHP_COM_CMN_CONFIG + Store (0x15, HMCS) // PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL + Store (0x04, HDM1) // PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 + Store (0x01, HCCM) // PCIE_GEN3_QHP_COM_CMN_MODE + Store (0x22, HVD1) // PCIE_GEN3_QHP_COM_VREGCLK_DIV1 + Store (0x00, HVD2) // PCIE_GEN3_QHP_COM_VREGCLK_DIV2 + Store (0x20, BGTR) // PCIE_GEN3_QHP_COM_BGV_TRIM + Store (0x07, BGCT) // PCIE_GEN3_QHP_COM_BG_CTRL + Store (0x00, L0C0) // PCIE_GEN3_QHP_L0_DRVR_CTRL0 + Store (0x0D, L0TE) // PCIE_GEN3_QHP_L0_DRVR_TAP_EN + Store (0x01, L0BM) // PCIE_GEN3_QHP_L0_TX_BAND_MODE + Store (0x3A, L0LM) // PCIE_GEN3_QHP_L0_LANE_MODE + Store (0x2F, L0PR) // PCIE_GEN3_QHP_L0_PARALLEL_RATE + Store (0x09, L0L0) // PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 + Store (0x09, L0L1) // PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 + Store (0x1B, L0L2) // PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 + Store (0x01, L0R1) // PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 + Store (0x07, L0R2) // PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 + Store (0x31, L0M0) // PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 + Store (0x31, L0M1) // PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 + Store (0x03, L0M2) // PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 + Store (0x02, L0CD) // PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE + Store (0x00, L0VD) // PCIE_GEN3_QHP_L0_VGA_THRESH_DFE + Store (0x12, L0X0) // PCIE_GEN3_QHP_L0_RXENGINE_EN0 + Store (0x25, L0TT) // PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME + Store (0x00, L0OT) // PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME + Store (0x05, L0RT) // PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME + Store (0x01, L0ET) // PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME + Store (0x26, L0VG) // PCIE_GEN3_QHP_L0_VGA_GAIN + Store (0x12, L0DG) // PCIE_GEN3_QHP_L0_DFE_GAIN + Store (0x04, L0EG) // PCIE_GEN3_QHP_L0_EQ_GAIN + Store (0x04, L0OG) // PCIE_GEN3_QHP_L0_OFFSET_GAIN + Store (0x09, L0PG) // PCIE_GEN3_QHP_L0_PRE_GAIN + Store (0x15, L0EI) // PCIE_GEN3_QHP_L0_EQ_INITVAL + Store (0x28, L0DI) // PCIE_GEN3_QHP_L0_EDAC_INITVAL + Store (0x7F, L0B0) // PCIE_GEN3_QHP_L0_RXEQ_INITB0 + Store (0x07, L0B1) // PCIE_GEN3_QHP_L0_RXEQ_INITB1 + Store (0x04, L0T1) // PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 + Store (0x70, L0RC) // PCIE_GEN3_QHP_L0_RXEQ_CTRL + Store (0x8B, L0F0) // PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 + Store (0x08, L0F1) // PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 + Store (0x0A, L0F2) // PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 + Store (0x03, L0S0) // PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 + Store (0x04, L0S1) // PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 + Store (0x04, L0S2) // PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 + Store (0x0C, L0SC) // PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG + Store (0x02, L0RB) // PCIE_GEN3_QHP_L0_RX_BAND + Store (0x5C, L0P0) // PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 + Store (0x3E, L0P1) // PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 + Store (0x3F, L0P2) // PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 + Store (0x01, L0SE) // PCIE_GEN3_QHP_L0_SIGDET_ENABLES + Store (0xA0, L0SN) // PCIE_GEN3_QHP_L0_SIGDET_CNTRL + Store (0x08, L0SD) // PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL + Store (0x01, L0DC) // PCIE_GEN3_QHP_L0_DCC_GAIN + Store (0xC3, L0RE) // PCIE_GEN3_QHP_L0_RX_EN_SIGNAL + Store (0x00, L0PC) // PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL + Store (0xBC, L0N0) // PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 + Store (0x7F, L0ER) // PCIE_GEN3_QHP_L0_TS0_TIMER + Store (0x15, L0HI) // PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE + Store (0x0C, L0C1) // PCIE_GEN3_QHP_L0_DRVR_CTRL1 + Store (0x00, L0C2) // PCIE_GEN3_QHP_L0_DRVR_CTRL2 + Store (0x04, L0RR) // PCIE_GEN3_QHP_L0_RX_RESECODE_OFFSET + Store (0x20, L0IN) // PCIE_GEN3_QHP_L0_VGA_INITVAL + Store (0x00, L1C0) // PCIE_GEN3_QHP_L1_DRVR_CTRL0 + Store (0x0D, L1TE) // PCIE_GEN3_QHP_L1_DRVR_TAP_EN + Store (0x01, L1BM) // PCIE_GEN3_QHP_L1_TX_BAND_MODE + Store (0x3A, L1LM) // PCIE_GEN3_QHP_L1_LANE_MODE + Store (0x2F, L1PR) // PCIE_GEN3_QHP_L1_PARALLEL_RATE + Store (0x09, L1L0) // PCIE_GEN3_QHP_L1_CML_CTRL_MODE0 + Store (0x09, L1L1) // PCIE_GEN3_QHP_L1_CML_CTRL_MODE1 + Store (0x1B, L1L2) // PCIE_GEN3_QHP_L1_CML_CTRL_MODE2 + Store (0x01, L1R1) // PCIE_GEN3_QHP_L1_PREAMP_CTRL_MODE1 + Store (0x07, L1R2) // PCIE_GEN3_QHP_L1_PREAMP_CTRL_MODE2 + Store (0x31, L1M0) // PCIE_GEN3_QHP_L1_MIXER_CTRL_MODE0 + Store (0x31, L1M1) // PCIE_GEN3_QHP_L1_MIXER_CTRL_MODE1 + Store (0x03, L1M2) // PCIE_GEN3_QHP_L1_MIXER_CTRL_MODE2 + Store (0x02, L1CD) // PCIE_GEN3_QHP_L1_CTLE_THRESH_DFE + Store (0x00, L1VD) // PCIE_GEN3_QHP_L1_VGA_THRESH_DFE + Store (0x12, L1X0) // PCIE_GEN3_QHP_L1_RXENGINE_EN0 + Store (0x25, L1TT) // PCIE_GEN3_QHP_L1_CTLE_TRAIN_TIME + Store (0x00, L1OT) // PCIE_GEN3_QHP_L1_CTLE_DFE_OVRLP_TIME + Store (0x05, L1RT) // PCIE_GEN3_QHP_L1_DFE_REFRESH_TIME + Store (0x01, L1ET) // PCIE_GEN3_QHP_L1_DFE_ENABLE_TIME + Store (0x26, L1VG) // PCIE_GEN3_QHP_L1_VGA_GAIN + Store (0x12, L1DG) // PCIE_GEN3_QHP_L1_DFE_GAIN + Store (0x04, L1EG) // PCIE_GEN3_QHP_L1_EQ_GAIN + Store (0x04, L1OG) // PCIE_GEN3_QHP_L1_OFFSET_GAIN + Store (0x09, L1PG) // PCIE_GEN3_QHP_L1_PRE_GAIN + Store (0x15, L1EI) // PCIE_GEN3_QHP_L1_EQ_INITVAL + Store (0x28, L1DI) // PCIE_GEN3_QHP_L1_EDAC_INITVAL + Store (0x7F, L1B0) // PCIE_GEN3_QHP_L1_RXEQ_INITB0 + Store (0x07, L1B1) // PCIE_GEN3_QHP_L1_RXEQ_INITB1 + Store (0x04, L1T1) // PCIE_GEN3_QHP_L1_RCVRDONE_THRESH1 + Store (0x70, L1RC) // PCIE_GEN3_QHP_L1_RXEQ_CTRL + Store (0x8B, L1F0) // PCIE_GEN3_QHP_L1_UCDR_FO_GAIN_MODE0 + Store (0x08, L1F1) // PCIE_GEN3_QHP_L1_UCDR_FO_GAIN_MODE1 + Store (0x0A, L1F2) // PCIE_GEN3_QHP_L1_UCDR_FO_GAIN_MODE2 + Store (0x03, L1S0) // PCIE_GEN3_QHP_L1_UCDR_SO_GAIN_MODE0 + Store (0x04, L1S1) // PCIE_GEN3_QHP_L1_UCDR_SO_GAIN_MODE1 + Store (0x04, L1S2) // PCIE_GEN3_QHP_L1_UCDR_SO_GAIN_MODE2 + Store (0x0C, L1SC) // PCIE_GEN3_QHP_L1_UCDR_SO_CONFIG + Store (0x02, L1RB) // PCIE_GEN3_QHP_L1_RX_BAND + Store (0x5C, L1P0) // PCIE_GEN3_QHP_L1_RX_RCVR_PATH1_MODE0 + Store (0x3E, L1P1) // PCIE_GEN3_QHP_L1_RX_RCVR_PATH1_MODE1 + Store (0x3F, L1P2) // PCIE_GEN3_QHP_L1_RX_RCVR_PATH1_MODE2 + Store (0x01, L1SE) // PCIE_GEN3_QHP_L1_SIGDET_ENABLES + Store (0xA0, L1SN) // PCIE_GEN3_QHP_L1_SIGDET_CNTRL + Store (0x08, L1SD) // PCIE_GEN3_QHP_L1_SIGDET_DEGLITCH_CNTRL + Store (0x01, L1DC) // PCIE_GEN3_QHP_L1_DCC_GAIN + Store (0xC3, L1RE) // PCIE_GEN3_QHP_L1_RX_EN_SIGNAL + Store (0x00, L1PC) // PCIE_GEN3_QHP_L1_PSM_RX_EN_CAL + Store (0xBC, L1N0) // PCIE_GEN3_QHP_L1_RX_MISC_CNTRL0 + Store (0x7F, L1ER) // PCIE_GEN3_QHP_L1_TS0_TIMER + Store (0x15, L1HI) // PCIE_GEN3_QHP_L1_DLL_HIGHDATARATE + Store (0x0C, L1C1) // PCIE_GEN3_QHP_L1_DRVR_CTRL1 + Store (0x00, L1C2) // PCIE_GEN3_QHP_L1_DRVR_CTRL2 + Store (0x04, L1RR) // PCIE_GEN3_QHP_L1_RX_RESECODE_OFFSET + Store (0x20, L1IN) // PCIE_GEN3_QHP_L1_VGA_INITVAL + Store (0x3F, HPSG) // PCIE_GEN3_HP_PCIE_PHY_POWER_STATE_CONFIG + Store (0x58, HTRC) // PCIE_GEN3_HP_PCIE_PHY_PCS_TX_RX_CONFIG + Store (0x19, HTM3) // PCIE_GEN3_HP_PCIE_PHY_TXMGN_MAIN_V0_M3P5DB + Store (0x07, HTP3) // PCIE_GEN3_HP_PCIE_PHY_TXMGN_POST_V0_M3P5DB + Store (0x17, HTM6) // PCIE_GEN3_HP_PCIE_PHY_TXMGN_MAIN_V0_M6DB + Store (0x09, HTP6) // PCIE_GEN3_HP_PCIE_PHY_TXMGN_POST_V0_M6DB + Store (0x9F, HPG5) // PCIE_GEN3_HP_PCIE_PHY_POWER_STATE_CONFIG5 + + // Version 2 and Higher Changes + If (LGreaterEqual (\_SB.SIDV,0x00020000)) + { + Store (0x0F, L0C2) // PCIE_GEN3_QHP_L0_DRVR_CTRL2 + Store (0x0F, L1C2) // PCIE_GEN3_QHP_L1_DRVR_CTRL2 + Store (0x50, HTRC) // PCIE_GEN3_HP_PCIE_PHY_PCS_TX_RX_CONFIG + } + + Store (0x00, HPSR) // PCIE_GEN3_HP_PCIE_PHY_SW_RESET + Store (0x01, L0ST) // PCIE_GEN3_QHP_L0_RSM_START + Store (0x01, L1ST) // PCIE_GEN3_QHP_L1_RSM_START + Store (0x01, HSTC) // PCIE_GEN3_HP_PCIE_PHY_START_CONTROL + + Store (HPST, Local0) // PCIE_PCS_PCS_STATUS + // loop until HWIO_PCIE_GEN3_HP_PCIE_PHY_PCS_STATUS_PHYSTATUS_BMSK is '0' + While(And (Local0 , 0x40)) + { + Sleep(1) + Increment(TOUT) + If (LEqual(TOUT, 0xF)) + { + Break + } + Store (HPST, Local0) + } + + If(LEqual(TOUT, 0xF)) + { + //Timeout occurred after 15 ms, so return an error value + Return(One) + } + Else + { + // PHY Init success + Return(Zero) + } +} + +// Setup Link +Method(LTS1, 0x0, Serialized) { + Name(TOUT, Zero) + + Store (G32C, Local0) + AND (Local0, 0xFFFFE0FF, Local0) + OR (Local0, 0x0100, Local0) + Store (Local0, G32C) // PCIE_GEN3_TYPE0_GEN2_CTRL_REG + + Store (0x155A0, GMDC) // PCIE_GEN3_GEN3_EQ_FB_MODE_DIR_CHANGE_REG + + Store (GEQC, Local0) + AND (Local0, 0xFFFFFFEF, Local0) + Store (Local0, GEQC) // PCIE_GEN3_TYPE0_GEN3_EQ_CONTROL_REG + + Store (0x01, CSW1) // PCIE_GEN3_MISC_CONTROL_1_REG + Store (0x77777777, P1PR) // PCIE PRESET + Store (0x00, CSW1) // PCIE_GEN3_MISC_CONTROL_1_REG + + Store (GPLC, Local0) + AND (Local0, 0xFFC0F0FF, Local0) + OR (Local0, 0x00030300, Local0) + Store (Local0, GPLC) // PCIE_GEN3_TYPE0_PORT_LINK_CTRL_REG + + Store (0x100, PLT1) // PARF_LTSSM = 0x100 + Store (EST1, Local0)// ELBI_SYS_STTS + While(LNotEqual(And(Local0 , 0x400), 0x400))// check for HWIO_PCIE20_ELBI_SYS_STTS_XMLH_LINK_UP_BMSK + { + Sleep(1) + Increment(TOUT) + If (LEqual(TOUT, 0x96)) + { + Break + } + Store (EST1, Local0) + } + + If(LEqual(TOUT, 0x96)) + { + //Timeout occurred after 150 ms, so return an error value + Return(One) + } + Else + { + // LTSSM success + Return(Zero) + } +} + +// Setup iATU +Method(IAT1, 0x0, Serialized) { + Store (0x01, IAV1)// IATU_VIEWPORT_REG + Store (0x40100000, ILB1)// PL_IATU_LWR_BASE_ADDR_REG_OUTBOUND_0 + Store (0x00, IUB1)// PL_IATU_UPPER_BASE_ADDR_REG_OUTBOUND_0 + Store (0x401FFFFF, ILR1)// PL_IATU_LIMIT_ADDR_REG_OUTBOUND_0 + Store (0x01000000, ILT1)// PL_IATU_LWR_TARGET_ADDR_REG_OUTBOUND_0 + Store (0x00, IUT1)// PL_IATU_UPPER_TARGET_ADDR_REG_OUTBOUND_0 + Store (0x04, CR11)// PL_IATU_REGION_CTRL_REG_1_OUTBOUND_0 + Store (0x80000000, CR21)// PL_IATU_REGION_CTRL_REG_2_OUTBOUND_0 + Store (0x010100, BNR1)// SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG +} + +// Rootport Ecam-Blocker Method +// Arg0 - Block Base Address +// Arg1 - Block Limit Address +Method(REB1, 0x2, Serialized) { + Store (PSC1, Local0) + // Disable ECAM Blocker Region-0 at 26th bit + AND (Local0, 0xFBFFFFFF, Local0) + Store (Local0, PSC1) + + // Configure Region Base and Limit + Store (Arg0, LBW0) + Store (0x00, HBW0) + Store (Arg1, LLW0) + Store (0x00, HLW0) + Store (Arg0, LBR0) + Store (0x00, HBR0) + Store (Arg1, LLR0) + Store (0x00, HLR0) + + Store (PSC1, Local0) + // Enable ECAM Blocker Region-0 at 26th bit + OR (Local0, 0x04000000, Local0) + Store (Local0, PSC1) +} + +// Endpoint Ecam-Blocker Method +// Arg0 - Block Base Address +// Arg1 - Block Limit Address +Method(EEB1, 0x2, Serialized) { + Store (PSC1, Local0) + // Disable ECAM Blocker Region-2 at 30th bit + AND (Local0, 0xBFFFFFFF, Local0) + Store (Local0, PSC1) + + // Configure Region Base and Limit + Store (Arg0, LBW1) + Store (0x00, HBW1) + Store (Arg1, LLW1) + Store (0x00, HLW1) + Store (Arg0, LBR1) + Store (0x00, HBR1) + Store (Arg1, LLR1) + Store (0x00, HLR1) + + Store (PSC1, Local0) + // Enable ECAM Blocker Region-2 at 30th bit + OR (Local0, 0x40000000, Local0) + Store (Local0, PSC1) +} + +// Configure the limit for PCIe0 RP ECAM blocker +Name(E1LT, 0x400FFFFF) + +// Setup Misc Configuration +Method(MSC1, 0x0, Serialized) { + // Memory Enable Compliance + Store (SCR1, Local0) + OR (Local0, 0x2, Local0) + Store (Local0, SCR1) + + // Writing Slave address space size as 512MB + Store (0x20000000, PSL1)// PARF_SLV_ADDR_SPACE_SIZE + + // Clear REQ_NOT_ENTER_L1 Field + Store(PPC1, Local0) + AND (Local0, 0xFFFFFFDF, Local0) + Store (Local0, PPC1) + + // Enable DBI_RO_WR_EN to access CS1 region + Store (0x01, CSW1) + + // Writing Link capability for enabling L1 and disabling L0s + Store(LCA1, Local0) + // Enable Optionality Compliance + OR(Local0, 0x00400000, Local0) + // Enable L0s & L1 + OR(Local0, 0x00000C00, Local0) + Store(Local0 , LCA1) + + // Writing Bridge Class code + Store (CRI1, Local0) + AND (Local0, 0xFFFF, Local0) + OR (Local0, 0x06040000, Local0) + Store (Local0, CRI1) + + // Disable Hot Plug Enable in Slot capabilities register + Store (SCA1, Local0) + AND (Local0, 0xFFFFFFBF, Local0) + Store (Local0, SCA1) + + // Disable DBI_RO_WR_EN to access CS1 region + Store (0x00, CSW1) + + // Assert CS2 + Store (0x1, ECS1) + // Disable BAR0 and BAR1 + Store (0x0, R1B0) + Store (0x0, R1B1) + // De-Assert CS2 + Store (0x0, ECS1) + + // Store ECAM Base + Store (0x40000000, PEB1) + // Rootport Ecam-Blocker Method + REB1 (0x40001000, \_SB.E1LT) + // Endpoint Ecam-Blocker Method + EEB1 (0x40101000, 0x401FFFFF) +} + +Name(G1D3, Zero) +PowerResource(P1ON, 0x5, 0) { + Name (_DEP, Package(0x1) { + \_SB.GIO0 + }) + Method(_STA){Return(0)} + Method(_ON) { + //BreakPoint + If(G1D3) + { + Store (0x00, G1D3) + + // Assert and De-Assert the PCIE_1_BCR + Store(0x1, GP1B) + Sleep(1) + Store(0x0, GP1B) + + // Assert and De-Assert the PCIE_1_PHY_BCR + Store(0x1, G1PB) + Sleep(1) + Store(0x0, G1PB) + + // Setup PHY + if ( \_SB.PPU1() ) + { + // Method not returned 0x00, So handle the error + Store("PHY Init Failed for Port 1", Debug) + // Store(0x0, MV11) + // This infinite loop would cause a bug check in Windows + While (One) + { + } + } + + If(LEqual(\_SB.GIO0.GABL, 0x1)) + { + Store (0x00, \_SB.PCI1.MOD2) + } + + Sleep(10) + + If(LEqual(\_SB.GIO0.GABL, 0x1)) + { + Store (0x1, \_SB.PCI1.MOD2) + } + + // Setup the Link + If( \_SB.LTS1() ) + { + // Link training Failed!, block any potential access to Endpoint + // by extending the ECAM blocker region to hide the Endpoint + // config space + Store(0x401FFFFF, \_SB.E1LT) + } + Else + { + Store(0x400FFFFF, \_SB.E1LT) + } + + // Setup iATU + \_SB.IAT1() + + // Misc Configuration + \_SB.MSC1() + } + } + Method(_OFF) { + If(LEqual(G1D3, 0x0)) + { + BreakPoint + Name(PTO0, Zero) + Store(1,G1D3) + Store(PSC1 , Local0) + OR(Local0, 0x10, Local0) + Store(Local0, PSC1) + Store(ESC1, Local0) + OR(Local0, 0x10, Local0) + Store(Local0 , ESC1) + + Store (PPS1, Local0) + While(LNotEqual(And(Local0 , 0x20, Local0), 0x20)) + { + Sleep(10) + Add(PTO0, 0x1, PTO0) + If(LEqual(PTO0, 0xA)) + { + Break + } + Store (PPS1, Local0) + } + + If(LEqual(\_SB.GIO0.GABL, 0x1)) + { + Store (0x0, \_SB.PCI1.MOD2) + } + + // Power Down Sequence for Port PHY + Store (0x00, HPSR) // PCIE_GEN3_HP_PCIE_PHY_SW_RESET + Store (0x00, L0ST) // PCIE_GEN3_QHP_L0_RSM_START + Store (0x00, L1ST) // PCIE_GEN3_QHP_L1_RSM_START + Store (0x00, HSTC) // PCIE_GEN3_HP_PCIE_PHY_START_CONTROL + } + } +} + +PowerResource(P1OF, 0x5, 0) { + Name (_DEP, Package(0x1) { + \_SB.GIO0 + }) + Method(_STA){Return(0)} + Method(_ON) { + + } + Method(_OFF) { + + } + Method(_RST, 0x0, Serialized) { + // Assert and De-Assert the PCIE_1_BCR + Store(0x1, GP1B) + Sleep(1) + Store(0x0, GP1B) + + // Assert and De-Assert the PCIE_1_PHY_BCR + Store(0x1, G1PB) + Sleep(1) + Store(0x0, G1PB) + + // Setup PHY + if ( \_SB.PPU1() ) + { + // Method not returned 0x00, So handle the error + Store("PHY Init Failed for Port 1", Debug) + // Store(0x0, MV13) + // This infinite loop would cause a bug check in Windows + While (One) + { + } + } + + If(LEqual(\_SB.GIO0.GABL, 0x1)) + { + Store (0x00, \_SB.PCI1.MOD2) + } + + Sleep(10) + + If(LEqual(\_SB.GIO0.GABL, 0x1)) + { + Store (0x1, \_SB.PCI1.MOD2) + } + + // Setup the Link + If( \_SB.LTS1() ) + { + // Link training Failed!, block any potential access to Endpoint + // by extending the ECAM blocker region to hide the Endpoint + // config space + Store(0x401FFFFF, \_SB.E1LT) + } + Else + { + Store(0x400FFFFF, \_SB.E1LT) + } + + // Setup iATU + \_SB.IAT1() + + // Misc Configuration + \_SB.MSC1() + } +} + +Device (PCI1) { + Name (_DEP, Package(0x1) { + \_SB.PEP0 + }) + Name(_HID,EISAID("PNP0A08")) + Alias(\_SB.PSUB, _SUB) + Name(_CID,EISAID("PNP0A03")) + Name(_UID, 0x1) + Name(_SEG, 0x1) + Name(_BBN, 0x0) + Name(_PRT, Package(){ + Package(){0x0FFFF, 0, 0, 466}, // Slot 1, INTA + Package(){0x0FFFF, 1, 0, 467}, // Slot 1, INTB + Package(){0x0FFFF, 2, 0, 470}, // Slot 1, INTC + Package(){0x0FFFF, 3, 0, 471} // Slot 1, INTD + }) + + // On SDM850 CCA is supported default on GEN3 PCIe port + Method (_CCA, 0) + { + Return (One) + } + + Method(_STA, 0) + { + Return (0x0F) // EndPoints available + } + + Method(_PSC) { + Return(Zero) + } + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // [GEN3_DBI_BASE + 2MB(ECAM_SIZE)] to [GEN3_DBI_SIZE - 3MB(ECAM_SIZE) - 64KB IO Space] + Memory32Fixed (ReadWrite, 0x40200000, 0x01FDF000) + WordBusNumber (ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + , // Decode: PosDecode + 0, // AddressGranularity + 0, // AddressMinimum + 1, // AddressMaximum + 0, // AddressTranslation + 2) // RangeLength + }) + + Return (RBUF) + } + Name(SUPP, 0) + Name(CTRL, 0) + + Method(_DSW, 0x3, NotSerialized) { + + } + + Method(_OSC, 4) { + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + //No native hot plug support + //ASPM supported + //Clock PM supported + //MSI/MSI-X + + If(LNotEqual(And(SUPP, 0x16), 0x16)) + { + And(CTRL,0x1E) // Give control of everything to the OS + } + + And(CTRL,0x15,CTRL) + + If(LNotEqual(Arg1,One)) + { // Unknown revision + Or(CDW1,0x08,CDW1) + } + If(LNotEqual(CDW3,CTRL)) + { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } // Update DWORD3 in the buffer + + Store(CTRL,CDW3) + Return(Arg3) + } + Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + // + // Function 0: Return supported functions, based on revision + // + + case(0) + { + // revision 0: functions 1-9 are supported. + return (Buffer() {0xFF, 0x03}) + } + + // + // Function 1: For emulated ActiveBoth controllers, returns + // a package of controller-relative pin numbers. + // Each corresponding pin will have an initial + // polarity of ActiveHigh. + // + + case(1) + { + + Return (Package(2) { + Package(1){ + 1}, // Success + Package(3){ + 0,0x1,0x1}// Link Width supports x1??, PCI express card slot and WAKE# signal + + }) + } + case(2) + { + + Return (Package(1) { + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(3) + { + + Return (Package(1) { + 0}) //Random have to check , not implemented yet + + + } + case(4) // Not implemented yet + { + + Return (Package(2) { + Package(1){0}, + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(5) // PCI Boot Configuration + { + + Return (Package(1) { + 1 + }) + } + case(6) // Latency Scale and Value + { + + Return (Package(4) { + Package(1){0}, // Maximum Snoop Latency Scale + Package(1){0}, // Maximum Snoop Latency Value + Package(1){0}, // Maximum No-Snoop Latency Scale + Package(1){0} // Maximum No-Snoop Latency Value + + }) + } + case(7) // PCI Express Slot Parsing + { + + Return (Package(1) { + 2 + }) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + + default + { + // Functions 9+: not supported + } + + } + } + } + + Name(_S0W, 4) + + Name (RST1, ResourceTemplate () + { + GpioIo (Exclusive,PullNone,0,0, ,"\\_SB.GIO0", ,) {102} + }) + + Scope(\_SB.GIO0) { + OperationRegion(P1PR, GeneralPurposeIO, 0, 1) + } + Field(\_SB.GIO0.P1PR, ByteAcc, NoLock, Preserve) + { + Connection (\_SB.PCI1.RST1), // Following fields will be accessed atomically + MOD2, 1 // PERST + } + + Name(_PR0, Package(){ + \_SB.P1ON + }) + Name(_PR3, Package(){ + \_SB.P1ON + }) + + // PCIe Root Port 1 + Device(RP1) { + Name(_ADR, 0x0) + + Name(_PR0, Package(){ + \_SB.P1OF + }) + Name(_PR3, Package(){ + \_SB.P1OF + }) + Name(_PRR, Package(){ + \_SB.P1OF + }) + + Name (_DSD, Package () { + ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), + Package () { + Package (2) {"HotPlugSupportInD3", 1}, + } + }) + + Name(_S0W, 4) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + //WAKE + GpioInt(Edge, ActiveLow, ExclusiveAndWake, PullUp, 0, "\\_SB.GIO0", 0 , ResourceConsumer, , ) {104} + //PRSNT + GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullUp, 0, "\\_SB.GIO0", 0 , ResourceConsumer, , ) {113} + }) + Return (RBUF) + } + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + case(0) + { + // revision 0: functions 1-7 are not supported. + return (Buffer() {0x01, 0x03}) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + default + { + // Functions 1-7: not supported + } + } + } + } + } +} // End PCI1 \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/pcie_resources.asl b/sdm845Pkg/AcpiTables/common/pcie_resources.asl new file mode 100644 index 0000000..9076349 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pcie_resources.asl @@ -0,0 +1,404 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by pcie subsystem. +// +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + // PCIe Intra-Soc ports + Method(PEMD) + { + Return (PEMC) + } + + Name(PEMC, + package() + { + Package() + { + "DEVICE", + "\\_SB.PCI0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + // PCIE Analog + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L28 @1.0v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Head Room + }, + }, + + // PCIE Core + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO1_A", + 1, // Voltage Regulator Type, 1 = LDO + 880000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Headroom + }, + }, + + //Turning on PCIe core + Package() { "FOOTSWITCH", Package() { "pcie_0_gdsc", 1}}, + + // ICB votes through PSTATE + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_0_CFG", 75000000, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 400000000, 200000000}}, + + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}}, + + package() {"CLOCK", package() {"gcc_pcie_0_pipe_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_q2a_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_mstr_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_cfg_ahb_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_aux_clk", 8, 19200000, 3}}, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + package() {"CLOCK", package() {"gcc_pcie_0_pipe_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_q2a_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_mstr_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_cfg_ahb_clk", 2}}, + + // common clocks + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}}, + + // ICB votes + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_0_CFG", 0, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 0, 0}}, + + // Turn off PCIe core + Package() { "FOOTSWITCH", Package() { "pcie_0_gdsc", 2}}, + + // PCIE Analog + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L28 @1.0v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 1.2V : microvolts ( V ) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Head Room + }, + }, + + // PCIE Core + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO1_A", + 1, // Voltage Regulator Type, 1 = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Headroom + }, + }, + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI0.RP1", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + // PCIE Analog + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L28 @1.0v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Head Room + }, + }, + + // PCIE Core + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO1_A", + 1, // Voltage Regulator Type, 1 = LDO + 880000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Headroom + }, + }, + + //Turning on PCIe core + Package() { "FOOTSWITCH", Package() { "pcie_1_gdsc", 1}}, + + // ICB votes + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_1_CFG", 75000000, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_1", "ICBID_SLAVE_EBI1", 400000000, 200000000}}, + + /* + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() + { + "PPP_RESOURCE_ID_CXO_BUFFERS_LNBBCLK1_A", // Resource ID + 6, // Voltage Regulator type = CXO Buffer + 1, // Force enable from s/w + 0, // Disable pin control + }, + }, + */ + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}}, + + package() {"CLOCK", package() {"gcc_pcie_1_pipe_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_q2a_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_mstr_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_cfg_ahb_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_aux_clk", 8, 19200000, 3}}, + package() {"CLOCK", package() {"gcc_pcie_phy_refgen_clk", 8, 100000000, 3}}, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + package() {"CLOCK", package() {"gcc_pcie_1_pipe_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_phy_refgen_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_q2a_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_mstr_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_cfg_ahb_clk", 2}}, + + // common clocks + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}}, + + // ICB votes + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_1_CFG", 0, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_1", "ICBID_SLAVE_EBI1", 0, 0}}, + + // Turn off PCIe core + Package() { "FOOTSWITCH", Package() { "pcie_1_gdsc", 2}}, + /* + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() + { + "PPP_RESOURCE_ID_CXO_BUFFERS_LNBBCLK1_A", // Resource ID + 6, // Voltage Regulator type = CXO Buffer + 0, // Force enable from s/w + 0, // Disable pin control + }, + }, + */ + // PCIE Analog + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L28 @1.0v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 1.2V : microvolts ( V ) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Head Room + }, + }, + + // PCIE Core + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO1_A", + 1, // Voltage Regulator Type, 1 = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Headroom + }, + }, + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI1.RP1", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + }) +} diff --git a/sdm845Pkg/AcpiTables/common/pep_common.asl b/sdm845Pkg/AcpiTables/common/pep_common.asl new file mode 100644 index 0000000..fe7627a --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_common.asl @@ -0,0 +1,537 @@ +// +// The PEP Device & Driver Related Configuration +// + +Device (PEP0) +{ + Name (_HID, "HID_PEP0") + Name (_CID, "PNP0D80") + + Include("thz.asl") + + Method(_CRS) + { + // List interrupt resources in the order they are used in PEP_Driver.c + Return + ( + ResourceTemplate () + { + // TSENS threshold interrupts + // Controller 0: Low / high + Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {538} + // Controller 0: Critical + Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {540} + // Controller 1: Low / high + Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {539} + // Controller 1: Critical + Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {541} + + // apss amc finish irq + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {37} + // apss epcb timeout irq + //Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {47} + // mdss amc finish irq + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {161} + // mdss epcb timeout irq + //Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {160} + + // Inbound interrupt from AOP to Apps PEP Glink: + //SYS_apssQgicSPI[389] = 421 + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {421} + + //rpm_to_kpss_ipc_irq0 = SYSApcsQgicSpi169 = 201 (MPM) + //Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {201} + + //rpm_to_kpss_ipc_irq0 = SYSApcsQgicSpi171 = 203 (wakeup) + //Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {203} + + //o_pwr_dcvsh_interrupt: LMH debug interrupt for power cluster + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {64} + + //o_perf_dcvsh_interrupt: LMH debug interrupt for perf cluster + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {65} + + //ddrss_apps_interrupt[1]: BIMC BWMON + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {613} + } + ) + } + + + // need 20 char and 1 D state info + Field(\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve) + { + /* Connection Object - 0x007C is the unique identifier */ + Connection(I2CSerialBus( 0x0001,,0x0,, "\\_SB.ABD",,,,)), + AccessAs(BufferAcc, AttribRawBytes(21)), + FLD0, 168 + } + //Get port to connect to + Method(GEPT) + { + Name(BUFF, Buffer(4){}) + CreateByteField(BUFF, 0x00, STAT) + CreateWordField(BUFF, 0x02, DATA) + Store(0x1, DATA) //in this example we will connect to ABDO + Return(DATA) + } + + Name(ROST, 0x0) + // Number of CPUs to Park + Method(NPUR, 0x1, NotSerialized) + { + Store(Arg0, Index(\_SB_.AGR0._PUR, 1)) + Notify(\_SB_.AGR0, 0x80) + } + + + // ACPI method to return intr descriptor + Method(INTR, 0x0, NotSerialized) { + Name(RBUF, Package() + { + // Version + 0x00000002, + // Number of hosts + 0x00000001, + // number of memory regions + 0x00000003, + // number of IPC registers + 0x00000001, + + // Rpm: APCS_IPC(0) + // Host = SMEM_RPM + 0x00000006, + // Physical address + 0x17911008, + // Value + 0x00000001, + // Reserved + 0x00000000, + + // Shared memory + // Start address + 0x86000000, + // Size + 0x00200000, + // Reserved + 0x00000000, + // Reserved + 0x00000000, + + // MSG RAM + // Start address + 0x0C300000, + // Size + 0x00001000, + // Reserved + 0x00000000, + // Reserved + 0x00000000, + + // IMEM or TZ_WONCE + // Start address + 0x01fd4000, + // Size + 0x00000008, + // Reserved + 0x00000000, + // Reserved + 0x00000000, + + // IPC register 1 + // Physical addr + 0x1799000C, + // Reserved + 0x00000000, + // Reserved + 0x00000000, + // Reserved + 0x00000000, + }) + Return (RBUF) + } + + Method(CRTC) + { + return (CTRX) + } + + Name(CTRX, + Package() + { + // Methods (names are reversed) that are critical to + // system boot + "NSTC", // critical thermal sensors + "HLCB", // BCL sensor HID + "MMVD", // Discrete Vreg Mapping Package + "DSGP", //System Default Configuration, SDFR + "CCGP", // CPU Configuration + "MTPS", //Read the speaker calibration related parameters + "CPGP", // CPU cap for DCVS Package + "DMPP", // PEP resources (usually dummy devices required for power mgmt) + "VRDL", // DRV ID List + "GBDL", // Debugger configuration -- must be below DSGP (reading SDFR) + "SRDL", // Default resources -- must be below DSGP (reading SDFR) + } + ) + + Method(STND) + { + return (STNX) + } + + Name(STNX, + Package() + { + // Power resources for devices + // Names are reversed (so method OCMD becomes DMCO) + // + // Following format must be followed for name: + // DMxx -- Exists on QCOM SoC. Will use normal PoFX for power mgmt + // XMxx -- Exists off QCOM SoC and uses legacy power mgmt (_PS1, _PS2, etc) + // + // The files where these methods are declared must be included + // at the bottom of this file and must exists inside the scope: \_SB.PEP0 + "DMPO", //oem dummy + "DMSB", // buses resources + "DMQP", // dfs Resources + "DMMS", // SMMU + "DMPA", //AUDIO + "DMPC", //CAMERA + "DMPB", //COREBSP + "DM0G", //GRAPHICS + "DM1G", //GRAPHICS + "DM2G", //GRAPHICS + "DM3G", //GRAPHICS + "DM4G", //GRAPHICS + "DM5G", //GRAPHICS + "DM6G", //GRAPHICS + "DM7G", //GRAPHICS + "DM8G", //GRAPHICS + "DM9G", //GRAPHICS + "DMPS", //SUBSYSTEMDRIVERS + // "DMRC", //CRYPTO + "DMPL", // PLATFORM + // "DMTB", //BAMTestClient + "DMDQ", //QDSS + // "DMMT", //SMMUTestClient + "DMPI", //IPA + "DMWE", //EXTERNAL WIRELESS CONNECTIVITY + "XMPC", //CAMERA + "XMPL", // PLATFORM + // "XMPN", //SENSORS + "DMEP", //PCIE-Resources + } + ) + + // + // Core topology + // + Method(CTPM){ + Name( CTPN, package(){ + "CORE_TOPOLOGY", + 8 // Kyro cores + }) + + return(CTPN) + } + + // CPU/Core Configurations Packages + Name(CCFG, + Package () + { + // Post computex cpu names + Package () + { + "\\_SB.SYSM.CLUS.CPU0", + 0x10, // CPU0. + }, + Package () + { + "\\_SB.SYSM.CLUS.CPU1", + 0x11, // CPU1. + }, + Package () + { + "\\_SB.SYSM.CLUS.CPU2", + 0x12, // CPU2. + }, + Package () + { + "\\_SB.SYSM.CLUS.CPU3", + 0x13, // CPU3. + }, + Package () + { + "\\_SB.SYSM.CLUS.CPU4", + 0x14, // CPU4. + }, + Package () + { + "\\_SB.SYSM.CLUS.CPU5", + 0x15, // CPU5. + }, + Package () + { + "\\_SB.SYSM.CLUS.CPU6", + 0x16, // CPU6. + }, + Package () + { + "\\_SB.SYSM.CLUS.CPU7", + 0x17, // CPU7. + }, + }) + + + // Method to return CPU configuration packages + // PEP Get CPU Configuration + Method(PGCC) + { + Return(CCFG) + } + + // DRV ID Configurations Packages + Name(DRVC, + Package () + { + // PEP Supported DRV List + Package () + { + "HLOS_DRV", + 0x2, // HLOS Subsystem DRV ID. + "/icb/arbiter", // HLOS ICB resource node + }, + Package () + { + "DISPLAY_DRV", + 0x9, // Display Subsystem DRV ID. + "/icb/arbiter/display", //Display ICB resource node + }, + }) + + // Method to return DRV Id list packages + // PEP Get DRV Id list + Method(LDRV) + { + Return(DRVC) + } + + // CPU cap for DCVS Packages + Name(DCVS,0x0) + + // Method to return CPU cap for DCVS Package + Method(PGDS) + { + Return(DCVS) + } + + // PPP Supported Resources Package + Name (PPPP, + Package() + { + // Resource ID // Set Interface Type // Get Interface Type + //------------------------ ---------------------------------------------- ---------------------------------------------- + Package () { "PPP_RESOURCE_ID_SMPS1_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_SMPS2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_SMPS3_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_SMPS4_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_SMPS5_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_SMPS6_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + + Package () { "PPP_RESOURCE_ID_SMPS7_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_SMPS9_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + + Package () { "PPP_RESOURCE_ID_SMPS1_C", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_SMPS2_C", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_SMPS3_C", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + + Package () { "PPP_RESOURCE_ID_LDO1_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO3_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO4_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO5_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO6_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO7_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO8_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO9_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO10_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO11_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO12_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO13_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO14_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO15_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO16_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO17_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO18_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO19_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO20_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO21_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO22_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO23_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO24_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO25_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO26_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO27_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LDO28_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + + Package () { "PPP_RESOURCE_ID_LVS1_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_LVS2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK3_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK1_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK3_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK1_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK3_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + + Package () { "PPP_RESOURCE_ID_BUCK_BOOST1_B", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" }, + }) + + + // Method to return PPP Package + Method(PPPM) + { + Return (PPPP) + } + + // Method to return System Default config packages + Name (PRRP, + Package() + { + // Resource type range Initial supported resource Last supported resource + //-------------------- -------------------------- ------------------------- + "PPP_RESOURCE_RANGE_INFO_SMPS_A", "PPP_RESOURCE_ID_SMPS1_A", "PPP_RESOURCE_ID_SMPS13_A", + "PPP_RESOURCE_RANGE_INFO_SMPS_C", "PPP_RESOURCE_ID_SMPS1_C", "PPP_RESOURCE_ID_SMPS4_C", + "PPP_RESOURCE_RANGE_INFO_LDO_A", "PPP_RESOURCE_ID_LDO1_A", "PPP_RESOURCE_ID_LDO28_A", + "PPP_RESOURCE_RANGE_INFO_LVS_A", "PPP_RESOURCE_ID_LVS1_A", "PPP_RESOURCE_ID_LVS2_A", + "PPP_RESOURCE_RANGE_INFO_CXO_BUFFERS_A", "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK2_A", "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK3_A", + "PPP_RESOURCE_RANGE_INFO_BUCK_BOOST_B", "PPP_RESOURCE_ID_BUCK_BOOST1_B", "PPP_RESOURCE_ID_BUCK_BOOST1_B", + }) + + // Method to return Pep Ppp Resource Range Package + Method(PPRR) + { + Return (PRRP) + } + + // Method to return System Default config packages + // PEP Get System Default package + Method(PGSD) + { + Return(SDFR) + } + + // Full PEP Device Package + Name(FPDP,0x0) + + // Method to return Full PEP Managed Device List Package + Method(FPMD) + { + Return(FPDP) + } + + + // + // PEP Processor Performance configuration + // CPU cap for DCVS Packages + Name(PPPC,0x0) + + // Method to return CPU cap for DCVS Package + Method(PGPC) + { + Return(PPPC) + } + + + // Methods to read USB DP & DM interrupts polarity + // The return names should match with buffers + // declared and defined in usb.asl file. + + // This method allows PEP to read Polarity of + // eud_p0_dmse_int_mx & eud_p0_dpse_int_mx + // interrupts which belong to Primary USB Port (P0) + Method(DPRF) { + // Return DPRF + Return(\_SB.DPP0) + } + + // This method allows PEP to read Polarity of + // eud_p1_dmse_int_mx & eud_p1_dpse_int_mx + // interrupts which belong to Secondary USB Port (P1) + Method(DMRF) { + // Return DMRF + Return(\_SB.DPP1) + } + +} + +//Device (PRXY) // PEP proxy +//{ +// Name (_HID, "HID_PRXY") +// Name(_DEP, Package(0x2) { +// \_SB_.ABD, +// \_SB_.PEP0 +// }) +// Method (_CRS, 0x0, NotSerialized) +// { +// Name (RBUF, ResourceTemplate () +// { +// GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x20, 0x2, 0x1, 0x8}) {0x1003} +// GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x21, 0x2, 0x1, 0x8}) {0x1004} +// }) +// Return (RBUF) +// } + + //// need 20 char and 1 D state info +// Field(\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve) +// { + ///* Connection Object - 0x007C is the unique identifier */ +// Connection(I2CSerialBus( 0x0001,,0x0,, "\\_SB.ABD",,,,)), +// AccessAs(BufferAcc, AttribRawBytes(21)), +// FLD0, 168 +// } + ////Get port to connect to +// Method(GEPT) +// { +// Name(BUFF, Buffer(4){}) +// CreateByteField(BUFF, 0x00, STAT) +// CreateWordField(BUFF, 0x02, DATA) +// Store(0x1, DATA) +// Return(DATA) +// } +//} + +// Data required by PEP +Include("pep_libPdc.asl") +Include("pep_libPCU.asl") +Include("pep_vddresources.asl") +Include("pep_lmh.asl") +Include("pep_dvreg.asl") +Include("pep_dbgSettings.asl") +Include("pep_defaults.asl") +Include("pep_idle.asl") +Include("pep_cprh.asl") +Include("pep_dcvscfg.asl") +// DO NOT comment next line, since pep_tsens.asl is needed for PEP DeviceAdd +Include("pep_tsens.asl") + +// Resources by area +Include("audio_resources.asl") +Include("graphics_resources.asl") +Include("HoyaSmmu_resources.asl") +//Include("msft_resources.asl") +Include("oem_resources.asl") +Include("subsys_resources.asl") +Include("pep_resources.asl") +Include("corebsp_resources.asl") +Include("ipa_resources.asl") +//Include("crypto_resources.asl") +Include("wcnss_resources.asl") +//Include("cust_wcnss_resources.asl") +Include("qdss_resources.asl") +Include("pcie_resources.asl") diff --git a/sdm845Pkg/AcpiTables/common/pep_cprh.asl b/sdm845Pkg/AcpiTables/common/pep_cprh.asl new file mode 100644 index 0000000..027a0dc --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_cprh.asl @@ -0,0 +1,608 @@ +Scope(\_SB.PEP0) +{ + // Method to return CPR data + Method(CPRZ) + { + Return(CPRH) + } + + //----------------------------------------------------------------------------------------- + // CPRh Napali V1 + // ------------ + // + //----------------------------------------------------------------------------------------- + // CPR data + Name(CPRH, + Package(){ + "CPRH_SW_SETTING", // CPR SW Setting + 0, + Package(){ + "CPRH_CHIP_INFO", + 321, // chip ID + 1, // chip version + //----------------------------------------------------------------------------------------- + // APC Controller SW Setting + // ------------------------- + // + //----------------------------------------------------------------------------------------- + Package(){ + "CPRH_SW_CONTROLLER_SETTING", + 0, //instance_num (doc: CPR SW) + "APC0", //rail_name (doc: voltage plan) + 0x17DC0000, //cpr_register_addr (doc: SWI) + 0x4000, //cpr_register_size (doc: SWI) + 0, //count_mode (doc: voltage plan) + 20, //count_repeat (doc: voltage plan) + 15, //idle_clocks (doc: voltage plan) + 12, //step_quot_max (doc: voltage plan) + 11, //step_quot_min (doc: voltage plan) + 1, //reset_step_quot_loop_en (doc: voltage plan) - TBD + 8, //number_of_sensors (doc: HPG) + 0xf0, //sensor_thread_mask (doc: HPG) L3 using sensor #0,1,2,3 + 0, //sensor_mask (doc: voltage plan) + 0, //sensor_bypass (doc: voltage plan) + 0x17700, //auto_cont_interval (doc: voltage plan) //5ms + 400, //base_voltage_mV (doc: CPR SW) + 4, //voltage_multiplier (doc: CPR HPG) + 4, //target_multiplier (doc: CPR HPG) + 5, //mode_switch_timer (doc: voltage plan) + 0, //initial_mode (doc: CPR HPG) + 1, //temp_sensor_id_start (doc: CPR HPG) + 5, //temp_sensor_id_end (doc: CPR HPG) + 1, //error_step_limit_dn (doc: voltage plan) + 1, //error_step_limit_up (doc: voltage plan) + 1, //thread_aggregation_enable (doc: CPR HPG) + 1, //thread_has_always_vote (doc: CPR HPG) + 23, //1.2us/19.2MHz MarginTimerSettleVoltage (doc: CPR HPG) - TBD - PMIC delay for one step / CPR clock period + 0x4b00, //MarginTimerLowerVoltage (doc: CPR HPG) + //Below are temp adj related - Setting to zero for now. + 0, //MarginInitialTempBand; (doc: voltage plan) + 4, //MarginMaxNumCores; (doc: CPUSS HPG) + 1, //MarginLowerVoltageWaitSelect; (doc: CPR HPG) + 4, //MarginPmicStepSize; (doc: PMIC HPG) + 1, //MarginClosedLoopEn; (doc: CPR HPG) + 0, //MarginCoreAdjEn; (doc: CPR HPG) + 0, //MarginTempAdjEn; (doc: CPR HPG) + //--------------------------------------------------------------------------------------------------------------------- + // Aging Setting + // ------------ + "", //aging_rail_id (doc: power grid) + 0, //aging_thread_index (doc: n/a) + 0, //aging_measurement_voltage_mV (doc: voltage plan) + 0, //aging_sensor_id (doc: voltage plan) + 0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan) + 0, //derate_scaling_factor (doc: voltage plan) + 0, //max_age_compensation (mV) (doc: voltage plan) + 0, //bypass_sensor (doc: voltage plan) + //--------------------------------------------------------------------------------------------------------------------- + // SAW4 Setting + // ------------ + 0x17840800, //saw_register_addr + 0x400, //saw_register_size + 1, //saw_enable + 1, //saw_ctl_sel + 0, //saw_tmr_clk_div + 1, //saw_vlvl_width + 1, //saw_vlvl_step_up + 1, //saw_vlvl_step_dn + //--------------------------------------------------------------------------------------------------------------------- + // Thread 0 SW Setting //TBD - Voltage plan does not have entries for L3 for settings below + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 0, "L3", 2, 2, 0, 0, }, + //--------------------------------------------------------------------------------------------------------------------- + // Thread 1 SW Setting + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 1, "Silver", 2, 2, 0, 0, }, + }, + Package(){ + "CPRH_SW_CONTROLLER_SETTING", + 1, //instance_num + "APC1", //rail_name + 0x17DB0000, //cpr_register_addr + 0x4000, //cpr_register_size + 0, //count_mode + 20, //count_repeat + 15, //idle_clocks + 14, //step_quot_max + 9, //step_quot_min + 1, //reset_step_quot_loop_en //TBD + 14, //number_of_sensors + 0, //sensor_thread_mask //Assigning to thread0 + 0, //sensor_mask + 0, //sensor_bypass + 0x17700, //auto_cont_interval + 400, //base_voltage_mV + 4, //voltage_multiplier + 4, //target_multiplier + 5, //mode_switch_timer + 0, //initial_mode + 6, //temp_sensor_id_start + 10, //temp_sensor_id_end + 1, //error_step_limit_dn + 1, //error_step_limit_up + 0, //thread_aggregation_enable + 0, //thread_has_always_vote (doc: CPR HPG) + 23, //1.2us/19.2MHz MarginTimerSettleVoltage + 0x4b00, //MarginTimerLowerVoltage + //Below are temp adj related - Setting to zero for now. + 0, //MarginInitialTempBand; + 4, //MarginMaxNumCores; + 1, //MarginLowerVoltageWaitSelect; + 4, //MarginPmicStepSize; + 1, //MarginClosedLoopEn; + 0, //MarginCoreAdjEn; + 0, //MarginTempAdjEn; + //--------------------------------------------------------------------------------------------------------------------- + // Aging Setting + // ------------ + "", //aging_rail_id (doc: power grid) + 0, //aging_thread_index (doc: n/a) + 0, //aging_measurement_voltage_mV (doc: voltage plan) + 0, //aging_sensor_id (doc: voltage plan) + 0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan) + 0, //derate_scaling_factor (doc: voltage plan) + 0, //max_age_compensation (mV) (doc: voltage plan) + 0, //bypass_sensor (doc: voltage plan) + //--------------------------------------------------------------------------------------------------------------------- + // SAW4 Setting + // ------------ + 0x17830800, //saw_register_addr + 0x400, //saw_register_size + 1, //saw_enable + 1, //saw_ctl_sel + 0, //saw_tmr_clk_div + 1, //saw_vlvl_width + 1, //saw_vlvl_step_up + 1, //saw_vlvl_step_dn + //--------------------------------------------------------------------------------------------------------------------- + // Thread 0 SW Setting + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 0, "Gold", 2, 2, 0, 2, }, + }, + }, + Package(){ + "CPRH_CHIP_INFO", + 321, // chip ID + 2, // chip version + //----------------------------------------------------------------------------------------- + // APC Controller SW Setting + // ------------------------- + // + //----------------------------------------------------------------------------------------- + Package(){ + "CPRH_SW_CONTROLLER_SETTING", + 0, //instance_num (doc: CPR SW) + "APC0", //rail_name (doc: voltage plan) + 0x17DC0000, //cpr_register_addr (doc: SWI) + 0x4000, //cpr_register_size (doc: SWI) + 0, //count_mode (doc: voltage plan) + 20, //count_repeat (doc: voltage plan) + 15, //idle_clocks (doc: voltage plan) + 12, //step_quot_max (doc: voltage plan) + 11, //step_quot_min (doc: voltage plan) + 1, //reset_step_quot_loop_en (doc: voltage plan) - TBD + 8, //number_of_sensors (doc: HPG) + 0xf0, //sensor_thread_mask (doc: HPG) L3 using sensor #0,1,2,3 + 0, //sensor_mask (doc: voltage plan) + 0, //sensor_bypass (doc: voltage plan) + 0x17700, //auto_cont_interval (doc: voltage plan) //5ms + 400, //base_voltage_mV (doc: CPR SW) + 4, //voltage_multiplier (doc: CPR HPG) + 4, //target_multiplier (doc: CPR HPG) + 5, //mode_switch_timer (doc: voltage plan) + 0, //initial_mode (doc: CPR HPG) + 1, //temp_sensor_id_start (doc: CPR HPG) + 5, //temp_sensor_id_end (doc: CPR HPG) + 1, //error_step_limit_dn (doc: voltage plan) + 1, //error_step_limit_up (doc: voltage plan) + 1, //thread_aggregation_enable (doc: CPR HPG) + 1, //thread_has_always_vote (doc: CPR HPG) + 23, //1.2us/19.2MHz MarginTimerSettleVoltage (doc: CPR HPG) - TBD - PMIC delay for one step / CPR clock period + 0x4b00, //MarginTimerLowerVoltage (doc: CPR HPG) + //Below are temp adj related - Setting to zero for now. + 0, //MarginInitialTempBand; (doc: voltage plan) + 4, //MarginMaxNumCores; (doc: CPUSS HPG) + 1, //MarginLowerVoltageWaitSelect; (doc: CPR HPG) + 4, //MarginPmicStepSize; (doc: PMIC HPG) + 1, //MarginClosedLoopEn; (doc: CPR HPG) + 0, //MarginCoreAdjEn; (doc: CPR HPG) + 0, //MarginTempAdjEn; (doc: CPR HPG) + //--------------------------------------------------------------------------------------------------------------------- + // Aging Setting + // ------------ + "", //aging_rail_id (doc: power grid) + 0, //aging_thread_index (doc: n/a) + 0, //aging_measurement_voltage_mV (doc: voltage plan) + 0, //aging_sensor_id (doc: voltage plan) + 0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan) + 0, //derate_scaling_factor (doc: voltage plan) + 0, //max_age_compensation (mV) (doc: voltage plan) + 0, //bypass_sensor (doc: voltage plan) + //--------------------------------------------------------------------------------------------------------------------- + // SAW4 Setting + // ------------ + 0x17840800, //saw_register_addr + 0x400, //saw_register_size + 1, //saw_enable + 1, //saw_ctl_sel + 0, //saw_tmr_clk_div + 1, //saw_vlvl_width + 1, //saw_vlvl_step_up + 1, //saw_vlvl_step_dn + //--------------------------------------------------------------------------------------------------------------------- + // Thread 0 SW Setting //TBD - Voltage plan does not have entries for L3 for settings below + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 0, "L3", 2, 2, 0, 0, }, + //--------------------------------------------------------------------------------------------------------------------- + // Thread 1 SW Setting + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 1, "Silver", 2, 2, 0, 0, }, + }, + Package(){ + "CPRH_SW_CONTROLLER_SETTING", + 1, //instance_num + "APC1", //rail_name + 0x17DB0000, //cpr_register_addr + 0x4000, //cpr_register_size + 0, //count_mode + 20, //count_repeat + 15, //idle_clocks + 14, //step_quot_max + 9, //step_quot_min + 1, //reset_step_quot_loop_en //TBD + 14, //number_of_sensors + 0, //sensor_thread_mask //Assigning to thread0 + 0, //sensor_mask + 0, //sensor_bypass + 0x17700, //auto_cont_interval + 400, //base_voltage_mV + 4, //voltage_multiplier + 4, //target_multiplier + 5, //mode_switch_timer + 0, //initial_mode + 6, //temp_sensor_id_start + 10, //temp_sensor_id_end + 1, //error_step_limit_dn + 1, //error_step_limit_up + 0, //thread_aggregation_enable + 0, //thread_has_always_vote (doc: CPR HPG) + 23, //1.2us/19.2MHz MarginTimerSettleVoltage + 0x4b00, //MarginTimerLowerVoltage + //Below are temp adj related - Setting to zero for now. + 0, //MarginInitialTempBand; + 4, //MarginMaxNumCores; + 1, //MarginLowerVoltageWaitSelect; + 4, //MarginPmicStepSize; + 1, //MarginClosedLoopEn; + 0, //MarginCoreAdjEn; + 0, //MarginTempAdjEn; + //--------------------------------------------------------------------------------------------------------------------- + // Aging Setting + // ------------ + "", //aging_rail_id (doc: power grid) + 0, //aging_thread_index (doc: n/a) + 0, //aging_measurement_voltage_mV (doc: voltage plan) + 0, //aging_sensor_id (doc: voltage plan) + 0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan) + 0, //derate_scaling_factor (doc: voltage plan) + 0, //max_age_compensation (mV) (doc: voltage plan) + 0, //bypass_sensor (doc: voltage plan) + //--------------------------------------------------------------------------------------------------------------------- + // SAW4 Setting + // ------------ + 0x17830800, //saw_register_addr + 0x400, //saw_register_size + 1, //saw_enable + 1, //saw_ctl_sel + 0, //saw_tmr_clk_div + 1, //saw_vlvl_width + 1, //saw_vlvl_step_up + 1, //saw_vlvl_step_dn + //--------------------------------------------------------------------------------------------------------------------- + // Thread 0 SW Setting + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 0, "Gold", 2, 2, 0, 2, }, + }, + }, + Package(){ + "CPRH_CHIP_INFO", + 341, // chip ID + 1, // chip version + //----------------------------------------------------------------------------------------- + // APC Controller SW Setting + // ------------------------- + // + //----------------------------------------------------------------------------------------- + Package(){ + "CPRH_SW_CONTROLLER_SETTING", + 0, //instance_num (doc: CPR SW) + "APC0", //rail_name (doc: voltage plan) + 0x17DC0000, //cpr_register_addr (doc: SWI) + 0x4000, //cpr_register_size (doc: SWI) + 0, //count_mode (doc: voltage plan) + 20, //count_repeat (doc: voltage plan) + 15, //idle_clocks (doc: voltage plan) + 12, //step_quot_max (doc: voltage plan) + 11, //step_quot_min (doc: voltage plan) + 1, //reset_step_quot_loop_en (doc: voltage plan) - TBD + 8, //number_of_sensors (doc: HPG) + 0xf0, //sensor_thread_mask (doc: HPG) L3 using sensor #0,1,2,3 + 0, //sensor_mask (doc: voltage plan) + 0, //sensor_bypass (doc: voltage plan) + 0x17700, //auto_cont_interval (doc: voltage plan) //5ms + 400, //base_voltage_mV (doc: CPR SW) + 4, //voltage_multiplier (doc: CPR HPG) + 4, //target_multiplier (doc: CPR HPG) + 5, //mode_switch_timer (doc: voltage plan) + 0, //initial_mode (doc: CPR HPG) + 1, //temp_sensor_id_start (doc: CPR HPG) + 5, //temp_sensor_id_end (doc: CPR HPG) + 1, //error_step_limit_dn (doc: voltage plan) + 1, //error_step_limit_up (doc: voltage plan) + 1, //thread_aggregation_enable (doc: CPR HPG) + 1, //thread_has_always_vote (doc: CPR HPG) + 23, //1.2us/19.2MHz MarginTimerSettleVoltage (doc: CPR HPG) - TBD - PMIC delay for one step / CPR clock period + 0x4b00, //MarginTimerLowerVoltage (doc: CPR HPG) + //Below are temp adj related - Setting to zero for now. + 0, //MarginInitialTempBand; (doc: voltage plan) + 4, //MarginMaxNumCores; (doc: CPUSS HPG) + 1, //MarginLowerVoltageWaitSelect; (doc: CPR HPG) + 4, //MarginPmicStepSize; (doc: PMIC HPG) + 1, //MarginClosedLoopEn; (doc: CPR HPG) + 0, //MarginCoreAdjEn; (doc: CPR HPG) + 0, //MarginTempAdjEn; (doc: CPR HPG) + //--------------------------------------------------------------------------------------------------------------------- + // Aging Setting + // ------------ + "", //aging_rail_id (doc: power grid) + 0, //aging_thread_index (doc: n/a) + 0, //aging_measurement_voltage_mV (doc: voltage plan) + 0, //aging_sensor_id (doc: voltage plan) + 0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan) + 0, //derate_scaling_factor (doc: voltage plan) + 0, //max_age_compensation (mV) (doc: voltage plan) + 0, //bypass_sensor (doc: voltage plan) + //--------------------------------------------------------------------------------------------------------------------- + // SAW4 Setting + // ------------ + 0x17840800, //saw_register_addr + 0x400, //saw_register_size + 1, //saw_enable + 1, //saw_ctl_sel + 0, //saw_tmr_clk_div + 1, //saw_vlvl_width + 1, //saw_vlvl_step_up + 1, //saw_vlvl_step_dn + //--------------------------------------------------------------------------------------------------------------------- + // Thread 0 SW Setting //TBD - Voltage plan does not have entries for L3 for settings below + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 0, "Silver", 2, 2, 0, 0, }, + //--------------------------------------------------------------------------------------------------------------------- + // Thread 1 SW Setting + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 1, "L3", 2, 2, 0, 0, }, + }, + Package(){ + "CPRH_SW_CONTROLLER_SETTING", + 1, //instance_num + "APC1", //rail_name + 0x17DB0000, //cpr_register_addr + 0x4000, //cpr_register_size + 0, //count_mode + 20, //count_repeat + 15, //idle_clocks + 14, //step_quot_max + 9, //step_quot_min + 1, //reset_step_quot_loop_en //TBD + 14, //number_of_sensors + 0, //sensor_thread_mask //Assigning to thread0 + 0, //sensor_mask + 0, //sensor_bypass + 0x17700, //auto_cont_interval + 400, //base_voltage_mV + 4, //voltage_multiplier + 4, //target_multiplier + 5, //mode_switch_timer + 0, //initial_mode + 6, //temp_sensor_id_start + 10, //temp_sensor_id_end + 1, //error_step_limit_dn + 1, //error_step_limit_up + 0, //thread_aggregation_enable + 0, //thread_has_always_vote (doc: CPR HPG) + 23, //1.2us/19.2MHz MarginTimerSettleVoltage + 0x4b00, //MarginTimerLowerVoltage + //Below are temp adj related - Setting to zero for now. + 0, //MarginInitialTempBand; + 4, //MarginMaxNumCores; + 1, //MarginLowerVoltageWaitSelect; + 4, //MarginPmicStepSize; + 1, //MarginClosedLoopEn; + 0, //MarginCoreAdjEn; + 0, //MarginTempAdjEn; + //--------------------------------------------------------------------------------------------------------------------- + // Aging Setting + // ------------ + "", //aging_rail_id (doc: power grid) + 0, //aging_thread_index (doc: n/a) + 0, //aging_measurement_voltage_mV (doc: voltage plan) + 0, //aging_sensor_id (doc: voltage plan) + 0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan) + 0, //derate_scaling_factor (doc: voltage plan) + 0, //max_age_compensation (mV) (doc: voltage plan) + 0, //bypass_sensor (doc: voltage plan) + //--------------------------------------------------------------------------------------------------------------------- + // SAW4 Setting + // ------------ + 0x17830800, //saw_register_addr + 0x400, //saw_register_size + 1, //saw_enable + 1, //saw_ctl_sel + 0, //saw_tmr_clk_div + 1, //saw_vlvl_width + 1, //saw_vlvl_step_up + 1, //saw_vlvl_step_dn + //--------------------------------------------------------------------------------------------------------------------- + // Thread 0 SW Setting + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 0, "Gold", 2, 2, 0, 2, }, + }, + }, + Package(){ + "CPRH_CHIP_INFO", + 341, // chip ID + 2, // chip version + //----------------------------------------------------------------------------------------- + // APC Controller SW Setting + // ------------------------- + // + //----------------------------------------------------------------------------------------- + Package(){ + "CPRH_SW_CONTROLLER_SETTING", + 0, //instance_num (doc: CPR SW) + "APC0", //rail_name (doc: voltage plan) + 0x17DC0000, //cpr_register_addr (doc: SWI) + 0x4000, //cpr_register_size (doc: SWI) + 0, //count_mode (doc: voltage plan) + 20, //count_repeat (doc: voltage plan) + 15, //idle_clocks (doc: voltage plan) + 12, //step_quot_max (doc: voltage plan) + 11, //step_quot_min (doc: voltage plan) + 1, //reset_step_quot_loop_en (doc: voltage plan) - TBD + 8, //number_of_sensors (doc: HPG) + 0xf0, //sensor_thread_mask (doc: HPG) L3 using sensor #0,1,2,3 + 0, //sensor_mask (doc: voltage plan) + 0, //sensor_bypass (doc: voltage plan) + 0x17700, //auto_cont_interval (doc: voltage plan) //5ms + 400, //base_voltage_mV (doc: CPR SW) + 4, //voltage_multiplier (doc: CPR HPG) + 4, //target_multiplier (doc: CPR HPG) + 5, //mode_switch_timer (doc: voltage plan) + 0, //initial_mode (doc: CPR HPG) + 1, //temp_sensor_id_start (doc: CPR HPG) + 5, //temp_sensor_id_end (doc: CPR HPG) + 1, //error_step_limit_dn (doc: voltage plan) + 1, //error_step_limit_up (doc: voltage plan) + 1, //thread_aggregation_enable (doc: CPR HPG) + 1, //thread_has_always_vote (doc: CPR HPG) + 23, //1.2us/19.2MHz MarginTimerSettleVoltage (doc: CPR HPG) - TBD - PMIC delay for one step / CPR clock period + 0x4b00, //MarginTimerLowerVoltage (doc: CPR HPG) + //Below are temp adj related - Setting to zero for now. + 0, //MarginInitialTempBand; (doc: voltage plan) + 4, //MarginMaxNumCores; (doc: CPUSS HPG) + 1, //MarginLowerVoltageWaitSelect; (doc: CPR HPG) + 4, //MarginPmicStepSize; (doc: PMIC HPG) + 1, //MarginClosedLoopEn; (doc: CPR HPG) + 0, //MarginCoreAdjEn; (doc: CPR HPG) + 0, //MarginTempAdjEn; (doc: CPR HPG) + //--------------------------------------------------------------------------------------------------------------------- + // Aging Setting + // ------------ + "", //aging_rail_id (doc: power grid) + 0, //aging_thread_index (doc: n/a) + 0, //aging_measurement_voltage_mV (doc: voltage plan) + 0, //aging_sensor_id (doc: voltage plan) + 0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan) + 0, //derate_scaling_factor (doc: voltage plan) + 0, //max_age_compensation (mV) (doc: voltage plan) + 0, //bypass_sensor (doc: voltage plan) + //--------------------------------------------------------------------------------------------------------------------- + // SAW4 Setting + // ------------ + 0x17840800, //saw_register_addr + 0x400, //saw_register_size + 1, //saw_enable + 1, //saw_ctl_sel + 0, //saw_tmr_clk_div + 1, //saw_vlvl_width + 1, //saw_vlvl_step_up + 1, //saw_vlvl_step_dn + //--------------------------------------------------------------------------------------------------------------------- + // Thread 0 SW Setting //TBD - Voltage plan does not have entries for L3 for settings below + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 0, "Silver", 2, 2, 0, 0, }, + //--------------------------------------------------------------------------------------------------------------------- + // Thread 1 SW Setting + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 1, "L3", 2, 2, 0, 0, }, + }, + Package(){ + "CPRH_SW_CONTROLLER_SETTING", + 1, //instance_num + "APC1", //rail_name + 0x17DB0000, //cpr_register_addr + 0x4000, //cpr_register_size + 0, //count_mode + 20, //count_repeat + 15, //idle_clocks + 14, //step_quot_max + 9, //step_quot_min + 1, //reset_step_quot_loop_en //TBD + 14, //number_of_sensors + 0, //sensor_thread_mask //Assigning to thread0 + 0, //sensor_mask + 0, //sensor_bypass + 0x17700, //auto_cont_interval + 400, //base_voltage_mV + 4, //voltage_multiplier + 4, //target_multiplier + 5, //mode_switch_timer + 0, //initial_mode + 6, //temp_sensor_id_start + 10, //temp_sensor_id_end + 1, //error_step_limit_dn + 1, //error_step_limit_up + 0, //thread_aggregation_enable + 0, //thread_has_always_vote (doc: CPR HPG) + 23, //1.2us/19.2MHz MarginTimerSettleVoltage + 0x4b00, //MarginTimerLowerVoltage + //Below are temp adj related - Setting to zero for now. + 0, //MarginInitialTempBand; + 4, //MarginMaxNumCores; + 1, //MarginLowerVoltageWaitSelect; + 4, //MarginPmicStepSize; + 1, //MarginClosedLoopEn; + 0, //MarginCoreAdjEn; + 0, //MarginTempAdjEn; + //--------------------------------------------------------------------------------------------------------------------- + // Aging Setting + // ------------ + "", //aging_rail_id (doc: power grid) + 0, //aging_thread_index (doc: n/a) + 0, //aging_measurement_voltage_mV (doc: voltage plan) + 0, //aging_sensor_id (doc: voltage plan) + 0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan) + 0, //derate_scaling_factor (doc: voltage plan) + 0, //max_age_compensation (mV) (doc: voltage plan) + 0, //bypass_sensor (doc: voltage plan) + //--------------------------------------------------------------------------------------------------------------------- + // SAW4 Setting + // ------------ + 0x17830800, //saw_register_addr + 0x400, //saw_register_size + 1, //saw_enable + 1, //saw_ctl_sel + 0, //saw_tmr_clk_div + 1, //saw_vlvl_width + 1, //saw_vlvl_step_up + 1, //saw_vlvl_step_dn + //--------------------------------------------------------------------------------------------------------------------- + // Thread 0 SW Setting + // ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn + // ------- --------------- ------------ ------------ -------------- -------------- + Package(){"CPRH_SW_THREAD_SETTING", 0, "Gold", 2, 2, 0, 2, }, + }, + }, + }) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/pep_dbgSettings.asl b/sdm845Pkg/AcpiTables/common/pep_dbgSettings.asl new file mode 100644 index 0000000..8fe637d --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_dbgSettings.asl @@ -0,0 +1,434 @@ +/** + * This file contains debugger and debugger power resource information used by + * the PEP driver. + */ +Scope(\_SB.PEP0) +{ + Method(LDBG){ + return(NDBG) + } + + Name( NDBG, + /** + * The debuggers package is used by PEP to detect when a debugger is connected, + * turn on the required power resources for a debugger and to turn off all + * debugger related resources when not in use (this logic is encompassed in PEP). + * + * The expected hiearchy of this package: + * DEBUGGERS + * TYPE + * String = SERIAL, USB2.0, USB3.0 + * INSTANCES + * The instancepath of the drivers which the debugger impersonates + * DEBUG_ON + * The resources that need to be turned on for the debugger to work + * for the given controller type (SERIAL/USB2.0/USB3.0) + * DEBUG_OFF + * The resources to turn off when no debugger is connected for this + * debugger type and no HLOS driver is loaded for any one of the given + * HLOS types. The implementation for this feature is documented within + * PEP. + * + */ + package(){ + "DEBUGGERS", + package() + { + "TYPE", + "SERIAL", + package() + { + "INSTANCES", + "\\_SB.UARD", + }, + + package() + { + "DEBUG_ON", + /** + * There is a limitation with KDCOM port, if RX engine is runnign when system + * enters deeper sleep mode, the UART can result in undefined behaviour, this may + * could lead to loss of Windbg connection. + **/ + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 1}},// enable clock + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 9,8}},// mark suppressible + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 9,12}},// always ON + + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 9,8 }}, // mark suppressible + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 9,12 }}, // always ON + + //Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk",3,7372800,4}}, //update frequency + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 9,8}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 9,12}}, + + Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 10000000,1666,"HLOS_DRV", "SUPPRESSIBLE"}}, + Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 10000000,5000000,"HLOS_DRV", "SUPPRESSIBLE"}}, + }, + + package() + { + "DEBUG_OFF", + } + }, + + // Secondary USB Port Debugger + package() + { + "TYPE", + "USB2.0", + package() + { + "INSTANCES", + "\\_SB.USB1", + //URS1 specific + //"\\_SB.URS1", + }, + + package() + { + "DEBUG_ON", + + package() + { + // L12 - VDDA_QUSB_HS0_1P8 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @ 3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + // Mark Always ON for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 12,}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + + // Mark Suppressible for gcc_aggre_usb3_sec_axi_clk + package() { "CLOCK", package() { "gcc_aggre_usb3_sec_axi_clk", 9, 8,}}, + // Mark Always ON for gcc_aggre_usb3_sec_axi_clk + package() { "CLOCK", package() { "gcc_aggre_usb3_sec_axi_clk", 9, 12,}}, + //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}}, + + // Mark Suppressible for gcc_cfg_noc_usb3_sec_axi_clk + package() { "CLOCK", package() { "gcc_cfg_noc_usb3_sec_axi_clk", 9, 8,}}, + // Mark Always ON for gcc_cfg_noc_usb3_sec_axi_clk + package() { "CLOCK", package() { "gcc_cfg_noc_usb3_sec_axi_clk", 9, 12,}}, + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}}, + + // Mark Suppressible for gcc_usb30_sec_master_clk + package() { "CLOCK", package() { "gcc_usb30_sec_master_clk", 9, 8,}}, + // Mark Always ON for gcc_usb30_sec_master_clk + package() { "CLOCK", package() { "gcc_usb30_sec_master_clk", 9, 12,}}, + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}}, + + // Mark Suppressible for gcc_usb3_sec_phy_aux_clk + package() { "CLOCK", package() { "gcc_usb3_sec_phy_aux_clk", 9, 8,}}, + // Mark Always ON for gcc_usb3_sec_phy_aux_clk + package() { "CLOCK", package() { "gcc_usb3_sec_phy_aux_clk", 9, 12,}}, + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + + // Mark Suppressible for gcc_usb_phy_cfg_ahb2phy_clk + package() { "CLOCK", package() { "gcc_usb_phy_cfg_ahb2phy_clk", 9, 8,}}, + // Mark Always ON for gcc_usb_phy_cfg_ahb2phy_clk + package() { "CLOCK", package() { "gcc_usb_phy_cfg_ahb2phy_clk", 9, 12,}}, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps + 0, // AB=0 MBps + "HLOS_DRV", // Optional: DRV Id + "SUPPRESSIBLE", // Optional: Set Type + } + }, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640, // AB=5Gbps + "HLOS_DRV", // Optional: DRV Id + "SUPPRESSIBLE", // Optional: Set Type + } + }, + + //Nominal==block vdd_min: + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}}, + }, + package() + { + "DEBUG_OFF", + } + }, + + package() + { + "TYPE", + "USB3.0", + package() + { + "INSTANCES", + "\\_SB.URS0", + }, + + package() + { + "DEBUG_ON", + // LDO1, 26, 12, 24 + + package() + { + // L12 - VDDA_QUSB_HS0_1P8 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @ 3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + // Mark Always ON for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 12,}}, + + // Mark Suppressible for gcc_aggre_usb3_prim_axi_clk + package() { "CLOCK", package() { "gcc_aggre_usb3_prim_axi_clk", 9, 8,}}, + // Mark Always ON for gcc_aggre_usb3_prim_axi_clk + package() { "CLOCK", package() { "gcc_aggre_usb3_prim_axi_clk", 9, 12,}}, + //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}}, + + // Mark Suppressible for gcc_cfg_noc_usb3_prim_axi_clk + package() { "CLOCK", package() { "gcc_cfg_noc_usb3_prim_axi_clk", 9, 8,}}, + // Mark Always ON for gcc_cfg_noc_usb3_prim_axi_clk + package() { "CLOCK", package() { "gcc_cfg_noc_usb3_prim_axi_clk", 9, 12,}}, + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}}, + + // Mark Suppressible for gcc_usb30_prim_master_clk + package() { "CLOCK", package() { "gcc_usb30_prim_master_clk", 9, 8,}}, + // Mark Always ON for gcc_usb30_prim_master_clk + package() { "CLOCK", package() { "gcc_usb30_prim_master_clk", 9, 12,}}, + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}}, + + // Mark Suppressible for gcc_usb3_prim_phy_aux_clk + package() { "CLOCK", package() { "gcc_usb3_prim_phy_aux_clk", 9, 8,}}, + // Mark Always ON for gcc_usb3_prim_phy_aux_clk + package() { "CLOCK", package() { "gcc_usb3_prim_phy_aux_clk", 9, 12,}}, + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + + // Mark Suppressible for gcc_usb_phy_cfg_ahb2phy_clk + package() { "CLOCK", package() { "gcc_usb_phy_cfg_ahb2phy_clk", 9, 8,}}, + // Mark Always ON for gcc_usb_phy_cfg_ahb2phy_clk + package() { "CLOCK", package() { "gcc_usb_phy_cfg_ahb2phy_clk", 9, 12,}}, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps + 0, // AB=0 MBps + "HLOS_DRV", // Optional: DRV Id + "SUPPRESSIBLE", // Optional: Set Type + } + }, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640, // AB=5Gbps + "HLOS_DRV", // Optional: DRV Id + "SUPPRESSIBLE", // Optional: Set Type + } + }, + + //Nominal==block vdd_min: + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}}, + + }, + package() + { + "DEBUG_OFF", + } + }, + }) +} diff --git a/sdm845Pkg/AcpiTables/common/pep_dcvscfg.asl b/sdm845Pkg/AcpiTables/common/pep_dcvscfg.asl new file mode 100644 index 0000000..9bbb892 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_dcvscfg.asl @@ -0,0 +1,194 @@ +Scope(\_SB.PEP0) +{ +// CPU DCVS Configurations Packages + Name(NDCV, + Package () + { + Package() //MSM v1 + { + "CHIP_INFO", + 321, // chip ID + 1, // chip major version + 0, // chip minor version + + 2, //Total number of CPU domain + + Package() // Big Cluster configuration + { + "BIG", // Type of cluster + 4, //Number of cores perf cluster. + "apcs_gold_sysleaf_clk", + Package(){300, 1037, 1574}, //Cpu Key Frequency + 3, // Number of Efficient Performance Levels + Package(){0, 9, 16}, //Cpu Efficient Performance Levels + }, + + Package() // Little Cluster configuration + { + "LITTLE", //Type of cluster + 4, //Number of cores perf cluster. + "apcs_silver_sysleaf_clk", + Package(){300, 1210, 1594}, //Cpu Key Frequency + 3, // Number of Efficient Performance Levels + Package(){0, 11, 16}, //Cpu Efficient Performance Levels + }, + + Package() // L3_CACHE domain configuration + { + "L3_CACHE", //Type of cluster + "apcs_l3_sysleaf_clk", //Clock ID. If this is NULL/0, that means no L3 domain supported on this platform + }, + }, + + Package() //MSM v2 + { + "CHIP_INFO", + 321, // chip ID + 2, // chip major version + 0, // chip minor version + + 2, //Total number of CPU domain + + Package() // Big Cluster configuration + { + "BIG", // Type of cluster + 4, //Number of cores perf cluster. + "apcs_gold_sysleaf_clk", + Package(){826, 1363, 1460}, //Cpu Key Frequency + 3, // Number of Efficient Performance Levels + Package(){0, 7, 15}, //Cpu Efficient Performance Levels + }, + + Package() // Little Cluster configuration + { + "LITTLE", //Type of cluster + 4, //Number of cores perf cluster. + "apcs_silver_sysleaf_clk", + Package(){300, 1229, 1325}, //Cpu Key Frequency + 3, // Number of Efficient Performance Levels + Package(){0, 11, 15}, //Cpu Efficient Performance Levels + }, + + Package() // L3_CACHE domain configuration + { + "L3_CACHE", //Type of cluster + "apcs_l3_sysleaf_clk", //Clock ID. If this is NULL/0, that means no L3 domain supported on this platform + }, + }, + + Package() //APQ v1 + { + "CHIP_INFO", + 341, // chip ID + 1, // chip major version + 0, // chip minor version + + 2, //Total number of CPU domain + + Package() // Big Cluster configuration + { + "BIG", // Type of cluster + 4, //Number of cores perf cluster. + "apcs_gold_sysleaf_clk", + Package(){300, 1037, 1574}, //Cpu Key Frequency + 3, // Number of Efficient Performance Levels + Package(){0, 9, 16}, //Cpu Efficient Performance Levels + }, + + Package() // Little Cluster configuration + { + "LITTLE", //Type of cluster + 4, //Number of cores perf cluster. + "apcs_silver_sysleaf_clk", + Package(){300, 1210, 1594}, //Cpu Key Frequency + 3, // Number of Efficient Performance Levels + Package(){0, 11, 16}, //Cpu Efficient Performance Levels + }, + + Package() // L3_CACHE domain configuration + { + "L3_CACHE", //Type of cluster + "apcs_l3_sysleaf_clk", //Clock ID. If this is NULL/0, that means no L3 domain supported on this platform + }, + }, + + Package() //APQ v2 + { + "CHIP_INFO", + 341, // chip ID + 2, // chip major version + 0, // chip minor version + + 2, //Total number of CPU domain + + Package() // Big Cluster configuration + { + "BIG", // Type of cluster + 4, //Number of cores perf cluster. + "apcs_gold_sysleaf_clk", + Package(){826, 1363, 1460}, //Cpu Key Frequency + 3, // Number of Efficient Performance Levels + Package(){0, 7, 15}, //Cpu Efficient Performance Levels + }, + + Package() // Little Cluster configuration + { + "LITTLE", //Type of cluster + 4, //Number of cores perf cluster. + "apcs_silver_sysleaf_clk", + Package(){300, 1229, 1325}, //Cpu Key Frequency + 3, // Number of Efficient Performance Levels + Package(){0, 11, 15}, //Cpu Efficient Performance Levels + }, + + Package() // L3_CACHE domain configuration + { + "L3_CACHE", //Type of cluster + "apcs_l3_sysleaf_clk", //Clock ID. If this is NULL/0, that means no L3 domain supported on this platform + }, + }, + + Package() //MSM v2 + { + "CHIP_INFO", + 348, // chip ID + 2, // chip major version + 0, // chip minor version + + 2, //Total number of CPU domain + + Package() // Big Cluster configuration + { + "BIG", // Type of cluster + 4, //Number of cores perf cluster. + "apcs_gold_sysleaf_clk", + Package(){826, 1363, 1460}, //Cpu Key Frequency + 3, // Number of Efficient Performance Levels + Package(){0, 7, 15}, //Cpu Efficient Performance Levels + }, + + Package() // Little Cluster configuration + { + "LITTLE", //Type of cluster + 4, //Number of cores perf cluster. + "apcs_silver_sysleaf_clk", + Package(){300, 1229, 1325}, //Cpu Key Frequency + 3, // Number of Efficient Performance Levels + Package(){0, 11, 15}, //Cpu Efficient Performance Levels + }, + + Package() // L3_CACHE domain configuration + { + "L3_CACHE", //Type of cluster + "apcs_l3_sysleaf_clk", //Clock ID. If this is NULL/0, that means no L3 domain supported on this platform + }, + }, + + }) //End of NDCV method + + // Method to return DCVS configuration packages + Method(LDCV) + { + return(NDCV) + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/pep_dvreg.asl b/sdm845Pkg/AcpiTables/common/pep_dvreg.asl new file mode 100644 index 0000000..6f24ca3 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_dvreg.asl @@ -0,0 +1,101 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contains the default discrete VREG mapping and method names +// +// +//=========================================================================== + +// NOTE: this file is included in the platform level pep.asl and can be replaced with platform +// specific discrete VREG definitions + +Scope(\_SB.PEP0) +{ + // Discrete Vreg Mapping Package + Name(DVMP, + Package() + { + // Virtual regulator to aggregate GPIO pin control of CHIP_PWD_L + // CHIP_PWD_L must be deasserted for BT to share a clock with AR6004 + // BT and WLAN devices will take a vote on this virtual regulator to + // control the shared GPIO pin + Package() + { + "PPP_RESOURCE_ID_PMIC_GPIO_DV1", // Discrete Vreg ID + "PPP_RESOURCE_TYPE_DISCRETE_PMIC_GPIO", // Vreg type + Package() + { + "PM_DISCRETE_VREG_STATE_ON", // Mapping for VREG ON + package() + { + 0, // pmic_number (PM8994) - must match pmic.asl + 8,// gpio_id - GPIO #9 + 0, // Mode - GPIO configured as output - 0, 1 for input + 0, // voltage_source - PM_GPIO_VIN0 + 1, // source - PM_GPIO_SOURCE_1 (drive logic HIGH) + 0, // out_buffer_config - PM_GPIO_OUT_BUFFER_CONFIG_CMOS + 1, // out_buffer_strength - PM_GPIO_OUT_BUFFER_LOW + 0, // inversion ?no invert + 1, // External pin enable - PM_GPIO_PERPH_EN_ENABLE + 5, // PM_GPIO_I_SOURCE_PULL_NO_PULL, ignored for Output mode. + }, + }, + Package() + { + "PM_DISCRETE_VREG_STATE_OFF", // Mapping for VREG OFF + package() + { + 0, // pmic_number 0 + 8,// gpio_id - GPIO #9 + 0, // Mode - GPIO configured as output - 0, 1 for input + 0, // voltage_source - PM_GPIO_VIN0 + 0, // source - PM_GPIO_SOURCE_0 (drive logic LOW) + 0, // out_buffer_config - PM_GPIO_OUT_BUFFER_CONFIG_CMOS + 1, // out_buffer_strength - PM_GPIO_OUT_BUFFER_LOW + 0, // inversion ?no invert + 1, // External pin enable - PM_GPIO_PERPH_EN_ENABLE + 5, // PM_GPIO_I_SOURCE_PULL_NO_PULL, ignored for Output mode. + }, + }, + }, + //discrete vreg vote for MPP4 + Package() + { + "PPP_RESOURCE_ID_PMIC_MPP_DV1", // Discrete Vreg ID + "PPP_RESOURCE_TYPE_DISCRETE_PMIC_MPP", // Vreg type + Package() + { + "PM_DISCRETE_VREG_STATE_ON", // Mapping for VREG ON + package() + { + 0, // PMIC number + 3, // MPP index (mpp #4) + 0, // Direction, 0 - output + 2, // VIO_2 + 1, // PM_MPP__DLOGIC__OUT_CTRL_HIGH + 0, // PM_MPP__DLOGIC__DBUS_NONE + }, + }, + Package() + { + "PM_DISCRETE_VREG_STATE_OFF", // Mapping for VREG OFF + package() + { + 0, // PMIC number + 3, // MPP index (mpp #4) + 0, // Direction, 0 - output + 2, // VIO_2 + 0, // PM_MPP__DLOGIC__OUT_CTRL_LOW + 0, // PM_MPP__DLOGIC__DBUS_NONE + }, + }, + }, + }) + + // Method to return Discrete Vreg Mapping Package + Method(DVMM) + { + Return(DVMP) + } +} + diff --git a/sdm845Pkg/AcpiTables/common/pep_idle.asl b/sdm845Pkg/AcpiTables/common/pep_idle.asl new file mode 100644 index 0000000..d5586ff --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_idle.asl @@ -0,0 +1,1242 @@ + +Scope(\_SB.PEP0) +{ + + Method(UIDL) + { + Return(NIDL) + } + + Name(NIDL, + package(){ + "MICROPEP_IDLE", + 0x1, + + package(){ + "LPR", + "KryoSilver0", // LPR Name + 0x0, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x0, //LastMan Adder + + package(){ + "MODE", + "C1", // Mode name + 0, // Mode Latency + 0, // Mode BreakEven + 0, // Mode Flags + 0, // Mode Clock Flags + 0x00000000, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C2d", // Mode name + 1000, // Mode Latency + 4000, // Mode BreakEven + 0x0, // Mode Flags + 0, // Mode Clock Flags + 0x00000002, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3", // Mode name + 3000, // Mode Latency + 4500, // Mode BreakEven + 0x3, // Mode Flags + 0, // Mode Clock Flags + 0x40000003, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3_NI", // Mode name + 3000, // Mode Latency + 4500, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000004, // Mode PSCI Flags + + }, + + }, + + package(){ + "LPR", + "KryoSilver1", // LPR Name + 0x1, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x0, //LastMan Adder + + package(){ + "MODE", + "C1", // Mode name + 0, // Mode Latency + 0, // Mode BreakEven + 0, // Mode Flags + 0, // Mode Clock Flags + 0x00000000, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C2d", // Mode name + 1000, // Mode Latency + 4000, // Mode BreakEven + 0x0, // Mode Flags + 0, // Mode Clock Flags + 0x00000002, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3", // Mode name + 3000, // Mode Latency + 4500, // Mode BreakEven + 0x3, // Mode Flags + 0, // Mode Clock Flags + 0x40000003, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3_NI", // Mode name + 3000, // Mode Latency + 4500, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000004, // Mode PSCI Flags + + }, + + }, + + package(){ + "LPR", + "KryoSilver2", // LPR Name + 0x2, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x0, //LastMan Adder + + package(){ + "MODE", + "C1", // Mode name + 0, // Mode Latency + 0, // Mode BreakEven + 0, // Mode Flags + 0, // Mode Clock Flags + 0x00000000, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C2d", // Mode name + 1000, // Mode Latency + 4000, // Mode BreakEven + 0x0, // Mode Flags + 0, // Mode Clock Flags + 0x00000002, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3", // Mode name + 3000, // Mode Latency + 4500, // Mode BreakEven + 0x3, // Mode Flags + 0, // Mode Clock Flags + 0x40000003, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3_NI", // Mode name + 3000, // Mode Latency + 4500, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000004, // Mode PSCI Flags + + }, + + }, + + package(){ + "LPR", + "KryoSilver3", // LPR Name + 0x3, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x0, //LastMan Adder + + package(){ + "MODE", + "C1", // Mode name + 0, // Mode Latency + 0, // Mode BreakEven + 0, // Mode Flags + 0, // Mode Clock Flags + 0x00000000, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C2d", // Mode name + 1000, // Mode Latency + 4000, // Mode BreakEven + 0x0, // Mode Flags + 0, // Mode Clock Flags + 0x00000002, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3", // Mode name + 3000, // Mode Latency + 4500, // Mode BreakEven + 0x3, // Mode Flags + 0, // Mode Clock Flags + 0x40000003, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3_NI", // Mode name + 3000, // Mode Latency + 4500, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000004, // Mode PSCI Flags + + }, + + }, + + package(){ + "LPR", + "KryoGold0", // LPR Name + 0x4, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x0, //LastMan Adder + + package(){ + "MODE", + "C1", // Mode name + 0, // Mode Latency + 0, // Mode BreakEven + 0, // Mode Flags + 0, // Mode Clock Flags + 0x00000000, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C2d", // Mode name + 800, // Mode Latency + 6000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x00000002, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3", // Mode name + 900, // Mode Latency + 70000, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000003, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3_NI", // Mode name + 900, // Mode Latency + 70000, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000004, // Mode PSCI Flags + + }, + + }, + + package(){ + "LPR", + "KryoGold1", // LPR Name + 0x5, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x0, //LastMan Adder + + package(){ + "MODE", + "C1", // Mode name + 0, // Mode Latency + 0, // Mode BreakEven + 0, // Mode Flags + 0, // Mode Clock Flags + 0x00000000, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C2d", // Mode name + 800, // Mode Latency + 6000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x00000002, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3", // Mode name + 900, // Mode Latency + 70000, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000003, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3_NI", // Mode name + 900, // Mode Latency + 70000, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000004, // Mode PSCI Flags + + }, + + }, + + package(){ + "LPR", + "KryoGold2", // LPR Name + 0x6, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x0, //LastMan Adder + + package(){ + "MODE", + "C1", // Mode name + 0, // Mode Latency + 0, // Mode BreakEven + 0, // Mode Flags + 0, // Mode Clock Flags + 0x00000000, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C2d", // Mode name + 800, // Mode Latency + 6000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x00000002, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3", // Mode name + 900, // Mode Latency + 70000, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000003, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3_NI", // Mode name + 900, // Mode Latency + 70000, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000004, // Mode PSCI Flags + + }, + + }, + + package(){ + "LPR", + "KryoGold3", // LPR Name + 0x7, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x0, //LastMan Adder + + package(){ + "MODE", + "C1", // Mode name + 0, // Mode Latency + 0, // Mode BreakEven + 0, // Mode Flags + 0, // Mode Clock Flags + 0x00000000, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C2d", // Mode name + 800, // Mode Latency + 6000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x00000002, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3", // Mode name + 900, // Mode Latency + 70000, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000003, // Mode PSCI Flags + + }, + + package(){ + "MODE", + "C3_NI", // Mode name + 900, // Mode Latency + 70000, // Mode BreakEven + 0x13, // Mode Flags + 0, // Mode Clock Flags + 0x40000004, // Mode PSCI Flags + + }, + + }, + + package(){ + "LPR", + "L2_Silver", // LPR Name + 0xFFFFFFFF, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x1000000, //LastMan Adder + + package(){ + "MODE", + "D2d", // Mode name + 1300, // Mode Latency + 3000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x20, // Mode PSCI Flags + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver0", // Dependency LPR + "C1", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver0", // Dependency LPR + "C2d", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver0", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver0", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver1", // Dependency LPR + "C1", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver1", // Dependency LPR + "C2d", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver1", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver1", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver2", // Dependency LPR + "C1", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver2", // Dependency LPR + "C2d", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver2", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver2", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver3", // Dependency LPR + "C1", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver3", // Dependency LPR + "C2d", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver3", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver3", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + + }, + + package(){ + "MODE", + "D2e", // Mode name + 1500, // Mode Latency + 3500, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x30, // Mode PSCI Flags + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver0", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver0", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver1", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver1", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver2", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver2", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver3", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver3", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + + }, + + package(){ + "MODE", + "D4", // Mode name + 9000, // Mode Latency + 64000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x40, // Mode PSCI Flags + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver0", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver0", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver1", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver1", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver2", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver2", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoSilver3", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoSilver3", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + + }, + + }, + + package(){ + "LPR", + "L2_Gold", // LPR Name + 0xFFFFFFFF, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x1000000, //LastMan Adder + + package(){ + "MODE", + "D2d", // Mode name + 2000, // Mode Latency + 9000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x20, // Mode PSCI Flags + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold0", // Dependency LPR + "C1", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold0", // Dependency LPR + "C2d", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold0", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold0", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold1", // Dependency LPR + "C1", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold0", // Dependency LPR + "C2d", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold1", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold1", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold2", // Dependency LPR + "C1", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold0", // Dependency LPR + "C2d", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold2", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold2", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold3", // Dependency LPR + "C1", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold0", // Dependency LPR + "C2d", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold3", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold3", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + + }, + + package(){ + "MODE", + "D2e", // Mode name + 4000, // Mode Latency + 10000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x30, // Mode PSCI Flags + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold0", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold0", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold1", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold1", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold2", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold2", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold3", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold3", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + + }, + + package(){ + "MODE", + "D4", // Mode name + 12000, // Mode Latency + 60000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x40, // Mode PSCI Flags + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold0", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold0", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold1", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold1", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold2", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold2", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "KryoGold3", // Dependency LPR + "C3", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "KryoGold3", // Dependency LPR + "C3_NI", // Dependency Mode + 7, // Dependency Type + }, + + }, + + + }, + + }, + + package(){ + "LPR", + "CCI", // LPR Name + 0xFFFFFFFF, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x2000000, //LastMan Adder + + package(){ + "MODE", + "E1", // Mode name + 5000, // Mode Latency + 26000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x100, // Mode PSCI Flags + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "L2_Silver", // Dependency LPR + "D2e", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "L2_Silver", // Dependency LPR + "D4", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "L2_Gold", // Dependency LPR + "D2e", // Dependency Mode + 7, // Dependency Type + }, + + package(){ + "DEPENDENCY", + "L2_Gold", // Dependency LPR + "D4", // Dependency Mode + 7, // Dependency Type + }, + + }, + + + }, + + package(){ + "MODE", + "E3", // Mode name + 11000, // Mode Latency + 30000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x400, // Mode PSCI Flags + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "L2_Silver", // Dependency LPR + "D4", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "L2_Gold", // Dependency LPR + "D4", // Dependency Mode + 7, // Dependency Type + }, + + }, + + + }, + + package(){ + "MODE", + "E3+RPM", // Mode name + 11500, // Mode Latency + 35000, // Mode BreakEven + 0x10, // Mode Flags + 0, // Mode Clock Flags + 0x500, // Mode PSCI Flags + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "L2_Silver", // Dependency LPR + "D4", // Dependency Mode + 7, // Dependency Type + }, + + }, + + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "L2_Gold", // Dependency LPR + "D4", // Dependency Mode + 7, // Dependency Type + }, + + }, + + + }, + + }, + + package(){ + "LPR", + "platform", // LPR Name + 0xFFFFFFFF, // LPR Core Mask (0xFFFFFFFF is coordinated) + 0x0, //LastMan Adder + + package(){ + "MODE", + "xo", // Mode name + 5000, // Mode Latency + 330000, // Mode BreakEven + 32, // Mode Flags + 0x10, // Mode Clock Flags + 0xFFFFFE00, // Mode PSCI Flags + package(){ + "DEPENDENCY_CONTAINER", + + package(){ + "DEPENDENCY", + "CCI", // Dependency LPR + "E3+RPM", // Dependency Mode + 7, // Dependency Type + }, + + }, + + + }, + + }, + + }) + +} + diff --git a/sdm845Pkg/AcpiTables/common/pep_libPCU.asl b/sdm845Pkg/AcpiTables/common/pep_libPCU.asl new file mode 100644 index 0000000..846ff87 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_libPCU.asl @@ -0,0 +1,28 @@ +Scope(\_SB.PEP0) +{ + Method(LPCU){ + return(NPCU) + } + + Name( NPCU, package(){ + "PCU_CONFIG", + 9, // number of cores + 1, // number of clusters + package(){ + "PCU_CLUSTER_CONFIG", + 9, + }, + package(){ + "PCU_PHYS_CONFIG", + 0x17E00040, // Core 0 + 0x17E10040, // Core 1 + 0x17E20040, // Core 2 + 0x17E30040, // Core 3 + 0x17E40040, // Core 4 + 0x17E50040, // Core 5 + 0x17E60040, // Core 6 + 0x17E70040, // Core 7 + 0x17810104, // L3 + } + }) +} diff --git a/sdm845Pkg/AcpiTables/common/pep_libPdc.asl b/sdm845Pkg/AcpiTables/common/pep_libPdc.asl new file mode 100644 index 0000000..3375e70 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_libPdc.asl @@ -0,0 +1,61 @@ +Scope(\_SB.PEP0) +{ + Method(LPDC){ + return(NPDC) + } + + Name( NPDC, package(){ + + package(){ + "INTERRUPT_CONFIG", + package(){ + /// Data Format: + /// { INDEX , LOCAL_IRQ, IRQ_TYPE, TRIGGER_TYPE, [optional] FLAGS } + /// + /// @param INDEX THIS IS ZERO BASED INDEX UNIQUE and INCREASING ORDER. + /// @param LOCAL_IRQ GPIO or QGIC IRQ number + /// @param IRQ_TYPE 0 for QGIC, 1 for GPIO + /// + /// @param TRIGGER_TYPE 0-4; Set when MPM is init; will be overriden by HLOS values + /// 0 = LEVEL_LOW + /// 1 = RISING_EDGE + /// 2 = FALLING_EDGE + /// 3 = DUAL_EDGE + /// 4 = LEVEL HIGH + /// + /// @param [opt] FLAGS 0-16 reference: file pdc_types.h + /// 0 = No Flags set (default) + /// 1 = Don't Program with HLOS given trigger type - instead use default PDC configuration + /// 2 = Program with Static trigger type + /// 4 = Forcefully disable pdc interrupt + /// 8 = Ignore OS sent Polarity configuration for PDC interrupt - instead use either default polarity or let it get updated internally + /// 16 = Ignore OS sent Mode configuration for PDC interrupt - instead use either default polarity or let it get updated internally + + // Tsens Wake able interrupts + // // Mandatory wake-capable Tsens interrupts + package(){ 0, 538, 0, 1 }, // tsense0_upper_lower_intr + package(){ 1, 539, 0, 1 }, // tsense1_upper_lower_intr + package(){ 2, 540, 0, 1 }, // tsense0_critical_intr + package(){ 3, 541, 0, 1 }, // tsense1_critical_intr + // // Preferable wake-capable interrupts (in the event Tsens use them for debugging min/max shutdowns) + package(){ 4, 536, 0, 1 }, // tsense0_tsense_max_min_int + package(){ 5, 537, 0, 1 }, // tsense1_tsense_max_min_int + + + // USB wakeup interrupts + // to be used in Host mode ( WD ) for device detection and + // wake up from suspend in SS and HS modes on Xo shutdown + Cx collapse. + package(){ 6, 518, 0, 1 }, // qmp_usb3_lfps_rxterm_irq USB SS Primary + package(){ 7, 519, 0, 1 }, // qmp_usb3_lfps_rxterm_irq USB SS Secondary + package(){ 8, 520, 0, 1 , 8}, // eud_p0_dmse_int_mx + package(){ 9, 521, 0, 1 , 8}, // eud_p0_dpse_int_mx + package(){10, 522, 0, 1 , 8}, // eud_p1_dmse_int_mx + package(){11, 523, 0, 1 , 8}, // eud_p1_dpse_int_mx + + // PMIC wakeup interrupt -- + // (Power Key button) + package(){12, 513, 0, 4 }, // ee0_apps_hlos_spmi_periph_irq + } + }, + }) +} diff --git a/sdm845Pkg/AcpiTables/common/pep_lmh.asl b/sdm845Pkg/AcpiTables/common/pep_lmh.asl new file mode 100644 index 0000000..3d2e723 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_lmh.asl @@ -0,0 +1,32 @@ +Scope(\_SB.PEP0) +{ + + Method(LLMH){ + return(NLMH) + } + Name( NLMH, package(){ + + package(){ + "PEP_LMH_CFG", + package(){ + 0, //SILVER_CLUSTER + 0, // 0 = SIMPLE_STEP_ALGO, 1 = TOCKEN_BUCKET_ALGO + 2995200, //Domain Max frequency for Silver cluster + 3330, //ARM Threshold in 10s K + 3675, //LOW Threshold in 10s K + 3680, //HIGH Threshold in 10s K + }, + + package(){ + 1, //GOLD_CLUSTER + 0, // 0 = SIMPLE_STEP_ALGO, 1 = TOCKEN_BUCKET_ALGO + 2995200, //Domain Max frequency for Gold cluster + 3330, //ARM Threshold in 10s K + 3675, //LOW Threshold in 10s K + 3680, //HIGH Threshold in 10s K + }, + }, + }) + + +} diff --git a/sdm845Pkg/AcpiTables/common/pep_resources.asl b/sdm845Pkg/AcpiTables/common/pep_resources.asl new file mode 100644 index 0000000..4aa3ba9 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_resources.asl @@ -0,0 +1,108 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by pep drivers. +// +// +//=========================================================================== + + + +Scope(\_SB_.PEP0) +{ + + // PEP + Method(PPMD) + { + Return(PPCC) + } + + Name(PPCC, + Package () + { + // PEP Proxy Driver + Package(){ + "DEVICE", + "\\_SB.PRXY", + Package(){ + "COMPONENT", + 0, + // F-State placeholders + Package(){ "FSTATE", 0, }, + }, + }, + // PEP Stats Driver + Package(){ + "DEVICE", + "\\_SB.STAT", + Package(){ + "COMPONENT", + 0, + // F-State placeholders + Package(){ "FSTATE", 0, }, + }, + }, + // Claim GPIO Device to enable wake up from XO etc + Package() + { + //GPIO + "DEVICE", + 0x81, // TransferrableIOIrq + "\\_SB.GIO0", + Package() + { + "COMPONENT", + 0, + // F-State placeholders + Package() {"FSTATE",0,}, + }, + Package() + { + "COMPONENT", + 1, + // F-State placeholders + Package() {"FSTATE",0}, + }, + }, + + }) + // System Default Resources Packages + Name(SDFR, + Package() + { + //System Resources + Package(){ + "DEVICE", + "\\_SB.SDFR", + + Package(){ + "COMPONENT", + 0, + Package(){ + "FSTATE", + 0, + // Place any resources required for nominal operation + // SDF will choose either Nominal or SVS at boot + }, + Package(){ + "FSTATE", + 1, + // Place any resources required for SVS operation + // SDF will choose either Nominal or SVS at boot + }, + Package(){ + "FSTATE", + 2, + // Common SDF resources; will be set when PEP finishes + // parsing standard ACPI resources + + }, + Package(){ + "FSTATE", + 3, + //Low Power Pad Settings + }, + }, + }, + }) +} diff --git a/sdm845Pkg/AcpiTables/common/pep_tsens.asl b/sdm845Pkg/AcpiTables/common/pep_tsens.asl new file mode 100644 index 0000000..6eb73a2 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_tsens.asl @@ -0,0 +1,233 @@ + + +Scope(\_SB.PEP0) +{ + Method(CTSN) + { + return (THSD) + } + + Method(PEPH) + { + Return(Package() + { + "HID_PEP0", + }) + } + + Method(BCLH) + { + Return(Package() + { + "HID_TZ_BCL", + }) + } + + // Thermal sensors PL specific configurations + Name(THSD, + + Package() + { + // Below package contains a list of all the identified physical thermal sensors mapped to unique HIDs + // + Package() + { + 21, //Total number of thermal physical sensors + + // sensor HID, sensor number associated to HID + Package() {"HID_TSENS0", 0}, + Package() {"HID_TSENS1", 1}, + Package() {"HID_TSENS2", 2}, + Package() {"HID_TSENS3", 3}, + Package() {"HID_TSENS4", 4}, + Package() {"HID_TSENS5", 5}, + Package() {"HID_TSENS6", 6}, + Package() {"HID_TSENS7", 7}, + Package() {"HID_TSENS8", 8}, + Package() {"HID_TSENS9", 9}, + Package() {"HID_TSENS10", 10}, + Package() {"HID_TSENS11", 11}, + Package() {"HID_TSENS12", 12}, + Package() {"HID_TSENS13", 13}, + package() {"HID_TSENS14", 14}, + Package() {"HID_TSENS15", 15}, + Package() {"HID_TSENS16", 16}, + Package() {"HID_TSENS17", 17}, + Package() {"HID_TSENS18", 18}, + Package() {"HID_TSENS19", 19}, + Package() {"HID_TSENS20", 20}, + }, + + // TSENSLIST Package + // This package contains "lists" of thermal sensors + // each list maps to a virtual thermal sensor + // Always the first package should be BIG CPU, second one is LITTLE CPU and third one is ALL CPU SENSOR lists. + // Do not interchage inside packages. Always add new sensor list package at the end. + + Package() + { + 3, //Number of virtual sensors. + + Package() // sensors associated with Little CPU + { + "HID_TZ_LITTLE_CPU_VIRT", + 21, // virtual sensor ID + 5, //Little cpu sensors + Package () {1, 2, 3, 4, 5}, + }, + + Package() // sensors associated with Big CPU + { + "HID_TZ_BIG_CPU_VIRT", + 22, // virtual sensor ID + 5, //Big cpu sensors + Package () {6, 7, 8, 9, 10}, // as per thermal floor plan + }, + + Package() // All MSM sensors + { + "HID_TZ_CRT_TEMP_VIRT", + 23, // virtual sensor ID + 21, //It should be total number of sensors. + Package () {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20}, + }, + }, + + // Sensor HID to Vadc thermistor mapping package + // INX and this needs to be in sync + // channel list/names need to obtained from tsens team + Package () + { + 10, //Number of VADC channels + + // channels name sensor HID, Sensor number ADC type + Package() {"SYS_THERM1", "HID_VADC_SENS0", 0, 0}, //vadc = 0, rradc = 1 + Package() {"SYS_THERM2", "HID_VADC_SENS1", 1, 0 }, + Package() {"PA_THERM", "HID_VADC_SENS2", 2, 0 }, + Package() {"PA_THERM1", "HID_VADC_SENS3", 3, 0 }, + Package() {"SYS_THERM3", "HID_VADC_SENS4", 4, 0 }, + Package() {"PMIC_THERM", "HID_VADC_SENS5", 5, 0 }, + Package() {"SKIN_THERM", "HID_VADC_SENS6", 6, 1 }, + Package() {"PMIC_TEMP2", "HID_VADC_SENS7", 7, 1 }, + Package() {"CHG_TEMP", "HID_VADC_SENS8", 8, 1 }, + Package() {"BATT_THERM", "HID_VADC_SENS9", 9, 1 }, + }, + + // Thermal Restriction data package + // high/low trigger point for each thermal restriction + // ID has to match to one of below enum from PEP_Themal_common.h + //typedef enum _INT_RESTR_ID + //{ + // FAST_THERMAL_MTG_RESTR_B_ID = 0x01, //Throttle just the big cluster to NOM + // LOW_TEMP_VOLTAGE_RESTR_ID = 0x02, //Vdd restriction at < 5C + // HIGH_TEMP_BOOST_RESTR_ID = 0x03, //Unused- Turn off Correlation + // NORMAL_TEMP_CL_RESTR_ID = 0x04, //8909 - Current Limiting - Disabled + // HIGH_TEMP_CL_RESTR_ID = 0x05, //8909 - Current Limiting - Disabled + // VERY_HIGH_TEMP_CL_RESTR_ID = 0x06, //8909 - Current Limiting - Disabled + // MAX_PERF_LIMITING_RESTR_ID = 0x7, //8994 - Num cores based perf limiting + // FAST_THERMAL_MTG_RESTR_L_ID = 0x8, //Throttle Little clusters to NOM + // INVALID_RESTR_ID = 0xffffffff, + //} INT_RESTR_ID, *PINT_RESTR_ID; + // + + Package () + { + 1, // number of Thermal Restrictions + Package () + { + 2, // tsensList. 2 indicates third package in TSENSLIST Package. In this case its All CPU sensors list + 2780, // Restriction ON temperature. ACPI uses 10s of K as temperatures, so 0C = 2730 ACPI UNITS. 2730+50=2780. + 2830, // Restriction OFF temperature. 100 + 2730 = 2830. + 2, // 2 - LOW_TEMP_VOLTAGE_RESTR_ID, Vdd restriction at < 5C + 1, // Restriction enabled = 1, disabled = 0. + }, + }, + + //QMI clients + Package () + { + 4, // Number Of QMI Clients. + Package () + { + "cpuv_restriction_cold", //mitigation device name + 1, //restriction ON = 1 and RESTRICTN OFF = 0 + 0, //MODEM QMI INSTANCE ID = 0 + }, + Package () + { + "cpuv_restriction_cold", //mitigation device name + 1, //restriction ON = 1 and RESTRICTN OFF = 0 + 1, //ADSP QMI INSTANCE ID = 1 + }, + Package () + { + "cpuv_restriction_cold", //mitigation device name + 1, //restriction ON = 1 and RESTRICTN OFF = 0 + 0x43, //CDSP QMI INSTANCE ID = 0x43 + }, + Package () + { + "cpuv_restriction_cold", //mitigation device name + 1, //restriction ON = 1 and RESTRICTN OFF = 0 + 0x53, //SLPI QMI INSTANCE ID = 0x53 + }, + }, + + // PPP PMIC VREG clients: ACPI is being parsed in the order defined in PEP_Thermal_Common.h + // Client info will be parsed incorrectly, if this package is removed. + Package () + { + 0, + }, + + // LTVR Package having 3 sub-packages: + // 1) Rail type from enum RAIL_TYPE in PEP_Thermal_Common.h + // 2) Voting type - available options are EnableKraitVFC(0), VoteViaPPP(1), VoteViaQMI(2), VoteViaAOP(3) and VoteViaCallBackObj(4) + // 3) Client subpackage number for Voting type clients package + // VoteViaAOP + // AOP does not require rail type to vote during LTVR. + // It just needs an event with value on or off and it places NOM vote on cx, mx & ebi. + // Only cx is added to get callback in LTVR. + // VoteViaCallBackObj + // LTVR callback notifies to all the registered clients. it is independent of rail type and voting type. + // + + Package () // LTVR VFC vote table + { + 7, // Available Rails + Package() { 0, //KRAIT = 0, + 0, //EnableKraitVFC = 0 + 0, // NULL + }, + Package() { 1, //CX = 1, + 3, //VoteViaAOP = 3 + 0, // NULL : Client data is not required; + }, + Package() { 3, //MSS = 3, + 2, //VoteViaQMI = 2 + 0, // 0 represents first package in QMI clients list + }, + Package() { 4, //ADSP = 4, + 2, //VoteViaQMI = 2 + 1, // 1 represents second package in QMI clients list + }, + Package() { 6, //CDSP = 6, + 2, //VoteViaQMI = 2 + 2, // 2 represents third package in QMI clients + }, + Package() { 8, //SLPI = 8, + 2, //VoteViaQMI = 2 + 3, // 3 represents forth package in QMI clients + }, + Package() { 2, //GFX = 2, NOP because call backs will be notified for all the registered clients. + // No need for separate rail entry for each of the rails which are relying on call backs. + 4, //VoteViaCallBackObj = 4. + 0, // NOP. + }, + } + } + ) +} + + + \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/pep_vddresources.asl b/sdm845Pkg/AcpiTables/common/pep_vddresources.asl new file mode 100644 index 0000000..3210718 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pep_vddresources.asl @@ -0,0 +1,50 @@ +//Cx & Mx supported vlvl +//RAIL_VOLTAGE_LEVEL_OFF = 0, +//RAIL_VOLTAGE_LEVEL_RETENTION = 16, +//RAIL_VOLTAGE_LEVEL_SVS_LOW = 64, +//RAIL_VOLTAGE_LEVEL_SVS = 128, +//RAIL_VOLTAGE_LEVEL_SVS_HIGH = 192, +//RAIL_VOLTAGE_LEVEL_NOMINAL = 256, +//RAIL_VOLTAGE_LEVEL_NOMINAL_HIGH = 320, +//RAIL_VOLTAGE_LEVEL_TURBO = 384, +//RAIL_VOLTAGE_LEVEL_TURBO_L1 = 384, + +// XO supported vlvl +//XO_LEVEL_CRYSTAL_OFF = 0x0, +//XO_LEVEL_PMIC_BUFFER_OFF = 0x20, +//XO_LEVEL_SOC_BUFFER_OFF = 0x50, +//XO_LEVEL_ON = 0x80, + +Scope(\_SB.PEP0) +{ + + Method(LVDD){ + return(NVDD) + } + Name( NVDD, package(){ + package(){ + "/arc/client/rail_cx", // Resource name + "RAIL_VOLTAGE_LEVEL_NOMINAL", // Initial value + }, + package(){ + "/arc/client/display/rail_cx", // Resource name + "RAIL_VOLTAGE_LEVEL_OFF", // Initial value + }, + package(){ + "/arc/client/rail_mx", // Resource name + "RAIL_VOLTAGE_LEVEL_NOMINAL", // Initial value + }, + package(){ + "/arc/client/display/rail_mx", // Resource name + "RAIL_VOLTAGE_LEVEL_OFF", // Initial value + }, + package(){ + "/arc/client/rail_xo", // Resource name + "XO_LEVEL_ON", // Initial value + }, + package(){ + "/arc/client/display/rail_xo", // Resource name + "XO_LEVEL_CRYSTAL_OFF", // Initial value + }, + }) +} diff --git a/sdm845Pkg/AcpiTables/common/pmic_batt.asl b/sdm845Pkg/AcpiTables/common/pmic_batt.asl new file mode 100644 index 0000000..0b87fd2 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pmic_batt.asl @@ -0,0 +1,496 @@ +// This file contains the Power Management IC (PMIC) +// ACPI device definitions, configuration and look-up tables. +// + +// Include("cust_pmic_batt.asl") + +// // +// //PMIC EIC +// // +// Device (PEIC) +// { + // Name (_HID, "HID_PEIC") + // Method (_CRS, 0x0, NotSerialized) { + // Name (RBUF, ResourceTemplate () { + // // SMB1380 + // I2CSerialBus( 0x08, , 400000,AddressingMode7Bit, "\\_SB.I2C7",,,,) + // }) + // Return (RBUF) + // } + // Method (PMCF) { + // Name (CFG0, + // Package(){ + // // Charger Info + // 0, // I2c Index - Resource Index + // 2, // Charger IC Type - PLAT_CONFIG_CHG_IC_SMB1380 + // }) + // Return (CFG0) + // } +// } + +// // +// //PMIC Battery Manger Driver +// // + // Device (PMBT) { + // Name (_HID, "HID_PMBT") + // Name (_DEP, Package(0x3) { + // \_SB_.PMIC, + // \_SB_.ADC1, + // \_SB_.PEIC + // }) + // Method (_CRS, 0x0, NotSerialized) { + // Name (RBUF, ResourceTemplate () + // { + // //GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,) {208} // 0x80 - PM_INT__SCHG_CHGR__CHGR_ERROR_RT_STS - Charger Error Interrupt + // //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {336} // 0x210 - PM_INT__FG_BCL__IBT_HI - IBAT greater than threshold Interrupt. + // //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {337} // 0x211 - PM_INT__FG_BCL__IBT_THI - VBatt less than threshold Interrupt + // //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {352} // 0x220 - PM_INT__FG_MEM_IF__IMA_RDY - MEMIF access Interrupt + // //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {215} // 0x87 - PM_INT__SCHG_CHGR__CHGR_7 - Termination Current Interrupt + // //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {209} // 0x81 - PM_INT__SCHG_CHGR__CHARGING_STATE_CHANGE - Charger Inhibit Interrupt + // GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {329} // 0x209 - PM_INT__FG_BATT_INFO__VBT_LOW - VBAT_LOW Interrupt + // //GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,) {240} // 0xA0 - PM_INT__SCHG_DC__DCIN_COLLAPSE - Qi Wireless Charger Interrupt + // GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {331} // 0x20B - PM_INT__FG_BATT_INFO__BT_MISS - BATT_MISSING Interrupt + // GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {237} // 0x9D - PM_INT__SCHG_USB__USBIN_SOURCE_CHANGE - AICL_DONE IRQ (Rising Only) + // //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {232} // 0x98 - PM_INT__SCHG_USB__USBIN_COLLAPSE - USB_UV IRQ (Rising Only) + // //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {322} // 0x202 - PM_INT__FG_BATT_SOC__BSOC_DELTA - FULL_SOC Interrupt + // //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {323} // 0x203 - PM_INT__FG_BATT_SOC__MSOC_DELTA - EMPTY_SOC Interrupt + // // GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {213} // 0x85 - PM_INT__SCHG_CHGR__FG_FVCAL_QUALIFIED - FVCAL_QUALIFIED IRQ + // GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {224} // 0x90 - PM_INT__SCHG_BATIF__BAT_TEMP - Jeita limit interrupt + // }) + // Return (RBUF) + // } + + // //ACPI methods for Battery Manager Device + // Method (BMNR) { + // Name (CFG0, + // Package(){ + // 1, //* 0: Select Platform: 0- No HW, 1- SMChg+FGGge, 2- SMB3pChg+SMB3pGge, 3- LBChg+VMBMS + // 0, //* 1: Error State Handling: 0- Don’t Shutdown, 1- Shutdown + // 1, //* 2: Listen to BatteryClass: 0- No 1- Yes + // 0, //* 3: Test Mode Power Flag: 0- Discharging, 1- PowerOnline+Charging + // "CUST_PMIC" //* 4: cust_pmic config identifier + // }) + // Store(CUST, Index(CFG0, 4)) + // Return (CFG0) + // } + // //ACPI methods for Timer + + // Method (BTIM) { + // Name (CFG0, + // Package(){ + // 30000, // Charging Heartbeat Timer + // 10000, // Charging Tolerable Delay + // 300000, // Discharging Heartbeat Timer + // 120000, // Discharging Tolerable Delay + // 0, // Poll Timer , 0=Timer not used. + // 0, // Poll Tolerable Delay + // 28080000, //Charging Timeout (TDone) Timer + // 0, //Charging Timeout(TDone) Tolerable Delay + // }) + // Return (CFG0) + // } + +// // + // //ACPI methods for Battery Info + // Method (BBAT) { + // Name (CFG0, + // Package(){ + // 1, //* 0: Battery Technology + // 0x4C494F4E, //* 1: Battery Chemistry: hex(LION) + // 0xFFFFFFFF, //* 2: BFCC: (mWh), Design Capacity + // 0xFFFFFFFF, //* 3: BFCC: (mWh), Full Charge Capacity + // 0xFFFFFFFF, //* 4: PCT1: (% of FCC), Default Alert 1 + // 0xFFFFFFFF, //* 5: PCT2: (% of FCC), Default Alert 2 + // "QCOMBATT01", //* 6: Device Name + // "Qualcomm", //* 7: Manufacture Name + // "QCOMBAT01_07012011", //* 8: Battery Unique ID + // "07012011", //* 9: Battery Serial Number + // 19, //* 10: Battery Manufacture Date + // 04, //* 11: Battery Manufacture Month + // 2014 //* 12: Battery Manufacture Year + // }) + // //Local2 = Default Alert1 = PCT1 * BFCC / 100 + // Multiply(PCT1,BFCC,Local0) + // Divide(Local0, 100, Local1, Local2) + // //Local3 = Default Alert2 = PCT2 * BFCC / 100 + // Multiply(PCT2,BFCC,Local0) + // Divide(Local0, 100, Local1, Local3) + // Store(BFCC, Index(CFG0, 2)) + // Store(BFCC, Index(CFG0, 3)) + // Store(Local2, Index(CFG0, 4)) + // Store(Local3, Index(CFG0, 5)) + // Return (CFG0) + // } + + // //ACPI methods for Proprietary chargers + // Method (BPCH) { + // Name (CFG0, + // Package(){ + // 1500, // QC2.0 charger current = 1500mA + // 1500, // QC3.0 charger current = 1500mA + // 1500 // Invalid Wall charger current = 1500mA + // }) + // Return (CFG0) + // } + + // //ACPI methods for foldback chargers + // Method (BFCH) { + // Name (CFG0, + // Package(){ + // 1, // Feature enable/disable + // 5, // No of consecutive times charger attach/detach + // 5000, // msecs, Time elapsed between attach/detach + // 900, // mA, Current setting for foldback charger + // }) + // Return (CFG0) + // } + + // //ACPI methods for coin cell charger + // Method (BCCC) { + // Name (CFG0, + // Package(){ + // 1, //Enable coin cell charger; 1 = enable, 0 = disable + // 0, // RSET, 0=2K1, 1=1K7, 2=1K2, 3 = 0K8 + // 0 // VSET, 0=2V5, 1=3V2, 2=3V1, 3=3V0 + // }) + // Return (CFG0) + // } + + // //ACPI methods for Recharge/Maintenance Mode + // Method (BRCH) { + // Name (CFG0, + // Package(){ + // 100, // Delta V Recharge threshold = 100mV + // 0 // Delta V Recharge Reduction below Normal= 0mV + // }) + // Return (CFG0) + // } + + // //ACPI methods for Qi Charging + // Method (_BQI) { + // Name (CFG0, + // Package(){ + // 0, + // }) + // Return (CFG0) + // } + + // //ACPI methods for Interrupt Name + // Method (BIRQ) { + // Name (CFG0, + // Package(){ + // //"ChgError", //Charger Error + // //"BclIrq1", //IBAT greater than threshold IRQ + // //"BclIrq2", // VBAT less than threshold IRQ + // //"MEMIFaccess", //MEMIF access granted IRQ + // //"TccReached", // Termination Current IRQ + // // "ChargerInhibit" // Charger Inhibit IRQ + // "VbatLow", // VBAT LOW IRQ + // //"QiWlcDet", // Qi charging + // "BattMissing", // BATT_MISSING IRQ + // // "AiclDone", // AICL Done + // // "UsbUv", //USB UV + // //"SOCFull", //SOC Full IRQ + // //"SOCEmpty", //SOC Empty IRQ + // "FvCal", //FVCAl IRQ + // "JeitaLimit" //JEITA limit IRQ + // }) + // Return (CFG0) + // } + // //ACPI methods for Platform File + // Method (BPLT) { + // Name (CFG0, + // Package(){ + // 1023, //* 0: ACPI Version + // 0xFFFFFFFF, //* 1: VNOM: (mV), Nominal Battery Voltage + // 0xFFFFFFFF, //* 2: VLOW: (mV), Low Battery Voltage + // 0xFFFFFFFF, //* 3: EMPT: (mV), VcutOff + // 0xFFFFFFFF, //* 4: DCMA: (mA), DC Current + // 1, //* 5: ChargePath Priority: Select 0 for DC, 1 for USB + // 50, //* 6: RSLOW for maxFlashCurrentPrediction + // 50, //* 7: RPARA for maxFlashCurrentPrediction + // 5000, //* 8: VINFLASH for maxFlashCurrentPrediction + // 8, //* 9: FlashParam for maxFlashCurrentPrediction + // 1, //* 10: AFP Mode Supported + // 80, //* 11: AFP Trigger Max Battery Temp (+80 deg C) + // 0xFFFFFFEC, //* 12: AFP Trigger Min Battery Temp (-20 deg C) + // 72, //* 13: Watchdog timer in secs + // 100, //* 14: Charger iterm 100 mA for now + // 30, //* 15: SRAM logging timer + // 5, //* 16: VBATT average Window Size + // 6, //* 17: Emergency Shutdown Initial SOC + // 500, //* 18: SoC convergent point + // 126, //* 19: LM_Threshold + // 400, //* 20: MH_Threshold + // 0xFFFFFFFF, //* 21: BOCP: (mA), OCP current used in BCL + // 750, //* 22: soc (75%) below which no soc linearization even in CV charging + // 1, //* 23: BMD - Battery Missing Detection Source when source is attached: BATT_ID (1=BATT_ID, 4=HW Misssing Algorithm) + // 0, //* 24: ibat src sensing : 0 for batfet and 1 for external sensing + // 50, //* 25: IFGD: (mA), FG Iterm delta; (iterm + this value) determines when FG report 100% + // 10, //* 26: VFGD: (mV), CC to CV Vdelta; (Vfloat - this value) determine when FG report 100% + // 1, //* 27: 0 - disable SOC linearization; 1 (nonzero): enable SOC linearization + // 0xFFFFFFEC, //* 28: (Celcius), Temperature threshold do have different SOC slope limiter + // 10, //* 29: (milli%) - SOC slope limiter when charging and at lower temperature than threshold + // 10, //* 30: (milli%) - SOC slope limiter when charging and at higher temperature than threshold + // 10, //* 31: (milli%) - SOC slope limiter when discharging and at lower temperature than threshold + // 10, //* 32: (milli%) - SOC slope limiter when discharging and at higher temperature than threshold + // 1, //* 33: 0 - disable FCC learning; 1 (nonzero): enable FCC leearning + // 150, //* 34: maximum starting SOC (in tenth percent)at which FCC learning would be turned on during charging + // 100, //* 35: maximum allowable decrement (in tenth percent) of battery capacity in FCC learning + // 5, //* 36: maximum allowable increment (in tenth percent) of battery capacity in FCC learning + // 10, //* 37: battery temperature in degree C below which switch to low temp ESR update steps + // 0x02, //* 38: ESR update step tight, (2 * 0.001953 = 0.0039 = 0.4% max change each update) + // 0x33, //* 39: ESR update step broad, (51* 0.001953 = 0.099603 = 10% max change each update) + // 0x02, //* 40: ESR update step tight at low temp (below 10 degree, 0.4% max change each update) + // 0x0A //* 41: ESR update step broad at low temp (below 10 degree, 2% max change each update) + // }) + // Store(VNOM, Index(CFG0, 1)) + // Store(VLOW, Index(CFG0, 2)) + // Store(EMPT, Index(CFG0, 3)) + // Store(DCMA, Index(CFG0, 4)) + // Store(BOCP, Index(CFG0, 21)) + // Store(IFGD, Index(CFG0, 25)) + // Store(VFGD, Index(CFG0, 26)) + // Return (CFG0) + // } + + // //ACPI methods for Platform File + // Method (BPTM) { + // Name (CFG0, + // Package(){ + // 15000, // Emergency Timer + // 0, // Emergency Tolerable Delay + // }) + // Return (CFG0) + // } + + // //ACPI methods for JEITA + // Method (BJTA) { + // Name (CFG0, + // Package(){ + // 2, //* 0: Select JEITA Configuration: 0- No JEITA, 1- SW JEITA, 2- HW JEITA + // 2, //* 1: Temperature Hysteresis (in deg C) + // Package(0xa){0,0,0,0,0,0,0,0,0,0} + // //* 2: Structure for default charge table + // }) + // //Use BCT1 as the Default Charge Table + // Store(\_SB_.PMBT.BCT1, Index(CFG0, 2)) + // Return (CFG0) + // } + + + // //ACPI methods for Battery Error Handling + // Method (BEHC) + // { + // //Actions for Battery Error Handling + // // 0x0 - Do Nothing + // // 0x1 - Reload Charge Table + // // 0x2 - Error Shutdown + // // 0x4 - Emergency Shutdown + // // 0x8 - Enter Test Mode + // Name (CFG0, + // Package(){ + // 1, //1-Feature Enable, 0-Feature Disable + // 0x8, //Action(s) for DEBUG state -> Enter Test Mode + // 0x1, //Action(s) for NORMAL state -> Reload Charge Table + // 0x0, //Action(s) for SMART_AUTHENTICATED state -> Do nothing + // 0x2, //Action(s) for UNKNOWN state -> Error Shutdown + // 0x2, //Action(s) for NOT_PRESENT state -> Error Shutdown + // 0x2, //Action(s) for INVALID state -> Error Shutdown + // 0x4 //Action(s) for OUT_OP_RANGE state -> AFP for out of operational range + // }) + // Return (CFG0) + // } + + // //ACPI methods for Charge Table Management Configuration + // Method (CTMC) + // { + // Name (CFG0, + // Package(){ + // 2000, //* 0: min RID for DEBUG category: 2K + // 14000, //* 1: max RID for DEBUG category: 14K + // 0xFFFFFFFF, //* 2: RID2: min RID for NORMAL category: 15K + // 0xFFFFFFFF, //* 3: RID3: max RID for NORMAL category: 140K + // 240000, //* 4: min RID for SMART category: 240K + // 450000, //* 5: max RID for SMART category: 450K + // 1, //* 6: Number of charging table + // }) + // Store(RID2, Index(CFG0, 2)) + // Store(RID3, Index(CFG0, 3)) + // Return (CFG0) + // } + + // //ACPI methods for Battery #1 (Ascent 860-82209-0000 3450mAh) + // Method (BAT1) + // { + // Name (CFG0, + // Package(){ + // 0, //* 0: Battery Category: 0-NORMAL, 1-SMART + // 0xFFFFFFEC, //* 1: min operating battery temp (-20 deg C) + // 65, //* 2: max operating battery temp (+65 deg C) + // Package(4){0,0,0,0}, //* 3: 128-bit battery info for future expansion + // Package(0xa){0,0,0,0,0,0,0,0,0,0} + // //* 4: Structure for charge table + // }) + // //assign Charge Table to BCT1 + // //Note: If the default charge table and desire charge table are different, + // // Create another table (ex: BCT2) with the same structure as BCT1 and modify BCT1 below with the new table name + // Store(\_SB_.PMBT.BCT1, Index(CFG0, 4)) + + // Return (CFG0) + // } + // Name (BCT1, Package(){ + // 4350, //* 0: (mV), Float Voltage (FV) + // 2100, //* 1: (mA), Full Charge Current (FCC) + // 0, //* 2: (C) hard cold limit - at which temperature charging will be disabled + // 10, //* 3: (C) soft cold limit - at which temperature charge current/float voltage will be reduced to JEITA compensated value + // 45, //* 4: (C) soft hot limit - at which temperature float voltage/charge current will be reduced to JEITA compensated value + // 55, //* 5: (C) hard hot limit - at which temperature charging will be disabled + // 105, //* 6: (mV) Float Voltage compensation (amount of FV reduction) when in battery hot-soft limit + // 0, //* 7: (mV) Float Voltage compensation (amount of FV reduction) when in battery cold-soft limit + // //* notes: put 0 value to disable + // //* These values (10 vs 11) should be the same when HW JEITA is enabled + // 0, //* 8: (mA) Charge Current compensation (amount of CC reduction) when in battery hot-soft limit + // 1000, //* 9: (mA) Charge Current compensation (amount of CC reduction) when in battery cold-soft limit + // //* notes: put 0 value to disable + // //* These values (12 vs 13) should be the same when HW JEITA is enabled + // }) + + // //ACPI methods for Parallel Charging + // Method (BMPC) { + // Name (CFG0, + // Package(){ + // 0, //* 0: Feaature Enable. 1: Enabled, 0: Disable + // 0, //* 1: Input Power Disctribution (HW) configuration: 0: MID-MID, 1: USBIN-USBIN + // 7000, //* 2: (mW) Input Power Threshold to decide if parallel charging to be enabled or not + // //* Note: Not applicable for MID-MID configuration + // 1000, //* 3: (mA) Charge Current Threshold to decide if parallel charging to be enabled or not + // 50, //* 4: (%) Slave Charger Initial Power Distribution + // 60, //* 5: (mV) Slave Charger Float Voltage Headroom + // 500, //* 6: (mA) Slave Charger Charge Current Done Threshold + // }) + // Return (CFG0) + // } + // } + +// // +// // PMIC Battery Miniclass Driver +// // + // Device (PMBM) { + // Name (_HID, "HID_PMBM") + // Name (_DEP, Package(0x1) + // { + // \_SB_.PMBT + // }) + + // Method (_CRS, 0x0, NotSerialized) { + // Name (RBUF, ResourceTemplate () { + // }) + // Return (RBUF) + // } + // } + +// +//FGBCL Driver +// +//Device (BCL1) { +// Name (_HID, "HID_BCL1") +// Alias(\_SB.PSUB, _SUB) +// Name (_DEP, Package(0x1) +// { +// \_SB_.PMIC +// }) +// +// Method (_CRS, 0x0, NotSerialized) { +// Name (RBUF, ResourceTemplate () { +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {64} // 0x1E8 - PM_INT__BCL_COMP__VCOMP_LOW0 - VCOMP_LOW0 IRQ +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {65} // 0x1E9 - PM_INT__BCL_COMP__VCOMP_LOW1 - VCOMP_LOW1 IRQ +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {66} // 0x1EA - PM_INT__BCL_COMP__VCOMP_LOW2 - VCOMP_LOW2 IRQ +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {67} // 0x1EB - PM_INT__BCL_COMP__VCOMP_HI - VCOMP_HI IRQ +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {68} // 0x1EC - PM_INT__BCL_COMP__SYS_OK - SYS_OK IRQ +// //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {72} // 0x1F0 - PM_INT__BCL_PLM__VCOMP_LVL0_PLM - LVL0_PLM IRQ +// //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {74} // 0x1F2 -PM_INT__BCL_PLM__VCOMP_LVL2_PLM - LVL2_PLM IRQ +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {75} // 0x1F3 - PM_INT__BCL_PLM__VCOMP_BA - BAN alarm IRQ +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {336} // 0x210 - PM_INT__FG_BCL__IBT_HI - ibatt high IRQ +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {337} // 0x211 - PM_INT__FG_BCL__IBT_THI - ibatt too high IRQ +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {339} // 0x213 - PM_INT__FG_BCL__VBT_LO_CMP - vbatt low irq +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {340} // 0x214 - PM_INT__FG_BCL__VBT_TLO_CMP - vbatt too low irq +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {324} // 0x204 - PM_INT__FG_BATT_SOC__MSOC_LOW - MSOC_Low Interrupt +// GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {326} // 0x206 - PM_INT__FG_BATT_SOC__MSOC_HIGH - MSOC_HI Interrupt +// GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {344} // 0x218 - PM_INT__FG_LMH__LMH_LVL0 - LMH_LVL0 IRQ +// GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {345} // 0x219 - PM_INT__FG_LMH__LMH_LVL1 - LMH_LVL1 IRQ +// GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {346} // 0x21A - PM_INT__FG_LMH__LMH_LVL2 - LMH_LVL2 IRQ +// }) +// Return (RBUF) +// } +// //ACPI methods for FGBCL device +// Method (BCLS) { +// Name (CFG0, +// Package(){ +// 2, //* FGBCL ACPI revision +// 1, //* 0: BCL disabled, 1: vph_pwr bcl enabled, 2: fg vbatt enabled, 4: fg ibatt enabled +// 5000, //* battery ocp current +// 80, //* ibatt high threshold is set to 80 for 80% of OCP +// 90, //* ibatt too high is set to 90 for 90% of OCP +// 3300, //* vbatt low is set to 3300 mV a little higher then Vcutoff +// 2600, //* vbatt too low is set to 2600 mV +// 3200, //* vcomp_low0 threshold is 3200 mv +// 2750, //* vcomp_low1 threshold is 2750 mv +// 2500, //* vcomp_low2 threshold is 2500 mV +// 10 //* poll timer for battery soc polling. +// }) +// Return (CFG0) +// } +// //ACPI methods for Interrupt Name +// Method (BCLQ) { +// Name (CFG0, +// Package(){ +// "VCOMP_LOW0", //vcomp_low0 IRQ +// "VCOMP_LOW1", //vcomp_low1 IRQ +// "VCOMP_LOW2", //vcomp_low2 IRQ +// "VCOMP_HI", //vcomp_hi IRQ +// "SYS_OK", // sys_ok irq +// //"LVL0_PLM", // LVL0_PLM IRQ +// //"LVL1_PLM" // LVL1_PLM IRQ +// //"LVL2_PLM", //LVL2_PLM IRQ +// "BAN_ALARM", // BAN_ALARM IRQ +// // "IBATT_HI", // IBATT HIGH IRQ +// // "IBATT_THI", // IBATT TOO HIGH IRQ +// // "VBATT_LOW", // VBATT_LOW IRQ +// // "VBATT_TLOW", // VBATT TOO LOW IRQ +// // "MSOC_LOW", //monotonic soc low IRQ +// // "MSOC_HI", //monotonic soc high IRQ +// // "LMH_LVL0", //LMH_LVL0 IRQ +// // "LMH_LVL1", //LMH_LVL1 IRQ +// // "LMH_LVL2", //LMH_LVL2 IRQ +// }) +// Return (CFG0) +// } +//} + +// +//PMIC Type-C Controler Driver (PMICTCC) Driver +// +Device(PTCC) +{ + Name (_HID, "HID_PTCC") + Alias(\_SB.PSUB, _SUB) + Name (_DEP, Package(0x1) {\_SB_.PMIC}) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {239} // 0x9F - PM_INT__SCHG_USB__TYPE_C_OR_RID_DETECTION_CHANGE - CC State Changed IRQ + GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {270} // 0xBE - PM_INT__USB_PD__MESSAGE_RX_DISCARDED - Message RX Discarded IRQ + GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {269} // 0xBD - PM_INT__USB_PD__MESSAGE_TX_DISCARDED - Message TX Discarded IRQ + GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {268} // 0xBC - PM_INT__USB_PD__MESSAGE_TX_FAILED - Message TX Failed IRQ + GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {267} // 0xBB - PM_INT__USB_PD__MESSAGE_RECEIVED - Message Received IRQ + GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {266} // 0xBA - PM_INT__USB_PD__MESSAGE_SENT - Message Sent IRQ + GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {265} // 0xB9 - PM_INT__USB_PD__SIGNAL_RECEIVED - Singal Received IRQ + GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {264} // 0xB8 - PM_INT__USB_PD__SIGNAL_SENT - Signal Sent IRQ + GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {217} // 0x89 - PM_INT__SCHG_OTG__OTG_OVERCURRENT - OTG_OC_IRQ + GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {263} // 0xB7 - PM_INT__SCHG_MISC__SWITCHER_POWER_OK - SWITCHER_POWER_OK (CHG_MISC) + GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {235} // 0x9B - PM_INT__SCHG_USB__USBIN_OV - USBIN_OV (CHG_USB) + // GpioIo (Exclusive, PullUp, 0, 0, , "\\_SB.PM01", , , , ) {493} // 0x668 - PM_INT__PM2_GPIO14__GPIO_IN_STS - GPIO14B ?For Type-C Debug Accessory Mode + }) + Return (RBUF) + } +} diff --git a/sdm845Pkg/AcpiTables/common/pmic_core.asl b/sdm845Pkg/AcpiTables/common/pmic_core.asl new file mode 100644 index 0000000..9d966ce --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/pmic_core.asl @@ -0,0 +1,268 @@ +// This file contains common Power Management IC (PMIC) ACPI device definitions +// + +// +// +//PMIC KMDF +// +Device (PMIC) +{ + Name (_DEP, Package(0x1) + { + \_SB_.SPMI + }) + Name (_HID, "HID_PMIC") + Name (_CID, "PNP0CA3") + + Method (PMCF) { + Name (CFG0, + Package() + { + // PMIC Info + 3, // Number of PMICs, must match the number of info packages + Package() + { + 0, + 1, + }, + Package() + { + 2, + 3, + }, + Package() + { + 4, + 5, + }, + }) + Return (CFG0) + } +} + +// +// PMIC GPIO PM8998 +// +Device (PM01) +{ + Name (_HID, "HID_PM01") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + Name (_DEP, + Package(0x1) { + \_SB_.PMIC + } + ) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, + ResourceTemplate() { + // QGIC Interrupt Resource + // Register for SPMI Interrupt 513 + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , ,) {513} + } + ) + Return (RBUF) + } + + // _DSM method to mark PM01's ActiveBoth interrupts + Method(_DSM, 0x4, NotSerialized) { + // DSM UUID + switch(ToBuffer(Arg0)) + { + // ACPI DSM UUID for GPIO + case(ToUUID("4F248F40-D5E2-499F-834C-27758EA1CD3F")) + { + // DSM Function + switch(ToInteger(Arg2)) + { + // Function 0: Return supported functions, based on revision + case(0) + { + // revision 0: function 0 & 1 are supported. + return (Buffer() {0x3}) + } + + // Function 1: For emulated ActiveBoth controllers, returns + // a package of controller-relative pin numbers. + // Each corresponding pin will have an initial + // polarity of ActiveHigh. + case(1) + { + // Marks pins KPDPWR_ON, RESIN_ON to be ActiveHigh. + Return (Package() {0, 1}) + } + + default + { + // Functions 2+: not supported + } + } + } + + default + { + // No other GUIDs supported + Return(Buffer(One) { 0x00 }) + } + } + } +} + +// +// PMIC Apps Driver +// +Device (PMAP) +{ + Name (_HID, "HID_PMAP") + Alias(\_SB.PSUB, _SUB) + Name(_DEP, Package(0x3) { + \_SB_.PMIC, + \_SB.ABD, + \_SB.SCM0 + }) + //PMAP is dependent on ABD for operation region access + + // Get pseudo SPB controller port which is used to handle the ACPI operation region access + Method(GEPT) + { + Name(BUFF, Buffer(4){}) + CreateByteField(BUFF, 0x00, STAT) + CreateWordField(BUFF, 0x02, DATA) + Store(0x2, DATA) + Return(DATA) + } + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + //Interrupts must be in this order to match PmicAppsDevice.c OnPrepareHardware + //LAB Vreg OK interrupt + GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {448} // 0xEF0 - PM_INT__LAB__VREG_OK + //WLED SC fault interrupt + //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {418} // 0xEC2 - PM_INT__WLED_CTRL__SC_FAULT + //IBB SC fault interrupt + //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {434} // 0xEE2 - PM_INT__IBB__SC_ERROR + //LAB SC fault interrupt + //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {449} // 0xEF1 - PM_INT__LAB__SC_ERROR + }) + Return (RBUF) + } +} + +// +// PMIC Apps Real Time Clock (RTC) +// +Device (PRTC) +{ + Name(_HID, "ACPI000E") + Name(_DEP, Package() {"\\_SB.PMAP"}) // PRTC is dependent on PMAP which implements the RTC Functions + + //Get the capabilities of the time and alarm device + Method(_GCP) + { + Return (0x04) //Bit 2 set indicating Get Set Supported + } + + Field(\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve) + { + Connection(I2CSerialBus( 0x0002,,0x0,, "\\_SB.ABD",,,,)), + AccessAs(BufferAcc, AttribRawBytes(24)), + FLD0,192 + } + + Method(_GRT) // Get the Real time + { + Name(BUFF, Buffer(26){}) // 18 bytes STAT(1), SIZE(1), Time(16) + CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time + CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field + CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field + Store(FLD0, BUFF) + Return(TME1) + } + + Method(_SRT, 1) // Set the Real time + { + Name(BUFF, Buffer(50){}) // 18 bytes STAT(1), SIZE(1), Time(16) + CreateByteField(BUFF, 0x0, STAT) // Create the STAT Field + CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time + CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field + CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field + Store(0x0, ACT1) + Store(Arg0, TME1) + Store(0x0, ACW1) + Store(Store(BUFF, FLD0),BUFF) // Write the transaction to the Psuedo I2C Port + + // Return the status + If(LNotEqual(STAT,0x00)) { + Return(1) // Call to OpRegion failed + } + Return(0) //success + } + + // + //Code to enable RTC AC/DC wake timers + // + + // Method(_TIV) // Get the AC TIMER Field + // { + // Name(BUFF, Buffer(26){}) // 18 bytes STAT(1), SIZE(1), Time(16) + // CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time + // CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field + // CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field + // Store(FLD0, BUFF) + // Return(ACT1) + // } + + // Method(_GWS) // Get the AC TIMER Wake Status + // { + // Name(BUFF, Buffer(26){}) // 18 bytes STAT(1), SIZE(1), Time(16) + // CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time + // CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field + // CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field + // Store(FLD0, BUFF) + // Return(ACW1) + // } + + // Method(_STV, 2) // Set alarm timer value + // { + // If(LEqual(Arg0,0x00)) { + // Name(BUFF, Buffer(50){}) // 18 bytes STAT(1), SIZE(1), Time(16) + // CreateByteField(BUFF, 0x0, STAT) // Create the STAT Field + // CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time + // CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field + // CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field + // Store(Arg1, ACT1) + // Store(0x0, TME1) + // Store(0x0, ACW1) + // Store(Store(BUFF, FLD0),BUFF) // Write the transaction to the Psuedo I2C Port + + // // Return the status + // If(LNotEqual(STAT,0x00)) { + // Return(1) // Call to OpRegion failed + // } + // Return(0) //success + // } + // Return(1) + // } + + // Method(_CWS, 1) // Clear wake alarm status + // { + // Name(BUFF, Buffer(50){}) // 18 bytes STAT(1), SIZE(1), Time(16) + // CreateByteField(BUFF, 0x0, STAT) // Create the STAT Field + // CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time + // CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field + // CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field + // Store(0x0, ACT1) + // Store(0x0, TME1) + // Store(Arg0, ACW1) + // Store(Store(BUFF, FLD0),BUFF) // Write the transaction to the Psuedo I2C Port + + // // Return the status + // If(LNotEqual(STAT,0x00)) { + // Return(1) // Call to OpRegion failed + // } + // Return(0) //success + // } +} diff --git a/sdm845Pkg/AcpiTables/common/qcdb.asl b/sdm845Pkg/AcpiTables/common/qcdb.asl new file mode 100644 index 0000000..b2381fc --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qcdb.asl @@ -0,0 +1,8 @@ +// +// Qualcomm DIAG Bridge +// +Device (QCDB) +{ + Name (_HID, "HID_QCDB") + Alias(\_SB.PSUB, _SUB) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/qcgpio.asl b/sdm845Pkg/AcpiTables/common/qcgpio.asl new file mode 100644 index 0000000..094817d --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qcgpio.asl @@ -0,0 +1,44 @@ +// +// TLMM controller. +// +Device (GIO0) +{ + Name (_HID, "HID_GIO0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // TLMM register address space + Memory32Fixed (ReadWrite, 0x03400000, 0x00C00000) + + // Summary Interrupt shared by all banks + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {648} // For PDC Wake up ::TLMM GPIo 126 SD Card Detection + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {568} // For PDC Wake up ::TLMM GPIo 54 + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {646} // For PDC Wake up ::TLMM GPIo 124, Hall sensor used for lid + }) + Return (RBUF) + } + // ACPI method to return Num pins + Method(OFNI, 0x0, NotSerialized) { + Name(RBUF, Buffer() + { + 0x96, // 0: TOTAL_GPIO_PINS + 0x00 // 1: TOTAL_GPIO_PINS + }) + Return (RBUF) + } + + Name(GABL, Zero) + Method(_REG, 0x2, NotSerialized) + { + If(LEqual(Arg0, 0x8)) + { + Store(Arg1, GABL) + } + } +} diff --git a/sdm845Pkg/AcpiTables/common/qcsp.asl b/sdm845Pkg/AcpiTables/common/qcsp.asl new file mode 100644 index 0000000..c8c2c48 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qcsp.asl @@ -0,0 +1,12 @@ +// +// Qualcomm Secure Procesor (QCSP) Driver +// +Device (QCSP) +{ + Name (_DEP, Package(0x1) + { + \_SB_.GLNK + }) + Name (_HID, "HID_QCSP") + Alias(\_SB.PSUB, _SUB) +} diff --git a/sdm845Pkg/AcpiTables/common/qdss_qpmda.asl b/sdm845Pkg/AcpiTables/common/qdss_qpmda.asl new file mode 100644 index 0000000..2838639 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qdss_qpmda.asl @@ -0,0 +1,442 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the QPMDA details needed by qdss driver. +// +//=========================================================================== + +Scope(\_SB.QDSS) +{ + // References: napali_v2.0_p2q0r15.3_partitioned_rtl.FLAT + // http://sew-napali.runq-sd-a-sm.qualcomm.com/prj/qct/chips/napali/sandiego/docs/SWI/HTML/latest_2.0/napali.index.html + // https://sharepoint.qualcomm.com/qct/DHW/Projects/Napali/Documents/Design/debug/TPDM/Napali_TPDM_list.xlsx + // https://sharepoint.qualcomm.com/qct/DHW/Projects/Napali/Documents/Design/debug/SOC%20DEBUG/Napali_ATB_Structure.xlsx + Method (TPDA) + { + Return + ( + Package() + { + // QtfTpdaName Index, positional value is Qdss Id + Package() { "QDSS", 0}, // QDSS Tpda Id 0 QDSS + Package() { "APSS", 6}, // QDSS Tpda Id 1 APSS + Package() { "MSS", 1}, // QDSS Tpda Id 2 MSS + Package() { "NAV", 4}, // QDSS Tpda Id 3 NAV + Package() { "OLC", 9}, // QDSS Tpda Id 4 OLC + Package() { "SP", 3}, // QDSS Tpda Id 5 SP + Package() { "SWAO", 5}, // QDSS Tpda Id 6 SWAO + Package() { "LLMGOLD", 8}, // QDSS Tpda Id 7 LLMGOLD + Package() { "LLMSILVER", 7}, // QDSS Tpda Id 8 LLMSILVER + Package() { "MSSDL", 2}, // QDSS Tpda Id 9 MSSDL + } + ) + } + + Method (TPDM) + { + Return + ( + Package() + { + // QtfTpdmName Index, positional value is Qdss Id + Package() { "VSENSE", 10}, // QDSS Tpda Id 0 VSENSE + //Package() { "DCC", 22}, // QDSS Tpda Id 1 DCC + Package() { "PRNG", 12}, // QDSS Tpda Id 1 PRNG + Package() { "QM", 17}, // QDSS Tpda Id 2 QM + Package() { "PIMEM", 13}, // QDSS Tpda Id 3 PIMEM + Package() { "KryoB", 1}, // QDSS Tpda Id 4 KryoB + Package() { "MSS1", 2}, // QDSS Tpda Id 5 MSS1 + Package() { "NAV", 3}, // QDSS Tpda Id 6 NAV + Package() { "OLC", 4}, // QDSS Tpda Id 7 OLC + Package() { "SP", 5}, // QDSS Tpda Id 8 SP + Package() { "RPMH0", 6}, // QDSS Tpda Id 9 RPMH0 + Package() { "RPMH1", 21}, // QDSS Tpda Id 10 RPMH1 + Package() { "DDR", 18}, // QDSS Tpda Id 11 DDR + Package() { "MSS0", 9}, // QDSS Tpda Id 12 MSS0 + Package() { "MMSS", 23}, // QDSS Tpda Id 13 MMSS + Package() { "LPASS", 11}, // QDSS Tpda Id 14 LPASS + Package() { "TURING", 14}, // QDSS Tpda Id 15 TOURING + Package() { "LLMGOLD", 7}, // QDSS Tpda Id 16 LLMGOLD + Package() { "LLMSILVER", 8}, // QDSS Tpda Id 17 LLMSILVER + } + ) + } + + Method (AGGC) // TPDA(Aggregator) Configuration + { + Return + ( + Package() + { + Package() + { + 0, // TpdaName(QDSS) Index + 0x06004000, // Base address of this TPDA + 0x1000, // Length of this TPDA + 65, // ATID + Package() + { + "BC", // TPDM Subunit + Package() { 10, 32}, // QM TPDM Port number, size + Package() { 13, 32}, // PIMEM TPDM Port number, size + }, + Package() + { + "DSB", // TPDM Subunit + Package() { 0, 32}, + Package() { 2, 32}, // MMSS TPDM Port number, size + Package() { 3, 32}, // DDR TPDM Port number, size + Package() { 5, 32}, // LPASS TPDM Port number, size + Package() { 6, 32}, // TOURING TPDM Port number, size + Package() { 10, 32}, // QM TPDM Port number, size + Package() { 11, 32}, + Package() { 13, 32}, + }, + Package() + { + "CMB", // TPDM Subunit + Package() { 3, 64}, // DDR TPDM Port number, size + Package() { 7, 64}, // VSENSE TPDM Port number, size + Package() { 8, 8}, // DCC TPDM Port number, size + Package() { 9, 64}, // PRNG TPDM Port number, size + Package() { 13, 64}, // PIMEM TPDM Port number, size + }, + }, + + Package() + { + 1, // TpdaName(APSS) Index + 0x07862000, // Base address of this TPDA + 0x1000, // Length of this TPDA + 66, // ATID + Package() + { + "DSB", // TPDM Subunit + Package() { 0, 32}, // KryoB TPDM Port number, size + }, + }, + + Package() + { + 2, // TpdaName(MSS) Index + 0x06833000, // Base address of this TPDA + 0x1000, // Length of this TPDA + 67, // ATID + Package() + { + "DSB", // TPDM Subunit + Package() { 0, 64}, // MSS1 TPDM Port number, size + }, + Package() + { + "CMB", // TPDM Subunit + Package() { 0, 64}, // MSS1 TPDM Port number, size + }, + }, + + Package() + { + 3, // TpdaName(NAV) Index + 0x06991000, // Base address of this TPDA + 0x1000, // Length of this TPDA + 68, // ATID + Package() + { + "CMB", // TPDM Subunit + Package() { 0, 32}, // NAV TPDM Port number, size + }, + }, + + Package() + { + 4, // TpdaName(OLC) Index + 0x07832000, // Base address of this TPDA + 0x1000, // Length of this TPDA + 69, // ATID + Package() + { + "CMB", // TPDM Subunit + Package() { 0, 64}, // OLC TPDM Port number, size + }, + }, + + Package() + { + 5, // TpdaName(SP) Index + 0x06882000, // Base address of this TPDA + 0x1000, // Length of this TPDA + 70, // ATID + Package() + { + "DSB", // TPDM Subunit + Package() { 0, 32}, // SP TPDM Port number, size + }, + }, + + Package() + { + 6, // TpdaName(SWAO) Index + 0x06B01000, // Base address of this TPDA + 0x1000, // Length of this TPDA + 71, // ATID + Package() + { + "DSB", // TPDM Subunit + Package() { 1, 32}, // RPMH1 TPDM Port number, size + }, + Package() + { + "CMB", // TPDM Subunit + Package() { 0, 64}, // RPMH0 TPDM Port number, size + }, + }, + + Package() + { + 7, // TpdaName(LLMGOLD) Index + 0x078D0000, // Base address of this TPDA + 0x1000, // Length of this TPDA + 73, // ATID + Package() + { + "CMB", // TPDM Subunit + Package() { 0, 32}, // LLMGOLD TPDM Port number, size + }, + }, + + Package() + { + 8, // TpdaName(LLMSILVER) Index + 0x078C0000, // Base address of this TPDA + 0x1000, // Length of this TPDA + 72, // ATID + Package() + { + "CMB", // TPDM Subunit + Package() { 0, 32}, // LLMSILVER TPDM Port number, size + }, + }, + + Package() + { + 9, // TpdaName(MSSDL) Index + 0x06831000, // Base address of this TPDA + 0x1000, // Length of this TPDA + 67, // ATID + Package() + { + "DSB", // TPDM Subunit + Package() { 0, 32}, // MSS0 TPDM Port number, size + }, + Package() + { + "CMB", // TPDM Subunit + Package() { 0, 64}, // MSS1 TPDM Port number, size + }, + }, + } + ) + } + + Method (MONC) // TPDM(Monitor) Configuration + { + Return + ( + Package() + { + Package() + { + 0, // VSENSE TPDM index + 0x06840000, // Base address of VSENSE TPDM + 0x1000, // Length of VSENSE TPDM + 0, // QDSS TPDA name index to which VSENSE TPDM is connected + 7, // TPDA port number on which VSENSE TPDM is connected + 0, // MSR-fix-Req + }, + + // As there is not user case and it is crashing in secure device while accessing DCC TPDM + // So we are removing the DCC TPDM details. + // while enabling make sure TPDM method and this method has aligned indexes + //Package() + //{ + // 1, // DCC TPDM index + // 0x06870000, // Base address of DCC TPDM + // 0x1000, // Length of DCC TPDM + // 0, // QDSS TPDA name index to which DCC TPDM is connected + // 8, // TPDA port number on which DCC TPDM is connected + // 0, // MSR-fix-Req + //}, + + Package() + { + 1, // PRNG TPDM index + 0x0684C000, // Base address of PRNG TPDM + 0x1000, // Length of PRNG TPDM + 0, // QDSS TPDA name index to which PRNG TPDM is connected + 9, // TPDA port number on which PRNG TPDM is connected + 0, // MSR-fix-Req + }, + + Package() + { + 2, // QM TPDM index + 0x069D0000, // Base address of QM TPDM + 0x1000, // Length of QM TPDM + 0, // QDSS TPDA name index to which QM TPDM is connected + 10, // TPDA port number on which this QM is connected + 0, // MSR-fix-Req + }, + + Package() + { + 3, // PIMEM TPDM index + 0x06850000, // Base address of PIMEM TPDM + 0x1000, // Length of PIMEM TPDM + 0, // QDSS TPDA name index to which PIMEM TPDM is connected + 13, // TPDA port number on which PIMEM TPDM is connected + 0, // MSR-fix-Req + }, + + Package() + { + 4, // KryoB TPDM index + 0x07860000, // Base address of KryoB TPDM + 0x1000, // Length of this TPDM + 1, // APSS TPDA name index to which KryoB TPDM is connected + 0, // TPDA port number on which KryoB TPDM is connected + 0, // MSR-fix-Req + }, + + Package() + { + 5, // MSS1 TPDM index + 0x06834000, // Base address of MSS1 TPDM + 0x1000, // Length of MSS1 TPDM + 2, // MSS TPDA name index to which MSS1 TPDM is connected + 0, // TPDA port number on which MSS1 TPDM is connected + 0, // MSR-fix-Req + }, + + Package() + { + 6, // NAV TPDM index + 0x06990000, // Base address of NAV TPDM + 0x1000, // Length of NAV TPDM + 3, // NAV TPDA name index to which NAV TPDM is connected + 0, // TPDA port number on which NAV TPDM is connected + 0, // MSR-fix-Req + }, + + Package() + { + 7, // OLC TPDM index + 0x07830000, // Base address of OLC TPDM + 0x1000, // Length of OLC TPDM + 4, // OLC TPDA name index to which OLC TPDM is connected + 0, // TPDA port number on which OLC TPDM is connected + 0, // MSR-fix-Req + }, + + Package() + { + 8, // SP TPDM index + 0x06880000, // Base address of SP TPDM + 0x1000, // Length of SP TPDM + 5, // SP TPDA name index to which SP TPDM is connected + 0, // TPDA port number on which SP TPDM is connected + 0, // MSR-fix-Req + }, + + Package() + { + 9, // RPMH0 TPDM index + 0x06B02000, // Base address of RPMH0 TPDM + 0x1000, // Length of RPMH0 TPDM + 6, // SWAO TPDA name index to which RPMH0 TPDM is connected + 0, // TPDA port number on which RPMH0 TPDM is connected + 0, // MSR-fix-Req + }, + + Package() + { + 10, // RPMH1 TPDM index + 0x06B03000, // Base address of RPMH1 TPDM + 0x1000, // Length of RPMH1 TPDM + 6, // SWAO TPDA name index to which RPMH1 TPDM is connected + 1, // TPDA port number on which RPMH1 TPDM is connected + 1, // MSR-fix-Req + }, + + Package() + { + 11, // DDR TPDM index + 0x069E0000, // Base address of DDR TPDM + 0x1000, // Length of DDR TPDM + 0, // QDSS TPDA name index to which DDR TPDM is connected + 3, // TPDA port number on which DDR TPDM is connected + 1, // MSR-fix-Req + }, + + Package() + { + 12, // MSS0 TPDM index + 0x06830000, // Base address of MSS0 TPDM + 0x1000, // Length of MSS0 TPDM + 9, // MSSDL TPDA name index to which MSS0 TPDM is connected + 0, // TPDA port number on which MSS0 TPDM is connected + 0, // MSR-fix-Req + }, + + Package() + { + 13, // MMSS TPDM index + 0x06C08000, // Base address of MMSS TPDM + 0x1000, // Length of MMSS TPDM + 0, // QDSS TPDA name index to which MMSS TPDM is connected + 2, // TPDA port number on which MMSS TPDM is connected + 1, // MSR-fix-Req + }, + + Package() + { + 14, // LPASS TPDM index + 0x06844000, // Base address of LPASS TPDM + 0x1000, // Length of LPASS TPDM + 0, // QDSS TPDA name index to which LPASS TPDM is connected + 5, // TPDA port number on which LPASS TPDM is connected + 1, // MSR-fix-Req + }, + + Package() + { + 15, // TURING TPDM index + 0x06860000, // Base address of TOURING TPDM + 0x1000, // Length of TOURING TPDM + 0, // QDSS TPDA name index to which TOURING TPDM is connected + 6, // TPDA port number on which TOURING TPDM is connected + 1, // MSR-fix-Req + }, + + Package() + { + 16, // LLMGOLD TPDM index + 0x078B0000, // Base address of LLMGOLD TPDM + 0x1000, // Length of LLMGOLD TPDM + 7, // LLMGOLD TPDA name index to which LLMGOLD TPDM is connected + 0, // TPDA port number on which LLMGOLD TPDM is connected + 0, // MSR-fix-Req + }, + + Package() + { + 17, // LLMSILVER TPDM index + 0x078A0000, // Base address of LLMSILVER TPDM + 0x1000, // Length of LLMSILVER TPDM + 8, // LLMSILVER TPDA name index to which LLMSILVER TPDM is connected + 0, // TPDA port number on which LPASS LLMSILVER is connected + 0, // MSR-fix-Req + }, + } + ) + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/qdss_remote_etm.asl b/sdm845Pkg/AcpiTables/common/qdss_remote_etm.asl new file mode 100644 index 0000000..4ee2207 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qdss_remote_etm.asl @@ -0,0 +1,49 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the REMOTE ETM details needed by qdss driver. +// +//=========================================================================== + +Scope(\_SB.QDSS) +{ + // References: + // http://agiledocument.qualcomm.com/AgileDocument?itemno=80-NH952-62 -- See section 2.4.2 Service Instance Values + + Method (RETM) // Remote ETMs + { + Return + ( + Package() + { + // ETM Subsystem source index - Need to aligned as per REMOTE_ETM_SUBSYS_TYPE defined QdssCommonTypes.h) + + // RemoteETMName, ETM Subsystem source id. + Package() { "MODEMQ6ETM", 1}, // Qdss Remote ETM index 0 MODEMQ6ETM + Package() { "SPSSETM", 12}, // Qdss Remote ETM index 1 SPSSETM + } + ) + } + + Method (RECF) // Remote ETM Config + { + Return + ( + Package() + { + Package() + { + 0, // Qdss Remote ETM index (MODEMQ6ETM) + 1, // QMI support flag + 2, // QMI inst ID + }, + Package() + { + 1, // Qdss Remote ETM index (SPSSETM) + 0, // QMI support flag + 0, // QMI inst ID + }, + } + ) + } +} diff --git a/sdm845Pkg/AcpiTables/common/qdss_replicator.asl b/sdm845Pkg/AcpiTables/common/qdss_replicator.asl new file mode 100644 index 0000000..4319aaf --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qdss_replicator.asl @@ -0,0 +1,49 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the REPLICATOR details needed by qdss driver. +// +// +// +//=========================================================================== + +Scope(\_SB.QDSS) +{ + // References: + // https://sharepoint.qualcomm.com/qct/DHW/Projects/Napali/Documents/Design/debug/SWAO/tmp_swao_hpg/SWAO_HPG.docm + Method (QREP) + { + Return + ( + Package() + { + // Replicator Index + "REPLICATOR", // 0 + "SWAO_REPLICATOR", // 1 + } + ) + } + + Method (REPC) // Replicator Configuration + { + Return + ( + Package() + { + Package() + { + 0, // Index + 0x06046000, // Base address of this ETF/ETB + 0x1000, // Length of this ETF/ETB + }, + + Package() + { + 1, // Index + 0x06B0A000, // Base address of this ETF/ETB + 0x1000, // Length of this ETF/ETB + }, + } + ) + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/qdss_resources.asl b/sdm845Pkg/AcpiTables/common/qdss_resources.asl new file mode 100644 index 0000000..b91704e --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qdss_resources.asl @@ -0,0 +1,175 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the power management resources needed by qdss driver. +// +// +//=========================================================================== + +//=========================================================================== +// Description & Possible use cases for Qdss's p-state implementation +// Qdss employs pstate-sets to robustly configure clock and tlmm registers +// pstate-set 0 has pstates for clock frequencies +// pstate-set 1 has pstates for managing tlmm registers for tpiu operation +//======================================================== +// Sinks p-states allowed +//-------------------------------------------------------- +// non-TPIU P{0,0} +// P{0,1} +// P{0,2} +// P{0,3} +// TPIU P{0,0} AND (P{1,1} OR P{1,3}) +// P{0,1} AND (P{1,0} OR P{1,2}) +// P{0,2} AND (P{1,0} OR P{1,2}) +// P{0,3} AND (P{1,0} OR P{1,2}) +// +// Description of pstate-sets and corresponding p-states : +// pstate-set-0 is the set with allowed qdss clock frequencies +// under set-0 each p-state holds the following meaning: +// pstate-0 CLOCK OFF (0 Hz) +// pstate-1 SVS CLOCK FREQUENCY (depends on the voltage; ranges 150 to 300 MHz) +// pstate-2 HIGH CLOCK FREQUENCY (300 MHz) +// pstate-3 LOW CLOCK FREQUENCY (150 MHz) +// +// under set-1 each p-state hold the following meaning: +// pstate-0 sets SET-B TLMM registers to make TPIU operational +// pstate-1 clears SET-B TLMM registers to make TPIU operational +// pstate-2 sets SD TLMM registers to make TPIU operational +// pstate-3 clears SD TLMM registers to make TPIU operational +//=========================================================================== + +Scope(\_SB.PEP0) +{ + Method(QDMD){ + Return(QDSC) + } + + Name(QDSC, + Package() + { + Package() + { + "DEVICE", + "\\_SB.QDSS", + Package() + { + "COMPONENT", + 0x0, + Package() + { + "FSTATE", + 0x0, + }, + Package() + { + "FSTATE", + 0x1, + Package() {"PSTATE_ADJUST", Package() {0, 0},}, + }, + Package() + { + "PSTATE_SET", + 0x0, + // p-state for turning off the clock + Package() + { + "PSTATE", + 0x0, + package() {"NPARESOURCE", package() {1, "/clk/qdss", 0},}, + }, + // p-state for setting the clock to SVS mode (depends on the voltage) + Package() + { + "PSTATE", + 0x1, + package() {"NPARESOURCE", package() {1, "/clk/qdss", 1},}, + }, + // p-state for high speed clock + Package() + { + "PSTATE", + 0x2, + package() {"NPARESOURCE", package() {1, "/clk/qdss", 2},}, + }, + // p-state for low speed mode + Package() + { + "PSTATE", + 0x3, + package() {"NPARESOURCE", package() {1, "/clk/qdss", 3},}, + }, + }, + Package() + { + "PSTATE_SET", + 0x1, + // p-state for enabling SET-B TPIU TLMM + // TODO: clean-up TPIU code and deprecate this functionality. TPIU is no longer used + package() + { + "PSTATE", + 0x0, + }, + // p-state for disabling SET-B TPIU TLMM + package() + { + "PSTATE", + 0x1, + }, + // p-state for enabling TPIU SD + package() + { + "PSTATE", + 0x2, + }, + // p-state for disabling TPIU SD + package() + { + "PSTATE", + 0x3, + }, + }, + + // pstate-set for enabling the HWEVT Mux clocks TO DO: requires hw event xml + // for subsystems that are under Qdss address map + // *the convention followed in the code is for a mux enable state is + // immediately followed by disable state.* + // e.g. as in 0 is to enable mmss clock and 0+1 is to disable mmss clock + // TODO: confirm with clkrgm team for "/clk/qdss" npa node support. + Package() + { + "PSTATE_SET", + 0x2, + // p-state for setting the /clk/qdss + package() + { + "PSTATE", + 0x0, + package() {"NPARESOURCE", package() {1, "/clk/qdss", 1},}, + }, + // p-state for shutting of the qdss clock + package() + { + "PSTATE", + 0x1, + package() {"NPARESOURCE", package() {1, "/clk/qdss", 0},}, + }, + }, + + // logger integrator GPIO + Package() + { + "PSTATE_SET", + 0x3, + // p-state for setting the /clk/qdss + package() + { + "PSTATE", + 0x0, + package() {"TLMMPORT", package() {0x33000, 0x07FF, 0x01C8},}, // TLMM_GPIO_CFG51, qdss_cti_trig0_out_mira, See http://ipcatalog.qualcomm.com/chipio/tlmm/chip/53/map/170 TLMM base address: TLMM_NORTH, see http://ipcatalog.qualcomm.com/swi/module/1279315#TLMM_GPIO_CFG51 + }, + }, + }, + }, + }) +} diff --git a/sdm845Pkg/AcpiTables/common/qdss_tgu.asl b/sdm845Pkg/AcpiTables/common/qdss_tgu.asl new file mode 100644 index 0000000..752efbf --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qdss_tgu.asl @@ -0,0 +1,47 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the REPLICATOR details needed by qdss driver. +// +// +// +//=========================================================================== + +Scope(\_SB.QDSS) +{ + // References: + // https://sharepoint.qualcomm.com/qct/DHW/Projects/Napali/Documents/Design/debug/SWAO/tmp_swao_hpg/SWAO_HPG.docm + /*TGU Config XLS : https://sharepoint.qualcomm.com/qct/DHW/Projects/Napali/_layouts/15/xlviewer.aspx?id=%2Fqct%2FDHW%2FProjects%2FNapali%2FDocuments%2FDesign%2Fdebug%2FTGU%2Fnapali%5Frpmhdebug%5Fipcbmonitor%5Fzmarzec%2Exlsx&DefaultItemOpen=1&Source=https%3A%2F%2Fsharepoint%2Equalcomm%2Ecom%2Fqct%2FDHW%2FProjects%2FNapali%2FDocuments%2FForms%2FAllItems%2Easpx%3FRootFolder%3D%252Fqct%252FDHW%252FProjects%252FNapali%252FDocuments%252FDesign%252Fdebug%252FTGU%26FolderCTID%3D0x012000D0792EEBBE0E7249BF21C2419C287E33%26View%3D%257B60739D41%2D3205%2D4125%2DA0BF%2D3AA54FEE0267%257D + */ + + Method (QTGU) + { + Return + ( + Package() + { + // TGU Index + "SWAO_TGU", // 0 + } + ) + } + + Method (TGUC) // TGU Configuration + { + Return + ( + Package() + { + Package() + { + 0, // Index + 0x06B0C000, // Base address of this TGU + 0x1000, // Length of this TGU + 0x3, // Max number of steps (from TGU config XLS. Refer refernces above) + 0x4, // Max number of conditions (from TGU config XLS. Refer refernces above) + 0x5, // Max number of registers (from IPCAT) + }, + } + ) + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/qdss_tmc.asl b/sdm845Pkg/AcpiTables/common/qdss_tmc.asl new file mode 100644 index 0000000..f7287b4 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qdss_tmc.asl @@ -0,0 +1,52 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the REPLICATOR details needed by qdss driver. +// +// +// +//=========================================================================== + +Scope(\_SB.QDSS) +{ + // References: + // https://sharepoint.qualcomm.com/qct/DHW/Projects/Napali/Documents/Design/debug/SWAO/tmp_swao_hpg/SWAO_HPG.docm + + Method (QTMC) + { + Return + ( + Package() + { + // ETF/ETB Index + "ETFETB", // 0 + "SWAO_TMC", // 1 + } + ) + } + + Method (TMCC) // ETF/ETB Configuration + { + Return + ( + Package() + { + Package() + { + 0, // Index + 0x06047000, // Base address of this ETF/ETB + 0x1000, // Length of this ETF/ETB + 0, // TPDA index + }, + + Package() + { + 1, // Index + 0x06B09000, // Base address of this ETF/ETB + 0x1000, // Length of this ETF/ETB + 6, // TPDA index + }, + } + ) + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/qdss_verifyclocks.asl b/sdm845Pkg/AcpiTables/common/qdss_verifyclocks.asl new file mode 100644 index 0000000..553a2a4 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qdss_verifyclocks.asl @@ -0,0 +1,59 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contains the clock registers needed by qdss driver. +// +// +// +//=========================================================================== + +Scope(\_SB.QDSS) +{ + Method (QVCR) // Qdss Verify Clock Register + { + Return + ( + Package() + { // CBC register Address, Enable bit position + Package() {0x00109024, 0}, // GCC_MMNOC_AT_CBCR, CLK_ENABLE + Package() {0x00172024, 0}, // GCC_SP_AT_CBCR, CLK_ENABLE + + Package() {0x00151004, 2}, // GCC_RPM_CLOCK_BRANCH_ENA_VOTE, QDSS_CFG_AHB_CLK_ENA + + Package() {0x0010C004, 0}, // GCC_QDSS_DAP_AHB_CBCR, CLK_ENABLE + Package() {0x0010C038, 0}, // GCC_QDSS_XO_CBCR, CLK_ENABLE + Package() {0x0010C01C, 0}, // GCC_QDSS_ETR_USB_CBCR, CLK_ENABLE + Package() {0x0010C020, 0}, // GCC_QDSS_STM_CBCR, CLK_ENABLE + Package() {0x0010C024, 0}, // GCC_QDSS_TRACECLKIN_CBCR, CLK_ENABLE + Package() {0x0010C030, 0}, // GCC_QDSS_DAP_CBCR, CLK_ENABLE + Package() {0x00104154, 0}, // GCC_SYS_NOC_AT_CBCR, CLK_ENABLE + Package() {0x0010C00C, 0}, // GCC_QDSS_CENTER_AT_CBCR, CLK_ENABLE + Package() {0x0010C010, 0}, // GCC_SOUTH_AT_CBCR, CLK_ENABLE + Package() {0x0010C014, 0}, // GCC_EAST_AT_CBCR, CLK_ENABLE + Package() {0x0010C018, 0}, // GCC_NORTH_AT_CBCR, CLK_ENABLE + Package() {0x0013C008, 0}, // GCC_AOSS_AT_CBCR, CLK_ENABLE + Package() {0x00144034, 0}, // GCC_DDRSS_AT_CBCR, CLK_ENABLE + Package() {0x00147010, 0}, // GCC_LPASS_AT_CBCR, CLK_ENABLE + Package() {0x00145010, 0}, // GCC_TURING_AT_CBCR, CLK_ENABLE + Package() {0x00148010, 0}, // GCC_CPUSS_AT_CBCR, CLK_ENABLE + Package() {0x0018A014, 0}, // GCC_MSS_AT_CBCR, CLK_ENABLE + Package() {0x00111010, 0}, // GCC_WCSS_AT_CBCR, CLK_ENABLE + Package() {0x00171008, 0}, // GCC_GPU_AT_CBCR, CLK_ENABLE + Package() {0x00148198, 0}, // GCC_APSS_QDSS_APB_CBCR, CLK_ENABLE + Package() {0x0018901C, 0}, // GCC_IPA_APB_CBCR, CLK_ENABLE + Package() {0x00111014, 0}, // GCC_WCSS_APB_CBCR, CLK_ENABLE + Package() {0x0010C02C, 0}, // GCC_QDSS_TRIG_CBCR, CLK_ENABLE + Package() {0x0014700C, 0}, // GCC_LPASS_TRIG_CBCR, CLK_ENABLE + Package() {0x0014800C, 0}, // GCC_CPUSS_TRIG_CBCR, CLK_ENABLE + Package() {0x0018A010, 0}, // GCC_MSS_TRIG_CBCR, CLK_ENABLE + Package() {0x00171014, 0}, // GCC_GPU_TRIG_CBCR, CLK_ENABLE + Package() {0x00172020, 0}, // GCC_SP_TRIG_CBCR, CLK_ENABLE + Package() {0x00148194, 0}, // GCC_APSS_QDSS_TSCTR_CBCR, CLK_ENABLE + Package() {0x00104148, 0}, // GCC_SYS_NOC_QDSS_STM_AXI_CBCR, CLK_ENABLE + Package() {0x0010B034, 0}, // GCC_MMSS_AT_CBCR, CLK_ENABLE + Package() {0x0010B03C, 0}, // GCC_MMSS_TRIG_CBCR, CLK_ENABLE + Package() {0x0010C028, 0}, // GCC_QDSS_TSCTR_CBCR, CLK_ENABLE + } + ) + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/qgpi.asl b/sdm845Pkg/AcpiTables/common/qgpi.asl new file mode 100644 index 0000000..8f99ca1 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qgpi.asl @@ -0,0 +1,250 @@ +// This file contains the QUPv3 ACPI device definitions. +// GPI is the interface used by buses drivers for different peripherals. +// + +// +// Device Map: +// QGPI +// +// List of Devices + +Device (QGP0) +{ + // Indicates dependency on PEP + //Name (_DEP, Package () { \_SB_.PEP0 }) + + Name (_HID, "HID_QGPI") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + // QUPV3_0 address space + Memory32Fixed (ReadWrite, 0x00804000, 0x50000) + + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {276} // GPII-ID 0x0 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {277} // GPII-ID 0x1 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {278} // GPII-ID 0x2 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {279} // GPII-ID 0x3 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {280} // GPII-ID 0x4 + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {281} // GPII-ID 0x5 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {282} // GPII-ID 0x6 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {283} // GPII-ID 0x7 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {284} // GPII-ID 0x8 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {285} // GPII-ID 0x9 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {286} // GPII-ID 0xA + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {287} // GPII-ID 0xB + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {288} // GPII-ID 0xC + }) + Return (RBUF) + } + + Method (GPII, 0x0, Serialized) + { + Return( Package() + { + //Package () + //{ + // 0x00, // QUPV3 Instance + // 0x00, // GPII ID + // 0x114 // Interrupt + //}, + //Package () + //{ + // 0x00, + // 0x01, + // 0x115 + //}, + //Package () + //{ + // 0x00, + // 0x02, + // 0x116 + //}, + //Package () + //{ + // 0x00, + // 0x03, + // 0x117 + //}, + //Package () + //{ + // 0x00, + // 0x04, + // 0x118 + //}, + Package () + { + 0x00, + 0x05, + 0x119 + } + //Package () + //{ + // 0x00, + // 0x06, + // 0x11A + //}, + //Package () + //{ + // 0x00, + // 0x07, + // 0x11B + //}, + //Package () + //{ + // 0x00, + // 0x08, + // 0x11C + //}, + //Package () + //{ + // 0x00, + // 0x09, + // 0x11D + //}, + //Package () + //{ + // 0x00, + // 0x0A, + // 0x11E + //}, + //Package () + //{ + // 0x00, + // 0x0B, + // 0x11F + //}, + //Package () + //{ + // 0x00, + // 0x0C, + // 0x120 + //} + }) + } +} + +Device (QGP1) +{ + // Indicates dependency on PEP + //Name (_DEP, Package () { \_SB_.PEP0 }) + + Name (_HID, "HID_QGPI") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + // QUPV3_1 address space + Memory32Fixed (ReadWrite, 0x00A04000, 0x50000) + + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {311} // GPII-ID : 0x0 + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {312} // GPII-ID : 0x1 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {313} // GPII-ID : 0x2 + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {314} // GPII-ID : 0x3 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {315} // GPII-ID : 0x4 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {316} // GPII-ID : 0x5 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {325} // GPII-ID : 0x6 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {326} // GPII-ID : 0x7 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {327} // GPII-ID : 0x8 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {328} // GPII-ID : 0x9 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {329} // GPII-ID : 0xA + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {330} // GPII-ID : 0xB + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {331} // GPII-ID : 0xC + + }) + Return (RBUF) + } + + Method (GPII, 0x0, Serialized) + { + Return( Package() + { + //Package () + //{ + // 0x01, + // 0x00, + // 0x137 + //}, + Package () + { + 0x01, + 0x01, + 0x138 + }, + //Package () + //{ + // 0x01, + // 0x02, + // 0x139 + //}, + Package () + { + 0x01, + 0x03, + 0x13A + } + //Package () + //{ + // 0x01, + // 0x04, + // 0x13B + //}, + //Package () + //{ + // 0x01, + // 0x05, + // 0x13C + //}, + //Package () + //{ + // 0x01, + // 0x06, + // 0x145 + //}, + //Package () + //{ + // 0x01, + // 0x07, + // 0x146 + //}, + //Package () + //{ + // 0x01, + // 0x08, + // 0x147 + //}, + //Package () + //{ + // 0x01, + // 0x09, + // 0x148 + //}, + //Package () + //{ + // 0x01, + // 0x0A, + // 0x149 + //}, + //Package () + //{ + // 0x01, + // 0x0B, + // 0x14A + //}, + //Package () + //{ + // 0x01, + // 0x0C, + // 0x14B + //} + }) + } +} diff --git a/sdm845Pkg/AcpiTables/common/qwpp.asl b/sdm845Pkg/AcpiTables/common/qwpp.asl new file mode 100644 index 0000000..480f4e4 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/qwpp.asl @@ -0,0 +1,25 @@ +Device (QWPP) +{ + Name (_DEP, Package () { \_SB_.PEP0 }) + + Name (_HID, "HID_QWPP") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method(_STA, 0) + { + return (0xB) // Loaded, but hidden + } + + Method (_CRS, 0x0, NotSerialized) + { + Return + ( + ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x1100000, 0x1EE000) // The CABO address space + Memory32Fixed (ReadWrite, 0x1380000, 0x320000) // MEMNOC address space + } + ) + } +} diff --git a/sdm845Pkg/AcpiTables/common/rfs.asl b/sdm845Pkg/AcpiTables/common/rfs.asl new file mode 100644 index 0000000..5e9e10a --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/rfs.asl @@ -0,0 +1,49 @@ +// +// RemoteFS +// +Device (RFS0) +{ + Name (_DEP, Package(0x2) + { + \_SB_.IPC0, + \_SB_.UFS0 + }) + + Name (_HID, "HID_RFS0") + Alias(\_SB.PSUB, _SUB) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // RemoteFS Shared Memory + Memory32Fixed (ReadWrite, 0x88888888, 0x99999999, RMTS) + + // RFSA MPSS Shared Memory + Memory32Fixed (ReadWrite, 0x11111111, 0x22222222, RFSM) + + // RFSA ADSP Shared Memory + Memory32Fixed (ReadWrite, 0x33333333, 0x44444444, RFSA) + }) + + CreateDWordField (RBUF, RMTS._BAS, RMTA) + CreateDWordField (RBUF, RMTS._LEN, RMTL) + CreateDWordField (RBUF, RFSM._BAS, RFMA) + CreateDWordField (RBUF, RFSM._LEN, RFML) + CreateDWordField (RBUF, RFSA._BAS, RFAA) + CreateDWordField (RBUF, RFSA._LEN, RFAL) + + Store(\_SB_.RMTB, RMTA) + Store(\_SB_.RMTX, RMTL) + Store(\_SB_.RFMB, RFMA) + Store(\_SB_.RFMS, RFML) + Store(\_SB_.RFAB, RFAA) + Store(\_SB_.RFAS, RFAL) + + Return (RBUF) + } + + Method (_STA) + { + Return(0xB) + } +} diff --git a/sdm845Pkg/AcpiTables/common/sar_manager.asl b/sdm845Pkg/AcpiTables/common/sar_manager.asl new file mode 100644 index 0000000..20f2bd5 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/sar_manager.asl @@ -0,0 +1,11 @@ + +// +// SARMGR Device +// +Device (SARM) +{ + Name (_HID, "HID_SARM") + Alias(\_SB.PSUB, _SUB) + //Method(_HRV) { Return(_BID) } +} + diff --git a/sdm845Pkg/AcpiTables/common/slimbus.asl b/sdm845Pkg/AcpiTables/common/slimbus.asl new file mode 100644 index 0000000..fe6d7a2 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/slimbus.asl @@ -0,0 +1,52 @@ +// +// SLIMbus controller +// +Device (SLM1) +{ + Name (_ADR, 0) + Name (_CCA, 0) + Alias(\_SB.PSUB, _SUB) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // SLIMbus register address space + Memory32Fixed (ReadWrite, 0x171C0000, 0x0002c000) + + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {195} + }) + Return (RBUF) + } + + Method (CHLD) + { + Return (Package() + { + "SLM1\\HID_ACD", + }) + } + + Include("audio_bus.asl") + +} + +Device (SLM2) +{ + Name (_ADR, 1) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // SLIMbus register address space + Memory32Fixed (ReadWrite, 0x17240000, 0x0002c000) + + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {323} + }) + Return (RBUF) + } +} + + diff --git a/sdm845Pkg/AcpiTables/common/spmi.asl b/sdm845Pkg/AcpiTables/common/spmi.asl new file mode 100644 index 0000000..d9c5c42 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/spmi.asl @@ -0,0 +1,22 @@ +// +//SPMI driver. +// +Device(SPMI) +{ + Name(_HID, "HID_SPMI") + Alias(\_SB.PSUB, _SUB) + Name (_CID, "PNP0CA2") + Name(_UID, One) + Name(_CCA, 0) + + Method(_CRS, 0x0, NotSerialized) + { + Name(RBUF, ResourceTemplate () + { + Memory32Fixed(ReadWrite, 0x0C400000, 0x02800000) + }) + Return(RBUF) + } + + Include("spmi_conf.asl") +} diff --git a/sdm845Pkg/AcpiTables/common/spmi_conf.asl b/sdm845Pkg/AcpiTables/common/spmi_conf.asl new file mode 100644 index 0000000..cd7dcdc --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/spmi_conf.asl @@ -0,0 +1,27 @@ +// +//SPMI driver configuration. +// +Method(CONF) +{ + Name(XBUF, + Buffer () { + 0x00, // uThisOwnerNumber + 0x01, // polling mode + 0x01, // reserved channel enable + 0x01, 0xFF, // reserved channel number (upper byte, lower byte) + 0x00, // dynamic channel mode enable + 0x02, 0x00, // number of channels (upper byte, lower byte) + 0x0A, // number of port priorities + 0x07, // number of PVC ports + 0x04, // number of PVC port PPIDs + 0x07, // number of masters + 0x01, 0xFF, // number of mapping table entries (upper byte, lower byte) + 0x10, // number of PIC accumulated status registers + 0x01, 0x00, // number of Program RAM REGS (upper byte, lower byte) + 0x01, // number of SPMI bus controllers + 0x0C, 0x40, 0x00, 0x00, // physical address 0 (byte3, byte2, byte1, byte0) + 0x02, 0x80, 0x00, 0x00 // physical size 0 (byte3, byte2, byte1, byte0) + } + ) + Return(XBUF) +} diff --git a/sdm845Pkg/AcpiTables/common/ssm.asl b/sdm845Pkg/AcpiTables/common/ssm.asl new file mode 100644 index 0000000..1f9d427 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/ssm.asl @@ -0,0 +1,14 @@ + +// +// SSM Driver +// +Device (SSM) +{ + Name (_DEP, Package(0x2) + { + \_SB_.GLNK, + \_SB_.TREE + }) + Name (_HID, "HID_SSM") + Alias(\_SB.PSUB, _SUB) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/ssm_ce_resources.asl b/sdm845Pkg/AcpiTables/common/ssm_ce_resources.asl new file mode 100644 index 0000000..46d34a1 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/ssm_ce_resources.asl @@ -0,0 +1,78 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by pep drivers. +// +// +// +//=========================================================================== + + + +Scope(\_SB_.PEP0) +{ + // CRYPTO + Method(SSMD) + { + Return(CSCC) + } + + Name(CSCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.SSM", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + package() { "BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE0", "ICBID_SLAVE_EBI1", 200000000, 200000000}}, + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce1", 100000000 } }, + }, + + Package() + { + "FSTATE", + 0x1, // f1 state + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/snoc", 0x0}}, + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/cnoc", 0x0}}, + package() { "BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE0", "ICBID_SLAVE_EBI1", 0, 0}}, + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce1", 0 } }, + }, + }, + + Package() + { + "COMPONENT", + 0x1, // Component 1. + Package() + { + "FSTATE", + 0x0, // f0 state + //package() {"REQUIRED_RESOURCE", package() { 1, "/clk/snoc", 0xffffffff}}, + //package() {"REQUIRED_RESOURCE", package() { 1, "/clk/cnoc", 0xffffffff}}, + package() { "BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE1", "ICBID_SLAVE_EBI1", 200000000, 200000000}}, + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce2", 100000000 } }, + }, + + Package() + { + "FSTATE", + 0x1, // f1 state + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/snoc", 0x0}}, + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/cnoc", 0x0}}, + package() { "BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE1", "ICBID_SLAVE_EBI1", 0, 0}}, + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce2", 0 } }, + }, + }, + }, + ///////////////////////////////////////////////////////////////////////////////////// + }) + +} diff --git a/sdm845Pkg/AcpiTables/common/subsys_resources.asl b/sdm845Pkg/AcpiTables/common/subsys_resources.asl new file mode 100644 index 0000000..49b2e2a --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/subsys_resources.asl @@ -0,0 +1,494 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by subsystem drivers. +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + + // Subsystem Drivers + Method(SPMD) + { + Return(SPCC) + } + + + Name(SPCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.AMSS", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "PSTATE", + 0x0, // P0 state + + // turning on MSS specific clocks which were earlier not power managed + // gcc_mss_gpll0_div_clk_src enabled using register in subsys amss code + // Action: 1 == ENABLE, 2 == DISABLE, 3 == SET_FREQ, 8 == ENABLE_SET_FREQ, 9 == CONFIGURE + // Match_Type: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST, 3 == CLOCK_FREQUENCY_HZ_CLOSEST + // ----------------------------------------------------------------------------------------------------- + // CLOCK Clock Name Action Freq (Hz) MatchType + // ----------------------------------------------------------------------------------------------------- + Package() { "CLOCK", Package() { "gcc_boot_rom_ahb_clk", 1,}}, + Package() { "CLOCK", Package() { "gcc_mss_cfg_ahb_clk", 1,}}, + Package() { "CLOCK", Package() { "gcc_mss_q6_memnoc_axi_clk", 1,}}, + Package() { "CLOCK", Package() { "gcc_mss_snoc_axi_clk", 1,}}, + Package() { "CLOCK", Package() { "gcc_mss_mfab_axis_clk", 1,}}, + Package() { "CLOCK", Package() { "gcc_prng_ahb_clk", 1,}}, + Package() { "CLOCK", Package() { "gcc_mss_axis2_clk", 1,}}, + + + // MSS HPG says that step 1 is to turn on the power rails + // to nominal settings. The HPG calls out the following: + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_SMPS2_C", // Voltage Regulator ID - PPP_RESOURCE_ID_SMPS2_C S2CPM8005 See http://ipcatalog.qualcomm.com/pmic/grids/73 + 2, // Voltage Regulator Type - 2 - SMPS + 752000, // Voltage - 0.752 V + 1, // Software Enable - 1 - Enable + 7, // Software Power Mode - 0 - Normal + 0, // Head Room - 0 + }, + }, + + Package() + { + "NPARESOURCE", + Package() + { + 1, //Required Resource - 1 or Non Required Resource - 0 + "/arc/client/rail_cx", + 384, //vlvl Vote - RAIL_VOLTAGE_LEVEL_TUR + }, + }, + + Package() + { + "NPARESOURCE", + Package() + { + 1, //Required Resource - 1 or Non Required Resource - 0 + "/arc/client/rail_mx", + 384, //vlvl Vote - RAIL_VOLTAGE_LEVEL_TUR + }, + }, + + Package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_IPA_CORE", // Master + "ICBID_SLAVE_IPA_CORE", // Slave + 37400, // IB= KHz ( map 37500 KHz needs to mapped to IB value ) + 0, // AB + "HLOS_DRV", // Optional: DRV Id + + }, + }, + }, + Package() + { + "PSTATE", + 1, + + // removing apps vote for MSS specific votable clocks + // gcc_mss_gpll0_div_clk_src disable using register in subsys amss code before we go to P1 state + // Action: 1 == ENABLE, 2 == DISABLE, 3 == SET_FREQ, 8 == ENABLE_SET_FREQ, 9 == CONFIGURE + // Match_Type: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST, 3 == CLOCK_FREQUENCY_HZ_CLOSEST + // ----------------------------------------------------------------------------------------------------- + // CLOCK Clock Name Action Freq (Hz) MatchType + // ----------------------------------------------------------------------------------------------------- + //Package() { "CLOCK", Package() { "gcc_boot_rom_ahb_clk", 2,}}, + Package() { "CLOCK", Package() { "gcc_prng_ahb_clk", 2,}}, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_SMPS2_C", // Voltage Regulator ID - PPP_RESOURCE_ID_SMPS2_C + 2, // Voltage Regulator Type - 2 - SMPS + 0, // Voltage - NA + 0, // Software Disable - 0 - Disable + 0, // Software Power Mode - 0 - NA + 0, // Head Room - 0 + }, + }, + + Package() + { + "NPARESOURCE", + Package() + { + 1, //Required Resource - 1 or Non Required Resource - 0 + "/arc/client/rail_cx", + 0, //vlvl Vote + }, + }, + + Package() + { + "NPARESOURCE", + Package() + { + 1, //Required Resource - 1 or Non Required Resource - 0 + "/arc/client/rail_mx", + 0, //vlvl Vote + }, + }, + + Package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_IPA_CORE", // Master + "ICBID_SLAVE_IPA_CORE", // Slave + 0, // IB= KHz ( map 37500 KHz needs to mapped to IB value ) + 0, // AB + "HLOS_DRV", // Optional: DRV Id + }, + }, + }, + Package() + { + "PSTATE", + 2, + + // removing apps vote for MSS specific votable clocks + // gcc_mss_gpll0_div_clk_src disable using register in subsys amss code before we go to P1 state + // Action: 1 == ENABLE, 2 == DISABLE, 3 == SET_FREQ, 8 == ENABLE_SET_FREQ, 9 == CONFIGURE + // Match_Type: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST, 3 == CLOCK_FREQUENCY_HZ_CLOSEST + // ----------------------------------------------------------------------------------------------------- + // CLOCK Clock Name Action Freq (Hz) MatchType + // ----------------------------------------------------------------------------------------------------- + Package() { "CLOCK", Package() { "gcc_boot_rom_ahb_clk", 2,}}, + Package() { "CLOCK", Package() { "gcc_prng_ahb_clk", 2,}}, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_SMPS2_C", // Voltage Regulator ID - PPP_RESOURCE_ID_SMPS2_C + 2, // Voltage Regulator Type - 2 - SMPS + 0, // Voltage - NA + 0, // Software Disable - 0 - Disable + 0, // Software Power Mode - 0 - NA + 0, // Head Room - 0 + }, + }, + + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + } + }, + ///////////////////////////////////////////////////////////////////////////////////// + + // ADSP device + Package() + { + "DEVICE", + "\\_SB.ADSP", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "PSTATE", + 0x0, // P0 state + }, + Package(){ + "PSTATE", + 1, // P1 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + ///////////////////////////////////////////////////////////////////////////////////// + + // SCSS (sensors subsystem bus) device + Package() + { + "DEVICE", + "\\_SB.SCSS", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "PSTATE", + 0x0, + + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO27_A", // VREG ID + 1, // Voltage Regulator type - LDO, + 752000, // Voltage is in micro volts - (0.752V = Nominal L27A, PM845. See http://ipcatalog.qualcomm.com/pmic/grids/chip/53/grid/98) + 1, // force enable from software - enable + 7, // power mode - Normal Power Mode (See go/pepuserguide for translation from mode to value) + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO4_A", // VREG ID + 1, // Voltage Regulator type - LDO + 800000, // Voltage is in micro volts - (0.8V = Nominal, L4A PM845. See http://ipcatalog.qualcomm.com/pmic/grids/chip/53/grid/98) + 1, // force enable from software - enable + 7, // power mode - Normal Power Mode (See go/pepuserguide for translation from mode to value) + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LVS2_A", + 4, // TYPE of VREG - LVS + 1800000, // 1.8V LVS2APM845 See http://ipcatalog.qualcomm.com/pmic/grids/73 + 1, // Force enable from s/w + }, + }, + + Package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_CLK_CTL", // Slave + 1, // IB + 1, // AB + }, + }, + }, + Package() + { + "PSTATE", + 0x1, + + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO27_A", // VREG ID + 1, // Voltage Regulator type - LDO + 576000, // Voltage is in micro volts - (0.576V = MinSVS L27A, PM845. See http://ipcatalog.qualcomm.com/hsr/213#) + 1, // force enable from software + 5, // power mode - Low Power Mode (See go/pepuserguide for translation from mode to value) + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO4_A", // VREG ID + 1, // Voltage Regulator type - LDO + 800000, // Voltage is in micro volts - (0.8V = Nominal (Lowest supported) L4A, PM845. See http://ipcatalog.qualcomm.com/hsr/213#) + 1, // force enable from software + 5, // power mode - Low Power Mode (See go/pepuserguide for translation from mode to value) + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LVS2_A", + 4, // TYPE of VREG - LVS + 0, // 0.0V + 0, // Force enable from s/w + }, + }, + + Package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_CLK_CTL", // Slave + 0, // IB + 0, // AB + }, + }, + }, + Package(){ + "PSTATE", + 2, + + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO27_A", // VREG ID + 1, // Voltage Regulator type - LDO + 0, // Voltage is in micro volts - NA + 0, // force enable from software - disable + 0, // power mode - NA + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO4_A", // VREG ID + 1, // Voltage Regulator type - LDO + 0, // Voltage is in micro volts - NA + 0, // force enable from software - disable + 0, // power mode - NA + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LVS2_A", + 4, // TYPE of VREG - LVS + 0, // 0.0V + 0, // Force enable from s/w + }, + }, + + Package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_CLK_CTL", // Slave + 0, // IB + 0, // AB + }, + }, + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + ///////////////////////////////////////////////////////////////////////////////////// + + // CDSP device + Package() + { + "DEVICE", + "\\_SB.CDSP", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "PSTATE", + 0x0, // P0 state + }, + Package(){ + "PSTATE", + 1, + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + ///////////////////////////////////////////////////////////////////////////////////// + }) + +} diff --git a/sdm845Pkg/AcpiTables/common/syscache.asl b/sdm845Pkg/AcpiTables/common/syscache.asl new file mode 100644 index 0000000..523284f --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/syscache.asl @@ -0,0 +1,24 @@ +// +// System Cache Driver +// + + +Device (LLC) +{ + Name (_DEP, Package(0x1) + { + \_SB_.PEP0 + }) + Name (_HID, "HID_QLLC") + Alias(\_SB.PSUB, _SUB) + + Method (_CRS, 0x0, NotSerialized) + { + Return (ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x01300000, 0x28000) + }) + } + +} + diff --git a/sdm845Pkg/AcpiTables/common/testbam_resources.asl b/sdm845Pkg/AcpiTables/common/testbam_resources.asl new file mode 100644 index 0000000..ae3a856 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/testbam_resources.asl @@ -0,0 +1,40 @@ +Scope(\_SB_.PEP0) +{ + // SoC Devices + Method(BTMD) + { + Return(BTCC) + } + Name(BTCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.BAT0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "PSTATE", + 0x0, // P0 state + package() {"CLOCK", package() {"gcc_bam_dma_ahb_clk", 1, 100000000, 1}}, + }, + + Package() + { + "PSTATE", + 0x1, // P1 state + package() {"CLOCK", package() {"gcc_bam_dma_ahb_clk", 2, 100000000, 1}}, + }, + }, + }, + }) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/thz.asl b/sdm845Pkg/AcpiTables/common/thz.asl new file mode 100644 index 0000000..8bc3ce2 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/thz.asl @@ -0,0 +1,558 @@ +// +// The Driver for Dynamically Changing Thresholds +// of Thermal Zones +// + +Method(THTZ, 0x4, NotSerialized) +{ + + // Switch based on thermal zone number + Switch(toInteger(Arg0)) + { + Case(1) + { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ1.TPSV) + Notify(\_SB.TZ1, 0x81) + } + Return(\_SB.TZ1._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ1.TTSP) + Notify(\_SB.TZ1, 0x81) + } + Return(\_SB.TZ1._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ1.TTC1) + Notify(\_SB.TZ1, 0x81) + } + Return(\_SB.TZ1._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ1.TTC2) + Notify(\_SB.TZ1, 0x81) + } + Return(\_SB.TZ1._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(3) + { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ3.TPSV) + Notify(\_SB.TZ3, 0x81) + } + Return(\_SB.TZ3._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ3.TTSP) + Notify(\_SB.TZ3, 0x81) + } + Return(\_SB.TZ3._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ3.TTC1) + Notify(\_SB.TZ3, 0x81) + } + Return(\_SB.TZ3._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ3.TTC2) + Notify(\_SB.TZ3, 0x81) + } + Return(\_SB.TZ3._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(20) + { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ20.TPSV) + Notify(\_SB.TZ20, 0x81) + } + Return(\_SB.TZ20._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ20.TTSP) + Notify(\_SB.TZ20, 0x81) + } + Return(\_SB.TZ20._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ20.TTC1) + Notify(\_SB.TZ20, 0x81) + } + Return(\_SB.TZ20._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ20.TTC2) + Notify(\_SB.TZ20, 0x81) + } + Return(\_SB.TZ20._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(21) + { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ21.TPSV) + Notify(\_SB.TZ21, 0x81) + } + Return(\_SB.TZ21._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ21.TTSP) + Notify(\_SB.TZ21, 0x81) + } + Return(\_SB.TZ21._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ21.TTC1) + Notify(\_SB.TZ21, 0x81) + } + Return(\_SB.TZ21._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ21.TTC2) + Notify(\_SB.TZ21, 0x81) + } + Return(\_SB.TZ21._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(33) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ33.TPSV) + Notify(\_SB.TZ33, 0x81) + } + Return(\_SB.TZ33._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ33.TTSP) + Notify(\_SB.TZ33, 0x81) + } + Return(\_SB.TZ33._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ33.TTC1) + Notify(\_SB.TZ33, 0x81) + } + Return(\_SB.TZ33._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ33.TTC2) + Notify(\_SB.TZ33, 0x81) + } + Return(\_SB.TZ33._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(36) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ36.TPSV) + Notify(\_SB.TZ36, 0x81) + } + Return(\_SB.TZ36._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ36.TTSP) + Notify(\_SB.TZ36, 0x81) + } + Return(\_SB.TZ36._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ36.TTC1) + Notify(\_SB.TZ36, 0x81) + } + Return(\_SB.TZ36._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ36.TTC2) + Notify(\_SB.TZ36, 0x81) + } + Return(\_SB.TZ36._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(37) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ37.TPSV) + Notify(\_SB.TZ37, 0x81) + } + Return(\_SB.TZ37._PSV) + } + + Case(1) + { + If(Arg2) + { + Store(Arg1, \_SB.TZ37.TCRT) + Notify(\_SB.TZ37, 0x81) + } + Return(\_SB.TZ37._CRT) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ37.TTSP) + Notify(\_SB.TZ37, 0x81) + } + Return(\_SB.TZ37._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ37.TTC1) + Notify(\_SB.TZ37, 0x81) + } + Return(\_SB.TZ37._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ37.TTC2) + Notify(\_SB.TZ37, 0x81) + } + Return(\_SB.TZ37._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(38) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ38.TPSV) + Notify(\_SB.TZ38, 0x81) + } + Return(\_SB.TZ38._PSV) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(40) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ40.TPSV) + Notify(\_SB.TZ40, 0x81) + } + Return(\_SB.TZ40._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ40.TTSP) + Notify(\_SB.TZ40, 0x81) + } + Return(\_SB.TZ40._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ40.TTC1) + Notify(\_SB.TZ40, 0x81) + } + Return(\_SB.TZ40._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ40.TTC2) + Notify(\_SB.TZ40, 0x81) + } + Return(\_SB.TZ40._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(44) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ44.TPSV) + Notify(\_SB.TZ44, 0x81) + } + Return(\_SB.TZ44._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ44.TTSP) + Notify(\_SB.TZ44, 0x81) + } + Return(\_SB.TZ44._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ44.TTC1) + Notify(\_SB.TZ44, 0x81) + } + Return(\_SB.TZ44._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ44.TTC2) + Notify(\_SB.TZ44, 0x81) + } + Return(\_SB.TZ44._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(98) + { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ98.TPSV) + Notify(\_SB.TZ98, 0x81) + } + Return(\_SB.TZ98._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ98.TTSP) + Notify(\_SB.TZ98, 0x81) + } + Return(\_SB.TZ98._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ98.TTC1) + Notify(\_SB.TZ98, 0x81) + } + Return(\_SB.TZ98._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ98.TTC2) + Notify(\_SB.TZ98, 0x81) + } + Return(\_SB.TZ98._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(99) + { + Switch(toInteger(Arg3)) + { + Case(1) { + If(Arg2) + { + Store(Arg1, \_SB.TZ99.TCRT) + Notify(\_SB.TZ99, 0x81) + } + Return(\_SB.TZ99._CRT) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ99.TTSP) + Notify(\_SB.TZ99, 0x81) + } + Return(\_SB.TZ99._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ99.TTC1) + Notify(\_SB.TZ99, 0x81) + } + Return(\_SB.TZ99._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ99.TTC2) + Notify(\_SB.TZ99, 0x81) + } + Return(\_SB.TZ99._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Default { + Return(0xFFFF) + } + } +} + diff --git a/sdm845Pkg/AcpiTables/common/tmm_resources.asl b/sdm845Pkg/AcpiTables/common/tmm_resources.asl new file mode 100644 index 0000000..d2dd6a1 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/tmm_resources.asl @@ -0,0 +1,296 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by SMMU test driver. +// +// +// +//=========================================================================== + +Scope(\_SB_.PEP0){ + // SMMU + Method(TMMD){ + Return(TMMC) + } + Name(TMMC, + Package(){ + Package(){ + "DEVICE", + "\\_SB.TMM0", + Package(){ + "COMPONENT", + 0, + Package(){ + "FSTATE", + 0, + package(){ + "FOOTSWITCH", + package(){ + "VDD_CAMSS_VFE", // Footswitch Name - VDD_CAMSS_VFE + 1, // Action - 1 - Enable + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_cpp_ahb_clk", // Clock Name - camss_vfe_cpp_ahb_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_cpp_clk", // Clock Name - camss_vfe_cpp_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe0_clk", // Clock Name - camss_vfe_vfe0_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe1_clk", // Clock Name - camss_vfe_vfe1_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe_ahb_clk", // Clock Name - camss_vfe_vfe_ahb_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe_axi_clk", // Clock Name - camss_vfe_vfe_axi_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_top_ahb_clk", // Clock Name - camss_top_ahb_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_ahb_clk", // Clock Name - camss_ahb_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "FOOTSWITCH", + package(){ + "VDD_VENUS0", // Footswitch Name - VDD_VENUS0 + 1, // Action - 1 - Enable + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_vcodec0_clk", // Clock Name - venus0_vcodec0_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_axi_clk", // Clock Name - venus0_axi_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_ahb_clk", // Clock Name - venus0_ahb_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_ocmemnoc_clk", // Clock Name - venus0_ocmemnoc_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "ocmemcx_ocmemnoc_clk", // Clock Name - ocmemcx_ocmemnoc_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + }, + Package(){ + "FSTATE", + 1, + package(){ + "CLOCK", + package(){ + "camss_vfe_cpp_ahb_clk", // Clock Name - camss_vfe_cpp_ahb_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_cpp_clk", // Clock Name - camss_vfe_cpp_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe0_clk", // Clock Name - camss_vfe_vfe0_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe1_clk", // Clock Name - camss_vfe_vfe1_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe_ahb_clk", // Clock Name - camss_vfe_vfe_ahb_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe_axi_clk", // Clock Name - camss_vfe_vfe_axi_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_top_ahb_clk", // Clock Name - camss_top_ahb_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_ahb_clk", // Clock Name - camss_ahb_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "FOOTSWITCH", + package(){ + "VDD_CAMSS_VFE", // Footswitch Name - VDD_CAMSS_VFE + 2, // Action - 2 - Disable + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_vcodec0_clk", // Clock Name - venus0_vcodec0_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_axi_clk", // Clock Name - venus0_axi_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_ahb_clk", // Clock Name - venus0_ahb_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_ocmemnoc_clk", // Clock Name - venus0_ocmemnoc_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "ocmemcx_ocmemnoc_clk", // Clock Name - ocmemcx_ocmemnoc_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "FOOTSWITCH", + package(){ + "VDD_VENUS0", // Footswitch Name - VDD_VENUS0 + 2, // Action - 2 - Disable + }, + }, + }, + }, + }, + }) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/ufs.asl b/sdm845Pkg/AcpiTables/common/ufs.asl new file mode 100644 index 0000000..dce7f3a --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/ufs.asl @@ -0,0 +1,44 @@ +// UFS Controller +Device (UFS0) +{ + Name (_DEP, Package(0x1) + { + \_SB.PEP0, + }) + + Name (_HID, "HID_UFS0") + Alias(\_SB.PSUB, _SUB) + Name (_CID, "ACPI\HID_UFS0") + Name (_UID, 0) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // UFS register address space + Memory32Fixed (ReadWrite, 0x1D84000, 0x14000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {297} + }) + Return (RBUF) + } + + // UFS Device + Device (DEV0) + { + // Memory Type + Method (_ADR) + { + Return (8) + } + + // Non-removable + Method (_RMV) + { + Return (0) + } + } + } + + + + diff --git a/sdm845Pkg/AcpiTables/common/usb.asl b/sdm845Pkg/AcpiTables/common/usb.asl new file mode 100644 index 0000000..3ab3f0d --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/usb.asl @@ -0,0 +1,953 @@ +Name(QUFN, 0x0 ) //enable flag for QcUsbFN driver stack + +//Holds the DPDM Polarity +//USB_DPDM_INVALID_INVALID = 0 +//USB_DPDM_INVALID_FALLING = 1 +//USB_DPDM_INVALID_RISING = 2 +//USB_DPDM_FALLING_INVALID = 3 +//USB_DPDM_RISING_INVALID = 4 +//USB_DPDM_FALLING_FALLING = 5 +//USB_DPDM_FALLING_RISING = 6 +//USB_DPDM_RISING_FALLING = 7 +//USB_DPDM_RISING_RISING = 8 +Name(DPP0, Buffer(){0x0}) + +// +// USB Role Switch +// +Device(URS0) +{ + //select HID based on flag for QcUsbFN driver stack + Method (URSI) { + If(Lequal(\_SB.QUFN, 0x0)) { + return("HID_URS0") + } + Else{ + return ("HID_URS1") + } + } + + Alias(URSI, _HID) + + Name(_CID, "PNP0CA1") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + Name(_CCA, Zero) // Cache-incoherent bus-master, Hardware does not manage cache coherency + Name(_DEP, Package(0x1) + { + \_SB_.PEP0 + }) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x0A600000, 0x000FFFFF) + }) + + // Dynamically enumerated device (host mode stack) on logical USB bus + Device(USB0) + { + Name(_ADR, 0) + Name(_S0W, 3) // Enable power management for SDM850 BU + + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x09, // Connector type: Type C connector - USB2 and SS with switch. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + Name(_CRS, ResourceTemplate() { + // usb30_ctrl_irq[0] + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xA5} + // Qusb2Phy_intr + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x17A} + // qmp_usb3_lfps_rxterm_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x206} + // eud_p0_dmse_int_mx - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x208} + // eud_p0_dpse_int_mx - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x209} + }) + + Method(_STA) + { + Return (0xf) + } + + //Method to set DPDM Polarity for Pep Driver + Method(DPM0, 0x1, NotSerialized) { + // ARG 0 ?DPDM polarity + Store(Arg0, \_SB.DPP0) //DPDM Polarity + Notify(\_SB.PEP0, 0xA0) + } + + // Returns CC Out + Method(CCVL) { + // Return CC OUT + Return(\_SB.CCST) + } + //Returns High Speed Enumeration Flag + Method(HSEN) { + // Return High Speed Enumeration Flag + Return(\_SB.HSFL) + } + + /* HS enumeration fix + //HSEI: High Speed pullup gpio + Name (HSEI, ResourceTemplate () + { + GpioIo (Exclusive,PullNone,0,0, ,"\\_SB.GIO0", ,) {8} + }) + + //define 1 byte long operation region HLEN w/ base address == 0 under GPIO0 devnode namespace + Scope(\_SB.GIO0) { + OperationRegion(HLEN, GeneralPurposeIO, 0, 1) // Note: Region is less than 8 pins long + } + + //now connect HLEN field in op region w/ HSEI resource + Field(\_SB.GIO0.HLEN, ByteAcc, NoLock, Preserve) + { + //Connect field to HSEI physical object + Connection (\_SB.URS0.USB0.HSEI), // Following fields will be accessed atomically + MOD1, 1 //MOD1 - variable name, 1 == 1bit wide + } + */ + + // Device Specific Method takes 4 args: + // Arg0 : Buffer containing a UUID [16 bytes] + // Arg1 : Integer containing the Revision ID + // Arg2 : Integer containing the Function Index + // Arg3 : Empty Package (Not used) + Method (_DSM, 0x4, NotSerialized) + { + // UUID selector + switch(ToBuffer(Arg0)) { + // UFX interface identifier + case(ToUUID("CE2EE385-00E6-48CB-9F05-2EDB927C4899")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {0,2,3,4} supported + case(0) { Return(Buffer(){0x1D}); Break; } + // Function 0 only supported for invalid revision + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 2: Port type identification + // 0x00 ?Regular USB + // 0x01 ?HSIC + // 0x02 ?SSIC + // 0x03 ?0xff reserved + case(2) { Return(0x0); Break; } + + // Function 3: Query Controller Capabilities + // bit 0 represents the support for software assisted USB endpoint offloading feature + // 1 - Offloading endpoint supported + case(3) { Return(0x1); Break; } + + // Function 4: Interrupter Number + case(4) { Return(0x2); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {CE2EE385-00E6-48CB-9F05-2EDB927C4899} + default { Return (Buffer(){0x00}); Break; } + } // UUID + } // _DSM + // + // The following values of PHY will be configured if OEMs do not + // overwrite the values. + // + // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY. + // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing + // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis. + // + // AccessMethod: + // 0 - DirectAccess: The register address is accessed directly from the mapped memory. + // + Method(PHYC, 0x0, NotSerialized) { + Name (CFG0, Package() + { + // AccessMethod, REG ADDR, Value + // ------------------------------- + //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR + //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing + //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis + }) + Return (CFG0) + } + + /* + Device(RHUB) + { + Name(_ADR, 0) // Value zero reserved for Root Hub + + // Device Specific Method takes 4 args: + // Arg0 : Buffer containing a UUID [16 bytes] + // Arg1 : Integer containing the Revision ID + // Arg2 : Integer containing the Function Index + // Arg3 : Empty Package (Not used) + Method (_DSM, 0x4, NotSerialized) + { + // UUID selector + switch(ToBuffer(Arg0)) { + // HS enumeration fix + case(ToUUID("A9A82A56-95A1-4B4A-B014-3BE47DF1B7D5")) + { + // Version selector + switch(ToInteger(Arg1)) + { + case(1) //DSM_SDM845_HS_RH_PORT_RESET_REVISION_1 + { + switch(ToInteger(Arg2)) //DSM_SDM845_HS_RH_PORT_RESET_FUNCTION_ + { + //DSM_SDM845_HS_RH_PORT_RESET_FUNCTION_PRE_RESET_ON - set GPIO high + case(1) + { + Store (0x01, \_SB.URS0.USB0.MOD1) + Return (Buffer(){0x01}) //return success + } + //DSM_SDM845_HS_RH_PORT_RESET_FUNCTION_POST_RESET_OFF - set GPIO low + case(0) + { + Store (0x00, \_SB.URS0.USB0.MOD1) + Return (Buffer(){0x01}) //return success + } + + default { Return (Buffer(){0x00})} + } + } + default { Return (Buffer(){0x00}) } + } + }//end (A9A82A56-95A1-4B4A-B014-3BE47DF1B7D5) + + default { Return (Buffer(){0x00}); Break; } + } // UUID + } // _DSM + } // Root Hub + */ + + } // USB0 + + // Dynamically enumerated device (peripheral mode stack) on logical USB bus + Device(UFN0) + { + Name(_ADR, 1) + Name(_S0W, 3) // Enable power management for Napali BU + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x09, // Connector type: Type C connector - USB2 and SS with switch. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + Name(_CRS, ResourceTemplate() { + // usb30_ctrl_irq[0] + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xA5} + //usb30_power_event_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0xA2} + }) + + // Returns CC Out + Method(CCVL) { + // Return CC OUT + Return(\_SB.CCST) + } + + // Device Specific Method takes 4 args: + // Arg0 : Buffer containing a UUID [16 bytes] + // Arg1 : Integer containing the Revision ID + // Arg2 : Integer containing the Function Index + // Arg3 : Package that contains function-specific arguments + Method (_DSM, 0x4, NotSerialized) + { + // UUID selector + switch(ToBuffer(Arg0)) { + // UFX interface identifier + case(ToUUID("FE56CFEB-49D5-4378-A8A2-2978DBE54AD2")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {1} supported + case(0) { Return(Buffer(){0x03}); Break; } + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 1: Return number of supported USB PHYSICAL endpoints + // Synopsys core configured to support 16 IN/16 OUT EPs, including EP0 + case(1) { Return(32); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {FE56CFEB-49D5-4378-A8A2-2978DBE54AD2} + + // QCOM specific interface identifier + case(ToUUID("18DE299F-9476-4FC9-B43B-8AEB713ED751")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {1} supported + case(0) { Return(Buffer(){0x03}); Break; } + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 1: Return device capabilities bitmap + // Bit Description + // --- ------------------------------- + // 0 Superspeed Gen1 supported + // 1 PMIC VBUS detection supported + // 2 USB PHY interrupt supported + // 3 Type-C supported + // 4 Delay USB initialization + // 5 HW based charger detection + case(1) { Return(0x39); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {18DE299F-9476-4FC9-B43B-8AEB713ED751} + + default { Return (Buffer(){0x00}); Break; } + } // UUID + } // _DSM + + // + // The following values of PHY will be configured if OEMs do not + // overwrite the values. + // + // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY. + // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing + // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis. + // + // AccessMethod: + // 0 - DirectAccess: The register address is accessed directly from the mapped memory. + // + Method(PHYC, 0x0, NotSerialized) { + Name (CFG0, Package() + { + // AccessMethod, REG ADDR, Value + // ------------------------------- + //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR + //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing + //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis + }) + Return (CFG0) + } + } // UFN0 +} // URS0 + +// HPD Notification Event in Display Driver +// HPD_STATUS_LOW_NOTIFY_EVENT - 0x92 +// HPD_STATUS_HIGH_NOTIFY_EVENT - 0x93 +// All other valus are invalid +Name(HPDB, 0x00000000) + +// DP Pin Assignment +// TYPEC_DISPLAYPORT_PINASSIGNMENTINVALID = 0x0 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTA = 0x01 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTB = 0x02 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTC = 0x03 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTD = 0x04 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTE = 0x05 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTF = 0x06 +// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTA = 0x07 +// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTB = 0x08 +// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTC = 0x09 +// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTD = 0x0A +// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTE = 0x0B +Name(PINA, 0x00000000) + +// Holds the CC OUT Status +// 0 -> CC1 +// 1 -> CC2 +// 2 -> CC Open +Name(CCST, Buffer(){0x02}) + +// Holds the HS Only enumeration Flag for display alternate mode +// 0 -> Super Speed Controller Enumeration support +// 1 -> High Speed Controller Enumeration support +// 2 -> Invalid +Name(HSFL, Buffer(){0x00}) + +// USB Capabilities bitmap +// Indicates the platform's USB capabilities, extend as required. +// Bit Description +// --- --------------------------------------------------- +// 0 Super Speed Gen1 supported (Synopsys IP) +// 1 PMIC VBUS detection supported +// 2 USB PHY interrupt supported (seperate from ULPI) +// 3 TypeC supported +Name(USBC, Buffer(){0x0B}) + + +// +// USB Type-C/PD Switch +// +Device(UCP0) +{ + Name(_HID, "HID_USBC") // QCOM24D3 + Name(_DEP, Package(0x3) + { + \_SB_.PEP0, + \_SB_.PTCC, + \_SB_.URS0 + }) + + Device(CON0) + { + // These devices are not meant to be enumerated by ACPI, hence you should not assign + // HWIDs to them. Instead, use _ADR to assign unique addresses to them. + // The addresses are required to be a 0-based index of the connector. First connector + // should have "0", second one "1", etc. + Name(_ADR, 0x00000000) + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x09, // Connector type: Type C connector - USB2 and SS with switch. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + Name(_DSD, Package() + { + // The UUID for Type-C connector capabilities. + ToUUID("6b856e62-40f4-4688-bd46-5e888a2260de"), + // The data structure which contains the connector capabilities. Each package + // element contains two elements: the capability type ID, and the capability data + // (which depends on the capability type). Note that any information defined here + // will override similar information described by the driver itself. For example, if + // the driver claims the port controller is DRP-capable, but ACPI says it is UFP-only + // ACPI will take precedence. + Package() + { + Package() {1, 4}, // Supported operating modes (DRP). + Package() {2, 3}, // Supported Type-C sourcing capabilities (DefaultUSB & 1500mA). + Package() {3, 0}, // Audio accessory capable (False). + Package() {4, 1}, // Is PD supported (True). + Package() {5, 3}, // Supported power roles (Sink and Source). + Package() + { + 6, // Capability type ID of PD Source Capabilities. + Package() + { + 0x00019096 // Source PDO #0: Fixed:5V, 1.5A. No need to describe fixed bits. + } + }, + Package() + { + 7, // Capability type ID of PD Sink Capabilities. + Package () + { + 0x0001912C, // Sink PDO #0: Fixed:5V, 3.0A. No need to describe fixed bits. + 0x0002D0C8, // Sink PDO #1: Fixed:9V, 2.0A. No need to describe fixed bits. + 0x0003C096, // Sink PDO #2: Fixed:12V, 1.5A. No need to describe fixed bits. + } + }, + Package() + { + 8, // Capability type ID of supported PD Alternate Modes. + Package() + { + 0xFF01, 0x3C86 // DFP_D capable (B0:1); DFP v1.3 signalling (B2:5); DP on Type-C plug (B6); + // usb r2.0 signalling not required (B7); Pin Assignment Supported - C,D,E,F (B8:15) + } + }, + Package() + { + 9, // Add Delay in loading of host stack + 1 + }, + Package() // Hardware CC debounce is supported + { + 0xA, + 1 + } + } + }) + } // Device(CON0) + + // Device Specific Method takes 4 args: + // Arg0 : Buffer containing a UUID [16 bytes] + // Arg1 : Integer containing the Revision ID + // Arg2 : Integer containing the Function Index + // Arg3 : Package that contains function-specific arguments + Method (_DSM, 0x4, NotSerialized) + { + // UUID selector + switch(ToBuffer(Arg0)) { + // QCOM specific interface identifier + case(ToUUID("18DE299F-9476-4FC9-B43B-8AEB713ED751")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {0,1} supported + case(0) { Return(Buffer(){0x01}); Break; } // TypeC support only, No PD + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function1: Return Capabilities Data Objects + case(1) { + switch(ToInteger(Arg3)) { + // Source Power PDO + case (0) { Return(Package(){0x36019050}); Break; } + // Sink Power PDO + case (1) { Return(Package(){0x3601912C}); Break; } + //default + default { Return (Package(){0x00}); Break; } + } + } + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {18DE299F-9476-4FC9-B43B-8AEB713ED751} + + default { Return (Buffer(){0x00}); Break; } + } // UUID + } // _DSM + // Method for updating the CC Out status and HS Mode Flag + // Arg 0 - CC Out value (CC1/CC2/CC Open) + // Arg 1 - HS Mode Flag (SS/HS/Invalid) + Method(CCOT, 0x2, NotSerialized) { + // ARG 0 - CC_OUT + Store(Arg0, \_SB.CCST) + Store(Arg1, \_SB.HSFL) + } + // Method for reading CC Out Value from Type-C client driver + // Only for sanity testing + Method(CCVL) { + // Return CC OUT + Return(\_SB.CCST) + } + + Method(HPDS, 0x0, NotSerialized) { + // Notify event ID - 0x92 to GFX driver on a hot plug-in event + Notify(\_SB.GPU0, 0x94) + } + + Method(HPDF, 0x2, NotSerialized) { + // ARG 0 - HPD Status + Store(Arg0, \_SB.HPDB) + // Arg 1 - Pin Assignment + Store(Arg1, \_SB.PINA) + // Invoke Display Driver HPD event + Notify(\_SB.GPU0, \_SB.HPDB) + } + + // Method for reading CC Out Value from Type-C client driver + // Only for sanity testing + Method(HPDV) { + // Return HPD + Return(\_SB.HPDB) + } + // Method for reading HPD and Pin Assignment values from Type-C client driver + // Only for sanity testing + Method(PINV) { + // Return Pin Assignment + Return(\_SB.PINA) + } + +} // UCP0 + +//Dummy device to allow KDNET on 2ndary port debugger registration +Device (USB1) +{ + Name (_DEP, Package(0x1) + { + \_SB_.PEP0 + }) + Name (_HID, "HID_USBD") // QCOM02BA + Name (_UID, 1) + + //set device status as not present, disabled, not shown in UI, not functioning properly + Name(STVL, 0x0) + + Method (_STA) { + Return (STVL) // return the current device status + } +} // USB1 + + +// +// USB Type-C Audio Driver +// +Device (USBA) +{ + Name (_DEP, Package(0x1) + { + \_SB_.IMM0 + }) + Name (_HID, "HID_USBA") + Alias(\_SB.PSUB, _SUB) +} + + +//URS1 specific +/* + +//Holds the DPDM Polarity +//USB_DPDM_INVALID_INVALID = 0 +//USB_DPDM_INVALID_FALLING = 1 +//USB_DPDM_INVALID_RISING = 2 +//USB_DPDM_FALLING_INVALID = 3 +//USB_DPDM_RISING_INVALID = 4 +//USB_DPDM_FALLING_FALLING = 5 +//USB_DPDM_FALLING_RISING = 6 +//USB_DPDM_RISING_FALLING = 7 +//USB_DPDM_RISING_RISING = 8 +Name(DPP1, Buffer(){0x0}) + +//USB Role Switch For Secondary Port +Device(URS1) +{ + Name(_HID, "HID_URS0") + Name(_CID, "PNP0CA1") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + Name(_CCA, Zero) // Cache-incoherent bus-master, Hardware does not manage cache coherency + Name(_DEP, Package(0x1) + { + \_SB_.PEP0 + }) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x0A800000, 0x000FFFFF) + //USBID pin Interrupt [USB_ID] + GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {488} + }) + + // Dynamically enumerated device (host mode stack) on logical USB bus + Device(USB1) + { + Name(_ADR, 0) + Name(_S0W, 3) // Enable power management + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x80,0x01, // Group Token:0; Group Position:1; So Connector ID is 1. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x06, // Connector type: uAB + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + //usb30_sec_ctrl_irq[0] + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xAA} + }) + Store(RBUF, Local0) + + ConcatenateResTemplate(Local0, ResourceTemplate() + { + //Qusb2Phy_sec_intr + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x17B} + // qmp_usb3_lfps_rxterm_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x207} + // eud_p1_dmse_int_mx - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x20A} + // eud_p1_dpse_int_mx - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x20B} + }, Local1) + + Return(Local1) + } + + Method(_STA) + { + Return (0xf) + } + + //Method to set DPDM Polarity for Pep Driver + Method(DPM1, 0x1, NotSerialized) { + // ARG 0 ?DPDM polarity + Store(Arg0, \_SB.DPP1) //DPDM Polarity + Notify(\_SB.PEP0, 0xA1) + } + + // Device Specific Method takes 4 args: + // Arg0 : Buffer containing a UUID [16 bytes] + // Arg1 : Integer containing the Revision ID + // Arg2 : Integer containing the Function Index + // Arg3 : Empty Package (Not used) + Method (_DSM, 0x4, NotSerialized) + { + // UUID selector + switch(ToBuffer(Arg0)) { + // UFX interface identifier + case(ToUUID("CE2EE385-00E6-48CB-9F05-2EDB927C4899")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {0,2,3} supported + case(0) { Return(Buffer(){0x0D}); Break; } + // Function 0 only supported for invalid revision + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 2: Port type identification + // 0x00 ?Regular USB + // 0x01 ?HSIC + // 0x02 ?SSIC + // 0x03 ?0xff reserved + case(2) { Return(0x0); Break; } + + // Function 3: Query Controller Capabilities + // bit 0 represents the support for software assisted USB endpoint offloading feature + // 1 - Offloading endpoint supported + case(3) { Return(0x1); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {CE2EE385-00E6-48CB-9F05-2EDB927C4899} + default { Return (Buffer(){0x00}); Break; } + } // UUID + } // _DSM + // + // The following values of PHY will be configured if OEMs do not + // overwrite the values. + // + // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY. + // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing + // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis. + // + // AccessMethod: + // 0 - DirectAccess: The register address is accessed directly from the mapped memory. + // + Method(PHYC, 0x0, NotSerialized) { + Name (CFG0, Package() + { + // AccessMethod, REG ADDR, Value + // ------------------------------- + //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR + //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing + //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis + }) + Return (CFG0) + } + } // USB1 + + // Dynamically enumerated device (peripheral mode stack) on logical USB bus + Device(UFN1) + { + Name(_ADR, 1) + Name(_S0W, 3) // Enable power management + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x80,0x01, // Group Token:0; Group Position:1; So Connector ID is 1. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x09, // Connector type: Type C connector - USB2 and SS with switch. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + Name(_CRS, ResourceTemplate() { + // usb30_sec_ctrl_irq[0] + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xAA} + //usb30_sec_power_event_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0xA7} + //Attach,Detach Interrupt [USB2_VUSB_DET] + GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0, "\\_SB.PM01",,,,RawDataBuffer() {0x00, 0x00, 0x00, 0x00}) {487} + }) + + // Device Specific Method takes 4 args: + // Arg0 : Buffer containing a UUID [16 bytes] + // Arg1 : Integer containing the Revision ID + // Arg2 : Integer containing the Function Index + // Arg3 : Package that contains function-specific arguments + Method (_DSM, 0x4, NotSerialized) + { + // UUID selector + switch(ToBuffer(Arg0)) { + // UFX interface identifier + case(ToUUID("FE56CFEB-49D5-4378-A8A2-2978DBE54AD2")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {1} supported + case(0) { Return(Buffer(){0x03}); Break; } + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 1: Return number of supported USB PHYSICAL endpoints + // Synopsys core configured to support 16 IN/16 OUT EPs, including EP0 + case(1) { Return(32); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {FE56CFEB-49D5-4378-A8A2-2978DBE54AD2} + + // QCOM specific interface identifier + case(ToUUID("18DE299F-9476-4FC9-B43B-8AEB713ED751")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {1} supported + case(0) { Return(Buffer(){0x03}); Break; } + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 1: Return device capabilities bitmap + // Bit Description + // --- ------------------------------- + // 0 Superspeed Gen1 supported + // 1 PMIC VBUS detection supported + // 2 USB PHY interrupt supported + // 3 Type-C supported + // 4 Delay USB initialization + // 5 HW based charger detection + case(1) { Return(0x33); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {18DE299F-9476-4FC9-B43B-8AEB713ED751} + + default { Return (Buffer(){0x00}); Break; } + } // UUID + } // _DSM + + // + // The following values of PHY will be configured if OEMs do not + // overwrite the values. + // + // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY. + // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing + // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis. + // + // AccessMethod: + // 0 - DirectAccess: The register address is accessed directly from the mapped memory. + // + Method(PHYC, 0x0, NotSerialized) { + Name (CFG0, Package() + { + // AccessMethod, REG ADDR, Value + // ------------------------------- + //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR + //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing + //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis + }) + Return (CFG0) + } + } // UFN1 +} // URS1 +*/ \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/wcnss_bt.asl b/sdm845Pkg/AcpiTables/common/wcnss_bt.asl new file mode 100644 index 0000000..968cc0c --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/wcnss_bt.asl @@ -0,0 +1,53 @@ +// This file contains ACPI definitions, configuration and look-up tables +// for Bluetooth Device +// + +// +// QCA6174 Bluetooth +// +Device(BTH0) +{ + Name(_HID, "HID_BTUR") + Alias(\_SB.PSUB, _SUB) + Name(_DEP, Package(0x3) + { + \_SB_.PEP0, + \_SB_.PMIC, + \_SB_.UAR7 // depends on UART ACPI definition + }) + Name(_PRW, Package(0x2) + { + Zero, + Zero + }) + Name(_S4W, 0x2) + Name(_S0W, 0x2) + Method(_CRS, 0x0, NotSerialized) + { + Name(PBUF, ResourceTemplate() + { + UARTSerialBus( + 115200, // ConnectionSpeed + DataBitsEight, // BitsPerByte (defaults to DataBitsEight) + StopBitsOne, // StopBits (defaults to StopBitsOne) + 0xC0, // LinesInUse + LittleEndian, // IsBigEndian (defaults to LittleEndian) + ParityTypeNone, // Parity (defaults to ParityTypeNone) + FlowControlHardware, // FlowControl (defaults to FlowControlNone) + 0x20, // ReceiveBufferSize + 0x20, // TransmitBufferSize + "\\_SB.UAR7", // depends on UART ACPI definition + 0, // ResourceSourceIndex (defaults to 0) + ResourceConsumer, // ResourceUsage (defaults to ResourceConsumer) + , // DescriptorName + ) + + // GpioIo(Exclusive, PullDown, 0, 0, , "\\_SB.PM01", , , , ) {146} // 0x690 - PM_INT__PM1_GPIO19__GPIO_IN_STS + }) + Return(PBUF) + } + Method(_STA, 0x0, NotSerialized) + { + Return(0xF) + } +}//End BTH0 diff --git a/sdm845Pkg/AcpiTables/common/wcnss_fm.asl b/sdm845Pkg/AcpiTables/common/wcnss_fm.asl new file mode 100644 index 0000000..8bd0f86 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/wcnss_fm.asl @@ -0,0 +1,27 @@ +// This file contains ACPI definitions, configuration and look-up tables +// for FM transport Device +// + +// +// Sillab FM chip +// +//Device (FMSL) +//{ +// Name (_DEP, Package(0x2) +// { +// \_SB_.PEP0, +// \_SB_.I2C7 +// }) +// Name (_HID, "HID_FMSL") + +// Method (_CRS, 0x0, NotSerialized) +// { +// Name (RBUF, ResourceTemplate () +// { +// I2CSerialBus( 0x11, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.I2C7",,,,) +// GpioInt(Edge, ActiveLow, Exclusive, PullUp, 0, "\\_SB.GIO0", ,) {38} +// GpioIo(Exclusive, PullUp, 0, 0, , "\\_SB.GIO0", ,) {39} +// }) +// Return (RBUF) +// } +//} diff --git a/sdm845Pkg/AcpiTables/common/wcnss_resources.asl b/sdm845Pkg/AcpiTables/common/wcnss_resources.asl new file mode 100644 index 0000000..8279356 --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/wcnss_resources.asl @@ -0,0 +1,385 @@ +// PEP resources for WCNSS +Scope(\_SB_.PEP0) +{ + //Wireless Connectivity Devices + Method(EWMD) + { + Return(WBRC) + } + + Name(WBRC, + Package() + { + // PEP settings for Wlan iHelium + Package() + { + "DEVICE", + "\\_SB.AMSS.QWLN", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + + Package() + { + "FSTATE", + 0x0, // F0 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS7_A", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 1028000, // Voltage = 1.028 V + 1, // Software Enable = Enable + 6, // Software Power Mode = Auto + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO5_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 800000, // Voltage = 0.8 V + 1, // Software Enable = Enable + 7, // Software Power Mode = NPM + 0, // Head Room + }, + }, + }, + Package() + { + "DSTATE", + 0x2, // D2 state + + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO5_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS7_A", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO5_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS7_A", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + }, + + package() + { + "ABANDON_DSTATE", + 2 // Abandon D state defined as D2 + }, + }, + // END AMSS.QWLN + + // PEP settings for Ltecoex device + Package() + { + "DEVICE", + "\\_SB.COEX", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + + Package() + { + "PSTATE", + 0x0, // P0 state + + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS7_A", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 1028000, // Voltage = 1.028 V + 1, // Software Enable = Enable + 6, // Software Power Mode = Auto + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO5_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 800000, // Voltage = 0.8 V + 1, // Software Enable = Enable + 7, // Software Power Mode = NPM + 0, // Head Room + }, + }, + }, + Package() + { + "PSTATE", + 0x1, // P1 state + + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO5_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS7_A", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + }, + }, + }, + // END _SB.COEX + + // PEP settings for Bluetooth SOC + Package() + { + "DEVICE", + "\\_SB.BTH0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS3_A", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 1352000, // Voltage = 1.352 V + 1, // Software Enable = Enable + 6, // Software Power Mode = Auto + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS5_A", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 2040000, // Voltage = 2.04 V + 1, // Software Enable = Enable + 6, // Software Power Mode = Auto + 0, // Head Room + }, + }, + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO7_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 1800000, // Voltage = 1.8 V + 1, // Software Enable = Enable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO17_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 1304000, // Voltage = 1.304 V + 1, // Software Enable = Enable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO25_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 3104000, // Voltage = 3.104 V + 1, // Software Enable = Enable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO7_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO17_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO25_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS3_A", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS5_A", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 5, // Software Power Mode = LPM + 0, // Head Room + }, + }, + }, + }, + // END BTH0 + + // PEP settings for FM SOC + // END FM + + }) // END WBRC +} + diff --git a/sdm845Pkg/AcpiTables/common/wcnss_wlan.asl b/sdm845Pkg/AcpiTables/common/wcnss_wlan.asl new file mode 100644 index 0000000..2b2a10d --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/wcnss_wlan.asl @@ -0,0 +1,82 @@ + +// +// iHelium WLAN +// +Device (QWLN) +{ + Name(_ADR, 0) + Name(_DEP, Package(2) + { + \_SB.PEP0, + \_SB.MMU0 + }) + Name(_PRW, Package() {0,0}) // wakeable from S0 + Name(_S0W, 2) // S0 should put device in D2 for wake + Name(_S4W, 2) // all other Sx (just in case) should also wake from D2 + Name(_PRR, Package(0x1) { \_SB.AMSS.QWLN.WRST }) // Power resource reference for device reset and recovery. + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // Shared memory + Memory32Fixed (ReadWrite, 0x18800000, 0x800000) //CE registers + Memory32Fixed (ReadWrite, 0xC250000, 0x10) //WCSSAON registers + Memory32Fixed (ReadWrite, 0x8C400000, 0x100000) //MSA image address + // CE interrupts + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {446} //CE0 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {447} //CE1 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {448} //CE2 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {449} //CE3 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {450} //CE4 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {451} //CE5 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {452} //CE6 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {453} //CE7 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {454} //CE8 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {455} //CE9 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {456} //CE10 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {457} //CE11 interrupt + }) + Return (RBUF) + } + + // wlan msa memory size + Method (WMSA) + { + Return(Package () + { + 0x100000 + }) + } + + PowerResource(WRST, 0x5, 0x0) + { + // + // Dummy _ON, _OFF, and _STA methods. All power resources must have these + // three defined. + // + Method(_ON, 0x0, NotSerialized) + { + } + Method(_OFF, 0x0, NotSerialized) + { + } + Method(_STA, 0x0, NotSerialized) + { + Return(0xf) + } + Method(_RST, 0x0, NotSerialized) + { + } + } +} + +//agent driver of wlan for supporting windows thermal framework +Scope(\_SB) +{ + Device (COEX) + { + Name (_HID, "HID_LTE_COEX_Manager_Driver") + Alias(\_SB.PSUB, _SUB) + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/common/win_mproc.asl b/sdm845Pkg/AcpiTables/common/win_mproc.asl new file mode 100644 index 0000000..4ce7dbd --- /dev/null +++ b/sdm845Pkg/AcpiTables/common/win_mproc.asl @@ -0,0 +1,359 @@ +// +// MPROC Drivers (PIL Driver and Subsystem Drivers) +// + + +// +// RPE Subsystem Notifier (RPEN) +// +Device (RPEN) +{ + Name (_HID, "HID_RPEN") + Alias(\_SB.PSUB, _SUB) +} + +// +// Peripheral Image Loader (PIL) Driver +// +Device (PILC) +{ + Name (_HID, "HID_PILC") + + Method(PILX) + { + return (PILP) + } + + Name(PILP, + Package() + { + // Methods needed for PIL bootup proceedure + // Drive will parse this list and call each + // method accordingly + "OPCA", // ACPO - ACPI Override for MBA load address + } + ) + + Method (ACPO) + { + Name(PKGG, Package() + { + Package () + { + // Represents MBA subsystem + 0x00000000, // Address + 0x00000000, // Length + ToUUID ("BA58766D-ABF2-4402-88D7-90AB243F6C77") + } + }) + + // Copy ACPI globals for Address for this subsystem into above package for use in driver + Store (RMTB, Index(DeRefOf(Index (PKGG, 0)), 0)) + Store (RMTX, Index(DeRefOf(Index (PKGG, 0)), 1)) + + Return (PKGG) + } + +} + + +// +// RPE Crash Dump Injector (CDI) Driver +// +Device (CDI) +{ + Name (_DEP, Package(0x2) + { + \_SB_.PILC, + \_SB_.RPEN + }) + Name (_HID, "HID_CDI") + Alias(\_SB.PSUB, _SUB) + + Method(_STA, 0) + { + return (0xf) + } +} + + +// +// SCSS device : loads sensors subsystem (SCSS) image +// +Device (SCSS) +{ + Name (_DEP, Package(0x6) + { + \_SB_.PEP0, + \_SB_.PILC, + \_SB_.GLNK, + \_SB_.IPC0, + \_SB_.RPEN, + \_SB_.SSDD, + }) + + Name (_HID, "HID_SCSS") + Alias(\_SB.PSUB, _SUB) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // Inbound interrupt from SCSS dog bite + // See http://ipcatalog.qualcomm.com/irqs/chip/53/map/438 + // q6ss_irq_out_apps_ipc[5 = SYS_apssQgicSPI[377] = 409 + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {409} + }) + Return (RBUF) + } + + +} + +// +// ADSP Driver: load ADSP image +// +Device (ADSP) +{ + Name (_DEP, Package(0x7) + { + \_SB_.PEP0, + \_SB_.PILC, + \_SB_.GLNK, + \_SB_.IPC0, + \_SB_.RPEN, + \_SB_.SSDD, + \_SB_.PDSR, + }) + Name (_HID, "HID_ADSP") + Alias(\_SB.PSUB, _SUB) + // + // WDIR - Watch Dog Interrupt Registers + // + Method (WDIR) + { + // See http://ipcatalog.qualcomm.com/swi/module/1280630 + Return( Package () + { + 0x02, // Interrupt number - 2nd bit in Seventh register + 0x17A0011C, // APSS_GICD_ISENABLERn (n represents Seventh register), register used to enable WDOG bite interrupt. 0x17A00000 + 0x00000100 (0x17A00100) + 0x4 * (n), n=7 + 0x17A0019C, // APSS_GICD_ICENABLERn (n represents Seventh register), register used to disable WDOG bite interrupt. 0x17A00000 + 0x00000180 (0x17A00180) + 0x4 * (n), n=7 + 0x17A0021C // APSS_GICD_ISPENDRn (n represents Seventh register), register used to clear pending WDOG bite interrupt. 0x17A00000 + 0x00000200 (0x17A00200) + 0x4 * (n), n=7 + }) + } + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // Inbound interrupt from LPASS dog bite + // See http://ipcatalog.qualcomm.com/irqs/chip/53/map/438 + // u_lpass_lpass_irq_out_apcs[6] = SYS_apcsQgicSPI[162] = 194 + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {194} + }) + Return (RBUF) + } + + + + Include("slimbus.asl") +} + + +// +// AMSS Driver: Used for loading the modem binaries +// +Device (AMSS) +{ + Name(_CCA, 0) + Name (_DEP, Package(0x9) + { + \_SB_.PEP0, + //\_SB_.PMIC, + \_SB_.IPA, + \_SB_.GLNK, + \_SB_.IPC0, + \_SB_.PILC, + \_SB_.RFS0, + \_SB_.RPEN, + \_SB_.SSDD, + \_SB_.PDSR, + }) + Name (_HID, "HID_AMSS") + + Name (WLEN, 0x1) // Holds the enable/disable flag for WLAN + + + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // Inbound interrupt from Q6SW dog bite: refer http://ipcatalog.qualcomm.com/irqs/chip/53/map/438 + // q6ss_wdog_exp_irq = SYS_apssQgicSPI[266] = 298 + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {298} + }) + Return (RBUF) + } + + // + // WDIR - Watch Dog Interrupt Registers + // + Method (WDIR) + { + Return( Package () + { + // See http://ipcatalog.qualcomm.com/swi/module/1280630 + 0x00, // Interrupt number - 0th bit in Fifteenth register + 0x17A0013C, // APSS_GICD_ISENABLERn (n represents Fifteenth register), register used to enable WDOG bite interrupt. + 0x17A001BC, // APSS_GICD_ICENABLERn (n represents Fifteenth register), register used to disable WDOG bite interrupt. + 0x17A002BC // APSS_GICD_ICPENDRn (n represents Fifteenth register), register used to clear pending WDOG bite interrupt. + }) + } + + Method(_STA, 0) + { + return (0xf) + } + + Include("wcnss_wlan.asl") +} + + +// QMI Service manager +// +Device (QSM) +{ + Name (_HID, "HID_QSM") + + Alias(\_SB.PSUB, _SUB) + + Name (_DEP, Package(0x4) + { + \_SB_.GLNK, + \_SB_.IPC0, + \_SB_.PILC, + \_SB_.RPEN + }) + + // + // DHMS client memory config + // + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // UEFI memory bank for DHMS clients + // Note: must match order of flagged for carveout packages below. See http://ipcatalog.qualcomm.com/memmap/chip/53/map/353#block=755839 + Memory32Fixed(ReadWrite, 0x98f00000, 0x00600000) + }) + Return (RBUF) + } + + Method(_STA, 0) + { + return (0xf) + } + +} + +// +// Subsys Dependency Device +// Subsys devices that use QCCI should have an dependency on this +// +Device (SSDD) +{ + Name (_HID, "HID_SSDD") + + Alias(\_SB.PSUB, _SUB) + + Name (_DEP, Package(0x2) + { + \_SB_.GLNK, + \_SB_.TFTP + }) +} + + +// +// PDSR device +// +Device (PDSR) +{ + Name (_HID, "HID_PDSR") + + Alias(\_SB.PSUB, _SUB) + + Name (_DEP, Package(0x3) + { + \_SB_.PEP0, + \_SB_.GLNK, + \_SB_.IPC0, + }) +} + + +// +// CDSP Driver: load CDSP image +// +Device (CDSP) +{ + Name (_DEP, Package(0x7) + { + \_SB_.PEP0, + \_SB_.PILC, + \_SB_.GLNK, + \_SB_.IPC0, + \_SB_.RPEN, + \_SB_.SSDD, + \_SB_.PDSR, + }) + Name (_HID, "HID_CDSP") + Alias(\_SB.PSUB, _SUB) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // TURING QDSP6 WDOG Bite to APCS + // See http://ipcatalog.qualcomm.com/irqs/chip/53/map/480 + // q6ss_wdog_exp_irq = SYS_apssQgicSPI[578] = 610 + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {610} + }) + Return (RBUF) + } +} + + +// +// TFTP Device +// +Device (TFTP) +{ + Name (_HID, "HID_TFTP") + + Alias(\_SB.PSUB, _SUB) + + Name (_DEP, Package(0x1) + { + \_SB_.IPC0, + }) +} + +// QcShutdownSvc Device +Device (SSVC) +{ + Name (_DEP, Package(0x2) + { + \_SB_.IPC0, // IPC Router used by QMI, in turn depends on GLINK + \_SB_.QDIG // Qualcomm DIAG service + }) + Name (_HID, "HID_SSVC") + Alias(\_SB.PSUB, _SUB) + Name (_CID, "ACPI\HID_SSVC") + Name (_UID, 0) +} + +// Warning: Include these files after device scopes have been defined +//Include("cust_win_mproc.asl") // Customer specific data +Include("plat_win_mproc.asl") // Platform specific data + -- 2.45.2