From 1e6db6166b1e3f253aa7b9f248a66b1d3ee1b9d8 Mon Sep 17 00:00:00 2001 From: strongtz Date: Sat, 20 Mar 2021 17:30:42 +0800 Subject: [PATCH] WIP: fajita ACPI tables --- sdm845Pkg/AcpiTables/fajita/Dsdt.asl | 96 + sdm845Pkg/AcpiTables/fajita/abd.asl | 31 + sdm845Pkg/AcpiTables/fajita/adc.asl | 720 +++ sdm845Pkg/AcpiTables/fajita/addSub.asl | 2 + sdm845Pkg/AcpiTables/fajita/backlightcfg.asl | 89 + sdm845Pkg/AcpiTables/fajita/buses.asl | 4687 +++++++++++++++++ .../AcpiTables/fajita/corebsp_resources.asl | 4234 +++++++++++++++ sdm845Pkg/AcpiTables/fajita/cust_camera.asl | 653 +++ .../AcpiTables/fajita/cust_camera_exasoc.asl | 597 +++ .../fajita/cust_camera_exasoc_resources.asl | 651 +++ .../fajita/cust_camera_resources.asl | 1265 +++++ sdm845Pkg/AcpiTables/fajita/wlan_11ad.asl | 7 + 12 files changed, 13032 insertions(+) create mode 100755 sdm845Pkg/AcpiTables/fajita/Dsdt.asl create mode 100755 sdm845Pkg/AcpiTables/fajita/abd.asl create mode 100755 sdm845Pkg/AcpiTables/fajita/adc.asl create mode 100755 sdm845Pkg/AcpiTables/fajita/addSub.asl create mode 100755 sdm845Pkg/AcpiTables/fajita/backlightcfg.asl create mode 100755 sdm845Pkg/AcpiTables/fajita/buses.asl create mode 100755 sdm845Pkg/AcpiTables/fajita/corebsp_resources.asl create mode 100755 sdm845Pkg/AcpiTables/fajita/cust_camera.asl create mode 100755 sdm845Pkg/AcpiTables/fajita/cust_camera_exasoc.asl create mode 100755 sdm845Pkg/AcpiTables/fajita/cust_camera_exasoc_resources.asl create mode 100755 sdm845Pkg/AcpiTables/fajita/cust_camera_resources.asl create mode 100755 sdm845Pkg/AcpiTables/fajita/wlan_11ad.asl diff --git a/sdm845Pkg/AcpiTables/fajita/Dsdt.asl b/sdm845Pkg/AcpiTables/fajita/Dsdt.asl new file mode 100755 index 0000000..1c6c3dd --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/Dsdt.asl @@ -0,0 +1,96 @@ + +// +// NOTE: The 3rd parameter (i.e. ComplianceRevision) must be >=2 for 64-bit integer support. +// +DefinitionBlock("DSDT.AML", "DSDT", 0x02, "QCOMM ", "SDM850 ", 3) +{ + Scope(\_SB_) { + + Include("addSub.asl") + Include("dsdt_common.asl") + Include("cust_dsdt.asl") + + Include("usb.asl") + + // Thermal Zone devices depend on PEP (included in dsdt_common). Please be CAREFUL on location + Include("cust_thermal_zones.asl") + + + // + // Hardware Notifications + // + Include("cust_hwn.asl") + + // + // Touch + // + Include("cust_touch.asl") + + // + // Buttons + // + Include("cust_arraybutton.asl") + + // + // Data components + // + Include("data.asl") + + // + //Qualcomm Diagnostic Consumer Interface + // + Device (QDCI) + { + Name (_DEP, Package(0x1) + { + \_SB_.GLNK + }) + Name (_HID, "QCOM0224") + Alias(\_SB.PSUB, _SUB) + } + + // + // Sillab FM chip + // + //Include("wcnss_fm.asl") + + // + // Bluetooth + // + Include("wcnss_bt.asl") + + // + // QCOM App Profiler: Used by performance team + // + // Device (PER0) + // { + // Name (_HID, "QCOM02ED") + + // } + + // XOMC: 48MHz XO Mode configuration + // 0: NO 48MHz XO on HW, otherwise 1 + // Method WXOM = 'MOXW': WCNSS XO Mode configuration + // Returns XOMC value. Invoked by WCN driver. + // WCN driver turns ON or OFF 48MHz according to XOMC value. + // + // NOTE: this method explicitly sets the XO mode and when present bypasses auto-ID checking in the WCN driver. + // If this is not in ACPI, WCN driver will do auto-ID checking and decide the 48MHz XO mode according to the chip ID + //Scope(\_SB_.RIVA) + //{ + // Name(XOMC, 0x0) + // + // Method(WXOM) + // { + // return(XOMC) + // } + //} + + // + // ADC driver + // + Include("adc.asl") + //Include("Bringup_Disable.asl") + } + +} diff --git a/sdm845Pkg/AcpiTables/fajita/abd.asl b/sdm845Pkg/AcpiTables/fajita/abd.asl new file mode 100755 index 0000000..708dea3 --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/abd.asl @@ -0,0 +1,31 @@ +// +// This file contains ASL Bridge Device definitions +// + +// +// ASL BRIDGE Device +// +Device (ABD) +{ + Name (_DEP, Package(0x1) + { + \_SB_.PEP0 + }) + Name (_HID, "QCOM0242") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_STA) { + Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager + } + + OperationRegion(ROP1, GenericSerialBus, 0x00000000, 0x100) + Name(AVBL, Zero) + Method(_REG, 0x2, NotSerialized) + { + If(Lequal(Arg0, 0x9)) + { + Store(Arg1, AVBL) + } + } +} diff --git a/sdm845Pkg/AcpiTables/fajita/adc.asl b/sdm845Pkg/AcpiTables/fajita/adc.asl new file mode 100755 index 0000000..ca71474 --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/adc.asl @@ -0,0 +1,720 @@ +/*============================================================================ + FILE: adc.asl + + OVERVIEW: This file contains the board-specific configuration info for + ADC1 - qcadc analog-to-digital converter (ADC): ACPI device + definitions, common settings, etc. + +============================================================================*/ + + +// Note: FgAdc is enabled in NTAuthority's DSDT, but disabled in 850_CLS + + +/*---------------------------------------------------------------------------- + * QCADC + * -------------------------------------------------------------------------*/ + +Device(ADC1) +{ + /*---------------------------------------------------------------------------- + * Dependencies + * -------------------------------------------------------------------------*/ + Name(_DEP, Package(0x2) + { + \_SB_.SPMI, + \_SB_.PMIC + }) + + /*---------------------------------------------------------------------------- + * HID + * -------------------------------------------------------------------------*/ + Name(_HID, "QCOM0221") + Alias(\_SB.PSUB, _SUB) + Name(_UID, 0) + + /*---------------------------------------------------------------------------- + * ADC Resources + * -------------------------------------------------------------------------*/ + Method(_CRS) + { + /* + * Interrupts + */ + Name (INTB, ResourceTemplate() + { + // VAdc - EOC + // ID = {slave id}{perph id}{int} = {0}{0011 0001}{000} = 0x188 + GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {32} // 0x188 - PM_INT__VADC_HC1_USR__EOC + + // VAdc TM - All interrupts + // ID = {slave id}{perph id}{int} = {0}{0011 0100}{000} = 0x1A0 + GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {40} // 0x1A0 - PM_INT__VADC_HC7_BTM__THR + + // FgAdc - All interrupts + // ID = {slave id}{perph id}{int} = {10}{0100 0101}{000} = 0x1228 + GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {360} // 0x1228 - PM_INT__FG_ADC__BT_ID + }) + + /* + * SPMI peripherals + */ + Name(NAM, Buffer() {"\\_SB.SPMI"}) + + // VAdc + Name(VUSR, Buffer() + { + 0x8E, // SPB Descriptor + 0x13, 0x00, // Length including NAM above + 0x01, // +0x00 SPB Descriptor Revision + 0x00, // +0x01 Resource Source Index + 0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff + 0x02, // +0x03 Consumer + controller initiated + 0x00, 0x31, // +0x04 Type specific flags . Slave id, Upper8 bit address + 0x01, // +0x06 Type specific revision + 0x00, 0x00 // +0x07 type specific data length + // +0x09 - 0xd bytes for NULL-terminated NAM + // Length = 0x13 + }) + + // VAdc TM + Name(VBTM, Buffer() + { + 0x8E, // SPB Descriptor + 0x13, 0x00, // Length including NAM above + 0x01, // +0x00 SPB Descriptor Revision + 0x00, // +0x01 Resource Source Index + 0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff + 0x02, // +0x03 Consumer + controller initiated + 0x00, 0x34, // +0x04 Type specific flags . Slave id, Upper8 bit address + 0x01, // +0x06 Type specific revision + 0x00, 0x00 // +0x07 type specific data length + // +0x09 - 0xd bytes for NULL-terminated NAM + // Length = 0x13 + }) + + // FgAdc + Name(FGRR, Buffer() + { + 0x8E, // SPB Descriptor + 0x13, 0x00, // Length including NAM above + 0x01, // +0x00 SPB Descriptor Revision + 0x00, // +0x01 Resource Source Index + 0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff + 0x02, // +0x03 Consumer + controller initiated + 0x02, 0x45, // +0x04 Type specific flags . Slave id, Upper8 bit address + 0x01, // +0x06 Type specific revision + 0x00, 0x00 // +0x07 type specific data length + // +0x09 - 0xd bytes for NULL-terminated NAM + // Length = 0x13 + }) + + // Name(END, Buffer() {0x79, 0x00}) + + // {VUSR, NAM, VBTM, NAM, FGRR, NAM, INTB} + // {Local1, Local2, Local3, INTB} + // {Local4, Local5} + // {Local0} + // Concatenate(VUSR, NAM, Local1) + // Concatenate(VBTM, NAM, Local2) + // Concatenate(FGRR, NAM, Local3) + // Concatenate(Local1, Local2, Local4) + // Concatenate(Local3, INTB, Local5) + // Concatenate(Local4, Local5, Local0) + + // {VUSR, NAM, VBTM, NAM, INTB} + // {Local1, Local2, INTB} + // {Local3, INTB} + // {Local0} + Concatenate (VUSR, NAM, Local1) + Concatenate (VBTM, NAM, Local2) + Concatenate (FGRR, NAM, Local3) + Concatenate (Local1, Local2, Local4) + Concatenate (Local3, INTB, Local5) + Concatenate (Local4, Local5, Local0) + Return (Local0) + } + + /*---------------------------------------------------------------------------- + * Device configuration + * -------------------------------------------------------------------------*/ + /* + * General ADC properties + * + * bHasVAdc: + * Whether or not TM is supported. + * 0 - Not supported + * 1 - Supported + * + * bHasTM: + * Whether or not TM is supported. + * 0 - Not supported + * 1 - Supported + * + * bHasFgAdc: + * Whether or not FGADC is supported. + * 0 - Not supported + * 1 - Supported + * + */ + Method (ADDV) + { + Return (Package() + { + /* .bHasVAdc = */ 1, + /* .bHasTM = */ 1, + /* .bHasFgAdc = */ 1, + }) + } + + /*---------------------------------------------------------------------------- + * Voltage ADC (VADC) Configuration + * -------------------------------------------------------------------------*/ + /* + * General VADC properties + * + * bUsesInterrupts: + * End-of-conversion interrupt mode. + * 0 - Polling mode + * 1 - Interrupt mode + * + * uFullScale_code: + * Full-scale ADC code. + * + * uFullScale_uV: + * Full-scale ADC voltage in uV. + * + * uReadTimeout_us: + * Timeout for reading ADC channels in us. + * + * uLDOSettlingTime_us: + * LDO settling time in us. + * + * ucMasterID: + * Master ID to send the interrupt to. + * + * ucPmicDevice: + * PMIC which has the VAdc. + * + * usMinDigRev: + * Minimum digital version + * + * usMinAnaRev: + * Minimum analog version + * + * ucPerphType: + * ADC peripheral type. + * + */ + Method (GENP) + { + Return (Package() + { + /* .bUsesInterrupts = */ 0, + /* .uFullScale_code = */ 0x4000, + /* .uFullScale_uV = */ 1875000, + /* .uReadTimeout_us = */ 500000, + /* .uLDOSettlingTime_us = */ 17, + /* .ucMasterID = */ 0, + /* .ucPmicDevice = */ 0, + /* .usMinDigRev = */ 0x300, + /* .usMinAnaRev = */ 0x100, + /* .ucPerphType = */ 0x8, + }) + } + + /*=========================================================================== + + FUNCTION PTCF + + DESCRIPTION Scales the ADC result from millivolts to 0.001 degrees + Celsius using the PMIC thermistor conversion equation. + + DEPENDENCIES None + + PARAMETERS Arg0 [in] ADC result data (uMicroVolts) + + RETURN VALUE Scaled result in mDegC + + SIDE EFFECTS None + + ===========================================================================*/ + Method (PTCF, 1) + { + /* + * Divide by two to convert from microvolt reading to micro-Kelvin. + * + * Subtract 273160 to convert the temperature from Kelvin to + * 0.001 degrees Celsius. + */ + ShiftRight (Arg0, 1, Local0) + Subtract (Local0, 273160, Local0) + Return (Local0) + } + + /*=========================================================================== + + FUNCTION PTCI + + DESCRIPTION Inverse of PTCF - scaled PMIC temperature to microvolts. + + DEPENDENCIES None + + PARAMETERS Arg0 [in] temperature in mDegC + + RETURN VALUE ADC result data (uMicroVolts) + + SIDE EFFECTS None + + ===========================================================================*/ + Method (PTCI, 1) + { + Add (Arg0, 273160, Local0) + ShiftLeft (Local0, 1, Local0) + Return (Local0) + } + + /* + * VADC channel to GPIO mapping + * + */ + Method (VGIO) + { + Return (Package() + { + Package() + { + /* .GPIO = */ 8, + /* .aucChannels = */ Buffer(){0x12, 0x32, 0x52, 0x72}, + }, + + Package() + { + /* .GPIO = */ 9, + /* .aucChannels = */ Buffer(){0x13, 0x33, 0x53, 0x73}, + }, + + Package() + { + /* .GPIO = */ 10, + /* .aucChannels = */ Buffer(){0x14, 0x34, 0x54, 0x74}, + }, + + Package() + { + /* .GPIO = */ 11, + /* .aucChannels = */ Buffer(){0x15, 0x35, 0x55, 0x75}, + }, + + Package() + { + /* .GPIO = */ 12, + /* .aucChannels = */ Buffer(){0x16, 0x36, 0x56, 0x76}, + }, + + Package() + { + /* .GPIO = */ 21, + /* .aucChannels = */ Buffer(){0x17, 0x37, 0x57, 0x77, 0x97}, + }, + + Package() + { + /* .GPIO = */ 22, + /* .aucChannels = */ Buffer(){0x18, 0x38, 0x58, 0x78, 0x98}, + }, + + Package() + { + /* .GPIO = */ 23, + /* .aucChannels = */ Buffer(){0x19, 0x39, 0x59, 0x79, 0x99}, + }, + }) + } + + /*---------------------------------------------------------------------------- + * Voltage ADC Threshold Monitor (VADCTM) Configuration + * -------------------------------------------------------------------------*/ + /* + * General VADCTM properties + * + * eAverageMode: + * Obtains N ADC readings and averages them together. + * 0 - VADCTM_AVERAGE_1_SAMPLE + * 1 - VADCTM_AVERAGE_2_SAMPLES + * 2 - VADCTM_AVERAGE_4_SAMPLES + * 3 - VADCTM_AVERAGE_8_SAMPLES + * 4 - VADCTM_AVERAGE_16_SAMPLES + * + * eDecimationRatio: + * The decimation ratio. + * 0 - VADCTM_DECIMATION_RATIO_256 + * 1 - VADCTM_DECIMATION_RATIO_512 + * 2 - VADCTM_DECIMATION_RATIO_1024 + * + * uFullScale_code: + * Full-scale ADC code. + * + * uFullScale_uV: + * Full-scale ADC voltage in uV. + * + * ucMasterID: + * Master ID to send the interrupt to. + * + * ucPmicDevice: + * PMIC which has the VAdc. + * + * usMinDigRev: + * Minimum digital version + * + * usMinAnaRev: + * Minimum analog version + * + * ucPerphType: + * ADC peripheral type. + * + */ + Method (VTGN) + { + Return (Package() + { + /* .eAverageMode = */ 2, + /* .eDecimationRatio = */ 2, + /* .uFullScale_code = */ 0x4000, + /* .uFullScale_uV = */ 1875000, + /* .ucMasterID = */ 0, + /* .ucPmicDevice = */ 0, + /* .usMinDigRev = */ 0x300, + /* .usMinAnaRev = */ 0x100, + /* .ucPerphType = */ 0x8, + }) + } + + /*---------------------------------------------------------------------------- + * Fuel Gauge ADC (FGADC) Configuration + * -------------------------------------------------------------------------*/ + /* + * General FGADC properties + * + * skinTempThreshRange: + * Range for skin temperature thresholds + * + * chgTempThreshRange: + * Range for charger temperature thresholds + * + * uFullScale_code: + * Full scale ADC value in code. + * + * uFullScale_uV: + * Full scale ADC value in microvolts. + * + * uMicroVoltsPerMilliAmps: + * Microvolts per milliamp scaling factor. + * + * uCodePerKelvin: + * Code per Kelvin scaling factor. + * + * uBattIdClipThresh: + * Max code for a BATT ID channel. + * + * uMaxWaitTimeus: + * Maximum time to wait for a reading to complete in microseconds. + * + * uSlaveId: + * PMIC slave ID. + * + * ucPmicDevice: + * PMIC which has the VAdc. + * + * ucPerphType: + * ADC peripheral type. + * + */ + Method (GENF) + { + Return (Package() + { + /* .skinTempThreshRange.nMin = */ 0xFFFFFFE2, // -30 + /* .skinTempThreshRange.nMax = */ 97, + /* .chgTempThreshRange.nMin = */ 0xFFFFFFCE, // -50 + /* .chgTempThreshRange.nMax = */ 160, + /* .uFullScale_code = */ 0x3ff, + /* .uFullScale_uV = */ 2500000, + /* .uMicroVoltsPerMilliAmps = */ 500, + /* .uCodePerKelvin = */ 4, + /* .uBattIdClipThresh = */ 820, + /* .uMaxWaitTimeUs = */ 5000000, + /* .uSlaveId = */ 2, + /* .ucPmicDevice = */ 1, + /* .ucPerphType = */ 0xD, + }) + } + + /* + * FGADC Channel Configuration Table + * + * The following table is the list of channels the FGADC can read. Below is + * a description of each field: + * + * sName: + * Appropriate string name for the channel from AdcInputs.h. + * + * eChannel: + * Which channel. + * 0 - FGADC_CHAN_SKIN_TEMP + * 1 - FGADC_CHAN_BATT_ID + * 2 - FGADC_CHAN_BATT_ID_FRESH + * 3 - FGADC_CHAN_BATT_ID_5 + * 4 - FGADC_CHAN_BATT_ID_15 + * 5 - FGADC_CHAN_BATT_ID_150 + * 6 - FGADC_CHAN_BATT_THERM + * 7 - FGADC_CHAN_AUX_THERM + * 8 - FGADC_CHAN_USB_IN_V + * 9 - FGADC_CHAN_USB_IN_I + * 10 - FGADC_CHAN_DC_IN_V + * 11 - FGADC_CHAN_DC_IN_I + * 12 - FGADC_CHAN_DIE_TEMP + * 13 - FGADC_CHAN_CHARGER_TEMP + * 14 - FGADC_CHAN_GPIO + * + * eEnable: + * Whether or not to enable the channel. + * 0 - FGADC_DISABLE + * 1 - FGADC_ENABLE + * + * ucTriggers: + * Mask of triggers. Use 0x0 for default trigger configuration. + * + * scalingFactor.num: + * Numerator of the channel scaling + * + * scalingFactor.den: + * Denominator of the channel scaling + * + * eScaling: + * The scaling method to use. + * 0 - FGADC_SCALE_TO_MILLIVOLTS + * 1 - FGADC_SCALE_BATT_ID_TO_OHMS + * 2 - FGADC_SCALE_INTERPOLATE_FROM_MILLIVOLTS (requires uInterpolationTableName) + * 3 - FGADC_SCALE_THERMISTOR + * 4 - FGADC_SCALE_CURRENT_TO_MILLIAMPS + * + * uInterpolationTableName: + * The name of the lookup table in ACPI that will be interpolated to obtain + * a physical value. Note that the physical value (which has default units + * of millivolts unless custom scaling function is used) is passed as the + * input. This value corresponds to the first column of the table. The + * scaled output appears in the physical adc result. + * 0 - No interpolation table + * WXYZ - Where 'WXYZ' is the interpolation table name + * + */ + Method (FCHN) + { + Return (Package() + { + /* BATT_ID_OHMS (BATT_ID pin) */ + Package() + { + /* .sName = */ "BATT_ID_OHMS", + /* .eChannel = */ 1, + /* .eEnable = */ 1, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 1, + /* .scalingFactor.den = */ 1, + /* .eScaling = */ 1, + /* .uInterpolationTableName = */ 0, + }, + + /* BATT_ID_OHMS_FRESH (BATT_ID pin) */ + Package() + { + /* .sName = */ "BATT_ID_OHMS_FRESH", + /* .eChannel = */ 2, + /* .eEnable = */ 1, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 1, + /* .scalingFactor.den = */ 1, + /* .eScaling = */ 1, + /* .uInterpolationTableName = */ 0, + }, + + /* BATT_THERM (BATT_THERM pin) */ + Package() + { + /* .sName = */ "BATT_THERM", + /* .eChannel = */ 6, + /* .eEnable = */ 1, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 1, + /* .scalingFactor.den = */ 1, + /* .eScaling = */ 3, + /* .uInterpolationTableName = */ 0, + }, + + /* AUX_THERM (AUX_THERM pin) */ + Package() + { + /* .sName = */ "AUX_THERM", + /* .eChannel = */ 7, + /* .eEnable = */ 1, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 1, + /* .scalingFactor.den = */ 1, + /* .eScaling = */ 3, + /* .uInterpolationTableName = */ 0, + }, + + /* SKIN_THERM (AUX_THERM pin) */ + Package() + { + /* .sName = */ "SKIN_THERM", + /* .eChannel = */ 0, + /* .eEnable = */ 1, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 1, + /* .scalingFactor.den = */ 1, + /* .eScaling = */ 3, + /* .uInterpolationTableName = */ 0, + }, + + /* PMIC_TEMP2 (internal sensor) */ + Package() + { + /* .sName = */ "PMIC_TEMP2", + /* .eChannel = */ 12, + /* .eEnable = */ 1, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 3, + /* .scalingFactor.den = */ 2, + /* .eScaling = */ 2, + /* .uInterpolationTableName = */ FGDT, + }, + + /* CHG_TEMP (internal sensor) */ + Package() + { + /* .sName = */ "CHG_TEMP", + /* .eChannel = */ 13, + /* .eEnable = */ 1, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 3, + /* .scalingFactor.den = */ 2, + /* .eScaling = */ 2, + /* .uInterpolationTableName = */ FGCT, + }, + + /* USB_IN (USB_IN pin) */ + Package() + { + /* .sName = */ "USB_IN", + /* .eChannel = */ 8, + /* .eEnable = */ 1, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 1, + /* .scalingFactor.den = */ 8, + /* .eScaling = */ 0, + /* .uInterpolationTableName = */ 0, + }, + + /* USB_IN_I (USB_IN pin) */ + Package() + { + /* .sName = */ "USB_IN_I", + /* .eChannel = */ 9, + /* .eEnable = */ 1, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 1, + /* .scalingFactor.den = */ 1, + /* .eScaling = */ 4, + /* .uInterpolationTableName = */ 0, + }, + + /* DC_IN (DC_IN pin) */ + Package() + { + /* .sName = */ "DC_IN", + /* .eChannel = */ 10, + /* .eEnable = */ 1, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 1, + /* .scalingFactor.den = */ 8, + /* .eScaling = */ 0, + /* .uInterpolationTableName = */ 0, + }, + + /* DC_IN_I (DC_IN pin) */ + Package() + { + /* .sName = */ "DC_IN_I", + /* .eChannel = */ 11, + /* .eEnable = */ 1, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 1, + /* .scalingFactor.den = */ 1, + /* .eScaling = */ 4, + /* .uInterpolationTableName = */ 0, + }, + + /* FG_GPIO */ + Package() + { + /* .sName = */ "FG_GPIO", + /* .eChannel = */ 14, + /* .eEnable = */ 0, + /* .ucTriggers = */ 0x0, + /* .scalingFactor.num = */ 1, + /* .scalingFactor.den = */ 2, + /* .eScaling = */ 0, + /* .uInterpolationTableName = */ 0, + }, + }) + } + + /* + * Die temperature sensor scaling table + * + * The first column in the table is sensor voltage in millivolts and the + * second column is the temperature in milli degrees C. + * + * Scaling equation: + * + * milliDegC = (uV - 600000) / 2 + 25000 + * + */ + Method (FGDT) + { + Return (Package() + { + Package(){ 450, 0xFFFF3CB0}, // -50000 + Package(){ 870, 160000} + }) + } + + /* + * NOTE: CHG_TEMP on PMI8998 uses fab-dependent scaling in the driver. + * This is the default scaling if no fab-dependent scaling is found. + * It corresponds to GF. + */ + /* + * Charger temperature sensor scaling table + * + * The first column in the table is sensor voltage in millivolts and the + * second column is the temperature in milli degrees C. + * + * Scaling equation: + * + * milliDegC = (1303168 - uV) / 3.784 + 25000 + * + */ + Method (FGCT) + { + Return (Package() + { + Package(){ 1587, 0xFFFF3CB0}, // -50000 + Package(){ 792, 160000} + }) + } +} + +Include("cust_adc.asl") diff --git a/sdm845Pkg/AcpiTables/fajita/addSub.asl b/sdm845Pkg/AcpiTables/fajita/addSub.asl new file mode 100755 index 0000000..ffde278 --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/addSub.asl @@ -0,0 +1,2 @@ + +Name (PSUB, "CLS00850") \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/fajita/backlightcfg.asl b/sdm845Pkg/AcpiTables/fajita/backlightcfg.asl new file mode 100755 index 0000000..fe85f18 --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/backlightcfg.asl @@ -0,0 +1,89 @@ +/// +// BLCP Method - Backlight control packet method, returns a +// command buffer for a specific backlight level +// +// Input Parameters +// Backlight level - Integer from 0% to 100% +// +// Output Parameters +// +// Packet format: +// +--32bits--+-----variable (8bit alignment)--+ +// | Header | Packet payload | +// +----------+--------------------------------+ +// +// For DSI Command packets, payload data must be in this format +// +// +-- 8 bits-+----variable (8bit alignment)----+ +// | Cmd Type | Packet Data | +// +----------+---------------------------------+ +// +// For I2C Command packets, payload data must be in this format +// +// +-- 32 bits---+----variable (8bit alignment)----+----variable (8bit alignment)----+ +// | Packet size | Register Address | Register Value | +// +-------------+---------------------------------+---------------------------------+ +// +// All packets must follow with a DWORD header with 0x0 +// + +Method (BLCP, 1, NotSerialized) { + + Name(RBUF, Buffer(0x100){}) + Store(0x0, LOCAL0) + + CreateField(RBUF, Multiply(LOCAL0, 8), 32, PKHR) + Add(LOCAL0, 4, LOCAL0) + + CreateField(RBUF, Multiply(LOCAL0, 8), 8, PKCM) + Add(LOCAL0, 1, LOCAL0) + + CreateField(RBUF, Multiply(LOCAL0, 8), 8, PKDS) + Add(LOCAL0, 1, LOCAL0) + + CreateField(RBUF, Multiply(LOCAL0, 8), 8, PKUB) + Add(LOCAL0, 1, LOCAL0) + + CreateField(RBUF, Multiply(LOCAL0, 8), 8, PKLB) + Add(LOCAL0, 1, LOCAL0) + + // Add additonal ON command + Name (BON, // Backlight on + Buffer() {0x39, // Command 39 + 0x53, 0x24}) // Manual backlight control + + // Create the packet header field + CreateField(RBUF, Multiply(LOCAL0, 8), 32, PKH2) // Create the packet header + Add(LOCAL0, 4, LOCAL0) // Increment the data pointer + + // Create the packet payload field + CreateField(RBUF, Multiply(LOCAL0, 8), 32, PKP2) // Create the packet payload + Store(Sizeof(BON), PKH2) // Store the size of the buffer in the header + Store(BON, PKP2) // Store the packet payload + Add(LOCAL0, Sizeof(BON), LOCAL0) // Increment the offset by the packet size + + CreateDWordField(RBUF, Multiply(LOCAL0, 8), EOF) + + /*LOCAL1 = Arg0 * 10 // to map to 1024 + LOCAL2 = LOCAL1 >> 8 + LOCAL1 &= 0xFF*/ + + LOCAL1 = Arg0 * 1023 + LOCAL1 /= 0xFF + + LOCAL2 = Arg0 * 1023 + LOCAL2 /= 0xFF00 + LOCAL2 &= 3 + + PKHR = 4 + PKCM = 0x39 + PKDS = 0x51 + //PKUB = 0x00 + //PKLB = 0x10 + PKUB = LOCAL2 + PKLB = LOCAL1 + + EOF = 0x0 + + Return(RBUF) +} diff --git a/sdm845Pkg/AcpiTables/fajita/buses.asl b/sdm845Pkg/AcpiTables/fajita/buses.asl new file mode 100755 index 0000000..9a2850c --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/buses.asl @@ -0,0 +1,4687 @@ +// +// Copyright (c) 2016 - 2018 Qualcomm Technologies, Inc. All rights reserved. +// + +// +// +// Please note that not all the SE engine instances (I2C/SPI/UART) from below asl file can be used directly by icluding in the client ACPI, +// The corresponding Access Control needs to be enabled from TZ side to get the SE/usecase working End 2 End. +// +// + +// +// QUPV3_ID0_SE7 (attached to BT SOC) +// +Device (UAR7) +{ + Name (_HID, "QCOM0236") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 7) + Name (_DEP, Package() { \_SB_.PEP0 }) + Name (_CCA, 0) + + Method (_CRS) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0x00898000, 0x0004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {639} + GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {48} // UART RX, + }) + Return (RBUF) + } +} + +// +// QUPV3_ID1_SE2 (UART Debug port) +// + Device (UARD) + { + Name (_HID, "QCOM0236") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 10) + Name (_DEP, Package() { \_SB_.PEP0 }) + Name (_CCA, 0) + + Method (_CRS) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0x00A84000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {386} + GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {5} // UART RX + }) + Return (RBUF) + } + } + + Device (I2C1) + { + Name (_HID, "QCOM0220") // _HID: Hardware ID + Alias (\_SB.PSUB, _SUB) + Name (_UID, One) // _UID: Unique ID + Name (_DEP, Package (0x02) // _DEP: Dependencies + { + \_SB.PEP0, + \_SB.QGP0 + }) + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00880000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000279, + } + }) + Return (RBUF) /* \_SB_.I2C1._CRS.RBUF */ + } + } + Device (I2C3) + { + Name (_HID, "QCOM0220") // _HID: Hardware ID + Alias (\_SB.PSUB, _SUB) + Name (_UID, 0x03) // _UID: Unique ID + Name (_DEP, Package (0x02) // _DEP: Dependencies + { + \_SB.PEP0, + \_SB.QGP0 + }) + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00888000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000027B, + } + }) + Return (RBUF) /* \_SB_.I2C3._CRS.RBUF */ + } + } + Device (I2C4) + { + Name (_HID, "QCOM0220") // _HID: Hardware ID + Alias (\_SB.PSUB, _SUB) + Name (_UID, 0x04) // _UID: Unique ID + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + \_SB.PEP0//, + //\_SB.QGP0 + }) + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x0088C000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000027C, + } + }) + Return (RBUF) /* \_SB_.I2C4._CRS.RBUF */ + } + } + Device (I2C5) + { + Name (_HID, "QCOM0220") // _HID: Hardware ID + Alias (\_SB.PSUB, _SUB) + Name (_UID, 0x05) // _UID: Unique ID + Name (_DEP, Package (0x02) // _DEP: Dependencies + { + \_SB.PEP0, + \_SB.QGP0 + }) + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00890000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000027D, + } + }) + Return (RBUF) /* \_SB_.I2C5._CRS.RBUF */ + } + } + Device (I2C8) + { + Name (_HID, "QCOM0220") // _HID: Hardware ID + Alias (\_SB.PSUB, _SUB) + Name (_UID, 0x08) // _UID: Unique ID + Name (_DEP, Package (0x02) // _DEP: Dependencies + { + \_SB.PEP0, + \_SB.QGP0 + }) + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x0089C000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000280, + } + }) + Return (RBUF) /* \_SB_.I2C8._CRS.RBUF */ + } + } + Device (IC11) + { + Name (_HID, "QCOM0220") // _HID: Hardware ID + Alias (\_SB.PSUB, _SUB) + Name (_UID, 0x0B) // _UID: Unique ID + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + \_SB.PEP0//, + //\_SB.QGP0 + }) + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00A88000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000183, + } + }) + Return (RBUF) /* \_SB_.IC11._CRS.RBUF */ + } + } + Device (IC12) + { + Name (_HID, "QCOM0220") // _HID: Hardware ID + Alias (\_SB.PSUB, _SUB) + Name (_UID, 0x0C) // _UID: Unique ID + Name (_DEP, Package (0x02) // _DEP: Dependencies + { + \_SB.PEP0, + \_SB.QGP0 + }) + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00A8C000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000184, + } + }) + Return (RBUF) /* \_SB_.IC12._CRS.RBUF */ + } + } + Device (IC13) + { + Name (_HID, "QCOM0220") // _HID: Hardware ID + Alias (\_SB.PSUB, _SUB) + Name (_UID, 0x0D) // _UID: Unique ID + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + \_SB.PEP0 + }) + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00A90000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000185, + } + }) + Return (RBUF) /* \_SB_.IC13._CRS.RBUF */ + } + } + Device (IC15) + { + Name (_HID, "QCOM0220") // _HID: Hardware ID + Name (_UID, 0x0F) // _UID: Unique ID + Name (_DEP, Package (0x02) // _DEP: Dependencies + { + \_SB.PEP0, + \_SB.QGP0 + }) + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00A98000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000187, + } + }) + Return (RBUF) /* \_SB_.IC15._CRS.RBUF */ + } + } + Device (IC16) + { + Name (_HID, "QCOM0220") // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_DEP, Package (0x02) // _DEP: Dependencies + { + \_SB.PEP0, + \_SB.QGP0 + }) + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00A9C000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000188, + } + }) + Return (RBUF) /* \_SB_.IC16._CRS.RBUF */ + } + } + +//SPI9 - EPM + +Device (SPI9) +{ + Name (_HID, "QCOM021E") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 9) + Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP1}) + Name (_CCA, 0) + + Method (_CRS) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0xA80000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {385} + }) + Return (RBUF) + } +} + + +// +// PEP resources for buses +// +Scope(\_SB_.PEP0) +{ + Method(BSMD) + { + Return(BSRC) + } + + Method(PQMD) + { + If (LLess(\_SB.SIDV,0x00020000)) + { + Return(DFS1) + } + Else + { + Return(DFS2) + } + } + + Name (BSRC, Package (0x0C) + { + Package (0x04) + { + "DEVICE", + "\\_SB.UAR7", + Package (0x12) + { + "COMPONENT", + Zero, + Package (0x09) + { + "FSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_s6_clk", + One + } + } + }, + + Package (0x09) + { + "FSTATE", + One, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_s6_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + Zero, + Zero + } + } + }, + + Package (0x06) + { + "PSTATE", + Zero, + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x2D, + Zero, + One, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x2E, + Zero, + One, + Zero, + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x2F, + Zero, + One, + Zero, + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x30, + Zero, + One, + Zero, + One, + Zero + } + } + }, + + Package (0x06) + { + "PSTATE", + One, + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x2D, + Zero, + One, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x2E, + Zero, + One, + Zero, + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x2F, + Zero, + One, + Zero, + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x30, + Zero, + One, + Zero, + One, + Zero + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x02, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x00708000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x00E10000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x04, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x01C20000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x05, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x01E84800, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x06, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x02DC6C00, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x07, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x03D09000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x08, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x04C4B400, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x09, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x05B8D800, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x0A, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x061A8000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x0B, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x06ACFC00, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x0C, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x07080000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x0D, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s6_clk", + 0x03, + 0x07A12000, + 0x04 + } + } + } + }, + + Package (0x04) + { + "COMPONENT", + One, + Package (0x02) + { + "FSTATE", + Zero + }, + + Package (0x02) + { + "FSTATE", + One + } + } + }, + + Package (0x05) + { + "DEVICE", + 0x02, + "\\_SB.UARD", + Package (0x12) + { + "COMPONENT", + Zero, + Package (0x0A) + { + "FSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x00708000, + 0x04 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_s1_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + One + } + } + }, + + Package (0x09) + { + "FSTATE", + One, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_s1_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + Zero, + Zero + } + } + }, + + Package (0x04) + { + "PSTATE", + Zero, + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x05, + Zero, + One, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x04, + Zero, + One, + Zero, + Zero, + Zero + } + } + }, + + Package (0x04) + { + "PSTATE", + One, + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x05, + Zero, + One, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x04, + Zero, + One, + Zero, + Zero, + Zero + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x02, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x00708000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x00E10000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x04, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x01C20000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x05, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x01E84800, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x06, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x02DC6C00, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x07, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x03D09000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x08, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x04C4B400, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x09, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x05B8D800, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x0A, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x061A8000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x0B, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x06ACFC00, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x0C, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x07080000, + 0x04 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x0D, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s1_clk", + 0x03, + 0x07A12000, + 0x04 + } + } + } + }, + + Package (0x04) + { + "COMPONENT", + One, + Package (0x02) + { + "FSTATE", + Zero + }, + + Package (0x02) + { + "FSTATE", + One + } + } + }, + + Package (0x07) + { + "DEVICE", + "\\_SB.I2C1", + Package (0x03) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + } + }, + + Package (0x0B) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s0_clk", + 0x08, + 0x0124F800, + 0x04 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + Zero, + One, + One, + One, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + One, + One, + One, + One, + 0x03, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0B) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_s0_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + Zero, + Zero, + Zero, + Zero, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + One, + Zero, + Zero, + Zero, + 0x03, + Zero + } + } + } + }, + + Package (0x07) + { + "DEVICE", + "\\_SB.I2C3", + Package (0x03) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + } + }, + + Package (0x0B) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s2_clk", + 0x08, + 0x0124F800, + 0x04 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x1B, + One, + One, + One, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x1C, + One, + One, + One, + 0x03, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0B) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_s2_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x1B, + Zero, + Zero, + Zero, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x1C, + Zero, + Zero, + Zero, + 0x03, + Zero + } + } + } + }, + + Package (0x07) + { + "DEVICE", + "\\_SB.I2C4", + Package (0x03) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + } + }, + + Package (0x0B) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s3_clk", + 0x08, + 0x0124F800, + 0x04 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x29, + One, + One, + One, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x2A, + One, + One, + One, + 0x03, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0B) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_s3_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x29, + Zero, + Zero, + Zero, + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x2A, + Zero, + Zero, + Zero, + Zero, + Zero + } + } + } + }, + + Package (0x07) + { + "DEVICE", + "\\_SB.I2C5", + Package (0x03) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + } + }, + + Package (0x0B) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + 0x00E1D480, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s4_clk", + 0x08, + 0x0124F800, + 0x04 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x59, + One, + 0x02, + One, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x5A, + One, + 0x03, + One, + 0x03, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0B) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_s4_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x59, + Zero, + 0x02, + Zero, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x5A, + Zero, + 0x03, + Zero, + 0x03, + Zero + } + } + } + }, + + Package (0x07) + { + "DEVICE", + "\\_SB.I2C8", + Package (0x03) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + } + }, + + Package (0x0B) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap0_s7_clk", + 0x08, + 0x0124F800, + 0x04 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x5D, + One, + 0x03, + One, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x5E, + One, + 0x03, + One, + 0x03, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0B) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_0_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_s7_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap0_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_1", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_1", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x5D, + Zero, + 0x03, + Zero, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x5E, + Zero, + 0x03, + Zero, + 0x03, + Zero + } + } + } + }, + + Package (0x07) + { + "DEVICE", + "\\_SB.IC11", + Package (0x03) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + } + }, + + Package (0x0B) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s2_clk", + 0x08, + 0x0124F800, + 0x04 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x37, + One, + One, + One, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x38, + One, + One, + One, + 0x03, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0B) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_s2_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x37, + Zero, + Zero, + Zero, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x38, + Zero, + Zero, + Zero, + 0x03, + Zero + } + } + } + }, + + Package (0x07) + { + "DEVICE", + "\\_SB.IC12", + Package (0x03) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + } + }, + + Package (0x0B) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s3_clk", + 0x08, + 0x0124F800, + 0x04 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x1F, + One, + One, + One, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x20, + One, + One, + One, + 0x03, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0B) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_s3_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x1F, + Zero, + Zero, + Zero, + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x20, + Zero, + Zero, + Zero, + Zero, + Zero + } + } + } + }, + + Package (0x07) + { + "DEVICE", + "\\_SB.IC13", + Package (0x03) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + } + }, + + Package (0x0B) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s4_clk", + 0x08, + 0x0124F800, + 0x04 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x31, + One, + One, + One, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x32, + One, + One, + One, + 0x03, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0B) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_s4_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x31, + Zero, + Zero, + Zero, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x32, + Zero, + Zero, + Zero, + 0x03, + Zero + } + } + } + }, + + Package (0x07) + { + "DEVICE", + "\\_SB.IC15", + Package (0x03) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + } + }, + + Package (0x0B) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + 0x08F0D180, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s6_clk", + 0x08, + 0x0124F800, + 0x04 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x21, + One, + 0x02, + One, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x22, + One, + 0x02, + One, + 0x03, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0B) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_s6_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x21, + Zero, + Zero, + Zero, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x22, + Zero, + Zero, + Zero, + 0x03, + Zero + } + } + } + }, + + Package (0x07) + { + "DEVICE", + "\\_SB.IC16", + Package (0x03) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + } + }, + + Package (0x0B) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s7_clk", + 0x08, + 0x0124F800, + 0x04 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x51, + One, + 0x02, + One, + 0x03, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x52, + One, + 0x02, + One, + 0x03, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0B) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_s7_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x51, + Zero, + Zero, + Zero, + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x52, + Zero, + Zero, + Zero, + Zero, + Zero + } + } + } + } + }) + + Name (DFS1, Package (0x01) + { + Package (0x07) + { + "DEVICE", + "\\_SB.SPI9", + Package (0x0A) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + }, + + Package (0x03) + { + "PSTATE", + Zero, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x0124F800, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + One, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x01E84800, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x02, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x0249F000, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x02DC6C00, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x04, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x03D09000, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x05, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x05B8D800, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x06, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x05F5E100, + 0x03 + } + } + } + }, + + Package (0x0D) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_s0_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x41, + One, + 0x02, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x42, + One, + 0x02, + One, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x43, + One, + 0x02, + One, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x44, + One, + 0x02, + One, + One, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0D) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_s0_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x41, + Zero, + 0x02, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x42, + Zero, + 0x02, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x43, + Zero, + 0x02, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x44, + Zero, + 0x02, + Zero, + One, + Zero + } + } + } + } + }) + + Name (DFS2, Package (0x01) + { + Package (0x07) + { + "DEVICE", + "\\_SB.SPI9", + Package (0x0A) + { + "COMPONENT", + Zero, + Package (0x02) + { + "FSTATE", + Zero + }, + + Package (0x03) + { + "PSTATE", + Zero, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x0124F800, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + One, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x01E84800, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x02, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x02DC6C00, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x03D09000, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x04, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x05B8D800, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x05, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x05F5E100, + 0x03 + } + } + }, + + Package (0x03) + { + "PSTATE", + 0x06, + Package (0x02) + { + "CLOCK", + Package (0x04) + { + "gcc_qupv3_wrap1_s0_clk", + 0x03, + 0x07270E00, + 0x03 + } + } + } + }, + + Package (0x0D) + { + "DSTATE", + Zero, + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + 0x53724E00, + 0x0682 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + 0x08D24D00, + 0x02FAF080 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_s0_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + One + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + One + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x41, + One, + 0x02, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x42, + One, + 0x02, + One, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x43, + One, + 0x02, + One, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x44, + One, + 0x02, + One, + One, + Zero + } + } + }, + + Package (0x02) + { + "DSTATE", + One + }, + + Package (0x02) + { + "DSTATE", + 0x02 + }, + + Package (0x0D) + { + "DSTATE", + 0x03, + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_m_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap_1_s_ahb_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_s0_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_2x_clk", + 0x02 + } + }, + + Package (0x02) + { + "CLOCK", + Package (0x02) + { + "gcc_qupv3_wrap1_core_clk", + 0x02 + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_BLSP_2", + "ICBID_SLAVE_EBI1", + Zero, + Zero + } + }, + + Package (0x02) + { + "BUSARB", + Package (0x05) + { + 0x03, + "ICBID_MASTER_APPSS_PROC", + "ICBID_SLAVE_BLSP_2", + Zero, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x41, + Zero, + 0x02, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x42, + Zero, + 0x02, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x43, + Zero, + 0x02, + Zero, + One, + Zero + } + }, + + Package (0x02) + { + "TLMMGPIO", + Package (0x06) + { + 0x44, + Zero, + 0x02, + Zero, + One, + Zero + } + } + } + } + }) +} diff --git a/sdm845Pkg/AcpiTables/fajita/corebsp_resources.asl b/sdm845Pkg/AcpiTables/fajita/corebsp_resources.asl new file mode 100755 index 0000000..22dad21 --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/corebsp_resources.asl @@ -0,0 +1,4234 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by core BSP drivers. +// +//=========================================================================== + + +// I have no idea if it works or not. +// Copied from CLS + + +Scope(\_SB_.PEP0) +{ + + Method(BPMD) + { + Return(BPCC) + } + + Method(LPMD) + { + Return(LPCC) + } + + Name(BPCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.UFS0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + Package() { "PSTATE_ADJUST", Package() { 0, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 0 } }, + }, + Package() + { + "FSTATE", + 0x1, // f1 state + Package() { "PSTATE_ADJUST", Package() { 2, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 0, 1 } }, + }, + + Package() + { + "PSTATE_SET", + 0x0, + + Package() + { + "PSTATE", + 0x0, + Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 1 }}, + }, + Package() + { + "PSTATE", + 0x1, + Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 2 }}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x1, + + Package() + { + "PSTATE", + 0x0, + + Package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 8, 200000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 8, 150000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 8, 300000000, 2}}, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_mem_clkref_en", 1,}}, + }, + Package() + { + "PSTATE", + 0x1, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 2,}}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x2, + + Package() + { + "PSTATE", + 0x0, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 900000000, 900000000}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 299000000, 0}}, + }, + Package() + { + "PSTATE", + 0x1, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 0, 0}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + + Package() {"PSTATE_ADJUST", Package() { 2, 0 } }, + + Package() {"PSTATE_ADJUST", Package() { 0, 0 } }, + + // Vcc supply = L20 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO20_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq supply = L2 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO2_A", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq2 supply = S4 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_SMPS4_A", + 2, // Voltage Regulator type = SMPS + 1800000, // 1.8V + 1, // Force enable from software + 0, // Power mode - AUTO + 0, // head room voltage + }, + }, + + // PHY VDDA supply: L26 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO26_A", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // VDDA_UFS_CORE supply: L1 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO1_A", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"DELAY", package() { 35 }}, + + Package() {"PSTATE_ADJUST", Package() { 1, 0 } }, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() {"PSTATE_ADJUST", Package() { 1, 1 } }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO1_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO26_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO20_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"DELAY", package() { 35 }}, + + Package() {"PSTATE_ADJUST", Package() { 0, 1 } }, + + Package() {"PSTATE_ADJUST", Package() { 2, 1 } }, + }, + }, + Package() + { + "DEVICE", + "\\_SB.SDC2", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + + Package() + { + "PSTATE_SET", + 0x0, + + // + // Contract with SDBUS for card frequencies + // + // P-State Note + // -------- ----- + // 0 - 19 Reserved (Legacy) + // 20 Reset to 3.3v signal voltage (max fixed at 2.95v) + // 21 1.8v signal voltage (max fixed at 1.85v) + Package(){"PSTATE", 0, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 1, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 2, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 3, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 4, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 5, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 6, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 7, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 8, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 9, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 11, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 12, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 13, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 14, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 15, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 16, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 17, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 18, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 19, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 20, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO21_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO13_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO21_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO13_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + Package(){"PSTATE", 21, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO13_A", // VREG ID + 1, // Voltage Regulator type = LDO + 1850000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + Package(){"PSTATE", 22, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO21_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO13_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + Package(){"PSTATE", 23, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO21_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO13_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + }, + + // P-state set 1: APPS Clock frequencies + // 0: Disable + // 1: 20 MHz (SVS2) + // 2: 100 MHz (SVS) + // 3: 201.5 MHz (Nominal) + Package() + { + "PSTATE_SET", + 0x1, + + Package() + { + "PSTATE", + 0x0, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 2}}, + }, + Package() + { + "PSTATE", + 0x1, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 20000000, 2}}, + }, + Package() + { + "PSTATE", + 0x2, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 100000000, 2}}, + }, + Package() + { + "PSTATE", + 0x3, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 201500000, 2}}, + }, + }, + + // P-state set 2: Bus Bandwidth requests + // P0: IB = 400 MBps, AB = 200 MBps + // P1: IB = 200 MBps, AB = 100 MBps + // P2: IB = 40 MBps, AB = 20 MBps + // P3: IB = 0 MBps, AB = 0 MBps + Package() + { + "PSTATE_SET", + 0x2, + + Package() + { + "PSTATE", + 0x0, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 400000000, 200000000}}, + }, + + Package() + { + "PSTATE", + 0x1, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 200000000, 100000000}}, + }, + + Package() + { + "PSTATE", + 0x2, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 40000000, 20000000}}, + }, + + Package() + { + "PSTATE", + 0x3, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + }, + + // P-state set 3: MSFT P-states + // P0: Clk = 200 MHz, IB = 400 MBps, AB = 200 MBps + // P1: Clk = 100 MHz, IB = 200 MBps, AB = 100 MBps + // P2: Clk = 20 MHz, IB = 40 MBps, AB = 20 MBps + Package() + { + "PSTATE_SET", + 0x3, + + Package() + { + "PSTATE", + 0x0, + Package() { "PSTATE_ADJUST", Package() { 1, 3 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 0 } }, + }, + Package() + { + "PSTATE", + 0x1, + Package() { "PSTATE_ADJUST", Package() { 1, 2 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 1 } }, + }, + Package() + { + "PSTATE", + 0x2, + Package() { "PSTATE_ADJUST", Package() { 1, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 2 } }, + }, + }, + + + // P-state set 4: AHB clock + Package() + { + "PSTATE_SET", + 0x4, + + Package() + { + "PSTATE", + 0x0, + package() {"CLOCK", package() {"gcc_sdcc2_ahb_clk", 1,}}, // AHB freq should be 100 MHz + }, + Package() + { + "PSTATE", + 0x1, + package() {"CLOCK", package() {"gcc_sdcc2_ahb_clk", 2}}, + }, + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + + Package() {"PSTATE_ADJUST", Package () { 0, 22 }}, + package() {"TLMMPORT", package() { 0x99A000, 0x7FFF, 0x1FE4 }}, + Package() {"PSTATE_ADJUST", Package() { 2, 0 }}, + Package() {"PSTATE_ADJUST", Package() { 4, 0 }}, + Package() {"PSTATE_ADJUST", Package() { 1, 3 }}, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() {"PSTATE_ADJUST", Package() { 1, 0 }}, + Package() {"PSTATE_ADJUST", Package() { 4, 1 }}, + Package() {"PSTATE_ADJUST", Package() { 2, 3 }}, + package() {"TLMMPORT", package() { 0x99A000, 0x7FFF, 0xA00 }}, + Package() {"PSTATE_ADJUST", Package () { 0, 23 }}, + }, + }, + /////////////////////////////////////////////////////////////////////////////////////// + + Package() + { + "DEVICE", + "\\_SB.ADSP.SLM1", + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + Package() + { + "DEVICE", + "\\_SB.ADSP.SLM2", + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + ///////////////////////////////////////////////////////////////////////////////////// + }) + + Name(LPCC, + package () + { + Package() + { + "DEVICE", + "\\_SB.UCP0", + Package() + { + "COMPONENT",0, //Component 0: USB HS Rails for Charger Detection + Package(){"FSTATE", 0 }, //Dummy F-State, required for P-State operation + Package() + { + "PSTATE", 0, // P0 state - Component ON + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + }, + Package() + { + "PSTATE", 1, // P1 state - Component OFF + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + //Enable vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 0} + }, + + }, + }, + //D states + package() { + "DSTATE", 0x0, // D0 state + }, + package() { + "DSTATE", 0x1, // D1 state + }, + package() { + "DSTATE", 0x2, // D2 state + }, + package() { + "DSTATE", 0x3, // D3 state + }, + }, + + //PMIC Type-C Controller + //Component 0: USB HS rails for Automiatic Port Source Detection (APSD) + Package() + { + "DEVICE", + "\\_SB.PTCC", + Package() + { + "COMPONENT",0, //Component 0: USB HS Rails for Charger Detection + Package(){"FSTATE", 0 }, //Dummy F-State, required for P-State operation + Package() + { + "PSTATE", 0, // P0 state - Component ON + // LDO 24: ON, 3.075V, LDO 12: ON, 1.8V + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 1, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 1, // SW Power Mode = NPM + 0, // Head Room + }, + }, + }, + Package() + { + "PSTATE", 1, // P1 state - Component OFF + // LDO 24 & LDO 12 : OFF + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @0v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 0, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @0v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 0, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + }, + //D states + package() { + "DSTATE", 0x0, // D0 state + }, + package() { + "DSTATE", 0x1, // D1 state + }, + package() { + "DSTATE", 0x2, // D2 state + }, + package() { + "DSTATE", 0x3, // D3 state + }, + }, //End PMIC Type-C Controller + Package() + { + "DEVICE", + "\\_SB.URS0", + Package() + { + "COMPONENT", + Zero, + Package() {"FSTATE", 0}, + Package() {"PSTATE", 0}, + Package() {"PSTATE", 1} + }, + Package() {"DSTATE", 0 }, + Package() {"DSTATE", 1 }, + Package() {"DSTATE", 2 }, + Package() {"DSTATE", 3 } + }, + + + //USB SS/HS1 core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.URS0.USB0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Now Enable all the clocks + + //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps //LowSVS + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact) + //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact) + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact) + //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact) + 0 // AB=0 MBps + } + }, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() + { + "CLOCK", + package() { "gcc_usb3_prim_phy_aux_clk", 2} + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + // Disable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0 v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for USB0 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB0 + // + //************************* USB3.0 SS/HS0 core (Peripheral Stack) **************************** + // + package() + { + "DEVICE", + "\\_SB.URS0.UFN0", + package() + { + "COMPONENT", + 0x0, + // F-State placeholders + package() + { + "FSTATE", + 0x0, + }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + + package() + { // PERIPH D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @ 3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + + }, + package() + { + // PERIPH D1: Not supported by USBFN driver + "DSTATE", //USB SS+HS suspend state + 0x1, + }, + package() + { // PERIPH D2 + "DSTATE", //USB DCP/HVDCP charger state + 0x2, + + // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable ; + package() {"CLOCK", package() { "gcc_usb30_prim_master_clk", 2 } }, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + //Disable gcc_usb3_prim_phy_aux_clk + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + package() {1, "/arc/client/rail_cx", 256} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { + // PERIPH D3 + "DSTATE", + 0x3, // Detach State + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + // Disable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for UFN0 (peripheral) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End UFN0 + + //USB Primary Core (Host Stack) Standalone + Package() + { + "DEVICE", + "\\_SB.USB0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Now Enable all the clocks + + //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps //LowSVS + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact) + //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact) + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact) + //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact) + 0 // AB=0 MBps + } + }, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() + { + "CLOCK", + package() { "gcc_usb3_prim_phy_aux_clk", 2} + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + // Disable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0 v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for USB0 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB0 + + //Analogix TypeC + Package() + { + "DEVICE", + "\\_SB.ANX0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + package() + { + "TLMMGPIO", // TLMM resource + package() //ANX interrupt pin - set function 0 + { + 103, // PIN number = 103 + 0, // State: Low = 0 + 0, // Function select = 0 + 0, // Direction = Input + 0, // Pull value: 0 = PULL None + 0, // Drive Strength: 0 = 2mA + 0, // Enable low power state + }, + }, + package() + { + "TLMMGPIO", // TLMM resource + package() //1.8/3.3V ANX and TI redriver power + { + 129, // PIN number = 129 + 1, // State: High = 1 + 0, // Function select = 0 + 1, // Direction = Output. + 1, // Pull value: 1 = PULL Down + 2, // Drive Strength: 2 = 4mA + 0, // Enable low power state + }, + }, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + }, + package() + { // HOST D1 + "DSTATE", // D1 state + 0x1, + }, + package() + { // HOST D2 + "DSTATE", // D2 state + 0x2, + }, + package() + { // HOST D3 + "DSTATE", // D3 state + 0x3, + }, + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //end ANX0 + + //USB secondary core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.USB1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Now Enable all the clocks + + //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps //LowSVS + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact) + //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact) + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact) + //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact) + 0 // AB=0 MBps + } + }, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() + { + "CLOCK", + package() { "gcc_usb3_sec_phy_aux_clk", 2} + }, + + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + // Disable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0 v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for USB1 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB1 + + Package() + { + "DEVICE", + "\\_SB.URS1", + Package() + { + "COMPONENT", + Zero, + Package() {"FSTATE", 0}, + Package() + { + "PSTATE", + 0, // P0 -Disable Vbus + package() + { + "PMICGPIO", + Package() + { + "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", + 1, // PMI8998 + 9, // GPIO #10: USBOTG_VBUS_EN + 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS + 0, // PM_GPIO_VIN0 + 0, // EN_AND_SOURCE_SEL, 1: LOW + 1, // PM_GPIO_OUT_BUFFER_LOW + 4, // PM_GPIO_I_SOURCE_PULL_DOWN_10uA + }, + }, + }, + Package() + { + "PSTATE", + 1, // P1 - Enable Vbus + package() + { + "PMICGPIO", + Package() + { + "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", + 1, // PMI8998 + 9, // GPIO #10: USBOTG_VBUS_EN + 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS + 0, // PM_GPIO_VIN0 + 1, // EN_AND_SOURCE_SEL, 1: HIGH + 3, // PM_GPIO_OUT_BUFFER_HIGH + 5, // PM_GPIO_I_SOURCE_PULL_NO_PULL + }, + }, + } + }, + Package() {"DSTATE", 0 }, + Package() {"DSTATE", 1 }, + Package() {"DSTATE", 2 }, + Package() {"DSTATE", 3 } + }, + + + //USB secondary core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.URS1.USB1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Now Enable all the clocks + + //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps //LowSVS + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact) + //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact) + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact) + //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact) + 0 // AB=0 MBps + } + }, + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() + { + "CLOCK", + package() { "gcc_usb3_sec_phy_aux_clk", 2} + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L26 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + // Disable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM850 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0 v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for USB1 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB1 + + //************************* USB3.0 SS/HS0 core (Peripheral Secondary Stack) **************************** + // + package() + { + "DEVICE", + "\\_SB.URS1.UFN1", + package() + { + "COMPONENT", + 0x0, + // F-State placeholders + package() + { + "FSTATE", + 0x0, + }, + package() + { + "PSTATE", + 0x0, + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + + package() + { // PERIPH D0 + "DSTATE", + 0x0, + //Power Grid for SDM850 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L24 - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L24 @ 3.075v + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L26 - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}}, + + // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + + }, + package() + { + // PERIPH D1: Not supported by USBFN driver + "DSTATE", //USB SS+HS suspend state + 0x1, + }, + package() + { // PERIPH D2 + "DSTATE", //USB DCP/HVDCP charger state + 0x2, + + // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable ; + package() {"CLOCK", package() { "gcc_usb30_sec_master_clk", 2 } }, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + //Disable gcc_usb3_sec_phy_aux_clk + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + package() {1, "/arc/client/rail_cx", 256} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @3.075v + { + // L24 - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3075000, // Voltage = 3.075 V + 1, // SW Enable = Enable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // L26 is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @1.2v + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0V : microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L1 @ 0v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { + // PERIPH D3 + "DSTATE", + 0x3, // Detach State + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable gcc_usb_phy_cfg_ahb2phy_clk + package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + // Disable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L2 @0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L1 @ 0.88v + { + "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 5, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for UFN1 (peripheral) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End UFN1 + }) +} diff --git a/sdm845Pkg/AcpiTables/fajita/cust_camera.asl b/sdm845Pkg/AcpiTables/fajita/cust_camera.asl new file mode 100755 index 0000000..5e96358 --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/cust_camera.asl @@ -0,0 +1,653 @@ +//============================================================================== +// +// DESCRIPTION +// This file contains resources (such as memory address, GPIOs, etc.) and +// methods needed by camera drivers. +// +//============================================================================== + + +// These are not the correct configuration for your phone +// DO NOT INSTALL CAMERA DRIVERS + + + +Include("cust_camera_exasoc.asl") + +// +// CAMERA MIPI CSI (based on Titan 170 v1 hardware) +// +Device (MPCS) +{ + Name (_DEP, Package(0x1) + { + \_SB_.CAMP + }) + + Name (_HID, "QCOM02E8") + Name (_UID, 24) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0AC65000, 0x00000900) // PHY 0 memory + Memory32Fixed (ReadWrite, 0x0AC66000, 0x00000900) // PHY 1 memory + Memory32Fixed (ReadWrite, 0x0AC67000, 0x00000900) // PHY 2 memory + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {509} // PHY 0 interrupt, csiphy_0_irq + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {510} // PHY 1 interrupt, csiphy_1_irq + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {511} // PHY 2 interrupt, csiphy_2_irq + }) + + Return (RBUF) + } + + // PERF, EBUF left blank intentionally as only F state support required at this point. + // PEP Proxy is not needed as it is there for D state support. +} + +// +// JPEG ENCODER (JPGE) +// JPEG 0: a dedicated JPEG encode instance; +// JPEG 3: a DMA instance (for downscaling only, not for encoding). +// Each JPEG instance is controlled indpendently; having its own set of +// registers for control and hardware operation, and its own core clock. +// +Device (JPGE) +{ + Name (_DEP, Package(0x2) + { + \_SB_.CAMP, + \_SB_.MMU0 + }) + + Name (_HID, "QCOM0276") + Name (_UID, 23) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // TITAN_A_JPEG_0 + Memory32Fixed ( ReadWrite, 0x0AC4E000, 0x0340 ) + + // TITAN_A_JPEG_3 + Memory32Fixed ( ReadWrite, 0x0AC52000, 0x01B4 ) + + // titan_jpeg_0_irq (Destination Subsystem: Application Processor) + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) { 506 } + + // titan_jpeg_3_irq (Destination Subsystem: Application Processor) + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) { 507 } + }) + + Return (RBUF) + } + + Method (PERF) + { + Name (EBUF, Package() + { + Package() // JPEG instance 0 PSET_0 + { + "COMPONENT", + 0, // Component ID: JPEG_0 = 0, JPEG_3/DMA = 1 + + Package() + { + "PSTATE_SET", + 0, // P_Set Index + 0, // CLK = 0, BW = 1 + "JPEG0_CLK", + + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + 600000000, // cam_cc_jpeg_clk supported configurations (TURBO = NOM / SVS / Low SVS) + 600000000, + 404000000, + 200000000, + }, + }, + }, + + Package() // JPEG instance 3 PSET_0 + { + "COMPONENT", + 1, + + Package() { "PSTATE_SET", 0, 0, "DMA_CLK", Package() { "PSTATE", 0, 600000000, 600000000, 200000000, }, }, // cam_cc_jpeg_clk: Turbo / Nominal / LowSVS + }, + }) + + Return (EBUF) + } +} + +// +// VFE +// +Device (VFE0) +{ + Name (_DEP, Package(0x3) + { + \_SB_.MMU0, + \_SB_.PEP0, + \_SB_.CAMP + }) + + Name (_HID, "QCOM0243") + Name (_UID, 22) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // ICP + Memory32Fixed (ReadWrite, 0xAC00000, 0x20000) + + //CPASS_CDM + Memory32Fixed (ReadWrite, 0xAC48000, 0x1000) + + //FD_WRAPPER + Memory32Fixed (ReadWrite, 0xAC5A000, 0x4000) + + // LRME + Memory32Fixed (ReadWrite, 0xAC6B000, 0x1000) + + //BPS + Memory32Fixed (ReadOnly, 0xAC6F000, 0x8000) + + // IPE0 + Memory32Fixed (ReadOnly, 0xAC87000, 0xA000) + + // IPE1 + Memory32Fixed (ReadOnly, 0xAC91000, 0xA000) + + // IFE0 + Memory32Fixed (ReadWrite, 0xACAF000, 0x5000) + + //IFE1 + Memory32Fixed (ReadWrite, 0xACB6000, 0x5000) + + //IFE_LITE + Memory32Fixed (ReadWrite, 0xACC4000, 0x5000) + + //ICP FW + Memory32Fixed (ReadWrite, 0x8BF00000, 0x500000) + + + // CDM interrupt + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {493} + + // ICP interrupt + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {495} + + + // IFE0 interrupt + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {497} + + // IFE1 interrupt + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {499} + + // IFE LITE interrupt + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {501} + + // FD interrupt + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {494} + + // IFE0 CSID interrupt + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {496} + + // IFE1 CSID interrupt + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {498} + + // IFE LITE CSDI interrupt + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {500} + + + }) + Return (RBUF) + } + Method (PERF) + { + Name (EBUF, Package() + { + //------------------------------------------------------------------------------ + // VFE and CPP P-state values listed here specific to Platform + // These packages enumerates all of the expected P-state values that should be used + // for the P-state transitions decision by VFE/CPP cores + // Package format is mentioned below. + //------------------------------------------------------------------------------ + + // Package() + // { + // "COMPONENT" + // INTEGER, VFE0/JPEG = 0,VFE1 = 1,CPP = 2 + // Package() + // { + // "PSTATE_SET", + // PSTATE_INDEX_INTEGER, PStateIndex to access clocktable by index that contains Clock + // having PState. + // PSTATESET_TYPE_INTEGER, CLK = 0 , BW = 1 + // STRING, ResourceName + // Package() + // { + // "PSTATE" , Package type mentioned in ACPIPackageNames + // INTEGER, Chipversion list availabiliy + // + // Clock values , Chipversion supported, + // Clock values , Chipversion supported, + // Clock values , Chipversion supported, + // }, + // }, + // }, + + Package() + { + "COMPONENT", + 0, // IFE0 + // Clk Freq + Package() + { + "PSTATE_SET", + 0, // PStateSet Index + 0, // CLK = 0 , BW = 1 + "IFE0_CLK", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + // Clock value Chipversion supported + 600000000, + 480000000, + 404000000, + 0, + }, + }, + + // BW: TODO + Package() + { + "PSTATE_SET", + 1, // PStateSet Index + 1, // CLK =0 , BW =1 + "HF0_UNCOMP_BANDWIDTH", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + 38000000000, + 35000000000, + 28000000000, + 23000000000, + 20000000000, + 16000000000, + 14000000000, + 12000000000, + 4000000000, + 3500000000, + 3300000000, + 3100000000, + 2900000000, + 2700000000, + 2500000000, + 2300000000, + 2100000000, + 1900000000, + 1700000000, + 1500000000, + 1300000000, + 1100000000, + 900000000, + 700000000, + 500000000, + 400000000, + 300000000, + 200000000, + 100000000, + 0, + }, + }, + Package() + { + "PSTATE_SET", + 2, // PStateSet Index + 1, // CLK =0 , BW =1 + "HF0_BANDWIDTH", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + 38000000000, + 35000000000, + 28000000000, + 23000000000, + 20000000000, + 16000000000, + 14000000000, + 12000000000, + 4000000000, + 3500000000, + 3300000000, + 3100000000, + 2900000000, + 2700000000, + 2500000000, + 2300000000, + 2100000000, + 1900000000, + 1700000000, + 1500000000, + 1300000000, + 1100000000, + 900000000, + 700000000, + 500000000, + 400000000, + 300000000, + 200000000, + 100000000, + 0, + }, + }, + + // CSID Clk Freq: TODO + }, + + Package() + { + "COMPONENT", + 1, // IFE1 + // Clk Freq + Package() + { + "PSTATE_SET", + 0, // PStateSet Index + 0, // CLK = 0 , BW = 1 + "IFE1_CLK", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + // Clock value Chipversion supported + 600000000, + 480000000, + 404000000, + 0, + }, + }, + + // BW: TODO + Package() + { + "PSTATE_SET", + 1, // PStateSet Index + 1, // CLK =0 , BW =1 + "HF1_UNCOMP_BANDWIDTH", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + 38000000000, + 35000000000, + 28000000000, + 23000000000, + 20000000000, + 16000000000, + 14000000000, + 12000000000, + 4000000000, + 3500000000, + 3300000000, + 3100000000, + 2900000000, + 2700000000, + 2500000000, + 2300000000, + 2100000000, + 1900000000, + 1700000000, + 1500000000, + 1300000000, + 1100000000, + 900000000, + 700000000, + 500000000, + 400000000, + 300000000, + 200000000, + 100000000, + 0, + }, + }, + Package() + { + "PSTATE_SET", + 2, // PStateSet Index + 1, // CLK =0 , BW =1 + "HF1_BANDWIDTH", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + 38000000000, + 35000000000, + 28000000000, + 23000000000, + 20000000000, + 16000000000, + 14000000000, + 12000000000, + 4000000000, + 3500000000, + 3300000000, + 3100000000, + 2900000000, + 2700000000, + 2500000000, + 2300000000, + 2100000000, + 1900000000, + 1700000000, + 1500000000, + 1300000000, + 1100000000, + 900000000, + 700000000, + 500000000, + 400000000, + 300000000, + 200000000, + 100000000, + 0, + }, + }, + + // CSID Clk Freq: TODO + }, + + Package() + { + "COMPONENT", + 2, // IFE_LITE + // Clk Freq + Package() + { + "PSTATE_SET", + 0, // PStateSet Index + 0, // CLK = 0 , BW = 1 + "IFE_LITE_CLK", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + // Clock value Chipversion supported + 600000000, + 480000000, + 404000000, + 0, + }, + }, + + // BW: ICBID_MASTER_CAMNOC_HF1_UNCOMP is used for both ife1 & ife_lite + + // CSID Clk Freq: TODO + + }, + + Package() + { + "COMPONENT", + 3, // ICP + Package() + { + "PSTATE_SET", + 0, // PStateSet Index + 0, // CLK =0 , BW =1 + "ICP_CLK", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + // Clock value Chipversion supported + 600000000, + 400000000, + 0, + }, + }, + + // AHB Clk: TODO + }, + + Package() + { + "COMPONENT", + 4, // IPE + Package() + { + "PSTATE_SET", + 0, // PStateSet Index + 0, // CLK =0 , BW =1 + "IPE0_CLK", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + // Clock value Chipversion supported + 600000000, + 480000000, + 404000000, + 0, + }, + }, + Package() + { + "PSTATE_SET", + 1, // PStateSet Index + 0, // CLK =0 , BW =1 + "IPE1_CLK", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + // Clock value Chipversion supported + 600000000, + 480000000, + 404000000, + 0, + }, + }, + + // BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme + + // AHB Clk : TODO + + }, + + Package() + { + "COMPONENT", + 5, // BPS + Package() + { + "PSTATE_SET", + 0, // PStateSet Index + 0, // CLK =0 , BW =1 + "BPS_CLK", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + // Clock value Chipversion supported + 600000000, + 480000000, + 404000000, + 0, + }, + }, + + // BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme + + // AHB Clk : TODO + }, + + Package() + { + "COMPONENT", + 6, // LRME + Package() + { + "PSTATE_SET", + 0, // PStateSet Index + 0, // CLK =0 , BW =1 + "LRME_CLK", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + // Clock value Chipversion supported + 400000000, + 320000000, + 269000000, + 0, + }, + }, + + // BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme + + }, + + Package() + { + "COMPONENT", + 7, // FD + Package() + { + "PSTATE_SET", + 0, // PStateSet Index + 0, // CLK =0 , BW =1 + "FD_CLK", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + // Clock value Chipversion supported + 600000000, + 538000000, + 400000000, + 0, + }, + }, + + // BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme + + }, + + }) + + Return (EBUF) + } +} diff --git a/sdm845Pkg/AcpiTables/fajita/cust_camera_exasoc.asl b/sdm845Pkg/AcpiTables/fajita/cust_camera_exasoc.asl new file mode 100755 index 0000000..0043e35 --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/cust_camera_exasoc.asl @@ -0,0 +1,597 @@ +//============================================================================== +// +// DESCRIPTION +// This file contains resources (such as memory address, GPIOs, etc.) and +// methods needed by camera drivers for external components like sensors,flash etc. +// Customers can update these files for different external components +// +//============================================================================== + + +// These are not the correct configuration for your phone +// DO NOT INSTALL CAMERA DRIVERS + + + +// +// CAMERA PLATFORM +// +Device (CAMP) +{ + Name (_DEP, Package(0x2) + { + \_SB_.PEP0, + \_SB_.PMIC + }) + + Name (_HID, "QCOM026F") + Name (_UID, 27) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // TITAN_A_CPAS_0_CPAS_TOP_0 + Memory32Fixed ( ReadWrite, 0x0AC40000, 0x0000006C ) + + // TITAN_A_CAMNOC + Memory32Fixed ( ReadWrite, 0x0AC42000, 0x00004E8C ) + + // TITAN_A_CCI + Memory32Fixed ( ReadWrite, 0x0AC4A000, 0x00000C1C ) + + // titan_cci_irq (Destination Subsystem: Application Processor) + Interrupt( ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) { 492 } + + GpioIo(Exclusive,PullNone,0,0, ,"\\_SB.GIO0", ,){21} //PRIVACY LED FOR FFC + }) + + Return (RBUF) + } + // PLED returns GpioIo Index for Privacy LED in _CRS + // bits 0-7 index of the privacy LED + // bit 8 gpio active 0: high, 1:low + Method (PLED) + { + Return (0x0) + } + // + // PLATFROM CONFIGURATION (PCFG) METHOD + // + // [1] SENSOR PRESENCE + // -----------------------|-----------/-----------|-----------/-----------|-----------/------------ + // 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 | << BIT INDEX + // -----------------------|-----------/-----------|-----------/-----------|-----------/------------ + // | SENSOR PRESENCE [0/1] | << FIELD MEANING + // RESERVED | 7 6 5 4 3 2 1 0 | << SENSOR INDEX + // -----------------------|-----------------------|-----------------------|------------------------- + // 0b | 0 0 0 0 0 1 1 1 | << 0x07 + // -----------------------|-----------/-----------|-----------/-----------|-----------/------------ + // SENSOR INDEX: 0(RFC), 1(FFC), 2(AUX), etc. + // SENSOR PRESENCE: 0 (ABSENT) / 1(PRESENTED) + + // [2-9] SENSOR CONNECTION CONFIGURATION (here we only utilize three entires) + // -----------------------|-----------/-----------|-----------/-----------|-----------/------------ + // 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 | << BIT INDEX + // --------------------|--|-----------/-----------|-----------/-----------|-----------/------------ + // RESERVED |FA| CSI_PHY | I2C_BUS | RSVD | FL_INX |FP| DIR | ORI | << FIELD MEANING + // ------------------- --|-----------------------|-----------|--------|--|-----------|------------ + // 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 << 0x00000100 (RFC) + // 0b 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 << 0x00210010 (FFC) + // 0b 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 << 0x00110300 (AUX/IRIS); REVISIT AND DOUBLE CHECK FLASH_INDEX !!! + // -----------------------|-----------/-----------|-----------/-----------|-----------/------------ + // FACE AUTHENTICATION(FA) 1-bit field, valid values 0/1 respectively NOTSUPPORTED/SUPPORTED + // CSIPHY INDEX: 4-bit field, valid values 0/1/2, respectively CSIPHY_0/1/2 LD20-NE182-9 + // I2C_BUS INDEX: 4-bit field, valid values 0/1, respectively CCI_I2C_SDA/SCL0/1 LD20-NE182-7/42 + // FLASH_INDEX: 3-bit field, valid values 0/1/2, respectively FLASH_LED0/1/2 LD20-NE182-19/45 + // FLASH_PRESENCE: 1-bit field, valid values 0/1, respectively ABSENT/PRESENTED + // SENSOR_DIRECTION: 4-bit field, valid values 0/1, respectively Rear/Front + // SENSOR_ORIENTATION: 4-bit field, valid values 0/1/2/3 respectively 0/90/180/270 degrees + + Method (PCFG, 0x0, Serialized) + { + Return + ( + Package() + { + Package () + { + 0x00000007, // [1] SENSOR PRESENCE + 0x00000000, // [2] SENSOR_0/RFC CONNECTION + 0x00210010, // [3] SENSOR_1/FFC CONNECTION + 0x01110010, // [4] SENSOR_2/AUX/IRIS CONNECTION + 0x00000000, // [5] SENSOR_3 CONNECTION; RESERVED + 0x00000000, // [6] SENSOR_4 CONNECTION; RESERVED + 0x00000000, // [7] SENSOR_5 CONNECTION; RESERVED + 0x00000000, // [8] SENSOR_6 CONNECTION; RESERVED + 0x00000000 // [9] SENSOR_7 CONNECTION; RESERVED + } + } + ) + } + + // The method contains P state power setting used by the camera driver. The clock presented + // here MUST be consistent with the PSTATE_SET values under the CAMP section in the file of + // cust_camera_exasoc_resources.asl. + Method (PERF) + { + Name (EBUF, Package() + { + Package() + { + "COMPONENT", + 0, // Platform = 0 + + Package() + { + "PSTATE_SET", + 0, // PStateSet Index + 0, // CLK = 0, BW = 1 + "CAMP_CLK", + + Package() // The indexes and frequencies be consistent + { // with CCICLKFrqIdx in CCIResourceType.h and + "PSTATE", // cam_cc_cci_clk in cust_camera_exasoc_resources.asl + 0, // Chipversion list availabiliy + 37500000, // Index 0 clock + 19200000, // Index 1 clock + }, + }, + + Package() + { + "PSTATE_SET", + 1, // PStateSet Index + 1, // CLK =0 , BW =1 + "NRT_UNCOMP_BANDWIDTH", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + 12000000000, + 11500000000, + 11000000000, + 10500000000, + 10000000000, + 9500000000, + 9000000000, + 8500000000, + 8000000000, + 7500000000, + 7000000000, + 6500000000, + 6000000000, + 5500000000, + 5000000000, + 4500000000, + 4000000000, + 3500000000, + 3300000000, + 3100000000, + 2900000000, + 2700000000, + 2500000000, + 2300000000, + 2100000000, + 1900000000, + 1700000000, + 1500000000, + 1300000000, + 1100000000, + 900000000, + 700000000, + 500000000, + 400000000, + 300000000, + 200000000, + 100000000, + 0, + }, + }, + + Package() + { + "PSTATE_SET", + 2, // PStateSet Index + 1, // CLK =0 , BW =1 + "NRT_BANDWIDTH", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + 12000000000, + 11500000000, + 11000000000, + 10500000000, + 10000000000, + 9500000000, + 9000000000, + 8500000000, + 8000000000, + 7500000000, + 7000000000, + 6500000000, + 6000000000, + 5500000000, + 5000000000, + 4500000000, + 4000000000, + 3500000000, + 3300000000, + 3100000000, + 2900000000, + 2700000000, + 2500000000, + 2300000000, + 2100000000, + 1900000000, + 1700000000, + 1500000000, + 1300000000, + 1100000000, + 900000000, + 700000000, + 500000000, + 400000000, + 300000000, + 200000000, + 100000000, + 0, + }, + }, + }, + Package() + { + "COMPONENT", + 1, // Platform = 0 + Package() + { + "PSTATE_SET", + 0, // PStateSet Index + 1, // CLK =0 , BW =1 + "HF0_UNCOMP_BANDWIDTH", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + 1100000000, + 400000000, + 300000000, + 200000000, + 100000000, + 0, + }, + }, + Package() + { + "PSTATE_SET", + 1, // PStateSet Index + 1, // CLK =0 , BW =1 + "HF0_BANDWIDTH", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + 1100000000, + 400000000, + 300000000, + 200000000, + 100000000, + 0, + }, + }, + Package() + { + "PSTATE_SET", + 2, // PStateSet Index + 1, // CLK =0 , BW =1 + "NRT_UNCOMP_BANDWIDTH", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + 1100000000, + 400000000, + 300000000, + 200000000, + 100000000, + 0, + }, + }, + Package() + { + "PSTATE_SET", + 3, // PStateSet Index + 1, // CLK =0 , BW =1 + "NRT_BANDWIDTH", + Package() + { + "PSTATE", + 0, // Chipversion list availabiliy + 1100000000, + 400000000, + 300000000, + 200000000, + 100000000, + 0, + }, + }, + }, + }) + + Return (EBUF) + } +} + +// +// Primary Rear Camera (IMX318) +// +Device (CAMS) +{ + Name (_DEP, Package(0x1) + { + \_SB_.MPCS // MPCS has dependency on CAMP, which eventually ends up with PEP0 and PMIC + }) + + Name (_HID, "QCOM0245") + Name (_UID, 21) + + // Return 0x0 to disable CAMS sensor + Method (_STA) + { + Return (0xf) + } + + // + // SENSOR CONFIGURATION (SCFG) METHOD + // + // [1/2] Driver/Tuning binary file name (no more than 50 characters) + // + // [3] I2C Slave Information for Sensor Probing + //------------------------|-----------/-----------|-----------------------|------------------------ + // 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 | << BIT INDEX + // RESERVED | DTT | ADT | FRQ | SLAVE ADDRESS | << MEANING + // -----------------------------|-----|-----|-----|------------------------------------------------ + // 0b 0 1 0 1 0 1 FROM IMX318 REG MAP | << 0x150034 + // -----------------------|-----------/-----------|-----------------------|-----------/------------ + // Register Data Type (DTT): 0b00 -- CAMERA_I2C_BYTE_DATA, 0b01 -- WORD, 0b10 -- DWORD + // Register Address Type (ADT): 0b00 -- CAMERA_I2C_BYTE_ADDR, 0b01 -- WORD, 0b10 -- 3B + // I2C Frequency mode: 0b00 -- 100 KHz (standard), 0b01 -- 400 KHz (fast), 0b10 -- 1 MHz (fast_plus). + // + // [4] Slave Data Part 1 for and from Probing + // Expected Reading (16 bits; 0x318) + Register Address (16 bits; 0x16) + // + // [5] Slave Data Part 2 for and from Probing + // Same format as above; Reserved for Revision # (if applied) + + Method (SCFG, 0x0, Serialized) + { + Return + ( + Package() + { + Package () + { + "com.qti.sensormodule.liteon_ov13850.bin", // [1] Driver binary file name + "com.qti.tuned.liteon_ov13850.bin", // [2] Tuning binary file name + 0x00150020, // [3] I2C Slave Information for Sensor Probing + 0xD850300A, // [4] Slave Data Part 1 for and from Probing + 0x00000000 // [5] Slave Data Part 2 for and from Probing; Reserved + } + } + ) + } + + // PEP Proxy Support + Name(PGID, Buffer(10) {"\\_SB.CAMS"}) // Device ID buffer - PGID (Pep given ID) + + Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID (Pep given ID) + CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE + // HIDDEN 1 BYTE (SIZE) + CreateByteField(DBUF, 2, DVAL) // Packet value, 1 BYTES Device Status + CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES (160 Bits) + + Method (_S1D, 0) { Return (3) } // S1 => D3 + Method (_S2D, 0) { Return (3) } // S2 => D3 + Method (_S3D, 0) { Return (3) } // S3 => D3 + + Method(_PS0, 0x0, NotSerialized) + { + Store(Buffer(ESNL){}, DEID) + Store(0, DVAL) + Store(PGID, DEID) + If(\_SB.ABD.AVBL) + { + Store(DBUF, \_SB.PEP0.FLD0) + } + } + + Method(_PS3, 0x0, NotSerialized) + { + Store(Buffer(ESNL){}, DEID) + Store(3, DVAL) + Store(PGID, DEID) + If(\_SB.ABD.AVBL) + { + Store(DBUF, \_SB.PEP0.FLD0) + } + } +} + +// +// Primary Front Camera (IMX258) +// +Device (CAMF) +{ + Name (_DEP, Package(0x1) + { + \_SB_.MPCS + }) + + Name (_HID, "QCOM024A") + Name (_UID, 26) + + // Return 0x0 to disable CAMF sensor + Method (_STA) + { + Return (0xf) + } + + Method (SCFG, 0x0, Serialized) + { + Return + ( + Package() + { + Package () + { + "com.qti.sensormodule.liteon_ov5670.bin", + "com.qti.tuned.liteon_ov5670.bin", // NEED UPDATE!!! + 0x0015006C, // I2C Slave Info for Probing, primary address 0x34, secondary 0x20 + 0x5670300B, + 0x00000000 + } + } + ) + } + + // PEP Proxy Support + Name(PGID, Buffer(10) {"\\_SB.CAMF"}) // Device ID buffer - PGID (Pep given ID) + + Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID (Pep given ID) + CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE + // HIDDEN 1 BYTE (SIZE) + CreateByteField(DBUF, 2, DVAL) // Packet value, 1 BYTES Device Status + CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES (160 Bits) + + Method (_S1D, 0) { Return (3) } // S1 => D3 + Method (_S2D, 0) { Return (3) } // S2 => D3 + Method (_S3D, 0) { Return (3) } // S3 => D3 + + Method(_PS0, 0x0, NotSerialized) + { + Store(Buffer(ESNL){}, DEID) + Store(0, DVAL) + Store(PGID, DEID) + If(\_SB.ABD.AVBL) + { + Store(DBUF, \_SB.PEP0.FLD0) + } + } + + Method(_PS3, 0x0, NotSerialized) + { + Store(Buffer(ESNL){}, DEID) + Store(3, DVAL) + Store(PGID, DEID) + If(\_SB.ABD.AVBL) + { + Store(DBUF, \_SB.PEP0.FLD0) + } + } +} + +// +// Auxiliary sensor (OV7251, IR CAM) +// +Device (CAMI) +{ + Name (_DEP, Package(0x1) + { + \_SB_.MPCS + }) + + Name (_HID, "QCOM0247") + Name (_UID, 28) + + // Return 0x0 to disable CAMI sensor + Method (_STA) + { + Return (0xf) + } + + Method (SCFG, 0x0, Serialized) + { + Return + ( + Package() + { + Package () + { + "com.qti.sensormodule.tfc_ov7251.bin", + "\com.qti.tuned.liteon_ov7251.bin", + 0x001500C0, + 0x7750300A, + 0x00000000 + } + } + ) + } + + // PEP Proxy Support + Name(PGID, Buffer(10) {"\\_SB.CAMI"}) // Device ID buffer - PGID (Pep given ID) + + Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID (Pep given ID) + CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE + // HIDDEN 1 BYTE (SIZE) + CreateByteField(DBUF, 2, DVAL) // Packet value, 1 BYTES Device Status + CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES (160 Bits) + + Method (_S1D, 0) { Return (3) } // S1 => D3 + Method (_S2D, 0) { Return (3) } // S2 => D3 + Method (_S3D, 0) { Return (3) } // S3 => D3 + + Method(_PS0, 0x0, NotSerialized) + { + Store(Buffer(ESNL){}, DEID) + Store(0, DVAL) + Store(PGID, DEID) + If(\_SB.ABD.AVBL) + { + Store(DBUF, \_SB.PEP0.FLD0) + } + } + + Method(_PS3, 0x0, NotSerialized) + { + Store(Buffer(ESNL){}, DEID) + Store(3, DVAL) + Store(PGID, DEID) + If(\_SB.ABD.AVBL) + { + Store(DBUF, \_SB.PEP0.FLD0) + } + } +} + +// +// CAMERA WHITE LED FLASH +// +Device (FLSH) +{ + Name (_DEP, Package(0x1) + { + \_SB_.CAMP + }) + + Name (_HID, "QCOM025C") + Name (_UID, 25) + + // Return 0x0 to disable + Method (_STA) + { + Return (0) + } + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // "GPIO Interrupt Connection Resource Descriptor Macro" Format (ACPI $19.5.53): + // GpioInt (EdgeLevel, ActiveLevel, Shared, PinConfig, DebounceTimeout, ResourceSource, + // ResourceSourceIndex, ResourceUsage, DescriptorName, VendorData) {PinList} + }) + + Return (RBUF) + } +} diff --git a/sdm845Pkg/AcpiTables/fajita/cust_camera_exasoc_resources.asl b/sdm845Pkg/AcpiTables/fajita/cust_camera_exasoc_resources.asl new file mode 100755 index 0000000..f06cf12 --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/cust_camera_exasoc_resources.asl @@ -0,0 +1,651 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contains the resources needed by camera drivers for external components like sensors,flash etc. +// Customers can update these files for different external components. +// +// [1] Refer Table 3-10 "Titan 170 Power Use Cases" in "Titan Camera +// Hardware Architecture Specification" for the detailed information on +// the operating points under different use case scenarios. Based on +// the information in the table, this ACPI planned to support SVS and +// NOM frequencies. +// +// [2] Refer Chapter 2 "Defintions of Terms" in the ACPI Specification for +// the definitions of D, F, and P states. Refer the manual of PEP +// driver for the syntax of defining the power and clock resources. +// +// [3] ACPI keeps 2 mA for most GPIO pins by setting the field of +// "PullDriveStrength" to 0 on TLMMGPIO. For high frequency clock pins +// (such as cam_mclk0/1/2/3 running at 24 MHz), the strength shall be +// set to 6 mA to meet the timing requirement. +// +//=========================================================================== + + +// These are not the correct configuration for your phone +// DO NOT INSTALL CAMERA DRIVERS + + +Scope(\_SB_.PEP0) +{ + // Exa-SoC Devices + Method(CPMX) + { + Return (CPXC) + } + + Name(CPXC, + Package () + { + // Device CAMP Data + Package() + { + "DEVICE", + "\\_SB.CAMP", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + + Package() + { + "FSTATE", + 0x0, // F0 state (fully on) + + // FORMAT: FOOTSWITCH NAME; ACTION: 1 == ENABLE, 2 == DISABLE, 3 == HW_CONTROL_ENABLE, 4 == HW_CONTROL_ + // DISABLE. When the ACTION field is set to 1, the CLOCK driver shall set SW_COLLAPSE bit to 1 (which + // means DISABLING/NO SW_COLLAPSE) and poll PWR_ON bit on TITAN_CAM_CC_TITAN_TOP_GDSCR register (as + // inidicated in "$2.3.1.4 Core Power On Sequence" of Titan HPG). The CLOCK driver MUST ensure that + // the power domain has been enabled before returning. It shall be a blocking operation. If a HW block + // (e.g., IPE) is involved, use 3/4 to enable/disable it. HW ENABLING always overrides other settings. + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + + Package() { "PSTATE_ADJUST", Package() { 1, 35 } }, // Set to 2nd lowest BW, need revisit + Package() { "PSTATE_ADJUST", Package() { 2, 35 } }, // Set to 2nd lowest BW, need revisit + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + // Action: 1 == ENABLE, 2 == DISABLE, 3 == SET_FREQ, 8 == ENABLE_SET_FREQ, 9 == CONFIGURE, + // 12 == Disable and Set Frequency (combines actions 2 & 3)(must pair with 8) + // Match_Type: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST, 3 == CLOCK_FREQUENCY_HZ_CLOSEST + // ----------------------------------------------------------------------------------------------------- + // CLOCK Clock Name Action Freq (Hz) MatchType + // ----------------------------------------------------------------------------------------------------- + package() { "CLOCK", package() { "cam_cc_cci_clk", 1} }, // Func: CCI. For CCI operations. + + // Valid only in F-State; Used to adjust one or more current P-State within their respective P-State + // Sets. In this case, it will adjust to P state 0 in PSET 0 (to set cam_cc_cci_clk to 37.5 MHz). + Package() { "PSTATE_ADJUST", Package() { 0, 0 } }, + + // ----------------------------------------------------------------------------------------------------- + // GPIO PIN (Refer CAMS TLMMGPIO) Pin State Func Sel Direct PullDriveStrength + // ----------------------------------------------------------------------------------------------------- + // Camera CCI 0/1 + package() { "TLMMGPIO", package() { 17, 1, 1, 1, 3, 0, }, }, // cci_i2c_sda0 + package() { "TLMMGPIO", package() { 18, 1, 1, 1, 3, 0, }, }, // cci_i2c_scl0 + package() { "TLMMGPIO", package() { 19, 1, 1, 1, 3, 0, }, }, // cci_i2c_sda1 + package() { "TLMMGPIO", package() { 20, 1, 1, 1, 3, 0, }, }, // cci_i2c_scl1 + + // Camera MCLK + package() { "TLMMGPIO", package() { 13, 1, 1, 1, 0, 2, }, }, // cam_mclk0, for CAM0/RFC/OV13850 + package() { "TLMMGPIO", package() { 14, 1, 1, 1, 0, 2, }, }, // cam_mclk1, for CAM1/FFC/OV5670 + package() { "TLMMGPIO", package() { 15, 1, 1, 1, 0, 2, }, }, // cam_mclk2, for CAM2/IRCAMERA/OV7251 + }, + + Package() + { + "FSTATE", + 0x1, // F1 state (OFF) + + package() { "TLMMGPIO", package() { 15, 0, 0, 0, 1, 2, }, }, + package() { "TLMMGPIO", package() { 14, 0, 0, 0, 1, 2, }, }, + package() { "TLMMGPIO", package() { 13, 0, 0, 0, 1, 2, }, }, + + package() { "TLMMGPIO", package() { 20, 0, 0, 0, 1, 0, }, }, + package() { "TLMMGPIO", package() { 19, 0, 0, 0, 1, 0, }, }, + package() { "TLMMGPIO", package() { 18, 0, 0, 0, 1, 0, }, }, + package() { "TLMMGPIO", package() { 17, 0, 0, 0, 1, 0, }, }, + + package() { "CLOCK", package() { "cam_cc_cci_clk", 2 } }, + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "PSTATE_ADJUST", Package() { 2, 37 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 37 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + + // This packet contains P state power setting used by the PEP driver. The clock presented here + // MUST be consistent with the clock values under the PERF method in the file of cust_camera_exasoc.asl. + Package() + { + "PSTATE_SET", + 0, + + // Format: name / action / freq / match_type. The driver shall select the lowest frequency required to perform the task at the acceptable performance + // point. HPG recommends to limit the freq under 50 MHz. It is allowed to have multiple clock resources in one PSTATE package. The indexes and + // frequencies MUST be consistent with CCICLKFrqIdx in CCIResourceType.h and CAMP_CLK in cust_camera_exasoc.asl. + Package() { "PSTATE", 0, package() { "CLOCK", package() { "cam_cc_cci_clk", 3, 37500000, 3, } }, }, // LowSVS for all speeds from 100 KHz to 1 MHz. + Package() { "PSTATE", 1, package() { "CLOCK", package() { "cam_cc_cci_clk", 3, 19200000, 3, } }, }, // MinSVS, not used. + }, + + Package() + { + "PSTATE_SET", // PSET 1: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth); Driver limits the MaxComponentNameLen number as 40. + 1, + + // Format: Type-3 Bus Arbiter Req | Master Name | Slave Name | IB in bytes/sec | AB + Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 12000000000, 12000000000 } }, }, + Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 11500000000, 11500000000 } }, }, + Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 11000000000, 11000000000 } }, }, + Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 10500000000, 10500000000 } }, }, + Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 10000000000, 10000000000 } }, }, + Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 9500000000, 9500000000 } }, }, + Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 9000000000, 9000000000 } }, }, + Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 8500000000, 8500000000 } }, }, + Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 8000000000, 8000000000 } }, }, + Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 7500000000, 7500000000 } }, }, + Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 7000000000, 7000000000 } }, }, + Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 6500000000, 6500000000 } }, }, + Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 6000000000, 6000000000 } }, }, + Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 5500000000, 5500000000 } }, }, + Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 5000000000, 5000000000 } }, }, + Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 4500000000, 4500000000 } }, }, + Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 4000000000, 4000000000 } }, }, + Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3500000000, 3500000000 } }, }, + Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3300000000, 3300000000 } }, }, + Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3100000000, 3100000000 } }, }, + Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2900000000, 2900000000 } }, }, + Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2700000000, 2700000000 } }, }, + Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2500000000, 2500000000 } }, }, + Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2300000000, 2300000000 } }, }, + Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2100000000, 2100000000 } }, }, + Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1900000000, 1900000000 } }, }, + Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1700000000, 1700000000 } }, }, + Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1500000000, 1500000000 } }, }, + Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1300000000, 1300000000 } }, }, + Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } }, }, + Package() { "PSTATE", 30, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 900000000, 900000000 } }, }, + Package() { "PSTATE", 31, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 700000000, 700000000 } }, }, + Package() { "PSTATE", 32, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 500000000, 500000000 } }, }, + Package() { "PSTATE", 33, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } }, }, + Package() { "PSTATE", 34, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } }, }, + Package() { "PSTATE", 35, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } }, }, + Package() { "PSTATE", 36, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } }, }, + Package() { "PSTATE", 37, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } }, }, + }, + + Package() + { + "PSTATE_SET", // PSET 2: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth) + 2, + + // Format: Type-3 Bus Arbiter Req | Master Name | Slave Name | IB in bytes/sec | AB + Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 12000000000, 12000000000 } }, }, + Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 11500000000, 11500000000 } }, }, + Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 11000000000, 11000000000 } }, }, + Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 10500000000, 10500000000 } }, }, + Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 10000000000, 10000000000 } }, }, + Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 9500000000, 9500000000 } }, }, + Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 9000000000, 9000000000 } }, }, + Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 8500000000, 8500000000 } }, }, + Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 8000000000, 8000000000 } }, }, + Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 7500000000, 7500000000 } }, }, + Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 7000000000, 7000000000 } }, }, + Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 6500000000, 6500000000 } }, }, + Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 6000000000, 6000000000 } }, }, + Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 5500000000, 5500000000 } }, }, + Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 5000000000, 5000000000 } }, }, + Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 4500000000, 4500000000 } }, }, + Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 4000000000, 4000000000 } }, }, + Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 3500000000, 3500000000 } }, }, + Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 3300000000, 3300000000 } }, }, + Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 3100000000, 3100000000 } }, }, + Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2900000000, 2900000000 } }, }, + Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2700000000, 2700000000 } }, }, + Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2500000000, 2500000000 } }, }, + Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2300000000, 2300000000 } }, }, + Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2100000000, 2100000000 } }, }, + Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1900000000, 1900000000 } }, }, + Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1700000000, 1700000000 } }, }, + Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1500000000, 1500000000 } }, }, + Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1300000000, 1300000000 } }, }, + Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } }, }, + Package() { "PSTATE", 30, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 900000000, 900000000 } }, }, + Package() { "PSTATE", 31, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 700000000, 700000000 } }, }, + Package() { "PSTATE", 32, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 500000000, 500000000 } }, }, + Package() { "PSTATE", 33, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 400000000, 400000000 } }, }, + Package() { "PSTATE", 34, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 300000000, 300000000 } }, }, + Package() { "PSTATE", 35, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 200000000, 200000000 } }, }, + Package() { "PSTATE", 36, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 100000000, 100000000 } }, }, + Package() { "PSTATE", 37, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 0, 0 } }, }, + }, + }, + + Package() + { + "COMPONENT", + 0x1, // Component 1 + + Package() + { + "FSTATE", + 0x0, // F0 state (fully on) + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + + Package() { "PSTATE_ADJUST", Package() { 3, 4 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 4 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 4 } }, + Package() { "PSTATE_ADJUST", Package() { 0, 4 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + package() { "CLOCK", package() { "cam_cc_cci_clk", 1} }, // Func: CCI. For CCI operations. + }, + + Package() + { + "FSTATE", + 0x1, // F1 state (OFF) + + package() { "CLOCK", package() { "cam_cc_cci_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + + Package() { "PSTATE_ADJUST", Package() { 0, 5 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 5 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 5 } }, + Package() { "PSTATE_ADJUST", Package() { 3, 5 } }, + + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2} }, + }, + Package() + { + "PSTATE_SET", + 0, + Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } } }, + Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } } }, + Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } } }, + Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } } }, + Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } } }, + Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } } }, + }, + // BW - compressed + Package() + { + "PSTATE_SET", + 1, + Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } } }, + Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 400000000, 400000000 } } }, + Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 300000000, 300000000 } } }, + Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 200000000, 200000000 } } }, + Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 100000000, 100000000 } } }, + Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 0, 0 } } }, + }, + + // Moved BW from CAMP to here. this is temporary. + Package() + { + "PSTATE_SET", // PSET 3: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth) + 2, + Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } }, }, + Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } }, }, + Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } }, }, + Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } }, }, + Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } }, }, + Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } }, }, + }, + + // Moved BW from CAMP to here. this is temporary. + Package() + { + "PSTATE_SET", // PSET 3: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth) + 3, + Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } }, }, + Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 400000000, 400000000 } }, }, + Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 300000000, 300000000 } }, }, + Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 200000000, 200000000 } }, }, + Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 100000000, 100000000 } }, }, + Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 0, 0 } }, }, + }, + }, + + Package() + { + "COMPONENT", + 0x2, // Component 2 (SHARED_RES: DUMMY ENTRY) + + Package() {"FSTATE", 0x0,}, // F0 state (fully on) + Package() {"FSTATE", 0x1,}, // F1 state (OFF) + }, + }, + + // Primary RFC (OV13850) Power Setting Array from ov13850_lib.h (sensor vendor supplied). Mapping + // between lib and IP_CAT: VDIG (DVDD), VIO (DOVDD), VANA (AVDD), VAF (AF_VDD). + Package() + { + "DEVICE", + "\\_SB.CAMS", + + Package() + { + "DSTATE", + 0x0, // D0 state (ON) + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + // [1] TLMM_GPIO: set MCAM_PD_N to LOW; + package() + { + "TLMMGPIO", // Identifier: PMIC GPIO. Top Level Mode Mux (TLMM) + package() + { + 28, // Pin Number: MCAM_PD_N (Primary RFC) + 0, // State / OutVal: 0 == Low, 1 == High + 0, // Function Select: 0 == Generic I/O Pin, non-zero == Alternate Function + 1, // Direction: 0 == Input, 1 == Output + 0, // Pull Type: 0 == No Pull, 1 == Pull Down, 2 == Keeper, 3 == Pull Up + 0, // Strength: 0 == 2 mA, 1 == 4 mA, 2 == 6 mA, 3 == 8 mA, 4 == 10 mA, 5 == 12 mA, 4 == 14 mA, 7 == 16 mA + }, + }, + package() { "DELAY", package() { 1, }, }, // 1 ms(millisecond) delay + + + // [4] PMIC_VREG_VOTE: VIN_PM8998 - S4A - VIN_LVS1_LVS2 - LVS1A - DOVDD. LD20-NE182-41-B4. + // Regulator name from //deploy/qcom/qct/platform/wpci/prod/woa/QCDK/main/latest/inc/pmic/PmicIVreg.h + package() + { + //DVDD + "PMICVREGVOTE", // Identifier: PMIC VREG Resource + package() + { + "PPP_RESOURCE_ID_LVS1_A", // Voltage Regulator ID (Type VS) + 4, // TYPE of VREG: 4 == LVS (Low Voltage Switch), 5 == MVS (Medium Voltage Switch) + 1800000, // Voltage: 1.8 V + 1, // Software Enable: 0 == Disable, 1 == Enable (Recommended) + // "HLOS_DRV", // Optional: DRV ID (Default: HLOS_DRV; Valid: HLOS_DRV / DISPLAY_DRV) + // "REQUIRED", // Optional: Suppressible Type (Default: REQUIRED; Valid: REQUIRED / SUPPRESSIBLE) + }, + }, + + package() { "DELAY", package() { 1, }, }, + + Package() + { + // AVDD + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO22_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2800000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + package() { "DELAY", package() { 1, }, }, + + // [6] CLOCK; LD20-NE182-45-D4 + package() { "CLOCK", package() { "cam_cc_mclk0_clk", 8, 24000000, 3, } }, + package() { "DELAY", package() { 1, }, }, + + // [7] TLMM_GPIO: set CAM0_RST_N to HIGH + package() { "TLMMGPIO", package() { 28, 1, 0, 1, 0, 0, }, }, + package() { "DELAY", package() { 18, }, }, // 18 ms wait time between XCLR rising and sending streaming command + }, + + Package() + { + "DSTATE", + 0x3, // D3 state (OFF) + + + // [2] CAM0_RST_N LOW + package() { "TLMMGPIO", package() { 28, 0, 0, 1, 0, 0, }, }, + package() { "DELAY", package() { 1, }, }, + + // [1] CLOCK OFF + package() { "CLOCK", package() { "cam_cc_mclk0_clk", 2} }, + package() { "DELAY", package() { 1, }, }, + + // [3] AVDD OFF + Package() { "PMICVREGVOTE", Package() { "PPP_RESOURCE_ID_LDO22_A", 1, 0, 0, 0, 0, }, }, + + // [3] DOVDD OFF + package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 0, 0, }, }, + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + }, + + // Primary FFC (OV5670) Power Setting Array from ov5670_lib.h. + + Package() + { + "DEVICE", + "\\_SB.CAMF", + + Package() + { + "DSTATE", + 0x0, + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + package() { "TLMMGPIO", package() { 9, 0, 0, 1, 0, 0, }, }, + // [1] DOVDD + package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 1800000, 1, }, }, + + package() { "DELAY", package() { 1, }, }, + + Package() + { + // AVDD + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO22_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2800000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + package() { "DELAY", package() { 1, }, }, + + // [6] CLOCK; LD20-NE182-43-C2 + package() { "CLOCK", package() { "cam_cc_mclk1_clk", 8, 24000000, 3, } }, + package() { "DELAY", package() { 1, }, }, + + // [7] TLMM_GPIO: set CAM1_RST_N to HIGH; LD20-NE182-7-C6 + package() { "TLMMGPIO", package() { 9, 1, 0, 1, 0, 0, }, }, + package() { "DELAY", package() { 12, }, }, + }, + + Package() + { + "DSTATE", + 0x3, + + // [1] CAM1_RST_N LOW + package() { "TLMMGPIO", package() { 9, 0, 0, 1, 0, 0, }, }, + package() { "DELAY", package() { 1, }, }, + + // [2] CLOCK OFF + package(){ "CLOCK", package(){ "cam_cc_mclk1_clk", 12, 0, 3} }, + package() { "DELAY", package() { 1, }, }, + + // [3] AVDD OFF + Package() { "PMICVREGVOTE", Package() { "PPP_RESOURCE_ID_LDO22_A", 1, 0, 0, 0, 0, }, }, + + // [4] DOVDD OFF + package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 0, 0, }, }, + package() { "DELAY", package() { 1, }, }, + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + }, + + // FFC Auxiliary (OV7251) Power Setting Array from ov7251_lib.h. Refer OV7251 datasheet + // "power up sequence", figure 2-7, "power down sequence", and figure 2-9 for more + // information. + Package() + { + "DEVICE", + "\\_SB.CAMI", + + Package() + { + "DSTATE", + 0x0, + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + // [0] PMIC_GPIO: FLED_DEV_EN + package() + { + "PMICGPIO", + package() + { + "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", + 0, // PMIC Number: 0 == PM8998, 1 == PMI8998, 2 == PM8005 + 0, // GPIO Number: PM_GPIO_1 / FLED_DEV_EN + 0, // Out Buffer Config: 0 == PM_GPIO_OUT_BUFFER_CONFIG_CMOS + 1, // VIN: 0 == PM_GPIO_VIN0, 1 == VIN1 + 1, // Source: 0 == PM_GPIO_SOURCE_LOW, 1 == HIGH + 3, // Out Buffer Strength: 0 == PM_GPIO_OUT_BUFFER_RESERVED, 1 == LOW, 2 == MEDIUM, 3 == HIGH + 0, // I Source Pull: 0 == PM_GPIO_I_SOURCE_PULL_UP_30uA + }, + }, + package() { "DELAY", package() { 1, }, }, + // [1] VIO / DOVDD - VREG_LVS1A_1P8 (All camera 1.8 V IO); PM_IC_VREG_VOTE; LD20-NE182-41-B4, 42-D6 + package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 1800000, 1, }, }, + + package() { "DELAY", package() { 1, }, }, + + Package() + { + // AVDD + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO22_A", // VREG ID + 1, // Voltage Regulator type = LDO + 2800000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + package() { "DELAY", package() { 1, }, }, + + // [4] IR_PWDN_N LOW (IR Camera, 3rd camera in system); LD20-NE182-7-D6 + package() { "TLMMGPIO", package() { 23, 0, 0, 1, 0, 0, }, }, + package() { "DELAY", package() { 1, }, }, + + // [5] IR_PWDN_N HIGH + package() { "TLMMGPIO", package() { 23, 1, 0, 1, 0, 0, }, }, + package() { "DELAY", package() { 1, }, }, + + // [6] CLOCK; LD20-NE182-42-C6 + package() { "CLOCK", package() { "cam_cc_mclk2_clk", 8, 24000000, 3, } }, + package() { "DELAY", package() { 1, }, }, + }, + + Package() + { + "DSTATE", + 0x3, + + // [1] CLOCK OFF + package(){ "CLOCK", package(){ "cam_cc_mclk2_clk", 2} }, + package() { "DELAY", package() { 1, }, }, + + // [2] IR_PWDN_N HIGH + package() { "TLMMGPIO", package() { 23, 1, 0, 1, 0, 0, }, }, + package() { "DELAY", package() { 1, }, }, + + // [3] IR_PWDN_N LOW + package() { "TLMMGPIO", package() { 23, 0, 0, 1, 0, 0, }, }, + package() { "DELAY", package() { 1, }, }, + + // [4] AVDD OFF + Package() { "PMICVREGVOTE", Package() { "PPP_RESOURCE_ID_LDO22_A", 1, 0, 0, 0, 0, }, }, + + // [5] DOVDD OFF + package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 0, 0, }, }, + + package() { "PMICGPIO", package() { "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", 0, 0, 0, 1, 0, 3, 0, }, }, + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + } + }) +} diff --git a/sdm845Pkg/AcpiTables/fajita/cust_camera_resources.asl b/sdm845Pkg/AcpiTables/fajita/cust_camera_resources.asl new file mode 100755 index 0000000..b09d2b2 --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/cust_camera_resources.asl @@ -0,0 +1,1265 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contains the resources needed by camera drivers. +// +// [1] Refer Table 3-10 "Titan 170 Power Use Cases" in "Titan Camera +// Hardware Architecture Specification" for the detailed information on +// the operating points under different use case scenarios. Based on +// the information in the table, this ACPI planned to support SVS and +// NOM frequencies. +// +// [2] Refer Chapter 2 "Defintions of Terms" in the ACPI Specification for +// the definitions of D, F, and P states. Refer the manual of PEP +// driver for the syntax of defining the power and clock resources. +// +// [3] ACPI keeps 2 mA for most GPIO pins by setting the field of +// "PullDriveStrength" to 0 on TLMMGPIO. For high frequency clock pins +// (such as cam_mclk0/1/2/3 running at 24 MHz), the strength shall be +// set to 6 mA to meet the timing requirement. +// +//=========================================================================== + + +// These are not the correct configuration for your phone +// DO NOT INSTALL CAMERA DRIVERS + + + +Include("cust_camera_exasoc_resources.asl") + +Scope(\_SB_.PEP0) +{ + // CAMERA + Method(CPMD) + { + Return(CPCC) + } + + Name(CPCC, Package() + { + // JPEG ENCODER (JPGE) + Package() + { + "DEVICE", + "\\_SB.JPGE", + + Package() + { + "COMPONENT", + 0x0, // Component 0; JPEG 0 Encoder + + Package() + { + "FSTATE", + 0x0, // F0 State + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + package() { "CLOCK", package() { "cam_cc_jpeg_clk", 1} }, // For core processing on JPEG instance 0 and 3; SVS + + package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS + }, + + Package() + { + "FSTATE", + 0x1, // F1 State + + package() { "CLOCK", package() { "cam_cc_jpeg_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + + Package() + { + "PSTATE_SET", // PSET 0: Clock frequency adjustments + 0, + + Package() { "PSTATE", 0, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 600000000, 3, } }, }, // TURBO for driver turbo + Package() { "PSTATE", 1, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 600000000, 3, } }, }, // NOMINAL for driver nominal + Package() { "PSTATE", 2, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 404000000, 3, } }, }, // SVS only used in driver (revisit) + Package() { "PSTATE", 3, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 200000000, 3, } }, }, // LowSVS for driver Standby + }, + }, + + Package() + { + "COMPONENT", + 0x1, // Component 2; JPEG_3/DMA. Note that this is normally indexed as JPEG core "3" in diagrams, but the ACPI entry index is 2 here + + Package() + { + "FSTATE", + 0x0, // F0 State + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + package() { "CLOCK", package() { "cam_cc_jpeg_clk", 1} }, // LowSVS for standby (JPEG3 ONLY) + + package() { "PSTATE_ADJUST", Package() { 0, 2 }}, + }, + + Package() + { + "FSTATE", + 0x1, // F1 State + + package() { "CLOCK", package() { "cam_cc_jpeg_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + + Package() + { + "PSTATE_SET", + 0, + + Package() { "PSTATE", 0, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 600000000, 3, } }, }, // Turbo + Package() { "PSTATE", 1, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 600000000, 3, } }, }, // Nominal + Package() { "PSTATE", 2, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 200000000, 3, } }, }, // LowSVS for Standby + }, + }, + }, + + + // Device MPCS Data (DEVICE/COMPONENT/STATE) + Package() + { + "DEVICE", + "\\_SB.MPCS", + + Package() + { + "COMPONENT", + 0x0, // Component 0 (CSIPHY_0) + + Package() + { + "FSTATE", + 0x0, + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + Package() { "CLOCK", Package() { "phy_refgen_south", 1} }, //To enable REFGEN SOUTH + + package() { "CLOCK", package() { "cam_cc_csi0phytimer_clk", 8, 269330000, 3, }}, // SVS = NOM = TURBO + package() { "CLOCK", package() { "cam_cc_csiphy0_clk", 8, 384000000, 3, }}, // SVS = NOM = TURBO + }, + + Package() + { + "FSTATE", + 0x1, + + package() { "CLOCK", package() { "cam_cc_csiphy0_clk", 2}}, + package() { "CLOCK", package() { "cam_cc_csi0phytimer_clk", 2}}, + + Package() { "CLOCK", Package() { "phy_refgen_south", 2 }}, //To disable REFGEN SOUTH + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + }, + + Package() + { + "COMPONENT", + 0x1, // Component 1 (CSIPHY_1) + + Package() + { + "FSTATE", + 0x0, + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + Package() { "CLOCK", Package() { "phy_refgen_south", 1} }, //To enable REFGEN SOUTH + + package() { "CLOCK", package() { "cam_cc_csi1phytimer_clk", 8, 269330000, 3, }}, + package() { "CLOCK", package() { "cam_cc_csiphy1_clk", 8, 384000000, 3, }}, + }, + + Package() + { + "FSTATE", + 0x1, + + package() { "CLOCK", package() { "cam_cc_csiphy1_clk", 2}}, + package() { "CLOCK", package() { "cam_cc_csi1phytimer_clk", 2}}, + + Package() { "CLOCK", Package() { "phy_refgen_south", 2 }}, //To disable REFGEN SOUTH + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + }, + + Package() + { + "COMPONENT", + 0x2, // Component 2 (CSIPHY_2) + + Package() + { + "FSTATE", + 0x0, + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + Package() { "CLOCK", Package() { "phy_refgen_south", 1} }, //To enable REFGEN SOUTH + + package() { "CLOCK", package() { "cam_cc_csi2phytimer_clk", 8, 269330000, 3, }}, + package() { "CLOCK", package() { "cam_cc_csiphy2_clk", 8, 384000000, 3, }}, + }, + + Package() + { + "FSTATE", + 0x1, + + package() { "CLOCK", package() { "cam_cc_csiphy2_clk", 2}}, + package() { "CLOCK", package() { "cam_cc_csi2phytimer_clk", 2}}, + + + Package() { "CLOCK", Package() { "phy_refgen_south", 2 }}, //To disable REFGEN SOUTH + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + }, + }, + + //Device VFE0 Data + Package() + { + "DEVICE", + "\\_SB.VFE0", + Package() + { + "COMPONENT", + 0x0, // Component 0. //IFE0 component + Package() + { + "FSTATE", + 0x0, // F0 state + + // Footswitch Name; Action (1 == Enable; 2 == Disable; 3 = HW_CONTROL enable, 4 = HW_CONTROL disable) + + // Action: 1 == ENABLE 2 == DISABLE 3 == SET_FREQ 8 == EN_SETFREQ + // MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST 3 == CLOCK_FREQUENCY_HZ_CLOSEST + + // Clock Name Action Frequency MatchType + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + Package(){"PSTATE_ADJUST", Package () { 1, 10 }}, // bw voting + Package(){"PSTATE_ADJUST", Package () { 2, 10 }}, // bw voting + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + Package() { "FOOTSWITCH", Package() { "ife_0_gdsc", 1 } }, + + //IFE0 Clocks + package() { "PSTATE_ADJUST", Package() { 0, 1 } }, // Pstate adjustment for clock frequencies. Set to SVS + package(){ "CLOCK", package(){ "cam_cc_ife_0_clk", 1 } }, + package(){ "CLOCK", package(){ "cam_cc_ife_0_cphy_rx_clk", 8, 384000000, 3, } }, // SVS + package(){ "CLOCK", package(){ "cam_cc_ife_0_csid_clk", 8, 384000000, 3, } }, // SVS + package(){ "CLOCK", package(){ "cam_cc_ife_0_dsp_clk", 1} }, + + package(){ "CLOCK", package(){ "cam_cc_ife_0_axi_clk", 1} }, + + }, + Package() + { + "FSTATE", + 0x1, // F1 state + + package(){ "CLOCK", package(){ "cam_cc_ife_0_axi_clk", 2}}, + + package(){ "CLOCK", package(){ "cam_cc_ife_0_dsp_clk", 2}}, + package(){ "CLOCK", package(){ "cam_cc_ife_0_csid_clk", 2}}, + package(){ "CLOCK", package(){ "cam_cc_ife_0_cphy_rx_clk", 2}}, + //package() { "PSTATE_ADJUST", Package() { 0, 4 } }, + + package(){ "CLOCK", package(){ "cam_cc_ife_0_clk", 2}}, + + Package() { "FOOTSWITCH", Package() { "ife_0_gdsc", 2 } }, + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package(){"PSTATE_ADJUST", Package () { 2, 29 }}, // bw voting + Package(){"PSTATE_ADJUST", Package () { 1, 29 }}, // bw voting + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + + }, + + // Clk Freq + Package() + { + "PSTATE_SET", + 0, + // TURBO, NOM + Package() + { + "PSTATE", + 0, + Package(){ "CLOCK", Package(){ "cam_cc_ife_0_clk", 3, 600000000, 3, }}, + }, + // SVS_L1 + Package() + { + "PSTATE", + 1, + Package(){ "CLOCK", Package(){ "cam_cc_ife_0_clk", 3, 480000000, 3, }}, + }, + // SVS + Package() + { + "PSTATE", + 2, + Package(){ "CLOCK", Package(){ "cam_cc_ife_0_clk", 3, 404000000, 3, }}, + }, + // Off + Package() + { + "PSTATE", + 3, + Package(){ "CLOCK", Package(){ "cam_cc_ife_0_clk", 3, 0, 3, }}, + }, + }, + + + // BW - Uncompressed + Package() + { + "PSTATE_SET", + 1, + + // Req IB AB + // Type Master Slave Bytes/Sec Bytes/Sec + // ---- ----------------------- ---------------------- ---------- ---------- + Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 38000000000, 38000000000 } } }, + Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 35000000000, 35000000000 } } }, + Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 28000000000, 28000000000 } } }, + Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 23000000000, 23000000000 } } }, + Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 20000000000, 20000000000 } } }, + Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 16000000000, 16000000000 } } }, + Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 14000000000, 14000000000 } } }, + Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 12000000000, 12000000000 } } }, + Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 4000000000, 4000000000 } } }, + Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3500000000, 3500000000 } } }, + Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3300000000, 3300000000 } } }, + Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3100000000, 3100000000 } } }, + Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2900000000, 2900000000 } } }, + Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2700000000, 2700000000 } } }, + Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2500000000, 2500000000 } } }, + Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2300000000, 2300000000 } } }, + Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2100000000, 2100000000 } } }, + Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1900000000, 1900000000 } } }, + Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1700000000, 1700000000 } } }, + Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1500000000, 1500000000 } } }, + Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1300000000, 1300000000 } } }, + Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } } }, + Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 900000000, 900000000 } } }, + Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 700000000, 700000000 } } }, + Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 500000000, 500000000 } } }, + Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } } }, + Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } } }, + Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } } }, + Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } } }, + Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } } }, + }, + // BW - compressed + Package() + { + "PSTATE_SET", + 2, + + // Req IB AB + // Type Master Slave Bytes/Sec Bytes/Sec + // ---- ----------------------- ---------------------- ---------- ---------- + Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 38000000000, 38000000000 } } }, + Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 35000000000, 35000000000 } } }, + Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 28000000000, 28000000000 } } }, + Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 23000000000, 23000000000 } } }, + Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 20000000000, 20000000000 } } }, + Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 16000000000, 16000000000 } } }, + Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 14000000000, 14000000000 } } }, + Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 12000000000, 12000000000 } } }, + Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 4000000000, 4000000000 } } }, + Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 3500000000, 3500000000 } } }, + Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 3300000000, 3300000000 } } }, + Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 3100000000, 3100000000 } } }, + Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 2900000000, 2900000000 } } }, + Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 2700000000, 2700000000 } } }, + Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 2500000000, 2500000000 } } }, + Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 2300000000, 2300000000 } } }, + Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 2100000000, 2100000000 } } }, + Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1900000000, 1900000000 } } }, + Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1700000000, 1700000000 } } }, + Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1500000000, 1500000000 } } }, + Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1300000000, 1300000000 } } }, + Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } } }, + Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 900000000, 900000000 } } }, + Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 700000000, 700000000 } } }, + Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 500000000, 500000000 } } }, + Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 400000000, 400000000 } } }, + Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 300000000, 300000000 } } }, + Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 200000000, 200000000 } } }, + Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 100000000, 100000000 } } }, + Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 0, 0 } } }, + }, + + // CSID Clk Freq: TODO + + }, + + Package() + { + "COMPONENT", + 0x1, // Component 1. //IFE1 component + Package() + { + "FSTATE", + 0x0, // F0 state + + // Footswitch Name; Action (1 == Enable; 2 == Disable; 3 = HW_CONTROL enable, 4 = HW_CONTROL disable) + // Action: 1 == ENABLE 2 == DISABLE 3 == SET_FREQ 8 == EN_SETFREQ + // MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST 3 == CLOCK_FREQUENCY_HZ_CLOSEST + + // Clock Name Action Frequency MatchType + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + Package(){"PSTATE_ADJUST", Package () { 1, 10 }}, // bw voting + Package(){"PSTATE_ADJUST", Package () { 2, 10 }}, // bw voting + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + Package() { "FOOTSWITCH", Package() { "ife_1_gdsc", 1 } }, + + //IFE1 Clocks + package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS + package() { "CLOCK", package(){ "cam_cc_ife_1_clk", 1} }, + + package() { "CLOCK", package(){ "cam_cc_ife_1_cphy_rx_clk", 8, 384000000, 3, } }, // SVS + package() { "CLOCK", package(){ "cam_cc_ife_1_csid_clk", 8, 384000000, 3, } }, // SVS + package() { "CLOCK", package(){ "cam_cc_ife_1_dsp_clk", 1} }, + + package() { "CLOCK", package(){ "cam_cc_ife_1_axi_clk", 1} }, + + }, + Package() + { + "FSTATE", + 0x1, // F1 state + + package(){ "CLOCK", package(){ "cam_cc_ife_1_axi_clk", 2} }, + + package(){ "CLOCK", package(){ "cam_cc_ife_1_dsp_clk", 2} }, + package(){ "CLOCK", package(){ "cam_cc_ife_1_csid_clk", 2} }, + package(){ "CLOCK", package(){ "cam_cc_ife_1_cphy_rx_clk", 2} }, + + //package() { "PSTATE_ADJUST", Package() { 0, 4 } }, + package(){ "CLOCK", package(){ "cam_cc_ife_1_clk", 2} }, + + Package(){ "FOOTSWITCH", Package(){ "ife_1_gdsc", 2 } }, + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package(){"PSTATE_ADJUST", Package () { 2, 29 }}, // bw voting + Package(){"PSTATE_ADJUST", Package () { 1, 29 }}, // bw voting + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + + }, + + // Clk Freq + Package() + { + "PSTATE_SET", + 0, + // TURBO, NOM + Package() + { + "PSTATE", + 0, + Package(){ "CLOCK", Package(){ "cam_cc_ife_1_clk", 3, 600000000, 3, }}, + }, + // SVS_L1 + Package() + { + "PSTATE", + 1, + Package(){ "CLOCK", Package(){ "cam_cc_ife_1_clk", 3, 480000000, 3, }}, + }, + // SVS + Package() + { + "PSTATE", + 2, + Package(){ "CLOCK", Package(){ "cam_cc_ife_1_clk", 3, 404000000, 3, }}, + }, + // Off + Package() + { + "PSTATE", + 3, + Package(){ "CLOCK", Package(){ "cam_cc_ife_1_clk", 3, 0, 3, }}, + }, + }, + + // BW - Uncompressed + Package() + { + "PSTATE_SET", + 1, + + // Req IB AB + // Type Master Slave Bytes/Sec Bytes/Sec + // ---- ----------------------- ---------------------- ---------- ---------- + Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 38000000000, 38000000000 } } }, + Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 35000000000, 35000000000 } } }, + Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 28000000000, 28000000000 } } }, + Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 23000000000, 23000000000 } } }, + Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 20000000000, 20000000000 } } }, + Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 16000000000, 16000000000 } } }, + Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 14000000000, 14000000000 } } }, + Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 12000000000, 12000000000 } } }, + Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 4000000000, 4000000000 } } }, + Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3500000000, 3500000000 } } }, + Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3300000000, 3300000000 } } }, + Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3100000000, 3100000000 } } }, + Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2900000000, 2900000000 } } }, + Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2700000000, 2700000000 } } }, + Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2500000000, 2500000000 } } }, + Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2300000000, 2300000000 } } }, + Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2100000000, 2100000000 } } }, + Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1900000000, 1900000000 } } }, + Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1700000000, 1700000000 } } }, + Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1500000000, 1500000000 } } }, + Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1300000000, 1300000000 } } }, + Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } } }, + Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 900000000, 900000000 } } }, + Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 700000000, 700000000 } } }, + Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 500000000, 500000000 } } }, + Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } } }, + Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } } }, + Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } } }, + Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } } }, + Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } } }, + }, + // BW - compressed + Package() + { + "PSTATE_SET", + 2, + + // Req IB AB + // Type Master Slave Bytes/Sec Bytes/Sec + // ---- ----------------------- ---------------------- ---------- ---------- + Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 38000000000, 38000000000 } } }, + Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 35000000000, 35000000000 } } }, + Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 28000000000, 28000000000 } } }, + Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 23000000000, 23000000000 } } }, + Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 20000000000, 20000000000 } } }, + Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 16000000000, 16000000000 } } }, + Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 14000000000, 14000000000 } } }, + Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 12000000000, 12000000000 } } }, + Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 4000000000, 4000000000 } } }, + Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 3500000000, 3500000000 } } }, + Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 3300000000, 3300000000 } } }, + Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 3100000000, 3100000000 } } }, + Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 2900000000, 2900000000 } } }, + Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 2700000000, 2700000000 } } }, + Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 2500000000, 2500000000 } } }, + Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 2300000000, 2300000000 } } }, + Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 2100000000, 2100000000 } } }, + Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 1900000000, 1900000000 } } }, + Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 1700000000, 1700000000 } } }, + Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 1500000000, 1500000000 } } }, + Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 1300000000, 1300000000 } } }, + Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } } }, + Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 900000000, 900000000 } } }, + Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 700000000, 700000000 } } }, + Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 500000000, 500000000 } } }, + Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 400000000, 400000000 } } }, + Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 300000000, 300000000 } } }, + Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 200000000, 200000000 } } }, + Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 100000000, 100000000 } } }, + Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 0, 0 } } }, + }, + + }, + + Package() + { + "COMPONENT", + 0x2, // Component 2. //IFE LITE component + Package() + { + "FSTATE", + 0x0, // F0 state + + // Footswitch Name; Action (1 == Enable; 2 == Disable; 3 = HW_CONTROL enable, 4 = HW_CONTROL disable) + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + //IFE Lite Clocks + package(){ "CLOCK", package(){ "cam_cc_ife_lite_clk", 1 } }, + package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS + + package(){ "CLOCK", package(){ "cam_cc_ife_lite_cphy_rx_clk", 8, 384000000, 3, } }, // SVS + package(){ "CLOCK", package(){ "cam_cc_ife_lite_csid_clk", 8, 384000000, 3, } }, // SVS + + }, + Package() + { + "FSTATE", + 0x1, // F1 state + + package(){ "CLOCK", package(){ "cam_cc_ife_lite_csid_clk", 2 } }, + package(){ "CLOCK", package(){ "cam_cc_ife_lite_cphy_rx_clk", 2 } }, + + package() { "PSTATE_ADJUST", Package() { 0, 4 } }, + package(){ "CLOCK", package(){ "cam_cc_ife_lite_clk", 2 } }, + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + + // Clk Freq + Package() + { + "PSTATE_SET", + 0, + // TURBO, NOM + Package() + { + "PSTATE", + 0, + Package(){ "CLOCK", Package(){ "cam_cc_ife_lite_clk", 3, 600000000, 3, }}, + }, + // SVS_L1 + Package() + { + "PSTATE", + 1, + Package(){ "CLOCK", Package(){ "cam_cc_ife_lite_clk", 3, 480000000, 3, }}, + }, + // SVS + Package() + { + "PSTATE", + 2, + Package(){ "CLOCK", Package(){ "cam_cc_ife_lite_clk", 3, 404000000, 3, }}, + }, + // Off + Package() + { + "PSTATE", + 3, + Package(){ "CLOCK", Package(){ "cam_cc_ife_lite_clk", 3, 0, 3, }}, + }, + }, + + // BW: ICBID_MASTER_CAMNOC_HF1_UNCOMP is used for both ife1 & ife_lite + }, + + Package() + { + "COMPONENT", + 0x3, // Component 3. //ICP component + Package() + { + "FSTATE", + 0x0, // F0 state + + // Vote for QDSS to enable the following AOP clocks: + // cam_cc_icp_apb_clk : gcc_mmss_icp_apb_clk : gcc_apb_clk + // cam_cc_icp_atb_clk : gcc_mmss_icp_atb_clk : gcc_mmss_at_clk + // cam_cc_icp_cti_clk : gcc_mmss_icp_cti_clk : gcc_mmss_trig_clk + // cam_cc_icp_ts_clk : gcc_mmss_icp_ts_clk : gcc_qdss_tsctr_clk + // + package() {"NPARESOURCE", package() {1, "/clk/qdss", 1},}, + + // Footswitch Name; Action (1 == Enable; 2 == Disable) + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + package() { "CLOCK", package() { "cam_cc_icp_apb_clk", 1 } }, + + package() { "CLOCK", package() { "cam_cc_icp_clk", 1 } }, // SVS. DCVS recommendation + package() { "PSTATE_ADJUST", Package() { 0, 1 } }, // Pstate adjustment for clock frequencies. Set to SVS + + package() { "CLOCK", package() { "cam_cc_icp_atb_clk", 1 } }, + package() { "CLOCK", package() { "cam_cc_icp_cti_clk", 1 } }, + package() { "CLOCK", package() { "cam_cc_icp_ts_clk", 1 } }, + }, + Package() + { + "FSTATE", + 0x1, // F1 state + package(){ "CLOCK", package(){ "cam_cc_icp_ts_clk", 2 } }, + package(){ "CLOCK", package(){ "cam_cc_icp_cti_clk", 2 } }, + package(){ "CLOCK", package(){ "cam_cc_icp_atb_clk", 2 } }, + + package() { "PSTATE_ADJUST", Package() { 0, 2 } }, + package(){ "CLOCK", package(){ "cam_cc_icp_clk", 2 } }, + package(){ "CLOCK", package(){ "cam_cc_icp_apb_clk", 2 } }, + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + + // Remove the QDSS vote to disable the following AOP clocks: + // cam_cc_icp_apb_clk : gcc_mmss_icp_apb_clk : gcc_apb_clk + // cam_cc_icp_atb_clk : gcc_mmss_icp_atb_clk : gcc_mmss_at_clk + // cam_cc_icp_cti_clk : gcc_mmss_icp_cti_clk : gcc_mmss_trig_clk + // cam_cc_icp_ts_clk : gcc_mmss_icp_ts_clk : gcc_qdss_tsctr_clk + // + package() {"NPARESOURCE", package() {1, "/clk/qdss", 0},}, + }, + + Package() + { + "PSTATE_SET", + 0, + + // NOM + Package() + { + "PSTATE", + 0, + package() { "CLOCK", package() { "cam_cc_icp_clk", 3, 600000000, 3, } }, + + }, + + // SVS + Package() + { + "PSTATE", + 1, + package() { "CLOCK", package() { "cam_cc_icp_clk", 3, 400000000, 3, } }, + + }, + + // Off + Package() + { + "PSTATE", + 2, + package() { "CLOCK", package() { "cam_cc_icp_clk", 3, 0, 3, } }, + + }, + }, + }, + + Package() + { + "COMPONENT", + 0x4, // Component 4. //IPE0/1 component + Package() + { + "FSTATE", + 0x0, // F0 state + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + // IPE0 clocks + Package() { "FOOTSWITCH", Package() { "ipe_0_gdsc", 1 } }, + + package() { "CLOCK", package() { "cam_cc_ipe_0_ahb_clk", 1 } }, + + package() { "CLOCK", package() { "cam_cc_ipe_0_clk", 1 } }, + package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS + + package() { "CLOCK", package() { "cam_cc_ipe_0_areg_clk", 1 } }, + package() { "CLOCK", package() { "cam_cc_ipe_0_axi_clk", 1 } }, + + Package() { "FOOTSWITCH", Package() { "ipe_0_gdsc", 3 } }, // HW control (TODO: need to enable by ES) + + + // IPE1 clocks + Package() { "FOOTSWITCH", Package() { "ipe_1_gdsc", 1 } }, + + package() { "CLOCK", package() { "cam_cc_ipe_1_ahb_clk", 1 } }, + + package() { "CLOCK", package() { "cam_cc_ipe_1_clk", 1 } }, + package() { "PSTATE_ADJUST", Package() { 1, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS + + package() { "CLOCK", package() { "cam_cc_ipe_1_areg_clk", 1 } }, + package() { "CLOCK", package() { "cam_cc_ipe_1_axi_clk", 1 } }, + + Package() { "FOOTSWITCH", Package() { "ipe_1_gdsc", 3 } }, // HW control (TODO: need to enable by ES) + + }, + Package() + { + "FSTATE", + 0x1, // F1 state + + + Package() { "FOOTSWITCH", Package() { "ipe_1_gdsc", 4 } }, // HW control (TODO: need to enable by ES) + + package() { "CLOCK", package() { "cam_cc_ipe_1_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_ipe_1_areg_clk", 2 } }, + + package() { "PSTATE_ADJUST", Package() { 1, 4 } }, + package() { "CLOCK", package() { "cam_cc_ipe_1_clk", 2 } }, + + package() { "CLOCK", package() { "cam_cc_ipe_1_ahb_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "ipe_1_gdsc", 2 } }, + + Package() { "FOOTSWITCH", Package() { "ipe_0_gdsc", 4 } }, // HW control (TODO: need to enable by ES) + + package() { "CLOCK", package() { "cam_cc_ipe_0_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_ipe_0_areg_clk", 2 } }, + + package() { "PSTATE_ADJUST", Package() { 0, 4 } }, + package() { "CLOCK", package() { "cam_cc_ipe_0_clk", 2 } }, + + package() { "CLOCK", package() { "cam_cc_ipe_0_ahb_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "ipe_0_gdsc", 2 } }, + + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + + // Clk Freq + Package() + { + "PSTATE_SET", + 0, + Package() // Turbo + { + "PSTATE", + 0, + Package(){ "CLOCK", Package(){ "cam_cc_ipe_0_clk", 3, 600000000, 3, }}, + }, + Package() // SVS_L1 + { + "PSTATE", + 1, + Package(){ "CLOCK", Package(){ "cam_cc_ipe_0_clk", 3, 480000000, 3, }}, + }, + Package() // SVS + { + "PSTATE", + 2, + Package(){ "CLOCK", Package(){ "cam_cc_ipe_0_clk", 3, 404000000, 3, }}, + }, + Package() // Off + { + "PSTATE", + 3, + Package(){ "CLOCK", Package(){ "cam_cc_ipe_0_clk", 3, 0, 3, }}, + }, + }, + + // Clk Freq + Package() + { + "PSTATE_SET", + 1, + Package() // Turbo + { + "PSTATE", + 0, + Package(){ "CLOCK", Package(){ "cam_cc_ipe_1_clk", 3, 600000000, 3, }}, + }, + Package() // SVS_L1 + { + "PSTATE", + 1, + Package(){ "CLOCK", Package(){ "cam_cc_ipe_1_clk", 3, 480000000, 3, }}, + }, + Package() // SVS + { + "PSTATE", + 2, + Package(){ "CLOCK", Package(){ "cam_cc_ipe_1_clk", 3, 404000000, 3, }}, + }, + Package() // Off + { + "PSTATE", + 3, + Package(){ "CLOCK", Package(){ "cam_cc_ipe_1_clk", 3, 0, 3, }}, + }, + }, + + // IPE0/1 AHB & AREG Freq: TODO + }, + + Package() + { + "COMPONENT", + 0x5, // Component 5. //BPS component + Package() + { + "FSTATE", + 0x0, // F0 state + // Footswitch Name; Action (1 == Enable; 2 == Disable; 3 = HW_CONTROL enable, 4 = HW_CONTROL disable) + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + // BPS clocks + Package() { "FOOTSWITCH", Package() { "bps_gdsc", 1 } }, + + package() { "CLOCK", package() { "cam_cc_bps_ahb_clk", 1 } }, // SVS + + package() { "CLOCK", package() { "cam_cc_bps_clk", 1 } }, + package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS + + package() { "CLOCK", package() { "cam_cc_bps_areg_clk", 1 } }, // SVS + package() { "CLOCK", package() { "cam_cc_bps_axi_clk", 1 } }, + + Package() { "FOOTSWITCH", Package() { "bps_gdsc", 3 } }, // HW control (TODO: need to enable by ES) + + + }, + Package() + { + "FSTATE", + 0x1, // F1 state + + Package() { "FOOTSWITCH", Package() { "bps_gdsc", 4 } }, // HW control (TODO: need to enable by ES) + + package() { "CLOCK", package() { "cam_cc_bps_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_bps_areg_clk", 2 } }, + + package() { "PSTATE_ADJUST", Package() { 0, 4 } }, + package() { "CLOCK", package() { "cam_cc_bps_clk", 2 } }, + + package() { "CLOCK", package() { "cam_cc_bps_ahb_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "bps_gdsc", 2 } }, + + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + + // Clk Freq + Package() + { + "PSTATE_SET", + 0, + Package() // Turbo + { + "PSTATE", + 0, + Package(){ "CLOCK", Package(){ "cam_cc_bps_clk", 3, 600000000, 3, }}, + }, + Package() // SVS_L1 + { + "PSTATE", + 1, + Package(){ "CLOCK", Package(){ "cam_cc_bps_clk", 3, 480000000, 3, }}, + }, + Package() // SVS + { + "PSTATE", + 2, + Package(){ "CLOCK", Package(){ "cam_cc_bps_clk", 3, 404000000, 3, }}, + }, + Package() // Off + { + "PSTATE", + 3, + Package(){ "CLOCK", Package(){ "cam_cc_bps_clk", 3, 0, 3, }}, + }, + }, + // BPS AHB & AREG Freq: TODO + }, + + Package() + { + "COMPONENT", + 0x6, // Component 6. //LRME component + Package() + { + "FSTATE", + 0x0, // F0 state + + // Footswitch Name; Action (1 == Enable; 2 == Disable; ) + + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + // LRME clocks + package() { "CLOCK", package() { "cam_cc_lrme_clk", 1 } }, + package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS + }, + Package() + { + "FSTATE", + 0x1, // F1 state + + package() { "PSTATE_ADJUST", Package() { 0, 4 } }, + package() { "CLOCK", package() { "cam_cc_lrme_clk", 2 } }, + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + + // Clk Freq + Package() + { + "PSTATE_SET", + 0, + Package() // Turbo, NOM + { + "PSTATE", + 0, + Package(){ "CLOCK", Package(){ "cam_cc_lrme_clk", 3, 400000000, 3, }}, + }, + Package() // SVS_L1 + { + "PSTATE", + 1, + Package(){ "CLOCK", Package(){ "cam_cc_lrme_clk", 3, 320000000, 3, }}, + }, + Package() // SVS + { + "PSTATE", + 2, + Package(){ "CLOCK", Package(){ "cam_cc_lrme_clk", 3, 269000000, 3, }}, + }, + Package() // Off + { + "PSTATE", + 3, + Package(){ "CLOCK", Package(){ "cam_cc_lrme_clk", 3, 0, 3, }}, + }, + }, + }, + + + Package() + { + "COMPONENT", + 0x7, // Component 7. //FD component + Package() + { + "FSTATE", + 0x0, // F0 state + + // Footswitch Name; Action (1 == Enable; 2 == Disable; ) + package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} }, + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} }, + + package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC + + // FD clocks + Package() { "CLOCK", Package(){ "cam_cc_fd_core_clk", 1 }}, // SVS. DCVS recommendation + package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS + + }, + Package() + { + "FSTATE", + 0x1, // F1 state + + package() { "PSTATE_ADJUST", Package() { 0, 4 } }, + package() { "CLOCK", package() { "cam_cc_fd_core_clk", 2 } }, + + package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } }, + package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } }, + + Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } }, + package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } }, + package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } }, + }, + + // Clk Freq + Package() + { + "PSTATE_SET", + 0, + Package() // Turbo, NOM + { + "PSTATE", + 0, + Package(){ "CLOCK", Package(){ "cam_cc_fd_core_clk", 3, 600000000, 3, }}, + }, + Package() // SVS_L1 + { + "PSTATE", + 1, + Package(){ "CLOCK", Package(){ "cam_cc_fd_core_clk", 3, 538000000, 3, }}, + }, + Package() // SVS + { + "PSTATE", + 2, + Package(){ "CLOCK", Package(){ "cam_cc_fd_core_clk", 3, 400000000, 3, }}, + }, + Package() // Off + { + "PSTATE", + 3, + Package(){ "CLOCK", Package(){ "cam_cc_fd_core_clk", 3, 0, 3, }}, + }, + }, + }, + }, + }) +} diff --git a/sdm845Pkg/AcpiTables/fajita/wlan_11ad.asl b/sdm845Pkg/AcpiTables/fajita/wlan_11ad.asl new file mode 100755 index 0000000..b575915 --- /dev/null +++ b/sdm845Pkg/AcpiTables/fajita/wlan_11ad.asl @@ -0,0 +1,7 @@ +//WLAN_11ad driver ACPI Enumeration +//DISABLE for fajita + +Method(_STA, 0) +{ + Return (0x0) +} -- 2.45.2