From: Teguh Sobirin Date: 星期一, 26 Jul 2021 11:20:10 +0000 (+0700) Subject: Configuration follow Polaris Schematic and Linux source code X-Git-Url: https://git.renegade-project.org/?a=commitdiff_plain;h=f6dfd024c7f780c54eb5a31ba9af0df15c19241d;p=edk2-sdm845-acpi.git Configuration follow Polaris Schematic and Linux source code --- diff --git a/DSDT/common/SCM.asl b/DSDT/common/SCM.asl index 524d01b..070e776 100644 --- a/DSDT/common/SCM.asl +++ b/DSDT/common/SCM.asl @@ -11,57 +11,35 @@ Device (SCM0) // // TrEE Driver // -// Device (TREE) -// { -// Name (_HID, "QCOM02BB") -// Alias(\_SB.PSUB, _SUB) -// Name (_UID, 0) - -// Method (IMPT) -// { -// Name(TPPK, Package() -// { -// Package () -// { -// // Holds whether TPM is seperate app or not -// 0x00000000, // Will be filled by TPMA -// // Holds TPM type -// 0x00000000, // Will be filled by TDTV -// // Holds TrEE Carveout address -// 0x00000000, // Will be filled by TCMA -// // Holds TrEE Carveout length -// 0x00000000 // Will be filled by TCML -// } -// }) - -// // Copy ACPI globals for Address for this subsystem into above package for use in driver -// Store (TPMA, Index(DeRefOf(Index (TPPK, 0)), 0)) -// Store (TDTV, Index(DeRefOf(Index (TPPK, 0)), 1)) -// Store (TCMA, Index(DeRefOf(Index (TPPK, 0)), 2)) -// Store (TCML, Index(DeRefOf(Index (TPPK, 0)), 3)) - -// Return (TPPK) -// } -// } - -// HACK! Device (TREE) { - Name (_HID, "QCOM02BB") // _HID: Hardware ID - Alias (\_SB.PSUB, _SUB) - Name (_UID, Zero) // _UID: Unique ID - Method (MCGT, 0, NotSerialized) + Name (_HID, "QCOM02BB") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (IMPT) { - Name (TPKG, Package (One) + Name(TPPK, Package() { - Package (0x02) + Package () { - Zero, - Zero + // // Holds whether TPM is seperate app or not + // 0x00000000, // Will be filled by TPMA + // // Holds TPM type + // 0x00000000, // Will be filled by TDTV + // Holds TrEE Carveout address + 0x00000000, // Will be filled by TCMA + // Holds TrEE Carveout length + 0x00000000 // Will be filled by TCML } }) - DerefOf (TPKG [Zero]) [Zero] = TCMA /* \_SB_.TCMA */ - DerefOf (TPKG [Zero]) [One] = TCML /* \_SB_.TCML */ - Return (TPKG) /* \_SB_.TREE.MCGT.TPKG */ + + // Copy ACPI globals for Address for this subsystem into above package for use in driver + // Store (TPMA, Index(DeRefOf(Index (TPPK, 0)), 0)) + // Store (TDTV, Index(DeRefOf(Index (TPPK, 0)), 1)) + Store (TCMA, Index(DeRefOf(Index (TPPK, 0)), 0))//2 + Store (TCML, Index(DeRefOf(Index (TPPK, 0)), 1))//3 + + Return (TPPK) } } diff --git a/DSDT/common/corebsp_resources.asl b/DSDT/common/corebsp_resources.asl index 9b96e10..c104765 100644 --- a/DSDT/common/corebsp_resources.asl +++ b/DSDT/common/corebsp_resources.asl @@ -2476,1676 +2476,5 @@ Scope(\_SB_.PEP0) }, }, //End USB0 - //USB secondary core (Host Stack) - Package() - { - "DEVICE", - "\\_SB.USB1", - Package() - { - "COMPONENT", - 0x0, // Component 0. - Package() { "FSTATE", 0x0, }, - package() - { - "PSTATE", - 0x0, - // Enable USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, - // Mark Suppressible for USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, - // Mark Always On for USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, - //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL - // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, - // Enable PHY pipe Clock - package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, - // Mark Suppressible for USB PHY pipe Clock - package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, - }, - package() - { - "PRELOAD_PSTATE", - 0, - },// index 0 is P-state 0 here - }, - //D states - Package() - { // HOST D0 - "DSTATE", - 0x0, - //Power Grid for SDM850 - package() - { - // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L12 @1.8v - { - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1800000, // Voltage 1.8V : microvolts ( V ) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // L24 - VDDA_QUSB_HS0_3P1 - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L24 @3.075v - { - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 3075000, // Voltage = 3.075 V - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // L26 - VDDA_USB_SS_1P2 (QMP PHY) - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L26 @1.2v - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1200000, // Voltage 1.2V : microvolts ( V ) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // VDDA_USB_SS_CORE & VDDA_QUSB0_HS - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L1 @ 0.88v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 880000, // Voltage (microvolts) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - - // Enable usb30_sec_gdsc power domain - package() - { - "FOOTSWITCH", // Footswitch - package() - { - "usb30_sec_gdsc", // USB 3.0 Core Power domain - 1, //1==Enable - }, - }, - - // Now Enable all the clocks - - //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}}, - - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}}, - - // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}}, - - //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz - package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}}, - - // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz - package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, - - //Vote for max freq: BUS Arbiter Request (Type-3) - // Instantaneous BW BytesPerSec = 671088640; - // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 - package() - { - "BUSARB", - Package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1", // Master - "ICBID_SLAVE_EBI1", // Slave - 671088640, // IB=5Gbps //LowSVS - 671088640 // AB=5Gbps - } - }, - - //Nominal==block vdd_min: - package() - { - "NPARESOURCE", - Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact) - //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact) - }, - - // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) - // Required for gcc_usb_phy_cfg_ahb2phy_clk - //BUS Arbiter Request (Type-3) - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact) - //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact) - 0 // AB=0 MBps - } - }, - // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, - - // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) - package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, - - }, - package() - { // HOST D1 - "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) - 0x1, - - //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, - - // Disable USB 3.0 Master Clock 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, - - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, - - //Disable aggre_usb3_sec_axi - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, - - // Disable UTMI clk 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, - - // Remove Vote for CNOC 100 MHz - // Required for gcc_usb_phy_cfg_ahb2phy_clk - // BUS Arbiter Request (Type-3) - // Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 0, // IB=0 MBps - 0 // AB=0 MBps - } - }, - - // Disable gcc_usb_phy_cfg_ahb2phy_clk - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, - - - // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; - package() - { - "CLOCK", - package() { "gcc_usb3_sec_phy_aux_clk", 2} - }, - - - // Disable SS Phy Reference Clock (diff clock) 2 = Disable - package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, - - //BUS Arbiter Request (Type-3) - //Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1",// Master - "ICBID_SLAVE_EBI1", // Slave - 0, // IB=0 Mbps - 0 // AB=0Mbps - } - }, - - //enable vdd_min - package() - { - "NPARESOURCE", - package() { 1, "/arc/client/rail_cx", 0} - }, - - package() - { - "PMICVREGVOTE", - package() //Vote for L12 @1.8v - { - // L12 - VDDA_QUSB_HS0_1P8 - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1800000, // Voltage : microvolts ( V ) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - - package() - { - "PMICVREGVOTE", // PMICVREGVOTE resource - package() // Vote for L24 @3.075v - { - // L24 - VDDA_QUSB_HS0_3P1 - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 3075000, // Voltage = 3.075 V - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - - package() - { - // L26 is used for QMP PHY - // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L26 @1.2v - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1200000, // Voltage 1.2V : microvolts ( V ) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - // VDDA_USB_SS_CORE & VDDA_QUSB0_HS - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L1 @ 0.88v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 880000, // Voltage (microvolts) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - }, - package() - { // HOST D2 - "DSTATE", - 0x2, // Slave device disconnect (host cable is still connected) - - //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, - - // Disable USB 3.0 Master Clock 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, - - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, - - // Disable aggre_usb3_sec_axi - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, - - // Disable UTMI clk 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, - - // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; - package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, - - // Remove Vote for CNOC 100 MHz - // Required for gcc_usb_phy_cfg_ahb2phy_clk - // BUS Arbiter Request (Type-3) - // Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 0, // IB=0 MBps - 0 // AB=0 MBps - } - }, - - // Disable gcc_usb_phy_cfg_ahb2phy_clk - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, - - // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization - // No option of enabling it through ACPI - - // Disable SS Phy Reference Clock (diff clock) 2 = Disable - package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, - - // Enable usb30_sec_gdsc power domain - package() - { - "FOOTSWITCH", // Footswitch - package() - { - "usb30_sec_gdsc", // USB 3.0 Core Power domain - 1, //1==Enable - }, - }, - - //Vote for 0 freq - package() - { - "BUSARB", - Package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1", // Master - "ICBID_SLAVE_EBI1", // Slave - 0, // IB=0 Mbps - 0 // AB=0Mbps - } - }, - - //enable vdd_min - package() - { - "NPARESOURCE", - package() { 1, "/arc/client/rail_cx", 0} - }, - - //Power Grid for SDM850 - package() - { - "PMICVREGVOTE", - package() //Vote for L12 @1.8v - { - // L12 - VDDA_QUSB_HS0_1P8 - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1800000, // Voltage : microvolts ( V ) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", // PMICVREGVOTE resource - package() // Vote for L24 @3.075v - { - // L24 - VDDA_QUSB_HS0_3P1 - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 3075000, // Voltage = 3.075 V - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - // L26 is used for QMP PHY - // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L2 @1.2v - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1200000, // Voltage 1.2V : microvolts ( V ) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - // VDDA_USB_SS_CORE & VDDA_QUSB0_HS - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L1 @ 0.88v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 880000, // Voltage (microvolts) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - - }, - package() - { // HOST D3 - "DSTATE", - 0x3, // Abandon state - - //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, - - // Disable USB 3.0 Master Clock 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, - - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, - - // Disable aggre_usb3_sec_axi - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, - - // Disable UTMI clk 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, - - // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; - package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, - - // Remove Vote for CNOC 100 MHz - // Required for gcc_usb_phy_cfg_ahb2phy_clk - // BUS Arbiter Request (Type-3) - // Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 0, // IB=0 MBps - 0 // AB=0 MBps - } - }, - - // Disable gcc_usb_phy_cfg_ahb2phy_clk - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, - - - // Disable SS Phy Reference Clock (diff clock) 2 = Disable - package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, - - // Disable usb30_sec_gdsc power domain - package() - { - "FOOTSWITCH", // Footswitch - package() - { - "usb30_sec_gdsc", // USB 3.0 Core Power domain - 2, // 2==Disable - }, - }, - - //Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1",// Master - "ICBID_SLAVE_EBI1", // Slave - 0, // IB=0 Mbps - 0 // AB=0Mbps - } - }, - - //enable vdd_min - package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, - - //Power Grid for SDM850 - package() - { - "PMICVREGVOTE", // PMICVREGVOTE resource - package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 - { - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 0, // Voltage = 0 V - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", - package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 - { - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 0, // Voltage : 0 microvolts ( V ) - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2 - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 0, // Voltage 0 V : microvolts ( V ) - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS - package() // Vote for L1 @ 0 v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 0, // Voltage (microvolts) - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - }, - // Define Abandon State for USB1 (host) stack ie. Power State invoked when stack unloads/tears down - package() - { - "ABANDON_DSTATE", - 3 // Abandon D state defined as D3 - }, - }, //End USB1 - - Package() - { - "DEVICE", - "\\_SB.URS1", - Package() - { - "COMPONENT", - Zero, - Package() {"FSTATE", 0}, - Package() - { - "PSTATE", - 0, // P0 -Disable Vbus - package() - { - "PMICGPIO", - Package() - { - "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", - 1, // PMI8998 - 9, // GPIO #10: USBOTG_VBUS_EN - 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS - 0, // PM_GPIO_VIN0 - 0, // EN_AND_SOURCE_SEL, 1: LOW - 1, // PM_GPIO_OUT_BUFFER_LOW - 4, // PM_GPIO_I_SOURCE_PULL_DOWN_10uA - }, - }, - }, - Package() - { - "PSTATE", - 1, // P1 - Enable Vbus - package() - { - "PMICGPIO", - Package() - { - "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", - 1, // PMI8998 - 9, // GPIO #10: USBOTG_VBUS_EN - 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS - 0, // PM_GPIO_VIN0 - 1, // EN_AND_SOURCE_SEL, 1: HIGH - 3, // PM_GPIO_OUT_BUFFER_HIGH - 5, // PM_GPIO_I_SOURCE_PULL_NO_PULL - }, - }, - } - }, - Package() {"DSTATE", 0 }, - Package() {"DSTATE", 1 }, - Package() {"DSTATE", 2 }, - Package() {"DSTATE", 3 } - }, - - - //USB secondary core (Host Stack) - Package() - { - "DEVICE", - "\\_SB.URS1.USB1", - Package() - { - "COMPONENT", - 0x0, // Component 0. - Package() { "FSTATE", 0x0, }, - package() - { - "PSTATE", - 0x0, - // Enable USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, - // Mark Suppressible for USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, - // Mark Always On for USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, - //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL - // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, - // Enable PHY pipe Clock - package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, - // Mark Suppressible for USB PHY pipe Clock - package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, - }, - package() - { - "PRELOAD_PSTATE", - 0, - },// index 0 is P-state 0 here - }, - //D states - Package() - { // HOST D0 - "DSTATE", - 0x0, - //Power Grid for SDM850 - package() - { - // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L12 @1.8v - { - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1800000, // Voltage 1.8V : microvolts ( V ) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // L24 - VDDA_QUSB_HS0_3P1 - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L24 @3.075v - { - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 3075000, // Voltage = 3.075 V - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // L26 - VDDA_USB_SS_1P2 (QMP PHY) - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L26 @1.2v - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1200000, // Voltage 1.2V : microvolts ( V ) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // VDDA_USB_SS_CORE & VDDA_QUSB0_HS - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L1 @ 0.88v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 880000, // Voltage (microvolts) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - - // Enable usb30_sec_gdsc power domain - package() - { - "FOOTSWITCH", // Footswitch - package() - { - "usb30_sec_gdsc", // USB 3.0 Core Power domain - 1, //1==Enable - }, - }, - - // Now Enable all the clocks - - //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}}, - - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}}, - - // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}}, - - //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz - package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}}, - - // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz - package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, - - //Vote for max freq: BUS Arbiter Request (Type-3) - // Instantaneous BW BytesPerSec = 671088640; - // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 - package() - { - "BUSARB", - Package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1", // Master - "ICBID_SLAVE_EBI1", // Slave - 671088640, // IB=5Gbps //LowSVS - 671088640 // AB=5Gbps - } - }, - - //Nominal==block vdd_min: - package() - { - "NPARESOURCE", - Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact) - //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact) - }, - - // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) - // Required for gcc_usb_phy_cfg_ahb2phy_clk - //BUS Arbiter Request (Type-3) - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact) - //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact) - 0 // AB=0 MBps - } - }, - // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, - - // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) - package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, - - }, - package() - { // HOST D1 - "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) - 0x1, - - //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, - - // Disable USB 3.0 Master Clock 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, - - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, - - //Disable aggre_usb3_sec_axi - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, - - // Disable UTMI clk 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, - - // Remove Vote for CNOC 100 MHz - // Required for gcc_usb_phy_cfg_ahb2phy_clk - // BUS Arbiter Request (Type-3) - // Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 0, // IB=0 MBps - 0 // AB=0 MBps - } - }, - - // Disable gcc_usb_phy_cfg_ahb2phy_clk - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, - - - // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; - package() - { - "CLOCK", - package() { "gcc_usb3_sec_phy_aux_clk", 2} - }, - - // Disable SS Phy Reference Clock (diff clock) 2 = Disable - package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, - - //BUS Arbiter Request (Type-3) - //Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1",// Master - "ICBID_SLAVE_EBI1", // Slave - 0, // IB=0 Mbps - 0 // AB=0Mbps - } - }, - - //enable vdd_min - package() - { - "NPARESOURCE", - package() { 1, "/arc/client/rail_cx", 0} - }, - - package() - { - "PMICVREGVOTE", - package() //Vote for L12 @1.8v - { - // L12 - VDDA_QUSB_HS0_1P8 - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1800000, // Voltage : microvolts ( V ) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - - package() - { - "PMICVREGVOTE", // PMICVREGVOTE resource - package() // Vote for L24 @3.075v - { - // L24 - VDDA_QUSB_HS0_3P1 - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 3075000, // Voltage = 3.075 V - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - - package() - { - // L26 is used for QMP PHY - // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L26 @1.2v - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1200000, // Voltage 1.2V : microvolts ( V ) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - // VDDA_USB_SS_CORE & VDDA_QUSB0_HS - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L1 @ 0.88v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 880000, // Voltage (microvolts) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - }, - package() - { // HOST D2 - "DSTATE", - 0x2, // Slave device disconnect (host cable is still connected) - - //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, - - // Disable USB 3.0 Master Clock 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, - - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, - - // Disable aggre_usb3_sec_axi - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, - - // Disable UTMI clk 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, - - // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; - package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, - - // Remove Vote for CNOC 100 MHz - // Required for gcc_usb_phy_cfg_ahb2phy_clk - // BUS Arbiter Request (Type-3) - // Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 0, // IB=0 MBps - 0 // AB=0 MBps - } - }, - - // Disable gcc_usb_phy_cfg_ahb2phy_clk - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, - - // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization - // No option of enabling it through ACPI - - // Disable SS Phy Reference Clock (diff clock) 2 = Disable - package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, - - - // Enable usb30_sec_gdsc power domain - package() - { - "FOOTSWITCH", // Footswitch - package() - { - "usb30_sec_gdsc", // USB 3.0 Core Power domain - 1, //1==Enable - }, - }, - - //Vote for 0 freq - package() - { - "BUSARB", - Package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1", // Master - "ICBID_SLAVE_EBI1", // Slave - 0, // IB=0 Mbps - 0 // AB=0Mbps - } - }, - - //enable vdd_min - package() - { - "NPARESOURCE", - package() { 1, "/arc/client/rail_cx", 0} - }, - - //Power Grid for SDM850 - package() - { - "PMICVREGVOTE", - package() //Vote for L12 @1.8v - { - // L12 - VDDA_QUSB_HS0_1P8 - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1800000, // Voltage : microvolts ( V ) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", // PMICVREGVOTE resource - package() // Vote for L24 @3.075v - { - // L24 - VDDA_QUSB_HS0_3P1 - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 3075000, // Voltage = 3.075 V - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - // L26 is used for QMP PHY - // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L2 @1.2v - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1200000, // Voltage 1.2V : microvolts ( V ) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - // VDDA_USB_SS_CORE & VDDA_QUSB0_HS - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L1 @ 0.88v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 880000, // Voltage (microvolts) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - - }, - package() - { // HOST D3 - "DSTATE", - 0x3, // Abandon state - - //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, - - // Disable USB 3.0 Master Clock 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, - - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, - - // Disable aggre_usb3_sec_axi - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, - - // Disable UTMI clk 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, - - // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; - package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, - - // Remove Vote for CNOC 100 MHz - // Required for gcc_usb_phy_cfg_ahb2phy_clk - // BUS Arbiter Request (Type-3) - // Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 0, // IB=0 MBps - 0 // AB=0 MBps - } - }, - - // Disable gcc_usb_phy_cfg_ahb2phy_clk - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, - - // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization - // No option of enabling it through ACPI - - // Disable SS Phy Reference Clock (diff clock) 2 = Disable - package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, - - - // Disable usb30_sec_gdsc power domain - package() - { - "FOOTSWITCH", // Footswitch - package() - { - "usb30_sec_gdsc", // USB 3.0 Core Power domain - 2, // 2==Disable - }, - }, - - //Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1",// Master - "ICBID_SLAVE_EBI1", // Slave - 0, // IB=0 Mbps - 0 // AB=0Mbps - } - }, - - //enable vdd_min - package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, - - //Power Grid for SDM850 - package() - { - "PMICVREGVOTE", // PMICVREGVOTE resource - package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 - { - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 0, // Voltage = 0 V - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", - package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 - { - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 0, // Voltage : 0 microvolts ( V ) - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2 - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 0, // Voltage 0 V : microvolts ( V ) - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS - package() // Vote for L1 @ 0 v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 0, // Voltage (microvolts) - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - }, - // Define Abandon State for USB1 (host) stack ie. Power State invoked when stack unloads/tears down - package() - { - "ABANDON_DSTATE", - 3 // Abandon D state defined as D3 - }, - }, //End USB1 - - //************************* USB3.0 SS/HS0 core (Peripheral Secondary Stack) **************************** - // - package() - { - "DEVICE", - "\\_SB.URS1.UFN1", - package() - { - "COMPONENT", - 0x0, - // F-State placeholders - package() - { - "FSTATE", - 0x0, - }, - package() - { - "PSTATE", - 0x0, - // Enable USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, - // Mark Suppressible for USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, - // Mark Always On for USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, - - //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL - // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, - // Enable PHY pipe Clock - package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, - // Mark Suppressible for USB PHY pipe Clock - package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, - }, - package() - { - "PRELOAD_PSTATE", - 0, - },// index 0 is P-state 0 here - }, - - package() - { // PERIPH D0 - "DSTATE", - 0x0, - //Power Grid for SDM850 - package() - { - // L12 - VDDA_QUSB_HS0_1P8 - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L12 @1.8v - { - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1800000, // Voltage 1.8V : microvolts ( V ) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // L24 - VDDA_QUSB_HS0_3P1 - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L24 @ 3.075v - { - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 3075000, // Voltage = 3.075 V - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // L26 - VDDA_USB_SS_1P2 (QMP PHY) - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L2 @1.2v - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1200000, // Voltage 1.2V : microvolts ( V ) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // VDDA_USB_SS_CORE & VDDA_QUSB0_HS - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L1 @ 0.88v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 880000, // Voltage (microvolts) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - - // Enable usb30_sec_gdsc power domain - package() - { - "FOOTSWITCH", // Footswitch - package() - { - "usb30_sec_gdsc", // USB 3.0 Core Power domain - 1, //1==Enable - }, - }, - - //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}}, - - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}}, - - // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}}, - - // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz - package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, - - // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) - // Required for gcc_usb_phy_cfg_ahb2phy_clk - //BUS Arbiter Request (Type-3) - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 400000000, // IB=400 MBps - 0 // AB=0 MBps - } - }, - - // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, - - //Vote for max freq: BUS Arbiter Request (Type-3) - // Instantaneous BW BytesPerSec = 671088640; - // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 - package() - { - "BUSARB", - Package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1", // Master - "ICBID_SLAVE_EBI1", // Slave - 671088640, // IB=5Gbps - 671088640 // AB=5Gbps - } - }, - - //Nominal==block vdd_min: - package() - { - "NPARESOURCE", - Package() {1, "/arc/client/rail_cx", 256} - }, - - // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) - package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, - - }, - package() - { - // PERIPH D1: Not supported by USBFN driver - "DSTATE", //USB SS+HS suspend state - 0x1, - }, - package() - { // PERIPH D2 - "DSTATE", //USB DCP/HVDCP charger state - 0x2, - - // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS - // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, - - // Disable USB 3.0 Master Clock 2 = Disable ; - package() {"CLOCK", package() { "gcc_usb30_sec_master_clk", 2 } }, - - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, - - //Disable aggre_usb3_sec_axi - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, - - //Disable gcc_usb3_sec_phy_aux_clk - package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2}}, - - // Remove Vote for CNOC 100 MHz - // Required for gcc_usb_phy_cfg_ahb2phy_clk - // BUS Arbiter Request (Type-3) - // Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 0, // IB=0 MBps - 0 // AB=0 MBps - } - }, - - // Disable gcc_usb_phy_cfg_ahb2phy_clk - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, - - - // Disable SS Phy Reference Clock (diff clock) 2 = Disable - package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, - - - //BUS Arbiter Request (Type-3) - //Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1", // Master - "ICBID_SLAVE_EBI1", // Slave - 0, // IB=0 MBps - 0 // AB=0 MBps - } - }, - - //Nominal==block vdd_min: - package() - { - "NPARESOURCE", - package() {1, "/arc/client/rail_cx", 256} - }, - - package() - { - "PMICVREGVOTE", - package() //Vote for L12 @1.8v - { - // L12 - VDDA_QUSB_HS0_1P8 - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1800000, // Voltage : microvolts ( V ) - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", // PMICVREGVOTE resource - package() // Vote for L24 @3.075v - { - // L24 - VDDA_QUSB_HS0_3P1 - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 3075000, // Voltage = 3.075 V - 1, // SW Enable = Enable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - // L26 is used for QMP PHY - // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L2 @1.2v - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 0, // Voltage 0V : microvolts ( V ) - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - // VDDA_USB_SS_CORE & VDDA_QUSB0_HS - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L1 @ 0v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 0, // Voltage (microvolts) - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - }, - package() - { - // PERIPH D3 - "DSTATE", - 0x3, // Detach State - - //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, - - // Disable USB 3.0 Master Clock 2 = Disable - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, - - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, - - //Disable aggre_usb3_sec_axi - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, - - // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; - package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, - - // Remove Vote for CNOC 100 MHz - // Required for gcc_usb_phy_cfg_ahb2phy_clk - // BUS Arbiter Request (Type-3) - // Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 0, // IB=0 MBps - 0 // AB=0 MBps - } - }, - - // Disable gcc_usb_phy_cfg_ahb2phy_clk - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}}, - // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization - // No option of enabling it through ACPI - - // Disable SS Phy Reference Clock (diff clock) 2 = Disable - package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, - - // Disable usb30_sec_gdsc power domain - package() - { - "FOOTSWITCH", // Footswitch - package() - { - "usb30_sec_gdsc", // USB 3.0 Core Power domain - 2, // 2==Disable - }, - }, - - //Vote for 0 freq - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1",// Master - "ICBID_SLAVE_EBI1", // Slave - 0, // IB=0 MBps - 0 // AB=0 Mbps - } - }, - - //enable vdd_min - package() - { - "NPARESOURCE", - package() { 1, "/arc/client/rail_cx", 0} - }, - - package() - { - "PMICVREGVOTE", // PMICVREGVOTE resource - package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1 - { - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 0, // Voltage = 0 V - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", - package() // Vote for L12 @0V - VDDA_QUSB_HS0_1P8 - { - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 0, // Voltage : 0 microvolts ( V ) - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L2 @0v - VDDA_USB_SS_1P2 - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 0, // Voltage : 0 microvolts ( V ) - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - package() - { - "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS - package() // Vote for L1 @ 0.88v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 0, // Voltage (microvolts) - 0, // SW Enable = Disable - 5, // SW Power Mode = LPM - 0, // Head Room - }, - }, - }, - // Define Abandon State for UFN1 (peripheral) stack ie. Power State invoked when stack unloads/tears down - package() - { - "ABANDON_DSTATE", - 3 // Abandon D state defined as D3 - }, - }, //End UFN1 }) } diff --git a/DSDT/common/pep_common.asl b/DSDT/common/pep_common.asl index 3dfa039..bdcba86 100644 --- a/DSDT/common/pep_common.asl +++ b/DSDT/common/pep_common.asl @@ -459,14 +459,6 @@ Device (PEP0) // Return DPRF Return(\_SB.DPP0) } - - // This method allows PEP to read Polarity of - // eud_p1_dmse_int_mx & eud_p1_dpse_int_mx - // interrupts which belong to Secondary USB Port (P1) - Method(DMRF) { - // Return DMRF - Return(\_SB.DPP1) - } } @@ -500,5 +492,5 @@ Include("../common/ipa_resources.asl") // Include("crypto_resources.asl") Include("../common/wcnss_resources.asl") // Include("cust_wcnss_resources.asl") -Include("../common/qdss_resources.asl") +//Include("../common/qdss_resources.asl") Include("../common/pcie_resources.asl") diff --git a/DSDT/common/pep_dbgSettings.asl b/DSDT/common/pep_dbgSettings.asl index 8fe637d..39cf463 100644 --- a/DSDT/common/pep_dbgSettings.asl +++ b/DSDT/common/pep_dbgSettings.asl @@ -73,184 +73,6 @@ Scope(\_SB.PEP0) } }, - // Secondary USB Port Debugger - package() - { - "TYPE", - "USB2.0", - package() - { - "INSTANCES", - "\\_SB.USB1", - //URS1 specific - //"\\_SB.URS1", - }, - - package() - { - "DEBUG_ON", - - package() - { - // L12 - VDDA_QUSB_HS0_1P8 - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L12 @1.8v - { - "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1800000, // Voltage 1.8V : microvolts ( V ) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // L24 - VDDA_QUSB_HS0_3P1 - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L24 @ 3.075v - { - "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID - 1, // Voltage Regulator type 1 = LDO - 3075000, // Voltage = 3.075 V - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // L26 - VDDA_USB_SS_1P2 (QMP PHY) - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L2 @1.2v - { - "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 1200000, // Voltage 1.2V : microvolts ( V ) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - package() - { - // VDDA_USB_SS_CORE & VDDA_QUSB0_HS - "PMICVREGVOTE", // PMIC VREG resource - package() // Vote for L1 @ 0.88v - { - "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID - 1, // Voltage Regulator type = LDO - 880000, // Voltage (microvolts) - 1, // SW Enable = Enable - 7, // SW Power Mode = NPM - 0, // Head Room - }, - }, - // Enable usb30_sec_gdsc power domain - package() - { - "FOOTSWITCH", // Footswitch - package() - { - "usb30_sec_gdsc", // USB 3.0 Core Power domain - 1, //1==Enable - }, - }, - - // Mark Suppressible for USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, - // Mark Always On for USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, - // Enable USB 3.0 Sleep Clock - package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, - - // Mark Suppressible for USB PHY pipe Clock - package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, - // Mark Always ON for USB PHY pipe Clock - package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 12,}}, - // Enable PHY pipe Clock - package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, - - // Mark Suppressible for gcc_aggre_usb3_sec_axi_clk - package() { "CLOCK", package() { "gcc_aggre_usb3_sec_axi_clk", 9, 8,}}, - // Mark Always ON for gcc_aggre_usb3_sec_axi_clk - package() { "CLOCK", package() { "gcc_aggre_usb3_sec_axi_clk", 9, 12,}}, - //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}}, - - // Mark Suppressible for gcc_cfg_noc_usb3_sec_axi_clk - package() { "CLOCK", package() { "gcc_cfg_noc_usb3_sec_axi_clk", 9, 8,}}, - // Mark Always ON for gcc_cfg_noc_usb3_sec_axi_clk - package() { "CLOCK", package() { "gcc_cfg_noc_usb3_sec_axi_clk", 9, 12,}}, - // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock - // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}}, - - // Mark Suppressible for gcc_usb30_sec_master_clk - package() { "CLOCK", package() { "gcc_usb30_sec_master_clk", 9, 8,}}, - // Mark Always ON for gcc_usb30_sec_master_clk - package() { "CLOCK", package() { "gcc_usb30_sec_master_clk", 9, 12,}}, - // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz - package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}}, - - // Mark Suppressible for gcc_usb3_sec_phy_aux_clk - package() { "CLOCK", package() { "gcc_usb3_sec_phy_aux_clk", 9, 8,}}, - // Mark Always ON for gcc_usb3_sec_phy_aux_clk - package() { "CLOCK", package() { "gcc_usb3_sec_phy_aux_clk", 9, 12,}}, - // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz - package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, - - // Mark Suppressible for gcc_usb_phy_cfg_ahb2phy_clk - package() { "CLOCK", package() { "gcc_usb_phy_cfg_ahb2phy_clk", 9, 8,}}, - // Mark Always ON for gcc_usb_phy_cfg_ahb2phy_clk - package() { "CLOCK", package() { "gcc_usb_phy_cfg_ahb2phy_clk", 9, 12,}}, - // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC - package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}}, - - // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) - // Required for gcc_usb_phy_cfg_ahb2phy_clk - //BUS Arbiter Request (Type-3) - package() - { - "BUSARB", - package() - { - 3, // Req Type - "ICBID_MASTER_APPSS_PROC", // Master - "ICBID_SLAVE_USB3_1", // Slave - 400000000, // IB=400 MBps - 0, // AB=0 MBps - "HLOS_DRV", // Optional: DRV Id - "SUPPRESSIBLE", // Optional: Set Type - } - }, - - //Vote for max freq: BUS Arbiter Request (Type-3) - // Instantaneous BW BytesPerSec = 671088640; - // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 - package() - { - "BUSARB", - Package() - { - 3, // Req Type - "ICBID_MASTER_USB3_1", // Master - "ICBID_SLAVE_EBI1", // Slave - 671088640, // IB=5Gbps - 671088640, // AB=5Gbps - "HLOS_DRV", // Optional: DRV Id - "SUPPRESSIBLE", // Optional: Set Type - } - }, - - //Nominal==block vdd_min: - package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}}, - }, - package() - { - "DEBUG_OFF", - } - }, package() { diff --git a/DSDT/iasl.exe b/DSDT/iasl.exe new file mode 100644 index 0000000..0b7e69d Binary files /dev/null and b/DSDT/iasl.exe differ diff --git a/DSDT/polaris/buses.asl b/DSDT/polaris/buses.asl index fd1e11b..2cceae8 100644 --- a/DSDT/polaris/buses.asl +++ b/DSDT/polaris/buses.asl @@ -58,94 +58,91 @@ Device (UAR7) // // I2C4 - "Core I2C Bus" // -// Device (I2C4) -// { -// Name (_HID, "QCOM0220") -// Alias(\_SB.PSUB, _SUB) -// Name (_UID, 4) -// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) -// Name (_CCA, 0) - -// Method (_CRS, 0x0, NotSerialized) -// { -// Name (RBUF, ResourceTemplate () -// { -// Memory32Fixed (ReadWrite, 0x0088C000, 0x00004000) -// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {636} -// }) -// Return (RBUF) -// } -// } +Device (I2C4) +{ + Name (_HID, "QCOM0220") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 4) + Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0088C000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {636} + }) + Return (RBUF) + } +} // -// I2C5 - "Core I2C Bus" +// I2C6 - "Core I2C Bus" // -// Device (I2C6) -// { -// Name (_HID, "QCOM0220") -// Alias(\_SB.PSUB, _SUB) -// Name (_UID, 6) -// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) -// Name (_CCA, 0) - -// Method (_CRS, 0x0, NotSerialized) -// { -// Name (RBUF, ResourceTemplate () -// { -// Memory32Fixed (ReadWrite, 0x894000, 0x00004000) -// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {638} -// }) -// Return (RBUF) -// } -// } +Device (I2C6) +{ + Name (_HID, "QCOM0220") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 6) + Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x894000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {638} + }) + Return (RBUF) + } +} // // I2C11 - "Core I2C Bus" // -// Device (IC11) -// { -// Name (_HID, "QCOM0220") -// Alias(\_SB.PSUB, _SUB) -// Name (_UID, 11) -// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) -// Name (_CCA, 0) - -// Method (_CRS, 0x0, NotSerialized) -// { -// Name (RBUF, ResourceTemplate () -// { -// Memory32Fixed (ReadWrite, 0x00A88000, 0x00004000) -// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {387} -// }) -// Return (RBUF) -// } -// } +Device (IC11) +{ + Name (_HID, "QCOM0220") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 11) + Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00A88000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {387} + }) + Return (RBUF) + } +} // // I2C15 - "Core I2C Bus" // -//Device (IC15) -//{ -// Name (_HID, "QCOM0220") -// Name (_UID, 15) -// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) -// Name (_CCA, 0) - -// Method (_CRS, 0x0, NotSerialized) -// { -// Name (RBUF, ResourceTemplate () -// { -// Memory32Fixed (ReadWrite, 0x00A98000, 0x00004000) -// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {391} -// }) -// Return (RBUF) -// } -//} - +Device (IC15) +{ + Name (_HID, "QCOM0220") + Name (_UID, 15) + Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00A98000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {391} + }) + Return (RBUF) + } +} //SPI9 - EPM - Device (SPI9) { Name (_HID, "QCOM021E") @@ -500,60 +497,61 @@ Scope(\_SB_.PEP0) }, // "\\_SB.IC15" - //Package() - //{ - //"DEVICE", - //"\\_SB.IC15", - //Package() - //{ - //"COMPONENT", - //0x0, // Component 0. - //Package() - //{ - //"FSTATE", - //0x0, // f0 state - //}, - //}, - //Package() - //{ - //"DSTATE", - //0x0, // D0 state - //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}}, - //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}}, - //Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",8,19200000, 4}}, - //Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666 }}, - //Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000 }}, - - // Configure SDA and then SCL - //package() {"TLMMGPIO", package() {33, 1, 1, 1, 3, 0}}, - //package() {"TLMMGPIO", package() {34, 1, 1, 1, 3, 0}}, - //}, - //Package() - //{ - //"DSTATE", - //0x1, // D1 state - //}, - //Package() - //{ - //"DSTATE", - //0x2, // D2 state - //}, - //Package() - //{ - //"DSTATE", - //0x3, // D3 state - //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}}, - //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}}, - //Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",2}}, - //Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0 }}, - //Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0 }}, - - // Configure SCL and then SDA - //package() { "TLMMGPIO", package() {33, 0, 0, 0, 3, 0}}, - // package() { "TLMMGPIO", package() {34, 0, 0, 0, 3, 0}}, - //}, - //}, - }) + Package() + { + "DEVICE", + "\\_SB.IC15", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",8,19200000, 4}}, + Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666 }}, + Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000 }}, + + // Configure SDA and then SCL + package() {"TLMMGPIO", package() {33, 1, 1, 1, 3, 0}}, + package() {"TLMMGPIO", package() {34, 1, 1, 1, 3, 0}}, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",2}}, + Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0 }}, + Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0 }}, + + // Configure SCL and then SDA + package() { "TLMMGPIO", package() {33, 0, 0, 0, 3, 0}}, + package() { "TLMMGPIO", package() {34, 0, 0, 0, 3, 0}}, + }, + }, + } + ) Name(DFS1, Package() { diff --git a/DSDT/polaris/cust_arraybutton.asl b/DSDT/polaris/cust_arraybutton.asl index 515e7a1..44963a9 100644 --- a/DSDT/polaris/cust_arraybutton.asl +++ b/DSDT/polaris/cust_arraybutton.asl @@ -17,10 +17,10 @@ Device (BTNS) GpioInt(Edge, ActiveBoth, Exclusive, PullDown, 0, "\\_SB.PM01", ,) {1} // 0x41 - PM_INT__PON__RESIN_ON // Camera Focus - GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {135} // 0x638 - PM_INT__PM1_GPIO8__GPIO_IN_STS + //GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {135} // 0x638 - PM_INT__PM1_GPIO8__GPIO_IN_STS //Camera Snapshot - GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {134} // 0x630 - PM_INT__PM1_GPIO7__GPIO_IN_STS + //GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {134} // 0x630 - PM_INT__PM1_GPIO7__GPIO_IN_STS }) Return (RBUF) } diff --git a/DSDT/polaris/cust_touch.asl b/DSDT/polaris/cust_touch.asl index e3217b4..97a54b0 100644 --- a/DSDT/polaris/cust_touch.asl +++ b/DSDT/polaris/cust_touch.asl @@ -1,25 +1,56 @@ -//Improve Touch Driver, no it's not for polaris -Device (TSC5) +Device (TSC1) { - Name (_HID, "QCOM02F5") - Alias(\_SB.PSUB, _SUB) - Name (_UID, 1) - Name(_DEP, Package() + Name (_HID, "QCOM022A") + Name (_UID, 1) + Name (_DEP, Package() + { + \_SB.GIO0, + \_SB.IC15, + \_SB.PEP0, + }) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + I2CSerialBus( 0x20, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.IC15",,,,) + GpioInt(Level, ActiveLow, Exclusive, PullUp, 0, "\\_SB.GIO0", ,) {125} + }) + Return (RBUF) + } + + //PEP Proxy Support + Name(PGID, Buffer(10) {"\\_SB.TSC1"}) // Device ID buffer - PGID( Pep given ID ) + + Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID( Pep given ID ) + CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE + // HIDDEN 1 BYTE ( SIZE ) + CreateByteField(DBUF, 2, DVAL ) // Packet value, 1 BYTES Device Status + CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES(160 Bits) + + Method (_S1D, 0) { Return (3) } // S1 => D3 + Method (_S2D, 0) { Return (3) } // S2 => D3 + Method (_S3D, 0) { Return (3) } // S3 => D3 + + Method(_PS0, 0x0, NotSerialized) + { + Store(Buffer(ESNL){}, DEID) + Store(0, DVAL) + Store(PGID, DEID) + If(\_SB.ABD.AVBL) + { + Store(DBUF, \_SB.PEP0.FLD0) + } + } + + Method(_PS3, 0x0, NotSerialized) + { + Store(Buffer(ESNL){}, DEID) + Store(3, DVAL) + Store(PGID, DEID) + If(\_SB.ABD.AVBL) { - \_SB_.ARPC - }) - - //Disable Touch for V1s to support new SLPI - Method(_STA, 0) - { - - If(Lequal(\_SB_.SVMJ, 1)) - { - return (0x0) - } - Else - { - return (0xFF) - } - } + Store(DBUF, \_SB.PEP0.FLD0) + } + } } diff --git a/DSDT/polaris/cust_touch_resources.asl b/DSDT/polaris/cust_touch_resources.asl index 0ee6527..ffee5e9 100644 --- a/DSDT/polaris/cust_touch_resources.asl +++ b/DSDT/polaris/cust_touch_resources.asl @@ -15,6 +15,173 @@ Scope(\_SB_.PEP0) Name(LPXC, Package(){ - + // Touch LVS1 + Package() + { + "DEVICE", + "\\_SB.TSC1", + Package() + { + "DSTATE", + 0x0, // D0 state + + // TS_INT configuration + Package() + { + "TLMMGPIO", // TLMMGPIO resource TS_INT + Package() + { + 125, // PIN number = 125 + 0, // State: NOT active = 0x0 + 0, // Function select = 0 + 0, // direction = Input. + 3, // Pull Up + 0, // Drive Strength: 0x0 = 2mA + }, + }, + Package() + { + "TLMMGPIO", // TLMMGPIO resource RESET + Package() + { + 99, // PIN number = 99 + 0, // State: NOT active = 0x0 + 0, // Function select = 0 + 1, // direction = Output. + 0, // NO Pull + 0, // Drive Strength: 0x0 = 2mA + }, + }, + + // Synaptics Power source - VDD + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO28_A", // VREG ID + 1, // Voltage Regulator type = LDO + 3300000, // 3.3V + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // I2C Pull Up source + Package() + { + "TLMMGPIO", + Package() + { + 23, // PIN number = 23 + 1, // State: active = 0x1 + 0, // Function select = 0 + 1, // direction = Output. + 3, // Pull Up + 0, // Drive Strength: 0x0 = 2mA + }, + }, + + Package() + { + "DELAY", // Hold the RESET line LOW after power up for 2ms + Package() + { + 1000, // 2 Milsec delay + } + }, + + // Drive RESET Line High + Package() + { + "TLMMGPIO", // TLMMGPIO resource TS_RESET + Package() + { + 99, // PIN number = 99 + 1, // State: active = 0x1 + 0, // Function select = 0 + 1, // direction = O/P + 0, // Pull Up + 0, // Drive Strength: 0x0 = 2mA + }, + }, + + // Synaptics may need needs ~200 ms to be ready for comm + Package() + { + "DELAY", + Package() + { + 20000, // 200 Milsec delay + } + }, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + // Synaptics Power source - VDD + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO28_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // Force disable from s/w + 5, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + // I2C Pull Up source + Package() + { + "TLMMGPIO", + Package() + { + 23, // PIN number = 23 + 0, // State: IN active = 0x0 + 0, // Function select = 0 + 1, // direction = Output. + 1, // Pull Down + 0, // Drive Strength: 0x0 = 2mA + }, + }, + + // RESET pin - power save mode + Package() + { + "TLMMGPIO", // TLMMGPIO resource RESET + Package() + { + 99, // PIN number = 99 + 0, // State: IN active = 0x0 + 0, // Function select = 0 + 0, // direction = Output. + 1, // Pull Down + 0, // Drive Strength: 0x0 = 2mA + }, + }, + + // TS_INT configuration - power save mode + Package() + { + "TLMMGPIO", // TLMMGPIO resource TS_INT + Package() + { + 125, // PIN number = 125 + 0, // State: IN active = 0x0 + 0, // Function select = 0 + 0, // direction = Input. + 1, // Pull Down + 0, // Drive Strength: 0x0 = 2mA + }, + }, + }, + }, }) } diff --git a/DSDT/polaris/display.asl b/DSDT/polaris/display.asl index 2c290a2..95d2494 100644 --- a/DSDT/polaris/display.asl +++ b/DSDT/polaris/display.asl @@ -18,30 +18,15 @@ Method (_ROM, 3, NotSerialized) { //====================================================================================== Switch ( ToInteger (Arg2) ) { - // Truly WQHD Dual DSI Command Mode - Case (0x008010) { + // Sharp WQHD Video Mode + Case (0x008000) { Store (PCFG, Local2) } - // Truly WQHD Dual DSI Video Mode - Case (0x008011) { - Store (PCF1, Local2) - } - // Truly WQHD Single DSI DSC Command Mode - Case (0x008012) { - Store (PCF2, Local2) - } - // Truly WQHD Single DSI DSC Video Mode - Case (0x008013) { - Store (PCF3, Local2) - } - // 4k Dual DSC Sharp Command Mode - Case (0x00008000) { - Store (PCF4, Local2) - } - // 4k Dual DSC Sharp Video Mode - Case (0x00008056) { - Store (PCF5, Local2) - } + // Sharp WQHD Command Mode + //Case (0x008000) { + // Store (PCF1, Local2) + //} + // All others Default { Store (PCFG, Local2) diff --git a/DSDT/polaris/dsdt_common.asl b/DSDT/polaris/dsdt_common.asl index 111dd19..6ecd660 100644 --- a/DSDT/polaris/dsdt_common.asl +++ b/DSDT/polaris/dsdt_common.asl @@ -153,7 +153,7 @@ Include("../common/adsprpc.asl") Include("../common/gps.asl") // QDSS driver - Include("../common/Qdss.asl") + //Include("../common/Qdss.asl") // QUPV3 GPI device node and resources // diff --git a/DSDT/polaris/graphics.asl b/DSDT/polaris/graphics.asl index f222341..3d34856 100644 --- a/DSDT/polaris/graphics.asl +++ b/DSDT/polaris/graphics.asl @@ -107,13 +107,13 @@ Device (GPU0) // GpioIo(Exclusive, PullUp, 0, 0, , "\\_SB.GIO0", ,) {6} - // TLMM GPIO used to select DSI panel mode - // - GpioIo(Exclusive, PullUp, 0, 0, , "\\_SB.GIO0", ,) {52} + // // TLMM GPIO used to select DSI panel mode + // // + // GpioIo(Exclusive, PullUp, 0, 0, , "\\_SB.GIO0", ,) {52} - // TLMM GPIO used to DP AUX polarity select - // - GpioIo(Shared, PullUp, 0, 0, , "\\_SB.GIO0", ,) {51} + // // TLMM GPIO used to DP AUX polarity select + // // + // GpioIo(Shared, PullUp, 0, 0, , "\\_SB.GIO0", ,) {51} }) Return (RBUF) } @@ -258,23 +258,23 @@ Device (GPU0) "DISPLAY", // Owning Component }, - // TLMM GPIO used to select DSI panel mode - // - Package() - { - "RESOURCE", - "DSI_PANEL_MODE_SELECT", // Resource Name - "DISPLAY", // Owning Component - }, - - // TLMM GPIO used to DP AUX polarity select - // - Package() - { - "RESOURCE", - "DP_AUX", // Resource Name - "DISPLAY", // Owning Component - }, + // // TLMM GPIO used to select DSI panel mode + // // + // Package() + // { + // "RESOURCE", + // "DSI_PANEL_MODE_SELECT", // Resource Name + // "DISPLAY", // Owning Component + // }, + + // // TLMM GPIO used to DP AUX polarity select + // // + // Package() + // { + // "RESOURCE", + // "DP_AUX", // Resource Name + // "DISPLAY", // Owning Component + // }, }) Return (RINF) diff --git a/DSDT/polaris/panelcfg.asl b/DSDT/polaris/panelcfg.asl index e2e8e41..49ebab2 100644 --- a/DSDT/polaris/panelcfg.asl +++ b/DSDT/polaris/panelcfg.asl @@ -1,2096 +1,316 @@ Name (PCFG, - Buffer() {" -TFT2P2827-E -Truly Dual DSI Command Mode Panel (1440x2560 24bpp) - - 0x104D - 850 - 0x000001 - 0x01 - 0x1B - 1 - 3 - 0x80 - 0x07 - 0x0C - 0x78 - 0x2 - 0xC8 - 0xC0 - 0xA6 - 0x51 - 0x4B - 0x9E - 0x25 - 0x0E - 0x48 - 0x4B - 0x0 - 0x0 - 0x0 - - - - - - - - - - - 0x44 - 0x78 - 0x00 - - - 1440 - 100 - 32 - 16 - 0 - 0 - 0 - 2560 - 8 - 7 - 1 - 0 - 0 - 0 - False - False - False - 0x0 - - - 9 - 3 - - - 2 - 0 - 36 - 1 - 4 - 0x3C0000 - False - False - True - 1 - 120 - 1 - False - True - 0 - 2400 - - 00 01 - - - - 15 FF 20 - 15 fb 01 - 15 00 01 - 15 01 55 - 15 02 45 - 15 05 40 - 15 06 19 - 15 07 1E - 15 0B 73 - 15 0C 73 - 15 0E B0 - 15 0F AE - 15 11 B8 - 15 13 00 - 15 58 80 - 15 59 01 - 15 5A 00 - 15 5B 01 - 15 5C 80 - 15 5D 81 - 15 5E 00 - 15 5F 01 - 15 72 31 - 15 68 03 - 15 ff 24 - 15 fb 01 - 15 00 1C - 15 01 0B - 15 02 0C - 15 03 01 - 15 04 0F - 15 05 10 - 15 06 10 - 15 07 10 - 15 08 89 - 15 09 8A - 15 0A 13 - 15 0B 13 - 15 0C 15 - 15 0D 15 - 15 0E 17 - 15 0F 17 - 15 10 1C - 15 11 0B - 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