From: Marijan Limov Date: 星期天, 11 Oct 2020 16:54:31 +0000 (+0200) Subject: Added support for beryllium X-Git-Tag: v0.2~36^2~1 X-Git-Url: https://git.renegade-project.org/?a=commitdiff_plain;h=cd7a0dcb11699a4c834c1fcf274f413bc947613e;p=edk2-sdm845.git Added support for beryllium --- diff --git a/build.sh b/build.sh index 9af4472..9719825 100755 --- a/build.sh +++ b/build.sh @@ -6,6 +6,7 @@ DEVICES=( fajita polaris akari + beryllium ) ##################################### function _help(){ @@ -22,7 +23,7 @@ function _help(){ } cd "$(dirname "$0")" if ! [ -f sdm845Pkg/sdm845Pkg.dsc ] -then echo "cannot found sdm845Pkg/sdm845Pkg.dsc" >&2 +then echo "cannot find sdm845Pkg/sdm845Pkg.dsc" >&2 exit 1 fi typeset -l DEVICE diff --git a/device_specific/beryllium.dtb b/device_specific/beryllium.dtb new file mode 100755 index 0000000..f000413 Binary files /dev/null and b/device_specific/beryllium.dtb differ diff --git a/device_specific/beryllium.dts b/device_specific/beryllium.dts new file mode 100755 index 0000000..574c4e6 --- /dev/null +++ b/device_specific/beryllium.dts @@ -0,0 +1,25121 @@ +/dts-v1/; + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Xiaomi Technologies, Inc. Beryllium MP v2.1"; + compatible = "qcom,sdm845-mtp\0qcom,sdm845\0qcom,mtp"; + qcom,msm-id = <0x141 0x20001>; + interrupt-parent = <0x01>; + qcom,board-id = <0x45 0x00>; + + cpus { + #address-cells = <0x02>; + #size-cells = <0x00>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x00 0x00>; + enable-method = "psci"; + efficiency = <0x400>; + cache-size = <0x8000>; + cpu-release-addr = <0x00 0x90000000>; + qcom,lmh-dcvs = <0x02>; + #cooling-cells = <0x02>; + next-level-cache = <0x03>; + sched-energy-costs = <0x04 0x05>; + phandle = <0x11>; + + l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <0x02>; + next-level-cache = <0x06>; + phandle = <0x03>; + + l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x200000>; + cache-level = <0x03>; + phandle = <0x06>; + }; + }; + + l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + phandle = <0x119>; + }; + + l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + phandle = <0x121>; + }; + + l1-tlb { + qcom,dump-size = <0x6000>; + phandle = <0x12d>; + }; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x00 0x100>; + enable-method = "psci"; + efficiency = <0x400>; + cache-size = <0x8000>; + cpu-release-addr = <0x00 0x90000000>; + qcom,lmh-dcvs = <0x02>; + #cooling-cells = <0x02>; + next-level-cache = <0x07>; + sched-energy-costs = <0x04 0x05>; + phandle = <0x12>; + + l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <0x02>; + next-level-cache = <0x06>; + phandle = <0x07>; + }; + + l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + phandle = <0x11a>; + }; + + l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + phandle = <0x122>; + }; + + l1-tlb { + qcom,dump-size = <0x6000>; + phandle = <0x12e>; + }; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x00 0x200>; + enable-method = "psci"; + efficiency = <0x400>; + cache-size = <0x8000>; + cpu-release-addr = <0x00 0x90000000>; + qcom,lmh-dcvs = <0x02>; + #cooling-cells = <0x02>; + next-level-cache = <0x08>; + sched-energy-costs = <0x04 0x05>; + phandle = <0x13>; + + l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <0x02>; + next-level-cache = <0x06>; + phandle = <0x08>; + }; + + l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + phandle = <0x11b>; + }; + + l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + phandle = <0x123>; + }; + + l1-tlb { + qcom,dump-size = <0x6000>; + phandle = <0x12f>; + }; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x00 0x300>; + enable-method = "psci"; + efficiency = <0x400>; + cache-size = <0x8000>; + cpu-release-addr = <0x00 0x90000000>; + qcom,lmh-dcvs = <0x02>; + #cooling-cells = <0x02>; + next-level-cache = <0x09>; + sched-energy-costs = <0x04 0x05>; + phandle = <0x14>; + + l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <0x02>; + next-level-cache = <0x06>; + phandle = <0x09>; + }; + + l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + phandle = <0x11c>; + }; + + l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + phandle = <0x124>; + }; + + l1-tlb { + qcom,dump-size = <0x6000>; + phandle = <0x130>; + }; + }; + + cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x00 0x400>; + enable-method = "psci"; + efficiency = <0x6cc>; + cache-size = <0x20000>; + cpu-release-addr = <0x00 0x90000000>; + qcom,lmh-dcvs = <0x0a>; + #cooling-cells = <0x02>; + next-level-cache = <0x0b>; + sched-energy-costs = <0x0c 0x0d>; + phandle = <0x15>; + + l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <0x02>; + next-level-cache = <0x06>; + phandle = <0x0b>; + }; + + l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x24000>; + phandle = <0x11d>; + }; + + l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + phandle = <0x125>; + }; + + l1-tlb { + qcom,dump-size = <0x6800>; + phandle = <0x131>; + }; + }; + + cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x00 0x500>; + enable-method = "psci"; + efficiency = <0x6cc>; + cache-size = <0x20000>; + cpu-release-addr = <0x00 0x90000000>; + qcom,lmh-dcvs = <0x0a>; + #cooling-cells = <0x02>; + next-level-cache = <0x0e>; + sched-energy-costs = <0x0c 0x0d>; + phandle = <0x16>; + + l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <0x02>; + next-level-cache = <0x06>; + phandle = <0x0e>; + }; + + l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x24000>; + phandle = <0x11e>; + }; + + l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + phandle = <0x126>; + }; + + l1-tlb { + qcom,dump-size = <0x6800>; + phandle = <0x132>; + }; + }; + + cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x00 0x600>; + enable-method = "psci"; + efficiency = <0x6cc>; + cache-size = <0x20000>; + cpu-release-addr = <0x00 0x90000000>; + qcom,lmh-dcvs = <0x0a>; + #cooling-cells = <0x02>; + next-level-cache = <0x0f>; + sched-energy-costs = <0x0c 0x0d>; + phandle = <0x17>; + + l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <0x02>; + next-level-cache = <0x06>; + phandle = <0x0f>; + }; + + l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x24000>; + phandle = <0x11f>; + }; + + l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + phandle = <0x127>; + }; + + l1-tlb { + qcom,dump-size = <0x6800>; + phandle = <0x133>; + }; + }; + + cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x00 0x700>; + enable-method = "psci"; + efficiency = <0x6cc>; + cache-size = <0x20000>; + cpu-release-addr = <0x00 0x90000000>; + qcom,lmh-dcvs = <0x0a>; + #cooling-cells = <0x02>; + next-level-cache = <0x10>; + sched-energy-costs = <0x0c 0x0d>; + phandle = <0x18>; + + l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <0x02>; + next-level-cache = <0x06>; + phandle = <0x10>; + }; + + l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x24000>; + phandle = <0x120>; + }; + + l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + phandle = <0x128>; + }; + + l1-tlb { + qcom,dump-size = <0x6800>; + phandle = <0x134>; + }; + }; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x11>; + }; + + core1 { + cpu = <0x12>; + }; + + core2 { + cpu = <0x13>; + }; + + core3 { + cpu = <0x14>; + }; + }; + + cluster1 { + + core0 { + cpu = <0x15>; + }; + + core1 { + cpu = <0x16>; + }; + + core2 { + cpu = <0x17>; + }; + + core3 { + cpu = <0x18>; + }; + }; + }; + }; + + soc { + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0x00 0xffffffff>; + compatible = "simple-bus"; + + qcom,gdsc@0x16b004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_0_gdsc"; + reg = <0x16b004 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + phandle = <0x2de>; + }; + + qcom,gdsc@0x18d004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_1_gdsc"; + reg = <0x18d004 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + phandle = <0x2e3>; + }; + + qcom,gdsc@0x175004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_card_gdsc"; + reg = <0x175004 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + }; + + qcom,gdsc@0x177004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_phy_gdsc"; + reg = <0x177004 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + phandle = <0xd9>; + }; + + qcom,gdsc@0x10f004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_prim_gdsc"; + reg = <0x10f004 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + phandle = <0x338>; + }; + + qcom,gdsc@0x110004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_sec_gdsc"; + reg = <0x110004 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + phandle = <0x33e>; + }; + + qcom,gdsc@0x17d030 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; + reg = <0x17d030 0x04>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <0x1f4>; + status = "ok"; + phandle = <0x203>; + }; + + qcom,gdsc@0x17d03c { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; + reg = <0x17d03c 0x04>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <0x1f4>; + status = "ok"; + phandle = <0x204>; + }; + + qcom,gdsc@0x17d034 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; + reg = <0x17d034 0x04>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <0x1f4>; + status = "ok"; + phandle = <0x1fe>; + }; + + qcom,gdsc@0x17d038 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; + reg = <0x17d038 0x04>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <0x1f4>; + status = "ok"; + phandle = <0x1ff>; + }; + + qcom,gdsc@0x17d040 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + reg = <0x17d040 0x04>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <0x1f4>; + status = "ok"; + phandle = <0x200>; + }; + + qcom,gdsc@0x17d048 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + reg = <0x17d048 0x04>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <0x1f4>; + status = "ok"; + phandle = <0x201>; + }; + + qcom,gdsc@0x17d044 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + reg = <0x17d044 0x04>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <0x1f4>; + status = "ok"; + phandle = <0x202>; + }; + + qcom,gdsc@0xad06004 { + compatible = "qcom,gdsc"; + regulator-name = "bps_gdsc"; + reg = <0xad06004 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + qcom,support-hw-trigger; + phandle = <0x23e>; + }; + + qcom,gdsc@0xad09004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_0_gdsc"; + reg = <0xad09004 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + phandle = <0x23a>; + }; + + qcom,gdsc@0xad0a004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_1_gdsc"; + reg = <0xad0a004 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + phandle = <0x23b>; + }; + + qcom,gdsc@0xad07004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_0_gdsc"; + reg = <0xad07004 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + qcom,support-hw-trigger; + phandle = <0x23c>; + }; + + qcom,gdsc@0xad08004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_1_gdsc"; + reg = <0xad08004 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + qcom,support-hw-trigger; + phandle = <0x23d>; + }; + + qcom,gdsc@0xad0b134 { + compatible = "qcom,gdsc"; + regulator-name = "titan_top_gdsc"; + reg = <0xad0b134 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + phandle = <0x215>; + }; + + qcom,gdsc@0xaf03000 { + compatible = "qcom,gdsc"; + regulator-name = "mdss_core_gdsc"; + reg = <0xaf03000 0x04>; + qcom,poll-cfg-gdscr; + qcom,support-hw-trigger; + status = "ok"; + proxy-supply = <0x19>; + qcom,proxy-consumer-enable; + qcom,en-few-wait-val = <0x06>; + qcom,en-rest-wait-val = <0x05>; + phandle = <0x19>; + }; + + syscon@0x5091540 { + compatible = "syscon"; + reg = <0x5091540 0x04>; + phandle = <0x1a>; + }; + + qcom,gdsc@0x509106c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_cx_gdsc"; + reg = <0x509106c 0x04>; + hw-ctrl-addr = <0x1a>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <0x1f4>; + qcom,clk-dis-wait-val = <0x08>; + status = "ok"; + parent-supply = <0x1b>; + vdd_parent-supply = <0x1b>; + phandle = <0x1fd>; + }; + + qcom,gdsc@0x509100c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_gx_gdsc"; + reg = <0x509100c 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + clock-names = "core_root_clk"; + clocks = <0x1c 0x02>; + qcom,force-enable-root-clk; + parent-supply = <0x1d>; + domain-addr = <0x1e>; + sw-reset = <0x1f>; + qcom,reset-aon-logic; + phandle = <0x335>; + }; + + qcom,gdsc@0xab00874 { + compatible = "qcom,gdsc"; + regulator-name = "vcodec0_gdsc"; + reg = <0xab00874 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + qcom,support-hw-trigger; + phandle = <0x2d9>; + }; + + qcom,gdsc@0xab008b4 { + compatible = "qcom,gdsc"; + regulator-name = "vcodec1_gdsc"; + reg = <0xab008b4 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + qcom,support-hw-trigger; + phandle = <0x2da>; + }; + + qcom,gdsc@0xab00814 { + compatible = "qcom,gdsc"; + regulator-name = "venus_gdsc"; + reg = <0xab00814 0x04>; + qcom,poll-cfg-gdscr; + status = "ok"; + phandle = <0x117>; + }; + + qcom,mdss_dsi_pll@ae94a00 { + compatible = "qcom,mdss_dsi_pll_10nm"; + label = "MDSS DSI 0 PLL"; + cell-index = <0x00>; + #clock-cells = <0x01>; + reg = <0xae94a00 0x1e0 0xae94400 0x800 0xaf03000 0x08>; + reg-names = "pll_base\0phy_base\0gdsc_base"; + clocks = <0x20 0x00>; + clock-names = "iface_clk"; + clock-rate = <0x00>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + gdsc-supply = <0x19>; + phandle = <0x345>; + + qcom,platform-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,platform-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0x00>; + qcom,supply-max-voltage = <0x00>; + qcom,supply-enable-load = <0x00>; + qcom,supply-disable-load = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_pll@ae96a00 { + compatible = "qcom,mdss_dsi_pll_10nm"; + label = "MDSS DSI 1 PLL"; + cell-index = <0x01>; + #clock-cells = <0x01>; + reg = <0xae96a00 0x1e0 0xae96400 0x800 0xaf03000 0x08>; + reg-names = "pll_base\0phy_base\0gdsc_base"; + clocks = <0x20 0x00>; + clock-names = "iface_clk"; + clock-rate = <0x00>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + gdsc-supply = <0x19>; + phandle = <0x350>; + + qcom,platform-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,platform-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0x00>; + qcom,supply-max-voltage = <0x00>; + qcom,supply-enable-load = <0x00>; + qcom,supply-disable-load = <0x00>; + }; + }; + }; + + qcom,mdss_dp_pll@c011000 { + compatible = "qcom,mdss_dp_pll_10nm"; + label = "MDSS DP PLL"; + cell-index = <0x00>; + #clock-cells = <0x01>; + reg = <0x88ea000 0x200 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0xaf03000 0x08>; + reg-names = "pll_base\0phy_base\0ln_tx0_base\0ln_tx1_base\0gdsc_base"; + gdsc-supply = <0x19>; + clocks = <0x20 0x00 0x21 0x00 0x22 0x9f 0x22 0xa9 0x22 0xa3>; + clock-names = "iface_clk\0ref_clk_src\0ref_clk\0cfg_ahb_clk\0pipe_clk"; + clock-rate = <0x00>; + phandle = <0x35>; + + qcom,platform-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,platform-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0x00>; + qcom,supply-max-voltage = <0x00>; + qcom,supply-enable-load = <0x00>; + qcom,supply-disable-load = <0x00>; + }; + }; + }; + + qcom,smp2pgpio-rdbg-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <0x02>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x23>; + }; + + qcom,smp2pgpio_client_rdbg_2_in { + compatible = "qcom,smp2pgpio_client_rdbg_2_in"; + gpios = <0x23 0x00 0x00>; + }; + + qcom,smp2pgpio-rdbg-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <0x02>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x24>; + }; + + qcom,smp2pgpio_client_rdbg_2_out { + compatible = "qcom,smp2pgpio_client_rdbg_2_out"; + gpios = <0x24 0x00 0x00>; + }; + + qcom,smp2pgpio-rdbg-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <0x01>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x25>; + }; + + qcom,smp2pgpio_client_rdbg_1_in { + compatible = "qcom,smp2pgpio_client_rdbg_1_in"; + gpios = <0x25 0x00 0x00>; + }; + + qcom,smp2pgpio-rdbg-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <0x01>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x26>; + }; + + qcom,smp2pgpio_client_rdbg_1_out { + compatible = "qcom,smp2pgpio_client_rdbg_1_out"; + gpios = <0x26 0x00 0x00>; + }; + + qcom,smp2pgpio-rdbg-5-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <0x05>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x27>; + }; + + qcom,smp2pgpio_client_rdbg_5_in { + compatible = "qcom,smp2pgpio_client_rdbg_5_in"; + gpios = <0x27 0x00 0x00>; + }; + + qcom,smp2pgpio-rdbg-5-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <0x05>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x28>; + }; + + qcom,smp2pgpio_client_rdbg_5_out { + compatible = "qcom,smp2pgpio_client_rdbg_5_out"; + gpios = <0x28 0x00 0x00>; + }; + + qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0xae00000 0x81d40 0xaeb0000 0x2008 0xaeac000 0xf0>; + reg-names = "mdp_phys\0vbif_phys\0regdma_phys"; + clocks = <0x22 0x1b 0x22 0x1c 0x20 0x00 0x20 0x01 0x20 0x17 0x20 0x24>; + clock-names = "gcc_iface\0gcc_bus\0iface_clk\0bus_clk\0core_clk\0vsync_clk"; + clock-rate = <0x00 0x00 0x00 0x00 0x11e1a300 0x124f800 0x00>; + clock-max-rate = <0x00 0x00 0x00 0x00 0x19a14780 0x124f800 0x00>; + sde-vdd-supply = <0x19>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x53 0x00>; + interrupt-controller; + #interrupt-cells = <0x01>; + iommus = <0x29 0x880 0x08 0x29 0xc80 0x08>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #power-domain-cells = <0x00>; + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x45c>; + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600 0x2800>; + qcom,sde-ctl-size = <0xe4>; + qcom,sde-ctl-display-pref = "primary\0primary\0none\0none\0none"; + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x00 0x00 0x4a000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none"; + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x0c>; + qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; + qcom,sde-dspp-size = <0x17e0>; + qcom,sde-dest-scaler-top-off = <0x61000>; + qcom,sde-dest-scaler-top-size = <0x0c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <0x06>; + qcom,sde-wb-id = <0x02>; + qcom,sde-wb-clk-ctrl = <0x3b8 0x18>; + qcom,sde-intf-off = <0x6b000 0x6b800 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x280>; + qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; + qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800 0x73000>; + qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x01>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-te2-off = <0x2000 0x2000 0x00 0x00 0x00>; + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>; + qcom,sde-dsc-size = <0x140>; + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0 0x00>; + qcom,sde-dither-version = <0x10000>; + qcom,sde-dither-size = <0x20>; + qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma"; + qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000>; + qcom,sde-sspp-src-size = <0x1c8>; + qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d>; + qcom,sde-sspp-excl-rect = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>; + qcom,sde-sspp-smart-dma-priority = <0x05 0x06 0x07 0x08 0x01 0x02 0x03 0x04>; + qcom,sde-smart-dma-rev = "smart_dma_v2"; + qcom,sde-mixer-pair-mask = <0x02 0x01 0x06 0x00 0x00 0x03>; + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; + qcom,sde-sspp-clk-ctrl = <0x2ac 0x00 0x2b4 0x00 0x2bc 0x00 0x2c4 0x00 0x2ac 0x08 0x2b4 0x08 0x2bc 0x08 0x2c4 0x08>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-type = "qseedv3"; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <0xa00>; + qcom,sde-sspp-linewidth = <0xa00>; + qcom,sde-wb-linewidth = <0x1000>; + qcom,sde-mixer-blendstages = <0x0b>; + qcom,sde-highest-bank-bit = <0x02>; + qcom,sde-ubwc-version = <0x200>; + qcom,sde-smart-panel-align-mode = <0x0c>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + qcom,sde-has-dest-scaler; + qcom,sde-max-dest-scaler-input-linewidth = <0x800>; + qcom,sde-max-dest-scaler-output-linewidth = <0xa00>; + qcom,sde-max-bw-low-kbps = <0x927c00>; + qcom,sde-max-bw-high-kbps = <0x927c00>; + qcom,sde-min-core-ib-kbps = <0x493e00>; + qcom,sde-min-llcc-ib-kbps = <0xc3500>; + qcom,sde-min-dram-ib-kbps = <0xc3500>; + qcom,sde-dram-channels = <0x02>; + qcom,sde-num-nrt-paths = <0x00>; + qcom,sde-dspp-ad-version = <0x40000>; + qcom,sde-dspp-ad-off = <0x28000 0x27000>; + qcom,sde-vbif-off = <0x00>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0x00>; + qcom,sde-vbif-memtype-0 = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; + qcom,sde-vbif-memtype-1 = <0x03 0x03 0x03 0x03 0x03 0x03>; + qcom,sde-vbif-qos-rt-remap = <0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06>; + qcom,sde-vbif-qos-nrt-remap = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; + qcom,sde-danger-lut = <0x0f 0xffff 0x00 0x00>; + qcom,sde-safe-lut-linear = <0x04 0xfff8 0x00 0xfff0>; + qcom,sde-safe-lut-macrotile = <0x0a 0xfe00 0x0b 0xfc00 0x0c 0xf800 0x00 0xf000>; + qcom,sde-safe-lut-nrt = <0x00 0xffff>; + qcom,sde-safe-lut-cwb = <0x00 0xffff>; + qcom,sde-qos-lut-linear = <0x04 0x00 0x357 0x05 0x00 0x3357 0x06 0x00 0x23357 0x07 0x00 0x223357 0x08 0x00 0x2223357 0x09 0x00 0x22223357 0x0a 0x02 0x22223357 0x0b 0x22 0x22223357 0x0c 0x222 0x22223357 0x0d 0x2222 0x22223357 0x0e 0x12222 0x22223357 0x00 0x112222 0x22223357>; + qcom,sde-qos-lut-macrotile = <0x0a 0x03 0x44556677 0x0b 0x33 0x44556677 0x0c 0x233 0x44556677 0x0d 0x2233 0x44556677 0x0e 0x12233 0x44556677 0x00 0x112233 0x44556677>; + qcom,sde-qos-lut-nrt = <0x00 0x00 0x00>; + qcom,sde-qos-lut-cwb = <0x00 0x75300000 0x00>; + qcom,sde-cdp-setting = <0x01 0x01 0x01 0x00>; + qcom,sde-qos-cpu-mask = <0x03>; + qcom,sde-qos-cpu-dma-latency = <0x12c>; + qcom,sde-inline-rotator = <0x2a 0x00>; + qcom,sde-inline-rot-xin = <0x0a 0x0b>; + qcom,sde-inline-rot-xin-type = "sspp\0wb"; + qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x08 0x2bc 0x0c>; + qcom,sde-reg-dma-off = <0x00>; + qcom,sde-reg-dma-version = <0x01>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + connectors = <0x2b 0x2c>; + #cooling-cells = <0x02>; + phandle = <0x31>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x00 0x30001>; + qcom,sde-dspp-hsic = <0x800 0x10007>; + qcom,sde-dspp-memcolor = <0x880 0x10007>; + qcom,sde-dspp-sixzone = <0x900 0x10007>; + qcom,sde-dspp-vlut = <0xa00 0x10008>; + qcom,sde-dspp-gamut = <0x1000 0x40000>; + qcom,sde-dspp-pcc = <0x1700 0x40000>; + qcom,sde-dspp-gc = <0x17c0 0x10008>; + qcom,sde-dspp-hist = <0x800 0x10007>; + qcom,sde-dspp-dither = <0x82c 0x10007>; + }; + + qcom,platform-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,platform-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0x00>; + qcom,supply-max-voltage = <0x00>; + qcom,supply-enable-load = <0x00>; + qcom,supply-disable-load = <0x00>; + }; + }; + + qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <0x29 0x881 0x08 0x29 0xc81 0x08>; + }; + + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <0x03>; + qcom,msm-bus,num-paths = <0x02>; + qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x17 0x200 0x00 0x00 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800>; + }; + + qcom,sde-reg-bus { + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <0x04>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00 0x01 0x24e 0x00 0x249f0 0x01 0x24e 0x00 0x493e0>; + }; + + qcom,mdss_dsi_sim_video { + qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; + qcom,panel-ack-disabled; + phandle = <0x353>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x280>; + qcom,mdss-dsi-panel-height = <0x1e0>; + qcom,mdss-dsi-h-front-porch = <0x08>; + qcom,mdss-dsi-h-back-porch = <0x08>; + qcom,mdss-dsi-h-pulse-width = <0x08>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x06>; + qcom,mdss-dsi-v-front-porch = <0x06>; + qcom,mdss-dsi-v-pulse-width = <0x02>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-timings = <0x00 0x00 0x00>; + qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00]; + qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5030400>; + qcom,display-topology = <0x01 0x00 0x01 0x02 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_sim_cmd { + qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + qcom,mdss-dsi-t-clk-post = <0x0c>; + qcom,mdss-dsi-t-clk-pre = <0x29>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,ulps-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,panel-ack-disabled; + phandle = <0x355>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x5a0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x78>; + qcom,mdss-dsi-h-back-porch = <0x64>; + qcom,mdss-dsi-h-pulse-width = <0x28>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x64>; + qcom,mdss-dsi-v-front-porch = <0x64>; + qcom,mdss-dsi-v-pulse-width = <0x28>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; + qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <0x28>; + qcom,mdss-dsc-slice-width = <0x2d0>; + qcom,mdss-dsc-slice-per-pkt = <0x01>; + qcom,mdss-dsc-bit-per-component = <0x08>; + qcom,mdss-dsc-bit-per-pixel = <0x08>; + qcom,mdss-dsc-block-prediction-enable; + qcom,display-topology = <0x01 0x00 0x01 0x02 0x02 0x01>; + qcom,default-topology-index = <0x01>; + qcom,panel-roi-alignment = <0x2d0 0x28 0x2d0 0x28 0x2d0 0x28>; + qcom,partial-update-enabled = "single_roi"; + qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4030400>; + }; + + timing@1 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x780>; + qcom,mdss-dsi-h-front-porch = <0x78>; + qcom,mdss-dsi-h-back-porch = <0x1cc>; + qcom,mdss-dsi-h-pulse-width = <0x28>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x64>; + qcom,mdss-dsi-v-front-porch = <0x2e4>; + qcom,mdss-dsi-v-pulse-width = <0x28>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; + qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <0x28>; + qcom,mdss-dsc-slice-width = <0x21c>; + qcom,mdss-dsc-slice-per-pkt = <0x01>; + qcom,mdss-dsc-bit-per-component = <0x08>; + qcom,mdss-dsc-bit-per-pixel = <0x08>; + qcom,mdss-dsc-block-prediction-enable; + qcom,display-topology = <0x01 0x00 0x01 0x02 0x02 0x01>; + qcom,default-topology-index = <0x01>; + qcom,panel-roi-alignment = <0x21c 0x28 0x21c 0x28 0x21c 0x28>; + qcom,partial-update-enabled = "single_roi"; + qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4030400>; + }; + + timing@2 { + qcom,mdss-dsi-panel-width = <0x2d0>; + qcom,mdss-dsi-panel-height = <0x500>; + qcom,mdss-dsi-h-front-porch = <0x64>; + qcom,mdss-dsi-h-back-porch = <0x348>; + qcom,mdss-dsi-h-pulse-width = <0x28>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x64>; + qcom,mdss-dsi-v-front-porch = <0x564>; + qcom,mdss-dsi-v-pulse-width = <0x28>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; + qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <0x28>; + qcom,mdss-dsc-slice-width = <0x168>; + qcom,mdss-dsc-slice-per-pkt = <0x01>; + qcom,mdss-dsc-bit-per-component = <0x08>; + qcom,mdss-dsc-bit-per-pixel = <0x08>; + qcom,mdss-dsc-block-prediction-enable; + qcom,display-topology = <0x01 0x00 0x01 0x02 0x02 0x01>; + qcom,default-topology-index = <0x01>; + qcom,panel-roi-alignment = <0x168 0x28 0x168 0x28 0x168 0x28>; + qcom,partial-update-enabled = "single_roi"; + qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4030400>; + }; + }; + }; + + qcom,mdss_dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-panel-name = "Simulator cmd mode DSC 3.75:1 dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,adjust-timer-wakeup-ms = <0x01>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + phandle = <0x357>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-width = <0x5a0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x64>; + qcom,mdss-dsi-h-back-porch = <0x20>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x08>; + qcom,mdss-dsi-v-front-porch = <0x0a>; + qcom,mdss-dsi-v-pulse-width = <0x02>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2723115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00315 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <0x10>; + qcom,mdss-dsc-slice-width = <0x2d0>; + qcom,mdss-dsc-slice-per-pkt = <0x02>; + qcom,mdss-dsc-bit-per-component = <0x0a>; + qcom,mdss-dsc-bit-per-pixel = <0x08>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4030400>; + qcom,display-topology = <0x01 0x01 0x01>; + qcom,default-topology-index = <0x00>; + }; + + timing@1 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x780>; + qcom,mdss-dsi-h-front-porch = <0x00>; + qcom,mdss-dsi-h-back-porch = <0x00>; + qcom,mdss-dsi-h-pulse-width = <0x00>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x00>; + qcom,mdss-dsi-v-front-porch = <0x00>; + qcom,mdss-dsi-v-pulse-width = <0x00>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; + qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <0x10>; + qcom,mdss-dsc-slice-width = <0x21c>; + qcom,mdss-dsc-slice-per-pkt = <0x02>; + qcom,mdss-dsc-bit-per-component = <0x0a>; + qcom,mdss-dsc-bit-per-pixel = <0x08>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsi-panel-phy-timings = <0x150505 0x201f0505 0x3030400>; + qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_dual_sim_video { + qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-panel-broadcast-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0xc8 0x01 0x14>; + qcom,panel-ack-disabled; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + phandle = <0x354>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x500>; + qcom,mdss-dsi-panel-height = <0x5a0>; + qcom,mdss-dsi-h-front-porch = <0x78>; + qcom,mdss-dsi-h-back-porch = <0x2c>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x04>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x04>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5030400>; + qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_dual_sim_cmd { + qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + phandle = <0x356>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x21c>; + qcom,mdss-dsi-panel-height = <0x780>; + qcom,mdss-dsi-h-front-porch = <0x1c>; + qcom,mdss-dsi-h-back-porch = <0x04>; + qcom,mdss-dsi-h-pulse-width = <0x04>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x0c>; + qcom,mdss-dsi-v-front-porch = <0x0c>; + qcom,mdss-dsi-v-pulse-width = <0x02>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x78>; + qcom,mdss-dsi-on-command = <0x5010000 0x129>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-phy-timings = <0x240909 0x26240909 0x6030400>; + qcom,display-topology = <0x02 0x00 0x02>; + qcom,default-topology-index = <0x00>; + }; + + timing@1 { + qcom,mdss-dsi-panel-width = <0x2d0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x64>; + qcom,mdss-dsi-h-back-porch = <0x20>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x07>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x01>; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = <0x5010000 0x129>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-phy-timings = <0x300c0d 0x2a270c0d 0x9030400>; + qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; + qcom,default-topology-index = <0x00>; + }; + + timing@2 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0xf00>; + qcom,mdss-dsi-h-front-porch = <0x1e>; + qcom,mdss-dsi-h-back-porch = <0x64>; + qcom,mdss-dsi-h-pulse-width = <0x04>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x07>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x01>; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x28>; + qcom,mdss-dsi-on-command = <0x5010000 0x129>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4030400>; + qcom,display-topology = <0x02 0x00 0x02>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-panel-name = "Sim dual cmd mode DSC 3.75:1 dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + phandle = <0x358>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0xf00>; + qcom,mdss-dsi-h-front-porch = <0x1e>; + qcom,mdss-dsi-h-back-porch = <0x64>; + qcom,mdss-dsi-h-pulse-width = <0x04>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x07>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x01>; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <0x20>; + qcom,mdss-dsc-slice-width = <0x438>; + qcom,mdss-dsc-slice-per-pkt = <0x01>; + qcom,mdss-dsc-bit-per-component = <0x0a>; + qcom,mdss-dsc-bit-per-pixel = <0x08>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5030400>; + qcom,display-topology = <0x02 0x02 0x02>; + qcom,default-topology-index = <0x00>; + }; + + timing@1 { + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-width = <0x2d0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x64>; + qcom,mdss-dsi-h-back-porch = <0x20>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x07>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x01>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <0x10>; + qcom,mdss-dsc-slice-width = <0x2d0>; + qcom,mdss-dsc-slice-per-pkt = <0x01>; + qcom,mdss-dsc-bit-per-component = <0x0a>; + qcom,mdss-dsc-bit-per-pixel = <0x08>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4030400>; + qcom,display-topology = <0x02 0x02 0x02>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x01 0xc8 0x00 0xc8 0x01 0xc8>; + qcom,mdss-pan-physical-width-dimension = <0x47>; + qcom,mdss-pan-physical-height-dimension = <0x81>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <0x01>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-t-clk-post = <0x0c>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + phandle = <0x34a>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0xf00>; + qcom,mdss-dsi-h-front-porch = <0x1e>; + qcom,mdss-dsi-h-back-porch = <0x64>; + qcom,mdss-dsi-h-pulse-width = <0x04>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x07>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x01>; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 10 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <0x20>; + qcom,mdss-dsc-slice-width = <0x438>; + qcom,mdss-dsc-slice-per-pkt = <0x01>; + qcom,mdss-dsc-bit-per-component = <0x08>; + qcom,mdss-dsc-bit-per-pixel = <0x08>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4030400>; + qcom,display-topology = <0x02 0x02 0x02>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_sharp_4k_dsc_cmd { + qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x01 0xc8 0x00 0xc8 0x01 0xc8>; + qcom,mdss-pan-physical-width-dimension = <0x47>; + qcom,mdss-pan-physical-height-dimension = <0x81>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <0x01>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-t-clk-post = <0x0c>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + phandle = <0x34b>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0xf00>; + qcom,mdss-dsi-h-front-porch = <0x1e>; + qcom,mdss-dsi-h-back-porch = <0x64>; + qcom,mdss-dsi-h-pulse-width = <0x04>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x07>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x01>; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-jitter = <0x08 0x0a>; + qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <0x20>; + qcom,mdss-dsc-slice-width = <0x438>; + qcom,mdss-dsc-slice-per-pkt = <0x01>; + qcom,mdss-dsc-bit-per-component = <0x08>; + qcom,mdss-dsc-bit-per-pixel = <0x08>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4030400>; + qcom,display-topology = <0x02 0x02 0x02>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_nt35597_wqxga_video_truly { + qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x32>; + qcom,mdss-pan-physical-width-dimension = <0x4a>; + qcom,mdss-pan-physical-height-dimension = <0x83>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-underflow-color = <0x3ff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,dsi-supported-dfps-list = <0x3c 0x37 0x35>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <0x01>; + phandle = <0x34e>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x2d0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x64>; + qcom,mdss-dsi-h-back-porch = <0x20>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x07>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x01>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 03 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5030400>; + qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_nt35597_truly_wqxga_cmd { + qcom,mdss-dsi-panel-name = "Dual nt35597 cmd mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,adjust-timer-wakeup-ms = <0x01>; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x4a>; + qcom,mdss-pan-physical-height-dimension = <0x83>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <0x01>; + phandle = <0x34f>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-width = <0x2d0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x64>; + qcom,mdss-dsi-h-back-porch = <0x20>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x07>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x01>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-jitter = <0x01 0x01>; + qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 c0 00 29 01 00 00 00 00 0c c9 01 01 70 00 0a 06 67 04 c5 12 18 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5030400>; + qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; + qcom,default-topology-index = <0x00>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <0x2d0 0x80 0x2d0 0x80 0x5a0 0x80>; + }; + }; + }; + + qcom,mdss_dsi_nt35597_dsc_cmd_truly { + qcom,mdss-dsi-panel-name = "nt35597 cmd mode dsi truly panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-pan-physical-width-dimension = <0x4a>; + qcom,mdss-pan-physical-height-dimension = <0x83>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,adjust-timer-wakeup-ms = <0x01>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-t-clk-post = <0x0b>; + qcom,mdss-dsi-t-clk-pre = <0x23>; + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <0x01>; + phandle = <0x351>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-width = <0x5a0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x64>; + qcom,mdss-dsi-h-back-porch = <0x20>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x08>; + qcom,mdss-dsi-v-front-porch = <0x0a>; + qcom,mdss-dsi-v-pulse-width = <0x02>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-jitter = <0x01 0x01>; + qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2721115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00315 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <0x10>; + qcom,mdss-dsc-slice-width = <0x2d0>; + qcom,mdss-dsc-slice-per-pkt = <0x02>; + qcom,mdss-dsc-bit-per-component = <0x08>; + qcom,mdss-dsc-bit-per-pixel = <0x08>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsi-panel-phy-timings = <0x150505 0x201f0505 0x3030400>; + qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; + qcom,default-topology-index = <0x01>; + }; + }; + }; + + qcom,mdss_dsi_nt35597_dsc_video_truly { + qcom,mdss-dsi-panel-name = "nt35597 video mode dsi truly panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x4a>; + qcom,mdss-pan-physical-height-dimension = <0x83>; + qcom,mdss-dsi-dma-schedule-line = <0x05>; + qcom,mdss-dsi-t-clk-post = <0x0b>; + qcom,mdss-dsi-t-clk-pre = <0x23>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,dsi-supported-dfps-list = <0x3c 0x37 0x35>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <0x01>; + phandle = <0x352>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x5a0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x64>; + qcom,mdss-dsi-h-back-porch = <0x20>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x08>; + qcom,mdss-dsi-v-front-porch = <0x0a>; + qcom,mdss-dsi-v-pulse-width = <0x02>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2721115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00339 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x3150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <0x10>; + qcom,mdss-dsc-slice-width = <0x2d0>; + qcom,mdss-dsc-slice-per-pkt = <0x02>; + qcom,mdss-dsc-bit-per-component = <0x08>; + qcom,mdss-dsc-bit-per-pixel = <0x08>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsi-panel-phy-timings = <0x150505 0x201f0504 0x3030400>; + qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; + qcom,default-topology-index = <0x01>; + }; + }; + }; + + qcom,mdss_dsi_sharp_1080p_cmd { + qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; + qcom,mdss-dsi-panel-controller = <0x2d>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,mdss-dsi-panel-clockrate = <0x32a9f880>; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x40>; + qcom,mdss-pan-physical-height-dimension = <0x75>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-t-clk-post = <0x0c>; + qcom,mdss-dsi-t-clk-pre = <0x29>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <0x01>; + phandle = <0x34c>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x780>; + qcom,mdss-dsi-h-front-porch = <0x00>; + qcom,mdss-dsi-h-back-porch = <0x00>; + qcom,mdss-dsi-h-pulse-width = <0x00>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x00>; + qcom,mdss-dsi-v-front-porch = <0x00>; + qcom,mdss-dsi-v-pulse-width = <0x00>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; + qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-phy-timings = <0x1e0808 0x24220808 0x5030400>; + qcom,mdss-dsi-panel-clockrate = <0x35a4e900>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_r63417_truly_1080p_cmd { + qcom,mdss-dsi-panel-name = "r63417 truly 1080p cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x0c>; + qcom,mdss-dsi-t-clk-pre = <0x29>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-bl-min-level = <0x01>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + qcom,mdss-dsi-post-init-delay = <0x01>; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-on-check-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <0x01>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x780>; + qcom,mdss-dsi-h-front-porch = <0x60>; + qcom,mdss-dsi-h-back-porch = <0x40>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x10>; + qcom,mdss-dsi-v-front-porch = <0x04>; + qcom,mdss-dsi-v-pulse-width = <0x01>; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = [23 01 00 00 00 00 02 d6 01 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 05 01 00 00 78 00 02 11 00 23 01 00 00 00 00 02 b0 04 29 01 00 00 00 00 07 b3 04 00 00 00 00 00 29 01 00 00 00 00 03 b6 3a d3 29 01 00 00 00 00 03 c0 00 00 29 01 00 00 00 00 23 c1 84 60 10 eb ff 6f ce ff ff 17 02 58 73 ae b1 20 c6 ff ff 1f f3 ff 5f 10 10 10 10 00 02 01 22 22 00 01 29 01 00 00 00 00 08 c2 31 f7 80 06 08 00 00 29 01 00 00 00 00 17 c4 70 00 00 00 00 04 00 00 00 0c 06 00 00 00 00 00 04 00 00 00 0c 06 29 01 00 00 00 00 29 c6 78 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 00 78 00 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 29 01 00 00 00 00 0a cb 31 fc 3f 8c 00 00 00 00 c0 23 01 00 00 00 00 02 cc 0b 29 01 00 00 00 00 0b d0 11 81 bb 1e 1e 4c 19 19 0c 00 29 01 00 00 00 00 1a d3 1b 33 bb bb b3 33 33 33 00 01 00 a0 d8 a0 0d 4e 4e 33 3b 22 72 07 3d bf 33 29 01 00 00 00 00 08 d5 06 00 00 01 51 01 32 29 01 00 00 00 00 1f c7 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 29 01 00 00 14 00 14 c8 01 00 00 00 00 fc 00 00 00 00 00 fc 00 00 00 00 00 fc 00 05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-timings = <0xe6382600 0x686e2a3c 0x44030400>; + qcom,mdss-dsi-panel-phy-timings = <0x1e0808 0x24220808 0x5030400>; + qcom,mdss-dsi-panel-clockrate = <0x35a4e900>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dual_sharp_1080p_120hz_cmd { + qcom,mdss-dsi-panel-name = "sharp 1080p 120hz dual dsi cmd mode panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x01 0x01 0x0a>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,cmd-sync-wait-trigger; + qcom,mdss-tear-check-frame-rate = <0x2ee0>; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-t-clk-post = <0x0f>; + qcom,mdss-dsi-t-clk-pre = <0x36>; + phandle = <0x34d>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x21c>; + qcom,mdss-dsi-panel-height = <0x780>; + qcom,mdss-dsi-h-front-porch = <0x1c>; + qcom,mdss-dsi-h-back-porch = <0x04>; + qcom,mdss-dsi-h-pulse-width = <0x04>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x0c>; + qcom,mdss-dsi-v-front-porch = <0x0c>; + qcom,mdss-dsi-v-pulse-width = <0x02>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x78>; + qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ba 07 15 01 00 00 00 00 02 c0 00 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 d9 00 15 01 00 00 00 00 02 ef 70 15 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 06 3b 03 0e 0c 08 1c 15 01 00 00 00 00 02 e9 0e 15 01 00 00 00 00 02 ea 0c 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 c0 00 15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 59 6a 15 01 00 00 00 00 02 0b 1b 15 01 00 00 00 00 02 61 f7 15 01 00 00 00 00 02 62 6c 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 04 c8 15 01 00 00 00 00 02 05 1a 15 01 00 00 00 00 02 0d 93 15 01 00 00 00 00 02 0e 93 15 01 00 00 00 00 02 0f 7e 15 01 00 00 00 00 02 06 69 15 01 00 00 00 00 02 07 bc 15 01 00 00 00 00 02 10 03 15 01 00 00 00 00 02 11 64 15 01 00 00 00 00 02 12 5a 15 01 00 00 00 00 02 13 40 15 01 00 00 00 00 02 14 40 15 01 00 00 00 00 02 15 00 15 01 00 00 00 00 02 33 13 15 01 00 00 00 00 02 5a 40 15 01 00 00 00 00 02 5b 40 15 01 00 00 00 00 02 5e 80 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 80 15 01 00 00 00 00 02 14 80 15 01 00 00 00 00 02 01 80 15 01 00 00 00 00 02 15 80 15 01 00 00 00 00 02 02 80 15 01 00 00 00 00 02 16 80 15 01 00 00 00 00 02 03 0a 15 01 00 00 00 00 02 17 0c 15 01 00 00 00 00 02 04 06 15 01 00 00 00 00 02 18 08 15 01 00 00 00 00 02 05 80 15 01 00 00 00 00 02 19 80 15 01 00 00 00 00 02 06 80 15 01 00 00 00 00 02 1a 80 15 01 00 00 00 00 02 07 80 15 01 00 00 00 00 02 1b 80 15 01 00 00 00 00 02 08 80 15 01 00 00 00 00 02 1c 80 15 01 00 00 00 00 02 09 80 15 01 00 00 00 00 02 1d 80 15 01 00 00 00 00 02 0a 80 15 01 00 00 00 00 02 1e 80 15 01 00 00 00 00 02 0b 1a 15 01 00 00 00 00 02 1f 1b 15 01 00 00 00 00 02 0c 16 15 01 00 00 00 00 02 20 17 15 01 00 00 00 00 02 0d 1c 15 01 00 00 00 00 02 21 1d 15 01 00 00 00 00 02 0e 18 15 01 00 00 00 00 02 22 19 15 01 00 00 00 00 02 0f 0e 15 01 00 00 00 00 02 23 10 15 01 00 00 00 00 02 10 80 15 01 00 00 00 00 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9a 34 15 01 00 00 00 00 02 9b 03 15 01 00 00 00 00 02 9c 56 15 01 00 00 00 00 02 9d 03 15 01 00 00 00 00 02 9e 62 15 01 00 00 00 00 02 9f 03 15 01 00 00 00 00 02 a0 6c 15 01 00 00 00 00 02 a2 03 15 01 00 00 00 00 02 a3 74 15 01 00 00 00 00 02 a4 03 15 01 00 00 00 00 02 a5 80 15 01 00 00 00 00 02 a6 03 15 01 00 00 00 00 02 a7 89 15 01 00 00 00 00 02 a9 03 15 01 00 00 00 00 02 aa 8b 15 01 00 00 00 00 02 ab 03 15 01 00 00 00 00 02 ac 8d 15 01 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae 8e 15 01 00 00 00 00 02 af 00 15 01 00 00 00 00 02 b0 71 15 01 00 00 00 00 02 b1 00 15 01 00 00 00 00 02 b2 84 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 b4 a5 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 bb 15 01 00 00 00 00 02 b7 00 15 01 00 00 00 00 02 b8 ce 15 01 00 00 00 00 02 b9 00 15 01 00 00 00 00 02 ba e0 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 bc ef 15 01 00 00 00 00 02 bd 00 15 01 00 00 00 00 02 be ff 15 01 00 00 00 00 02 bf 01 15 01 00 00 00 00 02 c0 0b 15 01 00 00 00 00 02 c1 01 15 01 00 00 00 00 02 c2 38 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 c4 5b 15 01 00 00 00 00 02 c5 01 15 01 00 00 00 00 02 c6 95 15 01 00 00 00 00 02 c7 01 15 01 00 00 00 00 02 c8 c4 15 01 00 00 00 00 02 c9 02 15 01 00 00 00 00 02 ca 0d 15 01 00 00 00 00 02 cb 02 15 01 00 00 00 00 02 cc 4a 15 01 00 00 00 00 02 cd 02 15 01 00 00 00 00 02 ce 4c 15 01 00 00 00 00 02 cf 02 15 01 00 00 00 00 02 d0 85 15 01 00 00 00 00 02 d1 02 15 01 00 00 00 00 02 d2 c3 15 01 00 00 00 00 02 d3 02 15 01 00 00 00 00 02 d4 e9 15 01 00 00 00 00 02 d5 03 15 01 00 00 00 00 02 d6 16 15 01 00 00 00 00 02 d7 03 15 01 00 00 00 00 02 d8 34 15 01 00 00 00 00 02 d9 03 15 01 00 00 00 00 02 da 56 15 01 00 00 00 00 02 db 03 15 01 00 00 00 00 02 dc 62 15 01 00 00 00 00 02 dd 03 15 01 00 00 00 00 02 de 6c 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 74 15 01 00 00 00 00 02 e1 03 15 01 00 00 00 00 02 e2 80 15 01 00 00 00 00 02 e3 03 15 01 00 00 00 00 02 e4 89 15 01 00 00 00 00 02 e5 03 15 01 00 00 00 00 02 e6 8b 15 01 00 00 00 00 02 e7 03 15 01 00 00 00 00 02 e8 8d 15 01 00 00 00 00 02 e9 03 15 01 00 00 00 00 02 ea 8e 15 01 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 29]; + qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 05 01 00 00 10 00 01 28 15 01 00 00 00 00 02 b0 00 05 01 00 00 40 00 01 10 15 01 00 00 00 00 02 4f 01]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-phy-timings = <0x240909 0x26240909 0x6030400>; + qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_s6e3ha3_amoled_wqhd_cmd { + qcom,mdss-dsi-panel-name = "Dual s6e3ha3 amoled cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-panel-width = <0x2d0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x64>; + qcom,mdss-dsi-h-back-porch = <0x64>; + qcom,mdss-dsi-h-pulse-width = <0x28>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x1f>; + qcom,mdss-dsi-v-front-porch = <0x1e>; + qcom,mdss-dsi-v-pulse-width = <0x08>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-on-command = [05 01 00 00 05 00 02 11 00 39 01 00 00 00 00 05 2a 00 00 05 9f 39 01 00 00 00 00 05 2b 00 00 09 ff 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b0 10 39 01 00 00 00 00 02 b5 a0 39 01 00 00 00 00 02 c4 03 39 01 00 00 00 00 0a f6 42 57 37 00 aa cc d0 00 00 39 01 00 00 00 00 02 f9 03 39 01 00 00 00 00 14 c2 00 00 d8 d8 00 80 2b 05 08 0e 07 0b 05 0d 0a 15 13 20 1e 39 01 00 00 78 00 03 f0 a5 a5 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 02 51 60 05 01 00 00 05 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 3c 00 02 28 00 05 01 00 00 b4 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-lp-mode-on = [39 00 00 00 05 00 03 f0 5a 5a 39 00 00 00 05 00 03 f1 5a 5a 39 00 00 00 05 00 03 fc 5a 5a 39 00 00 00 05 00 02 b0 17 39 00 00 00 05 00 02 cb 10 39 00 00 00 05 00 02 b0 2d 39 00 00 00 05 00 02 cb cd 39 00 00 00 05 00 02 b0 0e 39 00 00 00 05 00 02 cb 02 39 00 00 00 05 00 02 b0 0f 39 00 00 00 05 00 02 cb 09 39 00 00 00 05 00 02 b0 02 39 00 00 00 05 00 02 f2 c9 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f2 c0 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f4 aa 39 00 00 00 05 00 02 b0 08 39 00 00 00 05 00 02 b1 30 39 00 00 00 05 00 02 b0 09 39 00 00 00 05 00 02 b1 0a 39 00 00 00 05 00 02 b0 0d 39 00 00 00 05 00 02 b1 10 39 00 00 00 05 00 02 b0 00 39 00 00 00 05 00 02 f7 03 39 00 00 00 05 00 02 fe 30 39 01 00 00 05 00 02 fe b0]; + qcom,mdss-dsi-lp-mode-off = [39 00 00 00 05 00 03 f0 5a 5a 39 00 00 00 05 00 03 f1 5a 5a 39 00 00 00 05 00 03 fc 5a 5a 39 00 00 00 05 00 02 b0 2d 39 00 00 00 05 00 02 cb 4d 39 00 00 00 05 00 02 b0 17 39 00 00 00 05 00 02 cb 04 39 00 00 00 05 00 02 b0 0e 39 00 00 00 05 00 02 cb 06 39 00 00 00 05 00 02 b0 0f 39 00 00 00 05 00 02 cb 05 39 00 00 00 05 00 02 b0 02 39 00 00 00 05 00 02 f2 b8 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f2 80 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f4 8a 39 00 00 00 05 00 02 b0 08 39 00 00 00 05 00 02 b1 10 39 00 00 00 05 00 02 b0 09 39 00 00 00 05 00 02 b1 0a 39 00 00 00 05 00 02 b0 0d 39 00 00 00 05 00 02 b1 80 39 00 00 00 05 00 02 b0 00 39 00 00 00 05 00 02 f7 03 39 00 00 00 05 00 02 fe 30 39 01 00 00 05 00 02 fe b0]; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <0x01>; + qcom,mdss-dsi-bl-max-level = <0xff>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x7a>; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + }; + + qcom,mdss_dsi_nt35597_wqxga_video { + qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0x3ff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x4a>; + qcom,mdss-pan-physical-height-dimension = <0x83>; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-min-refresh-rate = <0x37>; + qcom,mdss-dsi-max-refresh-rate = <0x3c>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + phandle = <0x359>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x2d0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x64>; + qcom,mdss-dsi-h-back-porch = <0x20>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x07>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x01>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ba 03 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 bb 03 15 01 00 00 00 00 02 b0 03 39 01 00 00 00 00 06 3b 03 08 08 64 9a 15 01 00 00 00 00 02 ff e0 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 6b 3d 15 01 00 00 00 00 02 6c 3d 15 01 00 00 00 00 02 6d 3d 15 01 00 00 00 00 02 6e 3d 15 01 00 00 00 00 02 6f 3d 15 01 00 00 00 00 02 35 02 15 01 00 00 00 00 02 36 72 15 01 00 00 00 00 02 37 10 15 01 00 00 00 00 02 08 c0 15 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 02 11 00 05 01 00 00 32 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 3c 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-timings = <0x1c0807 0x23220707 0x5030400>; + qcom,config-select = <0x2e>; + qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; + qcom,default-topology-index = <0x00>; + + config0 { + qcom,split-mode = "dualctl-split"; + phandle = <0x2e>; + }; + + config1 { + qcom,split-mode = "pingpong-split"; + }; + }; + }; + }; + + qcom,mdss_dsi_nt35597_wqxga_cmd { + qcom,mdss-dsi-panel-name = "Dual nt35597 cmd mode dsi panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,adjust-timer-wakeup-ms = <0x01>; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x4a>; + qcom,mdss-pan-physical-height-dimension = <0x83>; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,ulps-enabled; + phandle = <0x35a>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x2d0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x64>; + qcom,mdss-dsi-h-back-porch = <0x20>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x07>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x01>; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = <0x15010000 0x100002ff 0x10150100 0x100002 0xfb011501 0x1000 0x2ba0315 0x1000010 0x2e501 0x15010000 0x10000235 0x150100 0x100002 0xbb101501 0x1000 0x2b00315 0x1000010 0x2ffe0 0x15010000 0x100002fb 0x1150100 0x100002 0x6b3d1501 0x1000 0x26c3d15 0x1000010 0x26d3d 0x15010000 0x1000026e 0x3d150100 0x100002 0x6f3d1501 0x1000 0x2350215 0x1000010 0x23672 0x15010000 0x10000237 0x10150100 0x100002 0x8c01501 0x1000 0x2ff2415 0x1000010 0x2fb01 0x15010000 0x100002c6 0x6150100 0x100002 0xff100501 0xa000 0x2110005 0x10000a0 0x22900>; + qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 3c 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-timings = <0x1c0807 0x23220707 0x5030400>; + qcom,config-select = <0x2f>; + qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; + qcom,default-topology-index = <0x00>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <0x2d0 0x80 0x2d0 0x80 0x5a0 0x80>; + + config0 { + qcom,split-mode = "dualctl-split"; + phandle = <0x2f>; + }; + + config1 { + qcom,split-mode = "pingpong-split"; + }; + }; + }; + }; + + qcom,mdss_dsi_nt36850_truly_wqhd_cmd { + qcom,mdss-dsi-panel-name = "Dual nt36850 cmd mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <0x01>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x32>; + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x30>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-width = <0x2d0>; + qcom,mdss-dsi-panel-height = <0xa00>; + qcom,mdss-dsi-h-front-porch = <0x78>; + qcom,mdss-dsi-h-back-porch = <0x8c>; + qcom,mdss-dsi-h-pulse-width = <0x14>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x14>; + qcom,mdss-dsi-v-front-porch = <0x08>; + qcom,mdss-dsi-v-pulse-width = <0x04>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 44 03 e8 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 01 05 01 00 00 0a 00 02 20 00 15 01 00 00 00 00 02 bb 10 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-phy-timings = <0x1f0808 0x24230808 0x5030400>; + qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_test_oled_cmd { + qcom,mdss-dsi-panel-name = "Dual test cmd mode DSI amoled non-DSC panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,adjust-timer-wakeup-ms = <0x01>; + qcom,mdss-dsi-reset-sequence = <0x01 0x02 0x00 0x02 0x01 0x02>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-hfp-power-mode; + qcom,mdss-dsi-hbp-power-mode; + qcom,mdss-dsi-hsa-power-mode; + + qcom,mdss-dsi-display-timings { + + timing@0 { + }; + }; + }; + }; + + qcom,sde_rscc@af20000 { + cell-index = <0x00>; + compatible = "qcom,sde-rsc"; + reg = <0xaf20000 0x1c44 0xaf30000 0x3fd4>; + reg-names = "drv\0wrapper"; + qcom,sde-rsc-version = <0x01>; + vdd-supply = <0x19>; + clocks = <0x20 0x23 0x20 0x22>; + clock-names = "vsync_clk\0iface_clk"; + clock-rate = <0x00 0x00>; + qcom,sde-dram-channels = <0x02>; + mboxes = <0x30 0x00>; + mbox-names = "disp_rsc"; + phandle = <0x2b>; + + qcom,sde-data-bus { + qcom,msm-bus,name = "disp_rsc_mnoc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <0x03>; + qcom,msm-bus,num-paths = <0x02>; + qcom,msm-bus,vectors-KBps = <0x4e23 0x5023 0x00 0x00 0x4e24 0x5023 0x00 0x00 0x4e23 0x5023 0x00 0x61a800 0x4e24 0x5023 0x00 0x61a800 0x4e23 0x5023 0x00 0x61a800 0x4e24 0x5023 0x00 0x61a800>; + }; + + qcom,sde-llcc-bus { + qcom,msm-bus,name = "disp_rsc_llcc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <0x03>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x4e21 0x5021 0x00 0x00 0x4e21 0x5021 0x00 0x61a800 0x4e21 0x5021 0x00 0x61a800>; + }; + + qcom,sde-ebi-bus { + qcom,msm-bus,name = "disp_rsc_ebi"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <0x03>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x4e20 0x5020 0x00 0x00 0x4e20 0x5020 0x00 0x61a800 0x4e20 0x5020 0x00 0x61a800>; + }; + }; + + qcom,mdss_rotator@ae00000 { + compatible = "qcom,sde_rotator"; + reg = <0xae00000 0xac000 0xaeb8000 0x3000>; + reg-names = "mdp_phys\0rot_vbif_phys"; + #list-cells = <0x01>; + qcom,mdss-rot-mode = <0x01>; + qcom,mdss-highest-bank-bit = <0x02>; + qcom,msm-bus,name = "mdss_rotator"; + qcom,msm-bus,num-cases = <0x03>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x19 0x200 0x00 0x00 0x19 0x200 0x00 0x61a800 0x19 0x200 0x00 0x61a800>; + rot-vdd-supply = <0x19>; + qcom,supply-names = "rot-vdd"; + clocks = <0x22 0x1b 0x22 0x1c 0x20 0x00 0x20 0x20 0x20 0x01>; + clock-names = "gcc_iface\0gcc_bus\0iface_clk\0rot_clk\0axi_clk"; + interrupt-parent = <0x31>; + interrupts = <0x02 0x00>; + power-domains = <0x31>; + qcom,mdss-rot-vbif-qos-setting = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; + qcom,mdss-rot-vbif-memtype = <0x03 0x03>; + qcom,mdss-rot-cdp-setting = <0x01 0x01>; + qcom,mdss-rot-qos-lut = <0x00 0x00 0x00 0x00>; + qcom,mdss-rot-danger-lut = <0x00 0x00>; + qcom,mdss-rot-safe-lut = <0xffff 0xffff>; + qcom,mdss-inline-rot-qos-lut = <0x44556677 0x112233 0x44556677 0x112233>; + qcom,mdss-inline-rot-danger-lut = <0x55aaff 0xffff>; + qcom,mdss-inline-rot-safe-lut = <0xf000 0xff00>; + qcom,mdss-default-ot-rd-limit = <0x20>; + qcom,mdss-default-ot-wr-limit = <0x20>; + qcom,mdss-sbuf-headroom = <0x14>; + cache-slice-names = "rotator"; + cache-slices = <0x32 0x04>; + phandle = <0x2a>; + + qcom,rot-reg-bus { + qcom,msm-bus,name = "mdss_rot_reg"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00>; + }; + + qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <0x29 0x1090 0x00>; + }; + + qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <0x29 0x1091 0x00>; + }; + }; + + qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.2"; + label = "dsi-ctrl-0"; + cell-index = <0x00>; + reg = <0xae94000 0x400 0xaf08000 0x04>; + reg-names = "dsi_ctrl\0disp_cc_base"; + interrupt-parent = <0x31>; + interrupts = <0x04 0x00>; + vdda-1p2-supply = <0x33>; + clocks = <0x20 0x02 0x20 0x03 0x20 0x04 0x20 0x1a 0x20 0x1b 0x20 0x13>; + clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk"; + qcom,null-insertion-enabled; + phandle = <0x2d>; + + qcom,ctrl-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,ctrl-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <0x124f80>; + qcom,supply-max-voltage = <0x124f80>; + qcom,supply-enable-load = <0x5528>; + qcom,supply-disable-load = <0x04>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,core-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0x00>; + qcom,supply-max-voltage = <0x00>; + qcom,supply-enable-load = <0x00>; + qcom,supply-disable-load = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.2"; + label = "dsi-ctrl-1"; + cell-index = <0x01>; + reg = <0xae96000 0x400 0xaf08000 0x04>; + reg-names = "dsi_ctrl\0disp_cc_base"; + interrupt-parent = <0x31>; + interrupts = <0x05 0x00>; + vdda-1p2-supply = <0x33>; + clocks = <0x20 0x05 0x20 0x06 0x20 0x07 0x20 0x1c 0x20 0x1d 0x20 0x15>; + clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk"; + qcom,null-insertion-enabled; + phandle = <0x342>; + + qcom,ctrl-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,ctrl-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <0x124f80>; + qcom,supply-max-voltage = <0x124f80>; + qcom,supply-enable-load = <0x5528>; + qcom,supply-disable-load = <0x04>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,core-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0x00>; + qcom,supply-max-voltage = <0x00>; + qcom,supply-enable-load = <0x00>; + qcom,supply-disable-load = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_phy0@ae94400 { + compatible = "qcom,dsi-phy-v3.0"; + label = "dsi-phy-0"; + cell-index = <0x00>; + reg = <0xae94400 0x7c0>; + reg-names = "dsi_phy"; + gdsc-supply = <0x19>; + vdda-0p9-supply = <0x34>; + qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; + qcom,platform-lane-config = <0x00 0x00 0x00 0x00 0x80>; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + phandle = <0x343>; + + qcom,phy-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,phy-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <0xd6d80>; + qcom,supply-max-voltage = <0xd6d80>; + qcom,supply-enable-load = <0x8ca0>; + qcom,supply-disable-load = <0x20>; + }; + }; + }; + + qcom,mdss_dsi_phy0@ae96400 { + compatible = "qcom,dsi-phy-v3.0"; + label = "dsi-phy-1"; + cell-index = <0x01>; + reg = <0xae96400 0x7c0>; + reg-names = "dsi_phy"; + gdsc-supply = <0x19>; + vdda-0p9-supply = <0x34>; + qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = <0x00 0x00 0x00 0x00 0x80>; + phandle = <0x344>; + + qcom,phy-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,phy-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <0xd6d80>; + qcom,supply-max-voltage = <0xd6d80>; + qcom,supply-enable-load = <0x8ca0>; + qcom,supply-disable-load = <0x20>; + }; + }; + }; + + qcom,dp_display@0 { + cell-index = <0x00>; + compatible = "qcom,dp-display"; + gdsc-supply = <0x19>; + vdda-1p2-supply = <0x33>; + vdda-0p9-supply = <0x34>; + reg = <0xae90000 0xdc 0xae90200 0xc0 0xae90400 0x508 0xae90a00 0x94 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0xaf02000 0x1a0 0x780000 0x621c 0x88ea030 0x10 0x88e8000 0x20 0xaee1000 0x34>; + reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_mmss_cc\0qfprom_physical\0dp_pll\0usb3_dp_com\0hdcp_physical"; + interrupt-parent = <0x31>; + interrupts = <0x0c 0x00>; + clocks = <0x20 0x08 0x21 0x00 0x22 0x9f 0x22 0xa9 0x22 0xa3 0x20 0x0c 0x20 0x0e 0x20 0x11 0x20 0x0a 0x20 0x12 0x35 0x05>; + clock-names = "core_aux_clk\0core_usb_ref_clk_src\0core_usb_ref_clk\0core_usb_cfg_ahb_clk\0core_usb_pipe_clk\0ctrl_link_clk\0ctrl_link_iface_clk\0ctrl_pixel_clk\0crypto_clk\0pixel_clk_rcg\0pixel_parent"; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = <0x2413231d>; + qcom,aux-cfg2-settings = [28 24]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 bb]; + qcom,aux-cfg9-settings = [44 03]; + qcom,max-pclk-frequency-khz = <0xa4cb8>; + qcom,dp-usbpd-detection = <0x36>; + qcom,ext-disp = <0x37>; + pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; + pinctrl-0 = <0x38 0x39>; + pinctrl-1 = <0x3a 0x3b>; + qcom,aux-en-gpio = <0x3c 0x2b 0x00>; + qcom,aux-sel-gpio = <0x3c 0x33 0x00>; + qcom,usbplug-cc-gpio = <0x3c 0x26 0x00>; + status = "disabled"; + + qcom,ctrl-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,ctrl-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <0x124f80>; + qcom,supply-max-voltage = <0x124f80>; + qcom,supply-enable-load = <0x5528>; + qcom,supply-disable-load = <0x04>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,phy-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <0xd6d80>; + qcom,supply-max-voltage = <0xd6d80>; + qcom,supply-enable-load = <0x8ca0>; + qcom,supply-disable-load = <0x20>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,core-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0x00>; + qcom,supply-max-voltage = <0x00>; + qcom,supply-enable-load = <0x00>; + qcom,supply-disable-load = <0x00>; + }; + }; + }; + + qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x6000>; + qcom,bus-mas-id = <0x56>; + qcom,bus-slv-id = <0x200>; + qcom,iommu-s1-bypass; + phandle = <0x40>; + + qcom,iommu_qupv3_0_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <0x29 0x03 0x00>; + }; + }; + + qcom,qup_uart@0x898000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x898000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x58 0x22 0x6c 0x22 0x6d>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x3d 0x3e 0x3f>; + pinctrl-1 = <0x3d 0x3e 0x3f>; + interrupts-extended = <0x01 0x00 0x25f 0x00 0x3c 0x30 0x00>; + status = "ok"; + qcom,wakeup-byte = <0xfd>; + qcom,wrapper-core = <0x40>; + }; + + qcom,qup_uart@0x89c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x89c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x5a 0x22 0x6c 0x22 0x6d>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x41>; + pinctrl-1 = <0x42>; + interrupts-extended = <0x01 0x00 0x260 0x00 0x3c 0x60 0x00>; + status = "disabled"; + qcom,wakeup-byte = <0xfd>; + qcom,wrapper-core = <0x40>; + }; + + i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + interrupts = <0x00 0x259 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x4c 0x22 0x6c 0x22 0x6d>; + dmas = <0x43 0x00 0x00 0x03 0x40 0x00 0x43 0x01 0x00 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x44>; + pinctrl-1 = <0x45>; + qcom,wrapper-core = <0x40>; + status = "disabled"; + }; + + i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + interrupts = <0x00 0x25a 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x4e 0x22 0x6c 0x22 0x6d>; + dmas = <0x43 0x00 0x01 0x03 0x40 0x00 0x43 0x01 0x01 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x46>; + pinctrl-1 = <0x47>; + qcom,wrapper-core = <0x40>; + status = "disabled"; + }; + + i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + interrupts = <0x00 0x25b 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x50 0x22 0x6c 0x22 0x6d>; + dmas = <0x43 0x00 0x02 0x03 0x40 0x00 0x43 0x01 0x02 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x48>; + pinctrl-1 = <0x49>; + qcom,wrapper-core = <0x40>; + status = "disabled"; + }; + + i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + interrupts = <0x00 0x25c 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x52 0x22 0x6c 0x22 0x6d>; + dmas = <0x43 0x00 0x03 0x03 0x40 0x00 0x43 0x01 0x03 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x4a>; + pinctrl-1 = <0x4b>; + qcom,wrapper-core = <0x40>; + status = "ok"; + + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <0x3c 0x3f 0x00>; + qcom,nq-firm = <0x3c 0x58 0x00>; + qcom,nq-clkreq = <0x4c 0x15 0x00>; + qcom,nq-esepwr = <0x3c 0x74 0x00>; + interrupt-parent = <0x3c>; + qcom,clk-src = "BBCLK3"; + interrupts = <0x3f 0x00>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active\0nfc_suspend"; + pinctrl-0 = <0x4d 0x4e 0x4f>; + pinctrl-1 = <0x50 0x51>; + clocks = <0x21 0x04>; + clock-names = "ref_clk"; + }; + }; + + i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + interrupts = <0x00 0x25d 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x54 0x22 0x6c 0x22 0x6d>; + dmas = <0x43 0x00 0x04 0x03 0x40 0x00 0x43 0x01 0x04 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x52>; + pinctrl-1 = <0x53>; + qcom,wrapper-core = <0x40>; + status = "disabled"; + }; + + i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + interrupts = <0x00 0x25e 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x56 0x22 0x6c 0x22 0x6d>; + dmas = <0x43 0x00 0x05 0x03 0x40 0x00 0x43 0x01 0x05 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x54>; + pinctrl-1 = <0x55>; + qcom,wrapper-core = <0x40>; + status = "ok"; + + tas2559@4c { + compatible = "ti,tas2559"; + reg = <0x4c>; + ti,tas2559-reset-gpio = <0x3c 0x0c 0x00>; + ti,tas2560-reset-gpio = <0x3c 0x4c 0x00>; + ti,tas2559-irq-gpio = <0x3c 0x0b 0x00>; + ti,tas2560-irq-gpio = <0x3c 0x1e 0x00>; + ti,tas2559-addr = <0x4c>; + ti,tas2560-addr = <0x4d>; + ti,tas2559-channel = <0x00>; + ti,tas2560-channel = <0x01>; + ti,ycrc-enable = <0x01>; + ti,echo-ref = <0x00>; + ti,bit-rate = <0x10>; + status = "ok"; + }; + }; + + i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + interrupts = <0x00 0x25f 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x58 0x22 0x6c 0x22 0x6d>; + dmas = <0x43 0x00 0x06 0x03 0x40 0x00 0x43 0x01 0x06 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x56>; + pinctrl-1 = <0x57>; + qcom,wrapper-core = <0x40>; + status = "disabled"; + }; + + i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + interrupts = <0x00 0x260 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x5a 0x22 0x6c 0x22 0x6d>; + dmas = <0x43 0x00 0x07 0x03 0x40 0x00 0x43 0x01 0x07 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x58>; + pinctrl-1 = <0x59>; + qcom,wrapper-core = <0x40>; + status = "disabled"; + }; + + spi@880000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x880000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x4c 0x22 0x6c 0x22 0x6d>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x5a>; + pinctrl-1 = <0x5b>; + interrupts = <0x00 0x259 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x40>; + dmas = <0x43 0x00 0x00 0x01 0x40 0x00 0x43 0x01 0x00 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@884000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x884000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x4e 0x22 0x6c 0x22 0x6d>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x5c>; + pinctrl-1 = <0x5d>; + interrupts = <0x00 0x25a 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x40>; + dmas = <0x43 0x00 0x01 0x01 0x40 0x00 0x43 0x01 0x01 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@888000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x888000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x50 0x22 0x6c 0x22 0x6d>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x5e>; + pinctrl-1 = <0x5f>; + interrupts = <0x00 0x25b 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x40>; + dmas = <0x43 0x00 0x02 0x01 0x40 0x00 0x43 0x01 0x02 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@88c000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x88c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x52 0x22 0x6c 0x22 0x6d>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x60>; + pinctrl-1 = <0x61>; + interrupts = <0x00 0x25c 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x40>; + dmas = <0x43 0x00 0x03 0x01 0x40 0x00 0x43 0x01 0x03 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@890000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x890000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x54 0x22 0x6c 0x22 0x6d>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x62>; + pinctrl-1 = <0x63>; + interrupts = <0x00 0x25d 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x40>; + dmas = <0x43 0x00 0x04 0x01 0x40 0x00 0x43 0x01 0x04 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@894000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x894000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x56 0x22 0x6c 0x22 0x6d>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x64>; + pinctrl-1 = <0x65>; + interrupts = <0x00 0x25e 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x40>; + dmas = <0x43 0x00 0x05 0x01 0x40 0x00 0x43 0x01 0x05 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@898000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x898000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x58 0x22 0x6c 0x22 0x6d>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x66>; + pinctrl-1 = <0x67>; + interrupts = <0x00 0x25f 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x40>; + dmas = <0x43 0x00 0x06 0x01 0x40 0x00 0x43 0x01 0x06 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@89c000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x89c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x5a 0x22 0x6c 0x22 0x6d>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x68>; + pinctrl-1 = <0x69>; + interrupts = <0x00 0x260 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x40>; + dmas = <0x43 0x00 0x07 0x01 0x40 0x00 0x43 0x01 0x07 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x6000>; + qcom,bus-mas-id = <0x54>; + qcom,bus-slv-id = <0x200>; + qcom,iommu-s1-bypass; + phandle = <0x6c>; + + qcom,iommu_qupv3_1_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <0x29 0x6c3 0x00>; + }; + }; + + qcom,qup_uart@0xa84000 { + compatible = "qcom,msm-geni-console"; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x5e 0x22 0x6e 0x22 0x6f>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x6a>; + pinctrl-1 = <0x6b>; + interrupts = <0x00 0x162 0x00>; + qcom,wrapper-core = <0x6c>; + status = "ok"; + }; + + qcom,qup_uart@0xa88000 { + compatible = "qcom,msm-geni-console"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x60 0x22 0x6e 0x22 0x6f>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x6d>; + pinctrl-1 = <0x6e>; + interrupts = <0x00 0x163 0x00>; + qcom,wrapper-core = <0x6c>; + status = "disabled"; + }; + + i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + interrupts = <0x00 0x161 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x5c 0x22 0x6e 0x22 0x6f>; + dmas = <0x6f 0x00 0x00 0x03 0x40 0x00 0x6f 0x01 0x00 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x70>; + pinctrl-1 = <0x71>; + qcom,wrapper-core = <0x6c>; + status = "disabled"; + }; + + i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + interrupts = <0x00 0x162 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x5e 0x22 0x6e 0x22 0x6f>; + dmas = <0x6f 0x00 0x01 0x03 0x40 0x00 0x6f 0x01 0x01 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x72>; + pinctrl-1 = <0x73>; + qcom,wrapper-core = <0x6c>; + status = "disabled"; + }; + + i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + interrupts = <0x00 0x163 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x60 0x22 0x6e 0x22 0x6f>; + dmas = <0x6f 0x00 0x02 0x03 0x40 0x00 0x6f 0x01 0x02 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x74>; + pinctrl-1 = <0x75>; + qcom,wrapper-core = <0x6c>; + status = "ok"; + + qcom,smb1355@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x08>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x76>; + interrupts = <0x00 0xd1 0x00 0x08>; + interrupt_names = "smb1355_0"; + interrupt-controller; + #interrupt-cells = <0x03>; + qcom,periph-map = <0x10 0x12 0x13 0x16>; + phandle = <0x78>; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + phandle = <0x77>; + }; + + qcom,smb1355-charger@1000 { + compatible = "qcom,smb1355"; + qcom,pmic-revid = <0x77>; + reg = <0x1000 0x700>; + #address-cells = <0x01>; + #size-cells = <0x01>; + interrupt-parent = <0x78>; + status = "ok"; + io-channels = <0x79 0x02 0x79 0x0c>; + io-channel-names = "charger_temp\0charger_temp_max"; + qcom,enable-ctm; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x10 0x01 0x01>; + interrupt-names = "chg-state-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x16 0x01 0x01 0x16 0x06 0x01>; + interrupt-names = "wdog-bark\0temperature-change"; + }; + }; + }; + + qcom,smb1355@c { + compatible = "qcom,i2c-pmic"; + reg = <0x0c>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x76>; + interrupts = <0x00 0xd1 0x00 0x08>; + interrupt_names = "smb1355_1"; + interrupt-controller; + #interrupt-cells = <0x03>; + qcom,periph-map = <0x10 0x12 0x13 0x16>; + phandle = <0x7b>; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + phandle = <0x7a>; + }; + + qcom,smb1355-charger@1000 { + compatible = "qcom,smb1355"; + qcom,pmic-revid = <0x7a>; + reg = <0x1000 0x700>; + #address-cells = <0x01>; + #size-cells = <0x01>; + interrupt-parent = <0x7b>; + status = "ok"; + io-channels = <0x79 0x02 0x79 0x0c>; + io-channel-names = "charger_temp\0charger_temp_max"; + qcom,enable-ctm; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x10 0x01 0x01>; + interrupt-names = "chg-state-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x16 0x01 0x01 0x16 0x06 0x01>; + interrupt-names = "wdog-bark\0temperature-change"; + }; + }; + }; + + lm3644@63 { + compatible = "leds-lm3644"; + reg = <0x63>; + lm3644,hwen-gpio = <0x3c 0x5d 0x00>; + lm3644,torch-gpio = <0x3c 0x60 0x00>; + lm3644,tx-gpio = <0x3c 0x87 0x00>; + pinctrl-names = "lm3644_led_active\0lm3644_led_active_pwm\0lm3644_led_suspend"; + pinctrl-0 = <0x7c 0x7d>; + pinctrl-1 = <0x7c 0x7e>; + pinctrl-2 = <0x7f 0x7d>; + lm3644,use-simulative-pwm; + pwms = <0x80 0x00 0x00>; + lm3644,period-us = <0x61a8>; + lm3644,duty-us = <0x9c4>; + }; + }; + + i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + interrupts = <0x00 0x164 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x62 0x22 0x6e 0x22 0x6f>; + dmas = <0x6f 0x00 0x03 0x03 0x40 0x00 0x6f 0x01 0x03 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x81>; + pinctrl-1 = <0x82>; + qcom,wrapper-core = <0x6c>; + status = "disabled"; + }; + + i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + interrupts = <0x00 0x165 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x64 0x22 0x6e 0x22 0x6f>; + dmas = <0x6f 0x00 0x04 0x03 0x40 0x00 0x6f 0x01 0x04 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x83>; + pinctrl-1 = <0x84>; + qcom,wrapper-core = <0x6c>; + status = "disabled"; + }; + + i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + interrupts = <0x00 0x166 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x66 0x22 0x6e 0x22 0x6f>; + dmas = <0x6f 0x00 0x05 0x03 0x40 0x00 0x6f 0x01 0x05 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x85>; + pinctrl-1 = <0x86>; + qcom,wrapper-core = <0x6c>; + status = "disabled"; + }; + + i2c@a98000 { + compatible = "qcom,i2c-geni"; + reg = <0xa98000 0x4000>; + interrupts = <0x00 0x167 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x68 0x22 0x6e 0x22 0x6f>; + dmas = <0x6f 0x00 0x06 0x03 0x40 0x00 0x6f 0x01 0x06 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x87>; + pinctrl-1 = <0x88>; + qcom,wrapper-core = <0x6c>; + status = "ok"; + + novatek@62 { + compatible = "novatek,NVT-ts"; + reg = <0x62>; + status = "ok"; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + novatek,vddio-reg-name = "vddio"; + novatek,lab-reg-name = "lab"; + novatek,ibb-reg-name = "ibb"; + novatek,reset-tddi = <0x3c 0x06 0x00>; + novatek,reset-gpio = <0x3c 0x20 0x00>; + novatek,irq-gpio = <0x3c 0x1f 0x2001>; + pinctrl-names = "pmx_ts_active\0pmx_ts_suspend"; + pinctrl-0 = <0x8c 0x8d>; + pinctrl-1 = <0x8e 0x8f>; + novatek,config-array-size = <0x02>; + + novatek,cfg_0 { + novatek,tp-vendor = <0x46>; + novatek,hw-version = <0x01>; + novatek,fw-name = "novatek_nt36672_e10_hw01.fw"; + }; + + novatek,cfg_1 { + novatek,tp-vendor = <0x46>; + novatek,hw-version = <0x02>; + novatek,fw-name = "novatek_nt36672_e10_hw02.fw"; + }; + }; + + focaltech@38 { + compatible = "focaltech,fts"; + reg = <0x38>; + interrupt-parent = <0x3c>; + interrupts = <0x1f 0x00>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + focaltech,reset-gpio = <0x3c 0x20 0x01>; + focaltech,irq-gpio = <0x3c 0x1f 0x02>; + focaltech,max-touch-number = <0x0a>; + focaltech,display-coords = <0x00 0x00 0x438 0x8c6>; + pinctrl-names = "pmx_ts_active\0pmx_ts_suspend"; + pinctrl-0 = <0x8c 0x8d>; + pinctrl-1 = <0x8e 0x8f>; + }; + }; + + i2c@a9c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa9c000 0x4000>; + interrupts = <0x00 0x168 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x6a 0x22 0x6e 0x22 0x6f>; + dmas = <0x6f 0x00 0x07 0x03 0x40 0x00 0x6f 0x01 0x07 0x03 0x40 0x00>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x90>; + pinctrl-1 = <0x91>; + qcom,wrapper-core = <0x6c>; + status = "disabled"; + }; + + spi@a80000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0xa80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x5c 0x22 0x6e 0x22 0x6f>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x92>; + pinctrl-1 = <0x92>; + interrupts = <0x00 0x161 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x6c>; + dmas = <0x6f 0x00 0x00 0x01 0x40 0x00 0x6f 0x01 0x00 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "ok"; + }; + + spi@a84000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x5e 0x22 0x6e 0x22 0x6f>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x93>; + pinctrl-1 = <0x94>; + interrupts = <0x00 0x162 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x6c>; + dmas = <0x6f 0x00 0x01 0x01 0x40 0x00 0x6f 0x01 0x01 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@a88000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x60 0x22 0x6e 0x22 0x6f>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x95>; + pinctrl-1 = <0x96>; + interrupts = <0x00 0x163 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x6c>; + dmas = <0x6f 0x00 0x02 0x01 0x40 0x00 0x6f 0x01 0x02 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@a8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x62 0x22 0x6e 0x22 0x6f>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x97>; + pinctrl-1 = <0x98>; + interrupts = <0x00 0x164 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x6c>; + dmas = <0x6f 0x00 0x03 0x01 0x40 0x00 0x6f 0x01 0x03 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@a90000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x64 0x22 0x6e 0x22 0x6f>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x99>; + pinctrl-1 = <0x9a>; + interrupts = <0x00 0x165 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x6c>; + dmas = <0x6f 0x00 0x04 0x01 0x40 0x00 0x6f 0x01 0x04 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@a94000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x66 0x22 0x6e 0x22 0x6f>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x9b>; + pinctrl-1 = <0x9c>; + interrupts = <0x00 0x166 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x6c>; + dmas = <0x6f 0x00 0x05 0x01 0x40 0x00 0x6f 0x01 0x05 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@a98000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0xa98000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x68 0x22 0x6e 0x22 0x6f>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x9d>; + pinctrl-1 = <0x9e>; + interrupts = <0x00 0x167 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x6c>; + dmas = <0x6f 0x00 0x06 0x01 0x40 0x00 0x6f 0x01 0x06 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + spi@a9c000 { + compatible = "qcom,spi-geni"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0xa9c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk\0m-ahb\0s-ahb"; + clocks = <0x22 0x6a 0x22 0x6e 0x22 0x6f>; + pinctrl-names = "default\0sleep"; + pinctrl-0 = <0x9f>; + pinctrl-1 = <0xa0>; + interrupts = <0x00 0x168 0x00>; + spi-max-frequency = <0x2faf080>; + qcom,wrapper-core = <0x6c>; + dmas = <0x6f 0x00 0x07 0x01 0x40 0x00 0x6f 0x01 0x07 0x01 0x40 0x00>; + dma-names = "tx\0rx"; + status = "disabled"; + }; + + jtagmm@7040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7040000 0x1000>; + reg-names = "etm-base"; + clocks = <0xa1 0x00>; + clock-names = "core_clk"; + qcom,coresight-jtagmm-cpu = <0x11>; + }; + + jtagmm@7140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7140000 0x1000>; + reg-names = "etm-base"; + clocks = <0xa1 0x00>; + clock-names = "core_clk"; + qcom,coresight-jtagmm-cpu = <0x12>; + }; + + jtagmm@7240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7240000 0x1000>; + reg-names = "etm-base"; + clocks = <0xa1 0x00>; + clock-names = "core_clk"; + qcom,coresight-jtagmm-cpu = <0x13>; + }; + + jtagmm@7340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7340000 0x1000>; + reg-names = "etm-base"; + clocks = <0xa1 0x00>; + clock-names = "core_clk"; + qcom,coresight-jtagmm-cpu = <0x14>; + }; + + jtagmm@7440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7440000 0x1000>; + reg-names = "etm-base"; + clocks = <0xa1 0x00>; + clock-names = "core_clk"; + qcom,coresight-jtagmm-cpu = <0x15>; + }; + + jtagmm@7540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7540000 0x1000>; + reg-names = "etm-base"; + clocks = <0xa1 0x00>; + clock-names = "core_clk"; + qcom,coresight-jtagmm-cpu = <0x16>; + }; + + jtagmm@7640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7640000 0x1000>; + reg-names = "etm-base"; + clocks = <0xa1 0x00>; + clock-names = "core_clk"; + qcom,coresight-jtagmm-cpu = <0x17>; + }; + + jtagmm@7740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7740000 0x1000>; + reg-names = "etm-base"; + clocks = <0xa1 0x00>; + clock-names = "core_clk"; + qcom,coresight-jtagmm-cpu = <0x18>; + }; + + interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + interrupt-controller; + #redistributor-regions = <0x01>; + redistributor-stride = <0x00 0x20000>; + reg = <0x17a00000 0x10000 0x17a60000 0x100000>; + interrupts = <0x01 0x09 0x04>; + interrupt-parent = <0xa2>; + ignored-save-restore-irqs = <0x26>; + phandle = <0xa2>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x01 0xf08 0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x00 0xf08>; + clock-frequency = <0x124f800>; + }; + + timer@0x17C90000 { + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c90000 0x1000>; + clock-frequency = <0x124f800>; + + frame@0x17CA0000 { + frame-number = <0x00>; + interrupts = <0x00 0x07 0x04 0x00 0x06 0x04>; + reg = <0x17ca0000 0x1000 0x17cb0000 0x1000>; + }; + + frame@17cc0000 { + frame-number = <0x01>; + interrupts = <0x00 0x08 0x04>; + reg = <0x17cc0000 0x1000>; + status = "disabled"; + }; + + frame@17cd0000 { + frame-number = <0x02>; + interrupts = <0x00 0x09 0x04>; + reg = <0x17cd0000 0x1000>; + status = "disabled"; + }; + + frame@17ce0000 { + frame-number = <0x03>; + interrupts = <0x00 0x0a 0x04>; + reg = <0x17ce0000 0x1000>; + status = "disabled"; + }; + + frame@17cf0000 { + frame-number = <0x04>; + interrupts = <0x00 0x0b 0x04>; + reg = <0x17cf0000 0x1000>; + status = "disabled"; + }; + + frame@17d00000 { + frame-number = <0x05>; + interrupts = <0x00 0x0c 0x04>; + reg = <0x17d00000 0x1000>; + status = "disabled"; + }; + + frame@17d10000 { + frame-number = <0x06>; + interrupts = <0x00 0x0d 0x04>; + reg = <0x17d10000 0x1000>; + status = "disabled"; + }; + }; + + restart@10ac000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x04 0x1fd3000 0x04>; + reg-names = "pshold-base\0tcsr-boot-misc-detect"; + qcom,force-warm-reboot; + }; + + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <0xa3 0x00>; + mbox-names = "aop"; + }; + + qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100 0xc600000 0x2000000 0xe600000 0x100000 0xe700000 0xa0000 0xc40a000 0x26000>; + reg-names = "core\0chnls\0obsrvr\0intr\0cnfg"; + interrupt-names = "periph_irq"; + interrupts = <0x00 0x1e1 0x00>; + qcom,ee = <0x00>; + qcom,channel = <0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + interrupt-controller; + #interrupt-cells = <0x04>; + cell-index = <0x00>; + phandle = <0x76>; + + qcom,pm8998@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x00 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x00 0x08 0x00 0x00 0x00 0x08 0x01 0x00 0x00 0x08 0x04 0x00 0x00 0x08 0x05 0x00>; + interrupt-names = "kpdpwr\0resin\0resin-bark\0kpdpwr-resin-bark"; + qcom,pon-dbc-delay = <0xf424>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <0x00>; + qcom,support-reset = <0x01>; + qcom,pull-up = <0x01>; + linux,code = <0x74>; + qcom,s1-timer = <0x1a40>; + qcom,s2-timer = <0x7d0>; + qcom,s2-type = <0x07>; + }; + + qcom,pon_2 { + qcom,pon-type = <0x01>; + qcom,pull-up = <0x01>; + linux,code = <0x72>; + }; + + qcom,pon_3 { + qcom,pon-type = <0x03>; + qcom,support-reset = <0x01>; + qcom,pull-up = <0x01>; + qcom,s1-timer = <0x548>; + qcom,s2-timer = <0x7d0>; + qcom,s2-type = <0x01>; + qcom,use-bark; + }; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x00 0x24 0x00 0x01>; + label = "pm8998_tz"; + qcom,channel-num = <0x06>; + qcom,temp_alarm-vadc = <0xa4>; + #thermal-sensor-cells = <0x00>; + phandle = <0x151>; + }; + + pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x1a00>; + interrupts = <0x00 0xc0 0x00 0x00 0x00 0xc1 0x00 0x00 0x00 0xc3 0x00 0x00 0x00 0xc4 0x00 0x00 0x00 0xc5 0x00 0x00 0x00 0xc6 0x00 0x00 0x00 0xc7 0x00 0x00 0x00 0xc8 0x00 0x00 0x00 0xc9 0x00 0x00 0x00 0xca 0x00 0x00 0x00 0xcb 0x00 0x00 0x00 0xcc 0x00 0x00 0x00 0xcd 0x00 0x00 0x00 0xcf 0x00 0x00 0x00 0xd0 0x00 0x00 0x00 0xd1 0x00 0x00 0x00 0xd2 0x00 0x00 0x00 0xd4 0x00 0x00 0x00 0xd6 0x00 0x00>; + interrupt-names = "pm8998_gpio1\0pm8998_gpio2\0pm8998_gpio4\0pm8998_gpio5\0pm8998_gpio6\0pm8998_gpio7\0pm8998_gpio8\0pm8998_gpio9\0pm8998_gpio10\0pm8998_gpio11\0pm8998_gpio12\0pm8998_gpio13\0pm8998_gpio14\0pm8998_gpio16\0pm8998_gpio17\0pm8998_gpio18\0pm8998_gpio19\0pm8998_gpio21\0pm8998_gpio23"; + gpio-controller; + #gpio-cells = <0x02>; + qcom,gpios-disallowed = <0x03 0x0f 0x14 0x16 0x18 0x19 0x1a>; + phandle = <0x4c>; + + key_home { + + key_home_default { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0x00>; + }; + }; + + led_bt { + + led_bt_default { + pins = "gpio5"; + function = "normal"; + power-source = <0x00>; + output-low; + }; + }; + + key_vol_up { + + key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0x00>; + phandle = <0x374>; + }; + }; + + key_cam_snapshot { + + key_cam_snapshot_default { + pins = "gpio7"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0x00>; + }; + }; + + key_cam_focus { + + key_cam_focus_default { + pins = "gpio8"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0x00>; + }; + }; + + led_wifi { + + led_wifi_default { + pins = "gpio9"; + function = "normal"; + power-source = <0x00>; + output-low; + }; + }; + + camera_dvdd_en { + + camera_dvdd_en_default { + pins = "gpio9"; + function = "normal"; + power-source = <0x00>; + output-low; + }; + }; + + camera_rear_avdd_en { + + camera_rear_avdd_en_default { + pins = "gpio10"; + function = "normal"; + power-source = <0x00>; + output-low; + }; + }; + + camera_rear_dvdd_en { + + camera_rear_dvdd_en_default { + pins = "gpio11"; + function = "normal"; + power-source = <0x00>; + output-low; + }; + }; + + nfc_clk { + + nfc_clk_default { + pins = "gpio21"; + function = "normal"; + input-enable; + power-source = <0x01>; + phandle = <0x4f>; + }; + }; + + gpio8_adc { + + gpio8_adc_default { + pins = "gpio8"; + function = "normal"; + bias-high-impedance; + phandle = <0xa5>; + }; + }; + }; + + qcom,coincell@2800 { + compatible = "qcom,qpnp-coincell"; + reg = <0x2800 0x100>; + }; + + qcom,pm8998_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <0x01>; + #size-cells = <0x01>; + qcom,qpnp-rtc-write = <0x00>; + qcom,qpnp-rtc-alarm-pwrup = <0x01>; + + qcom,pm8998_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pm8998_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x00 0x61 0x01 0x00>; + }; + }; + + vadc@3100 { + compatible = "qcom,qpnp-vadc-hc"; + reg = <0x3100 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupts = <0x00 0x31 0x00 0x01>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <0x753>; + pinctrl-names = "default"; + pinctrl-0 = <0xa5>; + phandle = <0xa4>; + + chan@6 { + label = "die_temp"; + reg = <0x06>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0x03>; + qcom,hw-settle-time = <0x00>; + qcom,fast-avg-setup = <0x00>; + qcom,cal-val = <0x00>; + }; + + chan@0 { + label = "ref_gnd"; + reg = <0x00>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0x00>; + qcom,hw-settle-time = <0x00>; + qcom,fast-avg-setup = <0x00>; + qcom,cal-val = <0x00>; + }; + + chan@1 { + label = "ref_1250v"; + reg = <0x01>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0x00>; + qcom,hw-settle-time = <0x00>; + qcom,fast-avg-setup = <0x00>; + qcom,cal-val = <0x00>; + }; + + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x01>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0x00>; + qcom,hw-settle-time = <0x00>; + qcom,fast-avg-setup = <0x00>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x01>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0x00>; + qcom,hw-settle-time = <0x00>; + qcom,fast-avg-setup = <0x00>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x04>; + qcom,hw-settle-time = <0x02>; + qcom,fast-avg-setup = <0x00>; + }; + + chan@4d { + label = "cam_therm0"; + reg = <0x4d>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,fast-avg-setup = <0x00>; + }; + + chan@4e { + label = "cam_therm1"; + reg = <0x4e>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,fast-avg-setup = <0x00>; + }; + + chan@4f { + label = "pa_therm0"; + reg = <0x4f>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,fast-avg-setup = <0x00>; + }; + + chan@50 { + label = "pa_therm1"; + reg = <0x50>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,fast-avg-setup = <0x00>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,fast-avg-setup = <0x00>; + }; + + chan@52 { + label = "backlight_therm"; + reg = <0x52>; + qcom,decimation = <0x02>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,fast-avg-setup = <0x00>; + }; + }; + + vadc@3400 { + compatible = "qcom,qpnp-adc-tm-hc"; + reg = <0x3400 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupts = <0x00 0x34 0x00 0x01>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <0x753>; + qcom,adc_tm-vadc = <0xa4>; + qcom,decimation = <0x00>; + qcom,fast-avg-setup = <0x00>; + #thermal-sensor-cells = <0x01>; + phandle = <0x175>; + + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <0x01>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0x00>; + qcom,hw-settle-time = <0x00>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x04>; + qcom,hw-settle-time = <0x02>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@4d { + label = "cam_therm0"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,btm-channel-number = <0x88>; + qcom,thermal-node; + }; + + chan@4e { + label = "cam_therm1"; + reg = <0x4e>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4f { + label = "pa_therm0"; + reg = <0x4f>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; + + chan@50 { + label = "pa_therm1"; + reg = <0x50>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,btm-channel-number = <0x90>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,btm-channel-number = <0x80>; + qcom,thermal-node; + }; + + chan@52 { + label = "backlight_therm"; + reg = <0x52>; + qcom,pre-div-channel-scaling = <0x00>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0x02>; + qcom,hw-settle-time = <0x02>; + qcom,btm-channel-number = <0x98>; + qcom,thermal-node; + }; + }; + + qcom,clkdiv@5b00 { + compatible = "qcom,qpnp-clkdiv"; + reg = <0x5b00 0x100>; + #clock-cells = <0x01>; + qcom,cxo-freq = <0x124f800>; + qcom,clkdiv-id = <0x01>; + qcom,clkdiv-init-freq = <0x124f800>; + }; + + qcom,clkdiv@5c00 { + compatible = "qcom,qpnp-clkdiv"; + reg = <0x5c00 0x100>; + #clock-cells = <0x01>; + qcom,cxo-freq = <0x124f800>; + qcom,clkdiv-id = <0x02>; + qcom,clkdiv-init-freq = <0x124f800>; + }; + + qcom,clkdiv@5d00 { + compatible = "qcom,qpnp-clkdiv"; + reg = <0x5d00 0x100>; + #clock-cells = <0x01>; + qcom,cxo-freq = <0x124f800>; + qcom,clkdiv-id = <0x03>; + qcom,clkdiv-init-freq = <0x124f800>; + }; + }; + + qcom,pm8998@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x01 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + }; + + qcom,pm8005@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x04 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x04 0x24 0x00 0x01>; + label = "pm8005_tz"; + #thermal-sensor-cells = <0x00>; + phandle = <0x154>; + }; + + pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x400>; + interrupts = <0x04 0xc0 0x00 0x00 0x04 0xc1 0x00 0x00>; + interrupt-names = "pm8005_gpio1\0pm8005_gpio2"; + gpio-controller; + #gpio-cells = <0x02>; + qcom,gpios-disallowed = <0x03 0x04>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + }; + + qcom,pm8005@5 { + compatible = "qcom,spmi-pmic"; + reg = <0x05 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + + regulator@1400 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x100>; + regulator-name = "pm8005_s1"; + status = "disabled"; + }; + + regulator@1700 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x100>; + regulator-name = "pm8005_s2"; + status = "disabled"; + }; + + regulator@1a00 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x100>; + regulator-name = "pm8005_s3"; + status = "disabled"; + }; + + regulator@1d00 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1d00 0x100>; + regulator-name = "pm8005_s4"; + status = "disabled"; + }; + }; + + qcom,pmi8998@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x02 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + qcom,fab-id-valid; + phandle = <0xa6>; + }; + + qcom,misc@900 { + compatible = "qcom,qpnp-misc"; + reg = <0x900 0x100>; + phandle = <0xb2>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x02 0x24 0x00 0x01>; + io-channels = <0x79 0x07>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0x00>; + phandle = <0x174>; + }; + + pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xe00>; + interrupts = <0x02 0xc0 0x00 0x00 0x02 0xc1 0x00 0x00 0x02 0xc2 0x00 0x00 0x02 0xc4 0x00 0x00 0x02 0xc5 0x00 0x00 0x02 0xc7 0x00 0x00 0x02 0xc8 0x00 0x00 0x02 0xc9 0x00 0x00 0x02 0xca 0x00 0x00 0x02 0xcb 0x00 0x00 0x02 0xcd 0x00 0x00>; + interrupt-names = "pmi8998_gpio1\0pmi8998_gpio2\0pmi8998_gpio3\0pmi8998_gpio5\0pmi8998_gpio6\0pmi8998_gpio8\0pmi8998_gpio9\0pmi8998_gpio10\0pmi8998_gpio11\0pmi8998_gpio12\0pmi8998_gpio14"; + gpio-controller; + #gpio-cells = <0x02>; + qcom,gpios-disallowed = <0x04 0x07 0x0d>; + phandle = <0x37f>; + + usb2_vbus_boost { + + usb2_vbus_boost_default { + pins = "gpio2"; + function = "normal"; + output-low; + power-source = <0x00>; + }; + }; + + qnovo_fet_ctrl { + + qnovo_fet_ctrl_default { + pins = "gpio6"; + function = "func1"; + output-low; + input-disable; + bias-disable; + power-source = <0x00>; + qcom,drive-strength = <0x01>; + phandle = <0xa7>; + }; + }; + + usb2_vbus_det { + + usb2_vbus_det_default { + pins = "gpio8"; + function = "normal"; + input-enable; + bias-pull-down; + power-source = <0x01>; + phandle = <0x382>; + }; + }; + + usb2_id_det { + + usb2_id_det_default { + pins = "gpio9"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0x00>; + }; + }; + + usb2_ext_5v_boost { + + usb2_ext_5v_boost_default { + pins = "gpio10"; + function = "normal"; + output-low; + power-source = <0x00>; + phandle = <0x380>; + }; + }; + + lm3644_pwm { + + lm3644_pwm_default { + pins = "gpio2"; + function = "normal"; + bias-high-impedance; + phandle = <0x7e>; + }; + + lm3644_pwm_disabled { + pins = "gpio2"; + function = "normal"; + bias-high-impedance; + phandle = <0x7d>; + }; + }; + }; + + qcom,qpnp-qnovo@1500 { + compatible = "qcom,qpnp-qnovo"; + reg = <0x1500 0x100>; + interrupts = <0x02 0x15 0x00 0x00>; + interrupt-names = "ptrain-done"; + qcom,pmic-revid = <0xa6>; + pinctrl-names = "default"; + pinctrl-0 = <0xa7>; + }; + + qcom,qpnp-smb2 { + compatible = "qcom,qpnp-smb2"; + #address-cells = <0x01>; + #size-cells = <0x01>; + #cooling-cells = <0x02>; + qcom,pmic-revid = <0xa6>; + io-channels = <0x79 0x08 0x79 0x0a 0x79 0x03 0x79 0x04>; + io-channel-names = "charger_temp\0charger_temp_max\0usbin_i\0usbin_v"; + qcom,boost-threshold-ua = <0x186a0>; + qcom,wipower-max-uw = <0x4c4b40>; + dpdm-supply = <0xa8>; + qcom,thermal-mitigation = <0x1b7740 0x186a00 0x155cc0 0x124f80 0xf4240 0xf4240 0xf4240>; + qcom,auto-recharge-soc; + qcom,suspend-input-on-debug-batt; + qcom,usb-icl-ua = <0x2dc6c0>; + qcom,fcc-max-ua = <0x2ab980>; + qcom,fcc-low-temp-delta = <0x2673c0>; + qcom,fcc-hot-temp-delta = <0x155cc0>; + qcom,fcc-cool-temp-delta = <0x1de840>; + qcom,sw-jeita-enable; + qcom,thermal-mitigation-dcp = <0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x1b7740 0x186a00 0x155cc0 0x124f80 0xf4240>; + qcom,thermal-mitigation-qc3 = <0x2dc6c0 0x299488 0x274a98 0x2500a8 0x22b6b8 0x206cc8 0x1e8480 0x1b7740 0x192d50 0x16e360 0x14c080 0x124f80 0x102ca0 0xdbba0 0xb7b74 0x802c8>; + qcom,thermal-mitigation-qc2 = <0x18cba8 0x18cba8 0x18cba8 0x18cba8 0x18cba8 0x174508 0x15be68 0x1437c8 0x12b128 0x112a88 0x9c7a98 0xe1d48 0xc96a8 0xb1008 0x98968 0x802c8>; + qcom,thermal-mitigation-pd-base = <0x2dc6c0 0x2ab980 0x27ac40 0x249f00 0x2191c0 0x1e8480 0x1b7740 0x186a00 0x186a00 0x155cc0 0x124f80 0x10c8e0 0xf4240 0xdbba0 0xb7b74 0x802c8>; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x02 0x10 0x00 0x01 0x02 0x10 0x01 0x01 0x02 0x10 0x02 0x01 0x02 0x10 0x03 0x01 0x02 0x10 0x04 0x01>; + interrupt-names = "chg-error\0chg-state-change\0step-chg-state-change\0step-chg-soc-update-fail\0step-chg-soc-update-request"; + }; + + qcom,otg@1100 { + reg = <0x1100 0x100>; + interrupts = <0x02 0x11 0x00 0x03 0x02 0x11 0x01 0x03 0x02 0x11 0x02 0x03 0x02 0x11 0x03 0x03>; + interrupt-names = "otg-fail\0otg-overcurrent\0otg-oc-dis-sw-sts\0testmode-change-detect"; + }; + + qcom,bat-if@1200 { + reg = <0x1200 0x100>; + interrupts = <0x02 0x12 0x00 0x01 0x02 0x12 0x01 0x03 0x02 0x12 0x02 0x03 0x02 0x12 0x03 0x03 0x02 0x12 0x04 0x03 0x02 0x12 0x05 0x03>; + interrupt-names = "bat-temp\0bat-ocp\0bat-ov\0bat-low\0bat-therm-or-id-missing\0bat-terminal-missing"; + }; + + qcom,usb-chgpth@1300 { + reg = <0x1300 0x100>; + interrupts = <0x02 0x13 0x00 0x03 0x02 0x13 0x01 0x03 0x02 0x13 0x02 0x03 0x02 0x13 0x03 0x03 0x02 0x13 0x04 0x03 0x02 0x13 0x05 0x01 0x02 0x13 0x06 0x01 0x02 0x13 0x07 0x01>; + interrupt-names = "usbin-collapse\0usbin-lt-3p6v\0usbin-uv\0usbin-ov\0usbin-plugin\0usbin-src-change\0usbin-icl-change\0type-c-change"; + }; + + qcom,dc-chgpth@1400 { + reg = <0x1400 0x100>; + interrupts = <0x02 0x14 0x00 0x03 0x02 0x14 0x01 0x03 0x02 0x14 0x02 0x03 0x02 0x14 0x03 0x03 0x02 0x14 0x04 0x03 0x02 0x14 0x05 0x03 0x02 0x14 0x06 0x01>; + interrupt-names = "dcin-collapse\0dcin-lt-3p6v\0dcin-uv\0dcin-ov\0dcin-plugin\0div2-en-dg\0dcin-icl-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x02 0x16 0x00 0x01 0x02 0x16 0x01 0x01 0x02 0x16 0x02 0x03 0x02 0x16 0x03 0x03 0x02 0x16 0x04 0x03 0x02 0x16 0x05 0x03 0x02 0x16 0x06 0x02 0x02 0x16 0x07 0x03>; + interrupt-names = "wdog-snarl\0wdog-bark\0aicl-fail\0aicl-done\0high-duty-cycle\0input-current-limiting\0temperature-change\0switcher-power-ok"; + }; + + qcom,smb2-vconn { + regulator-name = "smb2-vconn"; + phandle = <0xab>; + }; + + qcom,smb2-vbus { + regulator-name = "smb2-vbus"; + phandle = <0xaa>; + }; + }; + + qcom,usb-pdphy@1700 { + compatible = "qcom,qpnp-pdphy"; + reg = <0x1700 0x100>; + vdd-pdphy-supply = <0xa9>; + vbus-supply = <0xaa>; + vconn-supply = <0xab>; + interrupts = <0x02 0x17 0x00 0x01 0x02 0x17 0x01 0x01 0x02 0x17 0x02 0x01 0x02 0x17 0x03 0x01 0x02 0x17 0x04 0x01 0x02 0x17 0x05 0x01 0x02 0x17 0x06 0x01>; + interrupt-names = "sig-tx\0sig-rx\0msg-tx\0msg-rx\0msg-tx-failed\0msg-tx-discarded\0msg-rx-discarded"; + qcom,default-sink-caps = <0x1388 0xbb8 0x2328 0xbb8 0x2ee0 0x8ca>; + mi,limit_pd_vbus = <0x01>; + mi,pd_vbus_max_limit = <0x895440>; + phandle = <0x36>; + }; + + bcl@4200 { + compatible = "qcom,msm-bcl-lmh"; + reg = <0x4200 0xff 0x4300 0xff>; + reg-names = "fg_user_adc\0fg_lmh"; + interrupts = <0x02 0x42 0x00 0x00 0x02 0x42 0x01 0x00 0x02 0x42 0x02 0x00 0x02 0x42 0x03 0x00 0x02 0x42 0x04 0x00>; + interrupt-names = "bcl-high-ibat\0bcl-very-high-ibat\0bcl-low-vbat\0bcl-very-low-vbat\0bcl-crit-low-vbat"; + #thermal-sensor-cells = <0x01>; + phandle = <0x171>; + }; + + rradc@4500 { + compatible = "qcom,rradc"; + reg = <0x4500 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #io-channel-cells = <0x01>; + qcom,pmic-revid = <0xa6>; + phandle = <0x79>; + }; + + qpnp,fg { + compatible = "qcom,fg-gen3"; + #address-cells = <0x01>; + #size-cells = <0x01>; + qcom,pmic-revid = <0xa6>; + io-channels = <0x79 0x00>; + io-channel-names = "rradc_batt_id"; + qcom,rradc-base = <0x4500>; + qcom,fg-esr-timer-awake = <0x60 0x60>; + qcom,fg-esr-timer-asleep = <0x100 0x100>; + qcom,fg-esr-timer-charging = <0x00 0x60>; + qcom,cycle-counter-en; + qcom,fg-auto-recharge-soc; + qcom,fg-recharge-soc-thr = <0x63>; + status = "okay"; + qcom,fg-force-load-profile; + qcom,fg-sys-term-current = <0xfffffed4>; + qcom,fg-chg-term-current = <0xc8>; + qcom,fg-cutoff-voltage = <0xd48>; + qcom,fg-cutoff-current = <0xc8>; + qcom,fg-empty-voltage = <0xc1c>; + qcom,fg-jeita-hyst-temp = <0x02>; + qcom,fg-jeita-thresholds = <0x00 0x0f 0x2d 0x3c>; + qcom,fg-esr-clamp-mohms = <0x3c>; + qcom,fg-batt-temp-delta = <0x06>; + qcom,battery-data = <0xac>; + + qcom,fg-batt-soc@4000 { + status = "okay"; + reg = <0x4000 0x100>; + interrupts = <0x02 0x40 0x00 0x03 0x02 0x40 0x01 0x03 0x02 0x40 0x02 0x01 0x02 0x40 0x03 0x01 0x02 0x40 0x04 0x03 0x02 0x40 0x05 0x01 0x02 0x40 0x06 0x03 0x02 0x40 0x07 0x03>; + interrupt-names = "soc-update\0soc-ready\0bsoc-delta\0msoc-delta\0msoc-low\0msoc-empty\0msoc-high\0msoc-full"; + }; + + qcom,fg-batt-info@4100 { + status = "okay"; + reg = <0x4100 0x100>; + interrupts = <0x02 0x41 0x00 0x03 0x02 0x41 0x01 0x03 0x02 0x41 0x02 0x03 0x02 0x41 0x03 0x03 0x02 0x41 0x06 0x03>; + interrupt-names = "vbatt-pred-delta\0vbatt-low\0esr-delta\0batt-missing\0batt-temp-delta"; + }; + + qcom,fg-memif@4400 { + status = "okay"; + reg = <0x4400 0x100>; + interrupts = <0x02 0x44 0x00 0x03 0x02 0x44 0x01 0x03 0x02 0x44 0x02 0x01>; + interrupt-names = "ima-rdy\0mem-xcp\0dma-grant"; + }; + }; + }; + + qcom,pmi8998@3 { + compatible = "qcom,spmi-pmic"; + reg = <0x03 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + + pwm@b100 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb100 0x100 0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <0x01>; + qcom,supported-sizes = <0x06 0x09>; + qcom,ramp-index = <0x00>; + #pwm-cells = <0x02>; + status = "okay"; + qcom,period = <0x61a8>; + phandle = <0x80>; + + qcom,pwm { + label = "pwm"; + qcom,duty = <0x9c4>; + }; + }; + + pwm@b200 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb200 0x100 0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <0x02>; + qcom,supported-sizes = <0x06 0x09>; + qcom,ramp-index = <0x01>; + #pwm-cells = <0x02>; + status = "disabled"; + }; + + pwm@b300 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb300 0x100 0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <0x03>; + qcom,supported-sizes = <0x06 0x09>; + qcom,ramp-index = <0x02>; + #pwm-cells = <0x02>; + phandle = <0xaf>; + }; + + pwm@b400 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb400 0x100 0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <0x04>; + qcom,supported-sizes = <0x06 0x09>; + qcom,ramp-index = <0x03>; + #pwm-cells = <0x02>; + phandle = <0xae>; + }; + + pwm@b500 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb500 0x100 0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <0x05>; + qcom,supported-sizes = <0x06 0x09>; + qcom,ramp-index = <0x04>; + #pwm-cells = <0x02>; + phandle = <0xad>; + }; + + pwm@b600 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb600 0x100 0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <0x06>; + qcom,supported-sizes = <0x06 0x09>; + qcom,ramp-index = <0x05>; + #pwm-cells = <0x02>; + status = "disabled"; + }; + + qcom,leds@d000 { + compatible = "qcom,leds-qpnp"; + reg = <0xd000 0x100>; + label = "rgb"; + status = "okay"; + + qcom,rgb_0 { + label = "rgb"; + qcom,id = <0x03>; + qcom,mode = "pwm"; + pwms = <0xad 0x00 0x00>; + qcom,pwm-us = <0x3e8>; + qcom,max-current = <0x0c>; + qcom,default-state = "off"; + linux,name = "white"; + qcom,start-idx = <0x01>; + qcom,idx-len = <0x0b>; + qcom,duty-pcts = [00 05 0a 0f 14 1d 28 32 3c 4b 64]; + qcom,lut-flags = <0x1f>; + qcom,pause-lo = <0x7d0>; + qcom,pause-hi = <0x3e8>; + qcom,ramp-step-ms = <0x64>; + qcom,use-blink; + status = "okay"; + }; + + qcom,rgb_1 { + label = "rgb"; + qcom,id = <0x04>; + qcom,mode = "pwm"; + pwms = <0xae 0x00 0x00>; + qcom,pwm-us = <0x3e8>; + qcom,max-current = <0x0c>; + qcom,default-state = "off"; + linux,name = "green"; + status = "disabled"; + }; + + qcom,rgb_2 { + label = "rgb"; + qcom,id = <0x05>; + qcom,mode = "pwm"; + pwms = <0xaf 0x00 0x00>; + qcom,pwm-us = <0x3e8>; + qcom,max-current = <0x0c>; + qcom,default-state = "off"; + linux,name = "blue"; + status = "disabled"; + }; + }; + + qpnp-labibb-regulator { + compatible = "qcom,qpnp-labibb-regulator"; + #address-cells = <0x01>; + #size-cells = <0x01>; + qcom,pmic-revid = <0xa6>; + status = "ok"; + qcom,qpnp-labibb-mode = "lcd"; + + qcom,ibb@dc00 { + reg = <0xdc00 0x100>; + reg-names = "ibb_reg"; + regulator-name = "ibb_reg"; + regulator-min-microvolt = <0x4630c0>; + regulator-max-microvolt = <0x5b8d80>; + interrupts = <0x03 0xdc 0x02 0x01>; + interrupt-names = "ibb-sc-err"; + qcom,qpnp-ibb-min-voltage = <0x155cc0>; + qcom,qpnp-ibb-step-size = <0x186a0>; + qcom,qpnp-ibb-slew-rate = <0x1e8480>; + qcom,qpnp-ibb-use-default-voltage; + qcom,qpnp-ibb-init-voltage = <0x53ec60>; + qcom,qpnp-ibb-init-amoled-voltage = <0x3d0900>; + qcom,qpnp-ibb-init-lcd-voltage = <0x53ec60>; + qcom,qpnp-ibb-soft-start = <0x3e8>; + qcom,qpnp-ibb-lab-pwrup-delay = <0x3e8>; + qcom,qpnp-ibb-lab-pwrdn-delay = <0x3e8>; + qcom,qpnp-ibb-en-discharge; + qcom,qpnp-ibb-full-pull-down; + qcom,qpnp-ibb-pull-down-enable; + qcom,qpnp-ibb-switching-clock-frequency = <0x5c8>; + qcom,qpnp-ibb-limit-maximum-current = <0x60e>; + qcom,qpnp-ibb-debounce-cycle = <0x10>; + qcom,qpnp-ibb-limit-max-current-enable; + qcom,qpnp-ibb-ps-enable; + qcom,qpnp-ibb-discharge-resistor = <0x12c>; + phandle = <0x8b>; + }; + + qcom,lab@de00 { + reg = <0xde00 0x100>; + reg-names = "lab"; + regulator-name = "lab_reg"; + regulator-min-microvolt = <0x4630c0>; + regulator-max-microvolt = <0x5b8d80>; + interrupts = <0x03 0xde 0x00 0x01 0x03 0xde 0x01 0x01>; + interrupt-names = "lab-vreg-ok\0lab-sc-err"; + qcom,qpnp-lab-min-voltage = <0x4630c0>; + qcom,qpnp-lab-step-size = <0x186a0>; + qcom,qpnp-lab-slew-rate = <0x1388>; + qcom,qpnp-lab-use-default-voltage; + qcom,qpnp-lab-init-voltage = <0x53ec60>; + qcom,qpnp-lab-init-amoled-voltage = <0x4630c0>; + qcom,qpnp-lab-init-lcd-voltage = <0x53ec60>; + qcom,qpnp-lab-soft-start = <0x320>; + qcom,qpnp-lab-full-pull-down; + qcom,qpnp-lab-pull-down-enable; + qcom,qpnp-lab-switching-clock-frequency = <0x640>; + qcom,qpnp-lab-limit-maximum-current = <0x640>; + qcom,qpnp-lab-limit-max-current-enable; + qcom,qpnp-lab-ps-threshold = <0x46>; + qcom,qpnp-lab-ps-enable; + qcom,qpnp-lab-nfet-size = <0x64>; + qcom,qpnp-lab-pfet-size = <0x64>; + qcom,qpnp-lab-max-precharge-time = <0x1f4>; + phandle = <0x8a>; + }; + }; + + qcom,leds@d800 { + compatible = "qcom,qpnp-wled"; + reg = <0xd800 0x100 0xd900 0x100>; + reg-names = "qpnp-wled-ctrl-base\0qpnp-wled-sink-base"; + interrupts = <0x03 0xd8 0x01 0x01 0x03 0xd8 0x02 0x01>; + interrupt-names = "ovp-irq\0sc-irq"; + linux,name = "wled"; + linux,default-trigger = "bkl-trigger"; + qcom,fdbk-output = "auto"; + qcom,vref-uv = <0x1f20c>; + qcom,switch-freq-khz = <0x258>; + qcom,ovp-mv = <0x73a0>; + qcom,ilim-ma = <0x3ca>; + qcom,boost-duty-ns = <0x1a>; + qcom,mod-freq-khz = <0x2580>; + qcom,dim-mode = "hybrid"; + qcom,hyb-thres = <0x271>; + qcom,sync-dly-us = <0x320>; + qcom,fs-curr-ua = <0x4e20>; + qcom,cons-sync-write-delay-us = <0x3e8>; + qcom,led-strings-list = [00 01]; + qcom,en-ext-pfet-sc-pro; + qcom,pmic-revid = <0xa6>; + qcom,loop-auto-gm-en; + status = "okay"; + qcom,en-cabc; + }; + + qcom,leds@d300 { + compatible = "qcom,qpnp-flash-led-v2"; + status = "okay"; + reg = <0xd300 0x100>; + label = "flash"; + interrupts = <0x03 0xd3 0x00 0x01 0x03 0xd3 0x03 0x01 0x03 0xd3 0x04 0x01>; + interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; + qcom,hdrm-auto-mode; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <0xc8 0x1f4 0x3e8>; + qcom,isc-delay = <0xc0>; + qcom,pmic-revid = <0xa6>; + + qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <0x5dc>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0x00>; + qcom,current-ma = <0x3e8>; + qcom,duration-ms = <0x500>; + qcom,ires-ua = <0x30d4>; + qcom,hdrm-voltage-mv = <0x145>; + qcom,hdrm-vol-hi-lo-win-mv = <0x64>; + phandle = <0x36c>; + }; + + qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <0x5dc>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <0x01>; + qcom,current-ma = <0x3e8>; + qcom,duration-ms = <0x500>; + qcom,ires-ua = <0x30d4>; + qcom,hdrm-voltage-mv = <0x145>; + qcom,hdrm-vol-hi-lo-win-mv = <0x64>; + phandle = <0x36d>; + }; + + qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current = <0x2ee>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <0x02>; + qcom,current-ma = <0x1f4>; + qcom,duration-ms = <0x500>; + qcom,ires-ua = <0x30d4>; + qcom,hdrm-voltage-mv = <0x145>; + qcom,hdrm-vol-hi-lo-win-mv = <0x64>; + phandle = <0x371>; + }; + + qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <0x12c>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0x00>; + qcom,current-ma = <0x4b>; + qcom,ires-ua = <0x30d4>; + qcom,hdrm-voltage-mv = <0x145>; + qcom,hdrm-vol-hi-lo-win-mv = <0x64>; + phandle = <0x36e>; + }; + + qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <0x12c>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <0x01>; + qcom,current-ma = <0x4b>; + qcom,ires-ua = <0x30d4>; + qcom,hdrm-voltage-mv = <0x145>; + qcom,hdrm-vol-hi-lo-win-mv = <0x64>; + phandle = <0x36f>; + }; + + qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current = <0x1f4>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <0x02>; + qcom,current-ma = <0x12c>; + qcom,ires-ua = <0x30d4>; + qcom,hdrm-voltage-mv = <0x145>; + qcom,hdrm-vol-hi-lo-win-mv = <0x64>; + phandle = <0x372>; + }; + + qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <0x03>; + qcom,default-led-trigger = "switch0_trigger"; + phandle = <0x370>; + }; + + qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <0x04>; + qcom,default-led-trigger = "switch1_trigger"; + phandle = <0x373>; + }; + + qcom,led_switch_2 { + label = "switch"; + qcom,led-name = "led:switch_2"; + qcom,led-mask = <0x04>; + qcom,default-led-trigger = "switch2_trigger"; + pinctrl-names = "led_enable\0led_disable"; + pinctrl-0 = <0xb0>; + pinctrl-1 = <0xb1>; + }; + + qcom,flashlight { + label = "flash"; + qcom,led-name = "flashlight"; + qcom,max-current = <0x2ee>; + qcom,default-led-trigger = "flashlight_trigger"; + qcom,id = <0x03>; + qcom,current-ma = <0x1f4>; + qcom,duration-ms = <0x500>; + qcom,ires-ua = <0x30d4>; + qcom,hdrm-voltage-mv = <0x145>; + qcom,hdrm-vol-hi-lo-win-mv = <0x64>; + }; + }; + + qcom,haptics@c000 { + compatible = "qcom,qpnp-haptics"; + reg = <0xc000 0x100>; + interrupts = <0x03 0xc0 0x00 0x03 0x03 0xc0 0x01 0x03>; + interrupt-names = "hap-sc-irq\0hap-play-irq"; + qcom,pmic-revid = <0xa6>; + qcom,pmic-misc = <0xb2>; + qcom,misc-clk-trim-error-reg = <0xf3>; + qcom,actuator-type = <0x00>; + qcom,play-mode = "buffer"; + qcom,vmax-mv = <0xafc>; + qcom,ilim-ma = <0x320>; + qcom,sc-dbc-cycles = <0x08>; + qcom,wave-play-rate-us = <0x130e>; + qcom,en-brake; + qcom,lra-high-z = "opt1"; + qcom,lra-auto-res-mode = "qwd"; + qcom,lra-res-cal-period = <0x04>; + status = "okay"; + qcom,lra-auto-mode; + qcom,overdrive; + qcom,wave-shape = "sine"; + qcom,effect-max = <0x03>; + qcom,effect-arry = <0x3e3ebea0 0x00 0x3e3e3ebe 0xbe000000 0x3e3e3e3e 0xbebea090>; + }; + }; + }; + + qcom,spmi-debug@6b22000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x6b22000 0x60 0x7820a8 0x04>; + reg-names = "core\0fuse"; + clocks = <0xa1 0x00>; + clock-names = "core_clk"; + qcom,fuse-disable-bit = <0x0c>; + #address-cells = <0x02>; + #size-cells = <0x00>; + + qcom,pm8998-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x00 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + qcom,can-sleep; + }; + + qcom,pm8998-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x01 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + qcom,can-sleep; + }; + + qcom,pmi8998-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x02 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + qcom,can-sleep; + }; + + qcom,pmi8998-debug@3 { + compatible = "qcom,spmi-pmic"; + reg = <0x03 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + qcom,can-sleep; + }; + + qcom,pm8005-debug@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x04 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + qcom,can-sleep; + }; + + qcom,pm8005-debug@5 { + compatible = "qcom,spmi-pmic"; + reg = <0x05 0x00>; + #address-cells = <0x02>; + #size-cells = <0x00>; + qcom,can-sleep; + }; + }; + + qcom,cpubw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = <0x01 0x302>; + qcom,active-only; + qcom,bw-tbl = <0x8f0 0x11e1 0x1964 0x1fc4 0x23c3 0x300a 0x379c>; + phandle = <0xb3>; + }; + + qcom,cpu-bwmon { + compatible = "qcom,bimc-bwmon4"; + reg = <0x1436400 0x300 0x1436300 0x200>; + reg-names = "base\0global_base"; + interrupts = <0x00 0x245 0x04>; + qcom,mport = <0x00>; + qcom,hw-timer-hz = <0x124f800>; + qcom,target-dev = <0xb3>; + qcom,count-unit = <0x10000>; + }; + + qcom,llccbw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = <0x81 0x200>; + qcom,active-only; + qcom,bw-tbl = <0x2fa 0x478 0x6b8 0x826 0xa25 0xb71 0xf27 0x134f 0x172b 0x1ae1>; + phandle = <0xb4>; + }; + + qcom,llcc-bwmon { + compatible = "qcom,bimc-bwmon5"; + reg = <0x114a000 0x1000>; + reg-names = "base"; + interrupts = <0x00 0x244 0x04>; + qcom,hw-timer-hz = <0x124f800>; + qcom,target-dev = <0xb4>; + qcom,count-unit = <0x400000>; + qcom,byte-mid-mask = <0xe000>; + qcom,byte-mid-match = <0xe000>; + }; + + qcom,memlat-cpu0 { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <0x01 0x200>; + qcom,active-only; + qcom,bw-tbl = <0x2fa 0x478 0x6b8 0x826 0xa25 0xb71 0xf27 0x134f 0x172b 0x1ae1>; + phandle = <0xb5>; + }; + + qcom,memlat-cpu4 { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <0x01 0x200>; + qcom,active-only; + status = "ok"; + qcom,bw-tbl = <0x2fa 0x478 0x6b8 0x826 0xa25 0xb71 0xf27 0x134f 0x172b 0x1ae1>; + phandle = <0xb6>; + }; + + qcom,snoc_cnoc_keepalive { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <0x8b 0x273>; + qcom,active-only; + status = "ok"; + qcom,bw-tbl = <0x01>; + }; + + qcom,cpu0-memlat-mon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <0x11 0x12 0x13 0x14>; + qcom,target-dev = <0xb5>; + qcom,cachemiss-ev = <0x2a>; + qcom,core-dev-table = <0x493e0 0x2fa 0xb6d00 0x6b8 0x114900 0x826 0x15f900 0xb71 0x185100 0xf27>; + }; + + qcom,cpu4-memlat-mon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <0x15 0x16 0x17 0x18>; + qcom,target-dev = <0xb6>; + qcom,cachemiss-ev = <0x2a>; + qcom,core-dev-table = <0x493e0 0x2fa 0x79e00 0x6b8 0xc4e00 0x826 0xfd200 0xb71 0x122a00 0xf27 0x180600 0x134f 0x1a5e00 0x172b 0x1de200 0x1ae1>; + }; + + qcom,l3-cpu0 { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <0xb7 0x03>; + governor = "performance"; + phandle = <0xb8>; + }; + + qcom,l3-cpu4 { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <0xb7 0x04>; + governor = "performance"; + phandle = <0xb9>; + }; + + qcom,cpu0-l3lat-mon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <0x11 0x12 0x13 0x14>; + qcom,target-dev = <0xb8>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <0x493e0 0x11e1a300 0x75300 0x18085800 0x9f600 0x1c9c3800 0xb6d00 0x22551000 0xdc500 0x26e8f000 0xef100 0x2ca1c800 0x114900 0x325aa000 0x12c000 0x38137800 0x143700 0x3dcc5000 0x15ae00 0x43852800 0x172500 0x48190800 0x19c800 0x4dd1e000 0x1af400 0x538ab800>; + }; + + qcom,cpu4-l3lat-mon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <0x15 0x16 0x17 0x18>; + qcom,target-dev = <0xb9>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <0x493e0 0x11e1a300 0xc9900 0x22551000 0x114900 0x2ca1c800 0x14cd00 0x38137800 0x19c800 0x48190800 0x1e7800 0x4dd1e000 0x249f00 0x538ab800 0x29e500 0x5efc6800>; + }; + + qcom,l3-cdsp { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <0xb7 0x0d>; + governor = "powersave"; + phandle = <0xd0>; + }; + + cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <0x01 0x05 0x04>; + }; + + qcom,mincpubw { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <0x01 0x200>; + qcom,active-only; + qcom,bw-tbl = <0x2fa 0x478 0x6b8 0x826 0xa25 0xb71 0xf27 0x134f 0x172b 0x1ae1>; + phandle = <0xba>; + }; + + devfreq-cpufreq { + + mincpubw-cpufreq { + target-dev = <0xba>; + cpu-to-dev-map-0 = <0x1a1300 0x2fa>; + cpu-to-dev-map-4 = <0x1cb600 0x2fa 0x249f00 0xf27>; + }; + }; + + qcom,devfreq-compute { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <0x15 0x16 0x17 0x18>; + qcom,target-dev = <0xba>; + qcom,core-dev-table = <0x1cb600 0x2fa 0x286e00 0xf27 0x29e500 0x1ae1>; + }; + + qcom,rpmhclk { + compatible = "qcom,rpmh-clk-sdm845"; + #clock-cells = <0x01>; + mboxes = <0xbb 0x00>; + mbox-names = "apps"; + phandle = <0x21>; + }; + + qcom,gcc@100000 { + compatible = "qcom,gcc-sdm845-v2.1\0syscon"; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <0x1b>; + vdd_cx_ao-supply = <0xbc>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0x22>; + }; + + qcom,videocc@ab00000 { + compatible = "qcom,video_cc-sdm845-v2\0syscon"; + reg = <0xab00000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <0x1b>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0xd5>; + }; + + qcom,camcc@ad00000 { + compatible = "qcom,cam_cc-sdm845-v2\0syscon"; + reg = <0xad00000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <0x1b>; + vdd_mx-supply = <0xbd>; + qcom,cam_cc_csi0phytimer_clk_src-opp-handle = <0xbe>; + qcom,cam_cc_csi1phytimer_clk_src-opp-handle = <0xbf>; + qcom,cam_cc_csi2phytimer_clk_src-opp-handle = <0xc0>; + qcom,cam_cc_cci_clk_src-opp-handle = <0xc1>; + qcom,cam_cc_ife_0_csid_clk_src-opp-handle = <0xc2>; + qcom,cam_cc_ife_0_clk_src-opp-handle = <0xc3>; + qcom,cam_cc_ife_1_csid_clk_src-opp-handle = <0xc4>; + qcom,cam_cc_ife_1_clk_src-opp-handle = <0xc5>; + qcom,cam_cc_ife_lite_csid_clk_src-opp-handle = <0xc6>; + qcom,cam_cc_ife_lite_clk_src-opp-handle = <0xc7>; + qcom,cam_cc_icp_clk_src-opp-handle = <0xc8>; + qcom,cam_cc_ipe_0_clk_src-opp-handle = <0xc9>; + qcom,cam_cc_ipe_1_clk_src-opp-handle = <0xca>; + qcom,cam_cc_bps_clk_src-opp-handle = <0xcb>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + qcom,cam_cc_csi3phytimer_clk_src-opp-handle = <0xcc>; + phandle = <0xd6>; + }; + + qcom,dispcc@af00000 { + compatible = "qcom,dispcc-sdm845-v2\0syscon"; + reg = <0xaf00000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <0x1b>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0x20>; + }; + + qcom,gpucc@5090000 { + compatible = "qcom,gpucc-sdm845-v2\0syscon"; + reg = <0x5090000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <0x1b>; + vdd_mx-supply = <0xbd>; + qcom,gpu_cc_gmu_clk_src-opp-handle = <0xcd>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0xd7>; + }; + + qcom,gfxcc@5090000 { + compatible = "qcom,gfxcc-sdm845-v2"; + reg = <0x5090000 0x9000>; + reg-names = "cc_base"; + vdd_gfx-supply = <0x1d>; + qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <0xce>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0x1c>; + }; + + syscon@17970018 { + compatible = "syscon"; + reg = <0x17970018 0x04>; + phandle = <0xd8>; + }; + + qcom,cpucc@0x17d41000 { + compatible = "qcom,clk-cpu-osm-v2"; + reg = <0x17d41000 0x1400 0x17d43000 0x1400 0x17d45800 0x1400>; + reg-names = "osm_l3_base\0osm_pwrcl_base\0osm_perfcl_base"; + vdd_l3_mx_ao-supply = <0xcf>; + vdd_pwrcl_mx_ao-supply = <0xcf>; + qcom,mx-turbo-freq = <0x581e9800 0x64b54000 0xc4b20101>; + l3-devs = <0xb8 0xb9 0xd0 0xce>; + clock-names = "xo_ao"; + clocks = <0x21 0x01>; + #clock-cells = <0x01>; + phandle = <0xb7>; + + qcom,limits-dcvs@0 { + compatible = "qcom,msm-hw-limits"; + interrupts = <0x00 0x20 0x04>; + qcom,affinity = <0x00>; + #thermal-sensor-cells = <0x00>; + phandle = <0x02>; + }; + + qcom,limits-dcvs@1 { + compatible = "qcom,msm-hw-limits"; + interrupts = <0x00 0x21 0x04>; + qcom,affinity = <0x01>; + #thermal-sensor-cells = <0x00>; + isens_vref-supply = <0xd1>; + isens-vref-settings = <0xd6d80 0xd6d80 0x4e20>; + phandle = <0x0a>; + }; + + qcom,wil6210 { + compatible = "qcom,wil6210"; + qcom,pcie-parent = <0xd2>; + qcom,wigig-en = <0x3c 0x27 0x00>; + qcom,msm-bus,name = "wil6210"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x2d 0x200 0x00 0x00 0x2d 0x200 0x927c0 0xc3500>; + qcom,use-ext-supply; + vdd-supply = <0xd3>; + vddio-supply = <0xd4>; + qcom,use-ext-clocks; + clocks = <0x21 0x0a 0x21 0x0b>; + clock-names = "rf_clk3_clk\0rf_clk3_pin_clk"; + qcom,smmu-support; + qcom,smmu-mapping = <0x20000000 0xe0000000>; + qcom,smmu-s1-en; + qcom,smmu-fast-map; + qcom,smmu-coherent; + qcom,keep-radio-on-during-sleep; + status = "ok"; + }; + }; + + qcom,cc-debug@100000 { + compatible = "qcom,debugcc-sdm845"; + qcom,cc-count = <0x06>; + qcom,gcc = <0x22>; + qcom,videocc = <0xd5>; + qcom,camcc = <0xd6>; + qcom,dispcc = <0x20>; + qcom,gpucc = <0xd7>; + qcom,cpucc = <0xd8>; + clock-names = "xo_clk_src"; + clocks = <0x21 0x00>; + #clock-cells = <0x01>; + }; + + qcom,aopclk { + compatible = "qcom,aop-qmp-clk-v1"; + #clock-cells = <0x01>; + mboxes = <0xa3 0x00>; + mbox-names = "qdss_clk"; + phandle = <0xa1>; + }; + + ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk\0bus_clk\0iface_clk\0ice_core_clk"; + clocks = <0x22 0x8a 0x22 0x88 0x22 0x89 0x22 0x8c>; + qcom,op-freq-hz = <0x00 0x00 0x00 0x11e1a300>; + vdd-hba-supply = <0xd9>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x01 0x28a 0x00 0x00 0x01 0x28a 0x3e8 0x00>; + qcom,bus-vector-names = "MIN\0MAX"; + qcom,instance-type = "ufs"; + phandle = <0xdb>; + }; + + ufsphy_mem@1d87000 { + reg = <0x1d87000 0xda8>; + reg-names = "phy_mem"; + #phy-cells = <0x00>; + lanes-per-direction = <0x02>; + clock-names = "ref_clk_src\0ref_clk\0ref_aux_clk"; + clocks = <0x21 0x00 0x22 0x88 0x22 0xb9>; + status = "ok"; + compatible = "qcom,ufs-phy-qmp-v3"; + vdda-phy-supply = <0x34>; + vdda-pll-supply = <0x33>; + vdda-phy-max-microamp = <0xf5b4>; + vdda-pll-max-microamp = <0x477c>; + phandle = <0xda>; + }; + + ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x2500>; + interrupts = <0x00 0x109 0x00>; + phys = <0xda>; + phy-names = "ufsphy"; + ufs-qcom-crypto = <0xdb>; + lanes-per-direction = <0x02>; + dev-ref-clk-freq = <0x00>; + clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk\0rx_lane1_sync_clk"; + clocks = <0x22 0xb1 0x22 0xb7 0x22 0x89 0x22 0xb3 0x22 0xb5 0x21 0x00 0x22 0x92 0x22 0x90 0x22 0x91>; + freq-table-hz = <0x2faf080 0xbebc200 0x00 0x00 0x00 0x00 0x23c3460 0x8f0d180 0x47868c0 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + non-removable; + qcom,msm-bus,name = "ufshc_mem"; + qcom,msm-bus,num-cases = <0x16>; + qcom,msm-bus,num-paths = <0x02>; + qcom,msm-bus,vectors-KBps = <0x7b 0x200 0x00 0x00 0x01 0x2f5 0x00 0x00 0x7b 0x200 0x39a 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x734 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0xe68 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1cd0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x734 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0xe68 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1cd0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x39a0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1f334 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x3e667 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x3e667 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x7cccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x400000 0x00 0x01 0x2f5 0x32000 0x00 0x7b 0x200 0x247ae 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x48ccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x48ccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x9199a 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x400000 0x00 0x01 0x2f5 0x32000 0x64000 0x7b 0x200 0x74a000 0x00 0x01 0x2f5 0x4b000 0x00>; + qcom,bus-vector-names = "MIN\0PWM_G1_L1\0PWM_G2_L1\0PWM_G3_L1\0PWM_G4_L1\0PWM_G1_L2\0PWM_G2_L2\0PWM_G3_L2\0PWM_G4_L2\0HS_RA_G1_L1\0HS_RA_G2_L1\0HS_RA_G3_L1\0HS_RA_G1_L2\0HS_RA_G2_L2\0HS_RA_G3_L2\0HS_RB_G1_L1\0HS_RB_G2_L1\0HS_RB_G3_L1\0HS_RB_G1_L2\0HS_RB_G2_L2\0HS_RB_G3_L2\0MAX"; + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cpu-group-latency-us = <0x64 0x64>; + qcom,pm-qos-default-cpu = <0x00>; + pinctrl-names = "dev-reset-assert\0dev-reset-deassert"; + pinctrl-0 = <0xdc>; + pinctrl-1 = <0xdd>; + resets = <0x22 0x0e>; + reset-names = "core_reset"; + status = "ok"; + vdd-hba-supply = <0xd9>; + vdd-hba-fixed-regulator; + vcc-supply = <0xde>; + vcc-voltage-level = <0x2d0370 0x2d2a80>; + vccq2-supply = <0xdf>; + vcc-max-microamp = <0x927c0>; + vccq2-max-microamp = <0x927c0>; + qcom,vddp-ref-clk-supply = <0xe0>; + qcom,vddp-ref-clk-max-microamp = <0x64>; + }; + + sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + interrupts = <0x00 0xcc 0x00 0x00 0xde 0x00>; + interrupt-names = "hc_irq\0pwr_irq"; + qcom,bus-width = <0x04>; + qcom,large-address-bus; + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <0x08>; + qcom,msm-bus,num-paths = <0x02>; + qcom,msm-bus,vectors-KBps = <0x51 0x200 0x00 0x00 0x01 0x260 0x00 0x00 0x51 0x200 0x416 0x640 0x01 0x260 0x640 0x640 0x51 0x200 0xcc3e 0x13880 0x01 0x260 0x13880 0x13880 0x51 0x200 0xff50 0x186a0 0x01 0x260 0x186a0 0x186a0 0x51 0x200 0x1fe9e 0x30d40 0x01 0x260 0x208c8 0x208c8 0x51 0x200 0x3fd3e 0x30d40 0x01 0x260 0x249f0 0x249f0 0x51 0x200 0x3fd3e 0x61a80 0x01 0x260 0x493e0 0x493e0 0x51 0x200 0x146cc2 0x3e8000 0x01 0x260 0x146cc2 0x3e8000>; + qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x60152b0 0xbebc200 0xffffffff>; + qcom,restore-after-cx-collapse; + qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xc02a560>; + qcom,bus-speed-mode = "SDR12\0SDR25\0SDR50\0DDR50\0SDR104"; + qcom,devfreq,freq-table = <0x2faf080 0xc02a560>; + clocks = <0x22 0x70 0x22 0x71>; + clock-names = "iface_clk\0core_clk"; + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <0x46 0x46>; + qcom,pm-qos-cpu-groups = <0x3f 0xc0>; + qcom,pm-qos-legacy-latency-us = <0x46 0x46 0x46 0x46>; + status = "ok"; + vdd-supply = <0xe1>; + qcom,vdd-voltage-level = <0x2d0370 0x2d2a80>; + qcom,vdd-current-level = <0xc8 0xc3500>; + vdd-io-supply = <0xe2>; + qcom,vdd-io-voltage-level = <0x1b9680 0x2d2a80>; + qcom,vdd-io-current-level = <0xc8 0x55f0>; + pinctrl-names = "active\0sleep\0ds_400KHz\0ds_50MHz\0ds_100MHz\0ds_200MHz"; + pinctrl-0 = <0xe3 0xe4 0xe5 0xe6>; + pinctrl-1 = <0xe7 0xe8 0xe9 0xe6>; + pinctrl-2 = <0xea 0xeb 0xec>; + pinctrl-3 = <0xed 0xee 0xef>; + pinctrl-4 = <0xf0 0xf1 0xf2>; + pinctrl-5 = <0xf3 0xf4 0xf5>; + cd-gpios = <0x3c 0x7e 0x00>; + }; + + qcom,mss@4080000 { + compatible = "qcom,pil-q6v55-mss"; + reg = <0x4080000 0x100 0x1f63000 0x08 0x1f65000 0x08 0x1f64000 0x08 0x4180000 0x20 0xc2b0000 0x04 0xb2e0100 0x04 0x4180044 0x04>; + reg-names = "qdsp6_base\0halt_q6\0halt_modem\0halt_nc\0rmb_base\0restart_reg\0pdc_sync\0alt_reset"; + clocks = <0x21 0x00 0x22 0x2c 0x22 0x2f 0x22 0x0b 0x22 0x2d 0x22 0x30 0x22 0x2e 0x22 0x48>; + clock-names = "xo\0iface_clk\0bus_clk\0mem_clk\0gpll0_mss_clk\0snoc_axi_clk\0mnoc_axi_clk\0prng_clk"; + qcom,proxy-clock-names = "xo\0prng_clk"; + qcom,active-clock-names = "iface_clk\0bus_clk\0mem_clk\0gpll0_mss_clk\0snoc_axi_clk\0mnoc_axi_clk"; + interrupts = <0x00 0x10a 0x01>; + vdd_cx-supply = <0x1b>; + vdd_cx-voltage = <0x181>; + vdd_mx-supply = <0xbd>; + vdd_mx-uV = <0x181>; + vdd_mss-supply = <0xf6>; + vdd_mss-uV = <0x181>; + qcom,firmware-name = "modem"; + qcom,sequential-fw-load; + qcom,pil-self-auth; + qcom,sysmon-id = <0x00>; + qcom,minidump-id = <0x03>; + qcom,ssctl-instance-id = <0x12>; + qcom,override-acc; + qcom,signal-aop; + qcom,qdsp6v65-1-0; + qcom,mss_pdc_offset = <0x09>; + status = "ok"; + memory-region = <0xf7>; + qcom,mem-protect-id = <0x0f>; + qcom,gpio-err-fatal = <0xf8 0x00 0x00>; + qcom,gpio-err-ready = <0xf8 0x01 0x00>; + qcom,gpio-proxy-unvote = <0xf8 0x02 0x00>; + qcom,gpio-stop-ack = <0xf8 0x03 0x00>; + qcom,gpio-shutdown-ack = <0xf8 0x07 0x00>; + qcom,gpio-force-stop = <0xf9 0x00 0x00>; + mboxes = <0xa3 0x00>; + mbox-names = "mss-pil"; + + qcom,mba-mem@0 { + compatible = "qcom,pil-mba-mem"; + memory-region = <0xfa>; + }; + }; + + qcom,lpass@17300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x17300000 0x100>; + interrupts = <0x00 0xa2 0x01>; + vdd_cx-supply = <0x1b>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = <0x181 0x186a0>; + clocks = <0x21 0x00>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pas-id = <0x01>; + qcom,proxy-timeout-ms = <0x2710>; + qcom,smem-id = <0x1a7>; + qcom,sysmon-id = <0x01>; + status = "ok"; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + qcom,signal-aop; + memory-region = <0xfb>; + qcom,gpio-err-fatal = <0xfc 0x00 0x00>; + qcom,gpio-proxy-unvote = <0xfc 0x02 0x00>; + qcom,gpio-err-ready = <0xfc 0x01 0x00>; + qcom,gpio-stop-ack = <0xfc 0x03 0x00>; + qcom,gpio-force-stop = <0xfd 0x00 0x00>; + mboxes = <0xa3 0x00>; + mbox-names = "adsp-pil"; + }; + + qcom,ssc@5c00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5c00000 0x4000>; + interrupts = <0x00 0x1ee 0x01>; + vdd_cx-supply = <0xfe>; + qcom,vdd_cx-uV-uA = <0x181 0x00>; + vdd_mx-supply = <0xff>; + qcom,vdd_mx-uV-uA = <0x181 0x00>; + qcom,proxy-reg-names = "vdd_cx\0vdd_mx"; + qcom,keep-proxy-regs-on; + clocks = <0x21 0x00>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pas-id = <0x0c>; + qcom,proxy-timeout-ms = <0x2710>; + qcom,smem-id = <0x1a8>; + qcom,sysmon-id = <0x03>; + qcom,ssctl-instance-id = <0x16>; + qcom,signal-aop; + qcom,firmware-name = "slpi"; + status = "ok"; + memory-region = <0x100>; + qcom,gpio-err-fatal = <0x101 0x00 0x00>; + qcom,gpio-proxy-unvote = <0x101 0x02 0x00>; + qcom,gpio-err-ready = <0x101 0x01 0x00>; + qcom,gpio-stop-ack = <0x101 0x03 0x00>; + qcom,gpio-force-stop = <0x102 0x00 0x00>; + mboxes = <0xa3 0x00>; + mbox-names = "slpi-pil"; + }; + + slim@171c0000 { + cell-index = <0x01>; + compatible = "qcom,slim-ngd"; + reg = <0x171c0000 0x2c000 0x17184000 0x2a000>; + reg-names = "slimbus_physical\0slimbus_bam_physical"; + interrupts = <0x00 0xa3 0x00 0x00 0xa4 0x00>; + interrupt-names = "slimbus_irq\0slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x780000>; + qcom,ea-pc = <0x270>; + qcom,iommu-s1-bypass; + + qcom,iommu_slim_ctrl_cb { + compatible = "qcom,iommu-slim-ctrl-cb"; + iommus = <0x29 0x1806 0x00 0x29 0x180d 0x00 0x29 0x180e 0x01 0x29 0x1810 0x01>; + }; + + msm_dai_slim { + compatible = "qcom,msm-dai-slim"; + elemental-addr = [ff ff ff fe 17 02]; + }; + + tavil_codec { + compatible = "qcom,tavil-slim-pgd"; + elemental-addr = [00 01 50 02 17 02]; + interrupt-parent = <0x103>; + interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>; + qcom,wcd-rst-gpio-node = <0x104>; + clock-names = "wcd_clk"; + clocks = <0x105 0x00>; + cdc-vdd-buck-supply = <0xdf>; + qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>; + qcom,cdc-vdd-buck-current = <0x9eb10>; + cdc-buck-sido-supply = <0xdf>; + qcom,cdc-buck-sido-voltage = <0x1b7740 0x1b7740>; + qcom,cdc-buck-sido-current = <0x3d090>; + cdc-vdd-tx-h-supply = <0xdf>; + qcom,cdc-vdd-tx-h-voltage = <0x1b7740 0x1b7740>; + qcom,cdc-vdd-tx-h-current = <0x61a8>; + cdc-vdd-rx-h-supply = <0xdf>; + qcom,cdc-vdd-rx-h-voltage = <0x1b7740 0x1b7740>; + qcom,cdc-vdd-rx-h-current = <0x61a8>; + cdc-vddpx-1-supply = <0xdf>; + qcom,cdc-vddpx-1-voltage = <0x1b7740 0x1b7740>; + qcom,cdc-vddpx-1-current = <0x2710>; + qcom,cdc-static-supplies = "cdc-vdd-buck\0cdc-buck-sido\0cdc-vdd-tx-h\0cdc-vdd-rx-h\0cdc-vddpx-1"; + qcom,cdc-micbias1-mv = <0xa8c>; + qcom,cdc-micbias2-mv = <0x708>; + qcom,cdc-micbias3-mv = <0xa8c>; + qcom,cdc-micbias4-mv = <0xa8c>; + qcom,cdc-mclk-clk-rate = <0x927c00>; + qcom,cdc-slim-ifd = "tavil-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; + qcom,cdc-dmic-sample-rate = <0x493e00>; + qcom,cdc-mad-dmic-rate = <0x927c0>; + qcom,wdsp-cmpnt-dev-name = "tavil_codec"; + phandle = <0x37c>; + + wcd_pinctrl@5 { + compatible = "qcom,wcd-pinctrl"; + qcom,num-gpios = <0x05>; + gpio-controller; + #gpio-cells = <0x02>; + + us_euro_sw_wcd_active { + phandle = <0x10a>; + + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-high; + }; + }; + + us_euro_sw_wcd_sleep { + phandle = <0x10b>; + + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-low; + }; + }; + + spkr_1_wcd_en_active { + phandle = <0x106>; + + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spkr_1_wcd_en_sleep { + phandle = <0x107>; + + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spkr_2_sd_n_active { + phandle = <0x108>; + + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spkr_2_sd_n_sleep { + phandle = <0x109>; + + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + + hph_en0_wcd_active { + phandle = <0x10c>; + + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-high; + }; + }; + + hph_en0_wcd_sleep { + phandle = <0x10d>; + + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-low; + }; + }; + + hph_en1_wcd_active { + phandle = <0x10e>; + + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-high; + }; + }; + + hph_en1_wcd_sleep { + phandle = <0x10f>; + + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-low; + }; + }; + }; + + msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x106>; + pinctrl-1 = <0x107>; + phandle = <0x110>; + }; + + msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x108>; + pinctrl-1 = <0x109>; + phandle = <0x111>; + }; + + msm_cdc_pinctrl_us_euro_sw { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x10a>; + pinctrl-1 = <0x10b>; + }; + + msm_cdc_pinctrl_hph_en0 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x10c>; + pinctrl-1 = <0x10d>; + phandle = <0x31e>; + }; + + msm_cdc_pinctrl_hph_en1 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x10e>; + pinctrl-1 = <0x10f>; + phandle = <0x31f>; + }; + + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <0x02>; + #size-cells = <0x00>; + + wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <0x110>; + status = "disabled"; + phandle = <0x325>; + }; + + wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <0x111>; + status = "disabled"; + phandle = <0x326>; + }; + + wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <0x110>; + status = "disabled"; + phandle = <0x327>; + }; + + wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <0x111>; + status = "disabled"; + phandle = <0x328>; + }; + }; + + wcd_spi { + compatible = "qcom,wcd-spi-v2"; + qcom,master-bus-num = <0x00>; + qcom,chip-select = <0x00>; + qcom,max-frequency = <0x16e3600>; + qcom,mem-base-addr = <0x100000>; + phandle = <0x37d>; + }; + }; + }; + + slim@17240000 { + status = "ok"; + cell-index = <0x03>; + compatible = "qcom,slim-ngd"; + reg = <0x17240000 0x2c000 0x17204000 0x20000>; + reg-names = "slimbus_physical\0slimbus_bam_physical"; + interrupts = <0x00 0x123 0x00 0x00 0x124 0x00>; + interrupt-names = "slimbus_irq\0slimbus_bam_irq"; + qcom,iommu-s1-bypass; + + qcom,iommu_slim_ctrl_cb { + compatible = "qcom,iommu-slim-ctrl-cb"; + iommus = <0x29 0x1813 0x00>; + }; + + wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + qcom,msm-eud@88e0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = <0x00 0x1ec 0x04>; + reg = <0x88e0000 0x2000>; + reg-names = "eud_base"; + clocks = <0x22 0xa9>; + clock-names = "cfg_ahb_clk"; + vdda33-supply = <0xa9>; + status = "ok"; + phandle = <0x33a>; + }; + + qcom,spss@1880000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x188101c 0x04 0x1881024 0x04 0x1881028 0x04 0x188103c 0x04 0x1882014 0x04>; + reg-names = "sp2soc_irq_status\0sp2soc_irq_clr\0sp2soc_irq_mask\0rmb_err\0rmb_err_spare2"; + interrupts = <0x00 0x160 0x01>; + vdd_cx-supply = <0x1b>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = <0x181 0x186a0>; + vdd_mx-supply = <0xbd>; + vdd_mx-uV = <0x181 0x186a0>; + clocks = <0x21 0x00>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pil-generic-irq-handler; + status = "ok"; + qcom,pas-id = <0x0e>; + qcom,proxy-timeout-ms = <0x2710>; + qcom,signal-aop; + qcom,firmware-name = "spss"; + memory-region = <0x112>; + qcom,spss-scsr-bits = <0x18 0x19>; + mboxes = <0xa3 0x00>; + mbox-names = "spss-pil"; + }; + + qcom,wdt@17980000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17980000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0x00 0x00 0x00 0x00 0x01 0x00>; + qcom,bark-time = <0x4e20>; + qcom,pet-time = <0x3a98>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + interrupts = <0x00 0x242 0x01>; + vdd_cx-supply = <0x1b>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = <0x181 0x186a0>; + clocks = <0x21 0x00>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pas-id = <0x12>; + qcom,proxy-timeout-ms = <0x2710>; + qcom,smem-id = <0x259>; + qcom,sysmon-id = <0x07>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + qcom,signal-aop; + memory-region = <0x113>; + qcom,gpio-err-fatal = <0x114 0x00 0x00>; + qcom,gpio-proxy-unvote = <0x114 0x02 0x00>; + qcom,gpio-err-ready = <0x114 0x01 0x00>; + qcom,gpio-stop-ack = <0x114 0x03 0x00>; + qcom,gpio-force-stop = <0x115 0x00 0x00>; + status = "ok"; + mboxes = <0xa3 0x00>; + mbox-names = "cdsp-pil"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,mpm2-sleep-counter@0x0c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <0x8000>; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <0x116>; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <0x263>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <0x29 0x1401 0x30>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <0x29 0x1402 0x30>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <0x29 0x1403 0x30>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <0x29 0x1404 0x30>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <0x29 0x1405 0x30>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <0x29 0x1406 0x30>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <0x29 0x1407 0x30>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <0x29 0x1408 0x30>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <0x29 0x1409 0x30>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <0x29 0x140a 0x30>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <0x29 0x1823 0x00>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <0x29 0x1824 0x00>; + dma-coherent; + }; + }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x00 0x146bf000 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x08>; + }; + + dload_type@18 { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x18 0x04>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x04>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x04>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0x0c>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + qcom,venus@aae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaae0000 0x4000>; + vdd-supply = <0x117>; + qcom,proxy-reg-names = "vdd"; + clocks = <0xd5 0x0b 0xd5 0x08 0xd5 0x0a>; + clock-names = "core_clk\0iface_clk\0bus_clk"; + qcom,proxy-clock-names = "core_clk\0iface_clk\0bus_clk"; + qcom,pas-id = <0x09>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x3f 0x200 0x00 0x00 0x3f 0x200 0x00 0x4a380>; + qcom,proxy-timeout-ms = <0x64>; + qcom,firmware-name = "venus"; + memory-region = <0x118>; + status = "ok"; + }; + + qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + qcom,firmware-name = "slpi_br"; + }; + + cpuss_dump { + compatible = "qcom,cpuss-dump"; + + qcom,l1_i_cache0 { + qcom,dump-node = <0x119>; + qcom,dump-id = <0x60>; + }; + + qcom,l1_i_cache1 { + qcom,dump-node = <0x11a>; + qcom,dump-id = <0x61>; + }; + + qcom,l1_i_cache2 { + qcom,dump-node = <0x11b>; + qcom,dump-id = <0x62>; + }; + + qcom,l1_i_cache3 { + qcom,dump-node = <0x11c>; + qcom,dump-id = <0x63>; + }; + + qcom,l1_i_cache100 { + qcom,dump-node = <0x11d>; + qcom,dump-id = <0x64>; + }; + + qcom,l1_i_cache101 { + qcom,dump-node = <0x11e>; + qcom,dump-id = <0x65>; + }; + + qcom,l1_i_cache102 { + qcom,dump-node = <0x11f>; + qcom,dump-id = <0x66>; + }; + + qcom,l1_i_cache103 { + qcom,dump-node = <0x120>; + qcom,dump-id = <0x67>; + }; + + qcom,l1_d_cache0 { + qcom,dump-node = <0x121>; + qcom,dump-id = <0x80>; + }; + + qcom,l1_d_cache1 { + qcom,dump-node = <0x122>; + qcom,dump-id = <0x81>; + }; + + qcom,l1_d_cache2 { + qcom,dump-node = <0x123>; + qcom,dump-id = <0x82>; + }; + + qcom,l1_d_cache3 { + qcom,dump-node = <0x124>; + qcom,dump-id = <0x83>; + }; + + qcom,l1_d_cache100 { + qcom,dump-node = <0x125>; + qcom,dump-id = <0x84>; + }; + + qcom,l1_d_cache101 { + qcom,dump-node = <0x126>; + qcom,dump-id = <0x85>; + }; + + qcom,l1_d_cache102 { + qcom,dump-node = <0x127>; + qcom,dump-id = <0x86>; + }; + + qcom,l1_d_cache103 { + qcom,dump-node = <0x128>; + qcom,dump-id = <0x87>; + }; + + qcom,llcc1_d_cache { + qcom,dump-node = <0x129>; + qcom,dump-id = <0x140>; + }; + + qcom,llcc2_d_cache { + qcom,dump-node = <0x12a>; + qcom,dump-id = <0x141>; + }; + + qcom,llcc3_d_cache { + qcom,dump-node = <0x12b>; + qcom,dump-id = <0x142>; + }; + + qcom,llcc4_d_cache { + qcom,dump-node = <0x12c>; + qcom,dump-id = <0x143>; + }; + + qcom,l1_tlb_dump0 { + qcom,dump-node = <0x12d>; + qcom,dump-id = <0x120>; + }; + + qcom,l1_tlb_dump100 { + qcom,dump-node = <0x12e>; + qcom,dump-id = <0x121>; + }; + + qcom,l1_tlb_dump200 { + qcom,dump-node = <0x12f>; + qcom,dump-id = <0x122>; + }; + + qcom,l1_tlb_dump300 { + qcom,dump-node = <0x130>; + qcom,dump-id = <0x123>; + }; + + qcom,l1_tlb_dump400 { + qcom,dump-node = <0x131>; + qcom,dump-id = <0x124>; + }; + + qcom,l1_tlb_dump500 { + qcom,dump-node = <0x132>; + qcom,dump-id = <0x125>; + }; + + qcom,l1_tlb_dump600 { + qcom,dump-node = <0x133>; + qcom,dump-id = <0x126>; + }; + + qcom,l1_tlb_dump700 { + qcom,dump-node = <0x134>; + qcom,dump-id = <0x127>; + }; + }; + + kryo3xx-erp { + compatible = "arm,arm64-kryo3xx-cpu-erp"; + interrupts = <0x01 0x06 0x04 0x01 0x07 0x04 0x00 0x22 0x04 0x00 0x23 0x04>; + interrupt-names = "l1-l2-faultirq\0l1-l2-errirq\0l3-scu-errirq\0l3-scu-faultirq"; + }; + + qcom,llcc@1100000 { + compatible = "qcom,llcc-core\0syscon\0simple-mfd"; + reg = <0x1100000 0x250000>; + reg-names = "llcc_base"; + qcom,llcc-banks-off = <0x00 0x80000 0x100000 0x180000>; + qcom,llcc-broadcast-off = <0x200000>; + + qcom,sdm845-llcc { + compatible = "qcom,sdm845-llcc"; + #cache-cells = <0x01>; + max-slices = <0x20>; + phandle = <0x32>; + }; + + qcom,llcc-perfmon { + compatible = "qcom,llcc-perfmon"; + }; + + qcom,llcc-erp { + compatible = "qcom,llcc-erp"; + interrupt-names = "ecc_irq"; + interrupts = <0x00 0x246 0x04>; + }; + + qcom,llcc-amon { + compatible = "qcom,llcc-amon"; + }; + + llcc_1_dcache { + qcom,dump-size = <0x1141c0>; + phandle = <0x129>; + }; + + llcc_2_dcache { + qcom,dump-size = <0x1141c0>; + phandle = <0x12a>; + }; + + llcc_3_dcache { + qcom,dump-size = <0x1141c0>; + phandle = <0x12b>; + }; + + llcc_4_dcache { + qcom,dump-size = <0x1141c0>; + phandle = <0x12c>; + }; + }; + + qcom,ipc-spinlock@1f40000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0x1f40000 0x8000>; + qcom,num-locks = <0x08>; + }; + + qcom,smem@86000000 { + compatible = "qcom,smem"; + reg = <0x86000000 0x200000 0x17911008 0x04 0x778000 0x7000 0x1fd4000 0x08>; + reg-names = "smem\0irq-reg-base\0aux-mem1\0smem_targ_info_reg"; + qcom,mpu-enabled; + }; + + qcom,glink-mailbox-xprt-spss@1885008 { + compatible = "qcom,glink-mailbox-xprt"; + reg = <0x1885008 0x08 0x1885010 0x04 0x188501c 0x04 0x1886008 0x04>; + reg-names = "mbox-loc-addr\0mbox-loc-size\0irq-reg-base\0irq-rx-reset"; + qcom,irq-mask = <0x01>; + interrupts = <0x00 0x15c 0x04>; + label = "spss"; + qcom,tx-ring-size = <0x400>; + qcom,rx-ring-size = <0x400>; + }; + + qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + label = "aop"; + reg = <0xc300000 0x100000 0x1799000c 0x04>; + reg-names = "msgram\0irq-reg-base"; + qcom,irq-mask = <0x01>; + interrupts = <0x00 0x185 0x01>; + priority = <0x00>; + mbox-desc-offset = <0x00>; + #mbox-cells = <0x01>; + phandle = <0xa3>; + }; + + mailbox@179e0000 { + compatible = "qcom,tcs-drv"; + label = "apps_rsc"; + reg = <0x179e0000 0x100 0x179e0d00 0x3000>; + interrupts = <0x00 0x05 0x00>; + #mbox-cells = <0x01>; + qcom,drv-id = <0x02>; + qcom,tcs-config = <0x02 0x02 0x00 0x03 0x01 0x03 0x03 0x01>; + phandle = <0xbb>; + }; + + mailbox@af20000 { + compatible = "qcom,tcs-drv"; + label = "display_rsc"; + reg = <0xaf20000 0x100 0xaf21c00 0x3000>; + interrupts = <0x00 0x81 0x00>; + #mbox-cells = <0x01>; + qcom,drv-id = <0x00>; + qcom,tcs-config = <0x00 0x01 0x01 0x01 0x02 0x00 0x03 0x01>; + phandle = <0x30>; + }; + + system_pm { + compatible = "qcom,system-pm"; + mboxes = <0xbb 0x00>; + }; + + qcom,glink-smem-native-xprt-modem@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000 0x1799000c 0x04>; + reg-names = "smem\0irq-reg-base"; + qcom,irq-mask = <0x1000>; + interrupts = <0x00 0x1c1 0x01>; + label = "mpss"; + }; + + qcom,glink-smem-native-xprt-adsp@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000 0x1799000c 0x04>; + reg-names = "smem\0irq-reg-base"; + qcom,irq-mask = <0x100>; + interrupts = <0x00 0x9c 0x01>; + label = "lpass"; + cpu-affinity = <0x01 0x02>; + qcom,qos-config = <0x135>; + qcom,ramp-time = <0xaf>; + }; + + qcom,glink-qos-config-adsp { + compatible = "qcom,glink-qos-config"; + qcom,flow-info = <0x3c 0x00 0x3c 0x00 0x3c 0x00 0x3c 0x00>; + qcom,mtu-size = <0x800>; + qcom,tput-stats-cycle = <0x0a>; + phandle = <0x135>; + }; + + qcom,glink-smem-native-xprt-dsps@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000 0x1799000c 0x04>; + reg-names = "smem\0irq-reg-base"; + qcom,irq-mask = <0x1000000>; + interrupts = <0x00 0xaa 0x01>; + label = "dsps"; + }; + + qcom,glink-spi-xprt-wdsp { + compatible = "qcom,glink-spi-xprt"; + label = "wdsp"; + qcom,remote-fifo-config = <0x136>; + qcom,qos-config = <0x137>; + qcom,ramp-time = <0x10 0x20 0x30 0x40>; + phandle = <0x37e>; + }; + + qcom,glink-fifo-config-wdsp { + compatible = "qcom,glink-fifo-config"; + qcom,out-read-idx-reg = <0x12000>; + qcom,out-write-idx-reg = <0x12004>; + qcom,in-read-idx-reg = <0x1200c>; + qcom,in-write-idx-reg = <0x12010>; + phandle = <0x136>; + }; + + qcom,glink-qos-config-wdsp { + compatible = "qcom,glink-qos-config"; + qcom,flow-info = <0x80 0x00 0x70 0x01 0x60 0x02 0x50 0x03>; + qcom,mtu-size = <0x800>; + qcom,tput-stats-cycle = <0x0a>; + phandle = <0x137>; + }; + + qcom,glink-smem-native-xprt-cdsp@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000 0x1799000c 0x04>; + reg-names = "smem\0irq-reg-base"; + qcom,irq-mask = <0x10>; + interrupts = <0x00 0x23e 0x01>; + label = "cdsp"; + }; + + qcom,glink-ssr-modem { + compatible = "qcom,glink_ssr"; + label = "modem"; + qcom,edge = "mpss"; + qcom,notify-edges = <0x138 0x139 0x13a 0x13b>; + qcom,xprt = "smem"; + phandle = <0x13c>; + }; + + qcom,glink-ssr-adsp { + compatible = "qcom,glink_ssr"; + label = "adsp"; + qcom,edge = "lpass"; + qcom,notify-edges = <0x13c 0x139 0x13a>; + qcom,xprt = "smem"; + phandle = <0x138>; + }; + + qcom,glink-ssr-dsps { + compatible = "qcom,glink_ssr"; + label = "slpi"; + qcom,edge = "dsps"; + qcom,notify-edges = <0x13c 0x138 0x13a>; + qcom,xprt = "smem"; + phandle = <0x139>; + }; + + qcom,glink-ssr-cdsp { + compatible = "qcom,glink_ssr"; + label = "cdsp"; + qcom,edge = "cdsp"; + qcom,notify-edges = <0x13c 0x138 0x139>; + qcom,xprt = "smem"; + phandle = <0x13a>; + }; + + qcom,glink-ssr-spss { + compatible = "qcom,glink_ssr"; + label = "spss"; + qcom,edge = "spss"; + qcom,notify-edges = <0x13c>; + qcom,xprt = "mailbox"; + phandle = <0x13b>; + }; + + qcom,ipc_router { + compatible = "qcom,ipc_router"; + qcom,node-id = <0x01>; + }; + + qcom,ipc_router_modem_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "mpss"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <0x01>; + qcom,xprt-version = <0x01>; + qcom,fragmented-data; + }; + + qcom,ipc_router_q6_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "lpass"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <0x01>; + qcom,xprt-version = <0x01>; + qcom,fragmented-data; + }; + + qcom,ipc_router_dsps_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "dsps"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <0x01>; + qcom,xprt-version = <0x01>; + qcom,fragmented-data; + qcom,dynamic-wakeup-source; + qcom,low-latency-xprt; + }; + + qcom,ipc_router_cdsp_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "cdsp"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <0x01>; + qcom,xprt-version = <0x01>; + qcom,fragmented-data; + }; + + qcom,qsee_ipc_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,rx-irq-clr = <0x1888008 0x04>; + qcom,rx-irq-clr-mask = <0x01>; + qcom,dev-name = "qsee_ipc_irq_spss"; + interrupts = <0x00 0x15d 0x04>; + label = "spss"; + }; + }; + + qcom,spcom { + compatible = "qcom,spcom"; + qcom,spcom-ch-names = "sp_kernel\0sp_ssr"; + status = "ok"; + }; + + qcom,spss_utils { + compatible = "qcom,spss-utils"; + qcom,spss-fuse1-addr = <0x7841c4>; + qcom,spss-fuse1-bit = <0x1b>; + qcom,spss-fuse2-addr = <0x7841c4>; + qcom,spss-fuse2-bit = <0x1a>; + qcom,spss-dev-firmware-name = "spss2d"; + qcom,spss-test-firmware-name = "spss2t"; + qcom,spss-prod-firmware-name = "spss2p"; + qcom,spss-debug-reg-addr = <0x1886020>; + status = "ok"; + }; + + qcom,glink_pkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-loopback_cntl { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; + }; + + qcom,glinkpkt-loopback_data { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,sps { + compatible = "qcom,msm_sps_4k"; + qcom,pipe-attr-ee; + }; + + qcom,qbt1000 { + compatible = "qcom,qbt1000"; + clock-names = "core\0iface"; + clock-frequency = <0x17d7840>; + qcom,ipc-gpio = <0x3c 0x79 0x00>; + qcom,finger-detect-gpio = <0x4c 0x05 0x00>; + status = "disabled"; + }; + + qseecom@86d00000 { + compatible = "qcom,qseecom"; + reg = <0x86d00000 0x3c00000>; + reg-names = "secapp-region"; + qcom,hlos-num-ce-hw-instances = <0x01>; + qcom,hlos-ce-hw-instance = <0x00>; + qcom,qsee-ce-hw-instance = <0x00>; + qcom,disk-encrypt-pipe-pair = <0x02>; + qcom,support-fde; + qcom,no-clock-support; + qcom,fde-key-size; + qcom,commonlib64-loaded-by-uefi; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <0x04>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x30d40 0x61a80 0x7d 0x200 0x493e0 0xc3500 0x7d 0x200 0x61a80 0xf4240>; + clock-names = "core_clk_src\0core_clk\0iface_clk\0bus_clk"; + clocks = <0x22 0x11 0x22 0x11 0x22 0x0f 0x22 0x10>; + qcom,ce-opp-freq = <0xa37d070>; + qcom,qsee-reentrancy-support = <0x02>; + }; + + qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x01 0x26a 0x00 0x00 0x01 0x26a 0x00 0x493e0>; + clocks = <0x22 0x48>; + clock-names = "iface_clk"; + }; + + tz-log@146bf720 { + compatible = "qcom,tz-log"; + reg = <0x146bf720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000 0x1dc4000 0x24000>; + reg-names = "crypto-base\0crypto-bam-base"; + interrupts = <0x00 0x110 0x00>; + qcom,bam-pipe-pair = <0x03>; + qcom,ce-hw-instance = <0x00>; + qcom,ce-device = <0x00>; + qcom,ce-hw-shared; + qcom,bam-ee = <0x00>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180>; + clock-names = "core_clk_src\0core_clk\0iface_clk\0bus_clk"; + clocks = <0x22 0x11 0x22 0x11 0x22 0x0f 0x22 0x10>; + qcom,ce-opp-freq = <0xa37d070>; + qcom,request-bw-before-clk; + qcom,smmu-s1-enable; + iommus = <0x29 0x706 0x01 0x29 0x716 0x01>; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <0x29 0x712 0x00 0x29 0x71f 0x00>; + virtual-addr = <0x60000000>; + virtual-size = <0x40000000>; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <0x29 0x713 0x00 0x29 0x71c 0x00 0x29 0x71d 0x00 0x29 0x71e 0x00>; + virtual-addr = <0x60200000>; + virtual-size = <0x40000000>; + qcom,secure-context-bank; + }; + }; + + qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + qcrypto@1de0000 { + compatible = "qcom,qcrypto"; + reg = <0x1de0000 0x20000 0x1dc4000 0x24000>; + reg-names = "crypto-base\0crypto-bam-base"; + interrupts = <0x00 0x110 0x00>; + qcom,bam-pipe-pair = <0x02>; + qcom,ce-hw-instance = <0x00>; + qcom,ce-device = <0x00>; + qcom,bam-ee = <0x00>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180>; + clock-names = "core_clk_src\0core_clk\0iface_clk\0bus_clk"; + clocks = <0x22 0x11 0x22 0x11 0x22 0x0f 0x22 0x10>; + qcom,ce-opp-freq = <0xa37d070>; + qcom,request-bw-before-clk; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + iommus = <0x29 0x704 0x01 0x29 0x714 0x01>; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x00 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x01>; + qcom,guard-memory; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-loaduC; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + qcom,ipa@01e00000 { + compatible = "qcom,ipa"; + reg = <0x1e00000 0x34000 0x1e04000 0x2c000>; + reg-names = "ipa-base\0gsi-base"; + interrupts = <0x00 0x137 0x00 0x00 0x1b0 0x00>; + interrupt-names = "ipa-irq\0gsi-irq"; + qcom,ipa-hw-ver = <0x0d>; + qcom,ipa-hw-mode = <0x00>; + qcom,ee = <0x00>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,use-64-bit-dma-mask; + qcom,arm-smmu; + qcom,bandwidth-vote-for-ipa; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <0x05>; + qcom,msm-bus,num-paths = <0x04>; + qcom,msm-bus,vectors-KBps = <0x5a 0x200 0x00 0x00 0x5a 0x249 0x00 0x00 0x01 0x2a4 0x00 0x00 0x8f 0x309 0x00 0x00 0x5a 0x200 0x13880 0x927c0 0x5a 0x249 0x13880 0x55730 0x01 0x2a4 0x9c40 0x9c40 0x8f 0x309 0x00 0x4b 0x5a 0x200 0x13880 0x9c400 0x5a 0x249 0x13880 0x9c400 0x01 0x2a4 0x13880 0x13880 0x8f 0x309 0x00 0x96 0x5a 0x200 0x324b0 0xea600 0x5a 0x249 0x324b0 0xea600 0x01 0x2a4 0x324b0 0x27100 0x8f 0x309 0x00 0x12c 0x5a 0x200 0x324b0 0x36ee80 0x5a 0x249 0x324b0 0x36ee80 0x01 0x2a4 0x324b0 0x493e0 0x8f 0x309 0x00 0x163>; + qcom,bus-vector-names = "MIN\0SVS2\0SVS\0NOMINAL\0TURBO"; + qcom,ipa-ram-mmap = <0x280 0x00 0x00 0x288 0x78 0x4000 0x308 0x78 0x4000 0x388 0x78 0x4000 0x408 0x78 0x4000 0x0f 0x00 0x07 0x08 0x0e 0x488 0x78 0x4000 0x508 0x78 0x4000 0x0f 0x00 0x07 0x08 0x0e 0x588 0x78 0x4000 0x608 0x78 0x4000 0x688 0x140 0x7c8 0x00 0x800 0x7d0 0x200 0x9d0 0x200 0x00 0x00 0x00 0xbd8 0x1024 0x2000 0x00 0x2000 0x00 0x2000 0x00 0x2000 0x00 0x80 0x200 0x2000 0x2000 0x00 0x2000 0x00 0x2000 0x00 0x2000 0x00 0x1c00 0x400>; + + qcom,smp2pgpio_map_ipa_1_out { + compatible = "qcom,smp2pgpio-map-ipa-1-out"; + gpios = <0x13d 0x00 0x00>; + }; + + qcom,smp2pgpio_map_ipa_1_in { + compatible = "qcom,smp2pgpio-map-ipa-1-in"; + gpios = <0x13e 0x00 0x00>; + }; + + ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + qcom,smmu-s1-bypass; + iommus = <0x29 0x720 0x00>; + qcom,iova-mapping = <0x20000000 0x40000000>; + qcom,additional-mapping = <0x146bd000 0x146bd000 0x2000>; + }; + + ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + qcom,smmu-s1-bypass; + iommus = <0x29 0x721 0x00>; + qcom,additional-mapping = <0x1e60000 0x1e60000 0x80000>; + }; + + ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + qcom,smmu-s1-bypass; + iommus = <0x29 0x722 0x00>; + qcom,iova-mapping = <0x40000000 0x20000000>; + }; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0x0f>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <0x13f>; + }; + + qcom,chd_sliver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x17e00058 0x17e10058 0x17e20058 0x17e30058>; + qcom,config-arr = <0x17e00060 0x17e10060 0x17e20060 0x17e30060>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x17e40058 0x17e50058 0x17e60058 0x17e70058>; + qcom,config-arr = <0x17e40060 0x17e50060 0x17e60060 0x17e70060>; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect-v2"; + qcom,threshold-arr = <0x1799041c 0x17990420>; + qcom,config-reg = <0x17990434>; + }; + + qcom,msm-gladiator-v3@17900000 { + compatible = "qcom,msm-gladiator-v3"; + reg = <0x17900000 0xd080>; + reg-names = "gladiator_base"; + interrupts = <0x00 0x11 0x00>; + }; + + qcom,cmd-db@861e0000 { + compatible = "qcom,cmd-db"; + reg = <0xc3f000c 0x08>; + }; + + dcc_v2@10a2000 { + compatible = "qcom,dcc-v2"; + reg = <0x10a2000 0x1000 0x10ae000 0x2000>; + reg-names = "dcc-base\0dcc-ram-base"; + dcc-ram-offset = <0x6000>; + qcom,curr-link-list = <0x02>; + qcom,link-list = <0x00 0x1740300 0x06 0x00 0x00 0x1620500 0x04 0x00 0x00 0x7840000 0x01 0x00 0x00 0x7841010 0x0c 0x00 0x00 0x7842000 0x10 0x00 0x00 0x7842500 0x02 0x00 0x02 0x07 0x00 0x00 0x00 0x7841000 0x01 0x00 0x02 0x01 0x00 0x00 0x02 0xa5 0x00 0x00 0x00 0x7841008 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x17dc3a84 0x02 0x00 0x00 0x17db3a84 0x01 0x00 0x00 0x1301000 0x02 0x00 0x00 0x17990044 0x01 0x00 0x00 0x17d45f00 0x01 0x00 0x00 0x17d45f08 0x06 0x00 0x00 0x17d45f80 0x01 0x00 0x00 0x17d47418 0x01 0x00 0x00 0x17d47570 0x01 0x00 0x00 0x17d47588 0x01 0x00 0x00 0x17d43700 0x01 0x00 0x00 0x17d43708 0x06 0x00 0x00 0x17d43780 0x01 0x00 0x00 0x17d44c18 0x01 0x00 0x00 0x17d44d70 0x01 0x00 0x00 0x17d44d88 0x01 0x00 0x00 0x17d41700 0x01 0x00 0x00 0x17d41708 0x06 0x00 0x00 0x17d41780 0x01 0x00 0x00 0x17d42c18 0x01 0x00 0x00 0x17d42d70 0x01 0x00 0x00 0x17d42d88 0x01 0x00 0x01 0x69ea00c 0x600007 0x01 0x01 0x69ea01c 0x136800 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136810 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136820 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136830 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136840 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136850 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136860 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136870 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3e9a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3c0a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3d1a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3d2a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3d5a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3d6a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3b1a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3b2a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3b5a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3b6a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3c2a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3c5a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3c6a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0xf1e000 0x01 0x01 0x69ea008 0x07 0x01 0x00 0x13e7e00 0x1f 0x00 0x00 0x1132100 0x01 0x00 0x00 0x1136044 0x04 0x00 0x00 0x11360b0 0x01 0x00 0x00 0x113e030 0x02 0x00 0x00 0x1141000 0x01 0x00 0x00 0x1148058 0x04 0x00 0x00 0x1160410 0x03 0x00 0x00 0x11604a0 0x01 0x00 0x00 0x11604b8 0x01 0x00 0x00 0x1165804 0x01 0x00 0x00 0x1166418 0x01 0x00 0x00 0x11b2100 0x01 0x00 0x00 0x11b6044 0x04 0x00 0x00 0x11be030 0x02 0x00 0x00 0x11c1000 0x01 0x00 0x00 0x11c8058 0x04 0x00 0x00 0x11e0410 0x03 0x00 0x00 0x11e04a0 0x01 0x00 0x00 0x11e04b8 0x01 0x00 0x00 0x11e5804 0x01 0x00 0x00 0x11e6418 0x01 0x00 0x00 0x1232100 0x01 0x00 0x00 0x1236044 0x04 0x00 0x00 0x12360b0 0x01 0x00 0x00 0x123e030 0x02 0x00 0x00 0x1241000 0x01 0x00 0x00 0x1248058 0x04 0x00 0x00 0x1260410 0x03 0x00 0x00 0x12604a0 0x01 0x00 0x00 0x12604b8 0x01 0x00 0x00 0x1265804 0x01 0x00 0x00 0x1266418 0x01 0x00 0x00 0x12b2100 0x01 0x00 0x00 0x12b6044 0x03 0x00 0x00 0x12b6050 0x01 0x00 0x00 0x12b60b0 0x01 0x00 0x00 0x12be030 0x02 0x00 0x00 0x12c1000 0x01 0x00 0x00 0x12c8058 0x04 0x00 0x00 0x12e0410 0x03 0x00 0x00 0x12e04a0 0x01 0x00 0x00 0x12e04b8 0x01 0x00 0x00 0x12e5804 0x01 0x00 0x00 0x12e6418 0x01 0x00 0x00 0x1380900 0x08 0x00 0x00 0x1380d00 0x05 0x00 0x00 0x1430280 0x01 0x00 0x00 0x1430288 0x01 0x00 0x00 0x143028c 0x07 0x00 0x00 0x1132100 0x01 0x00 0x00 0x1136044 0x04 0x00 0x00 0x11360b0 0x01 0x00 0x00 0x113e030 0x02 0x00 0x00 0x1141000 0x01 0x00 0x00 0x1148058 0x04 0x00 0x00 0x1160410 0x03 0x00 0x00 0x11604a0 0x01 0x00 0x00 0x11604b8 0x01 0x00 0x00 0x1165804 0x01 0x00 0x00 0x1166418 0x01 0x00 0x00 0x11b2100 0x01 0x00 0x00 0x11b6044 0x04 0x00 0x00 0x11be030 0x02 0x00 0x00 0x11c1000 0x01 0x00 0x00 0x11c8058 0x04 0x00 0x00 0x11e0410 0x03 0x00 0x00 0x11e04a0 0x01 0x00 0x00 0x11e04b8 0x01 0x00 0x00 0x11e5804 0x01 0x00 0x00 0x11e6418 0x01 0x00 0x00 0x1232100 0x01 0x00 0x00 0x1236044 0x04 0x00 0x00 0x12360b0 0x01 0x00 0x00 0x123e030 0x02 0x00 0x00 0x1241000 0x01 0x00 0x00 0x1248058 0x04 0x00 0x00 0x1260410 0x03 0x00 0x00 0x12604a0 0x01 0x00 0x00 0x12604b8 0x01 0x00 0x00 0x1265804 0x01 0x00 0x00 0x1266418 0x01 0x00 0x00 0x12b2100 0x01 0x00 0x00 0x12b6044 0x03 0x00 0x00 0x12b6050 0x01 0x00 0x00 0x12b60b0 0x01 0x00 0x00 0x12be030 0x02 0x00 0x00 0x12c1000 0x01 0x00 0x00 0x12c8058 0x04 0x00 0x00 0x12e0410 0x03 0x00 0x00 0x12e04a0 0x01 0x00 0x00 0x12e04b8 0x01 0x00 0x00 0x12e5804 0x01 0x00 0x00 0x12e6418 0x01 0x00 0x00 0x1380900 0x08 0x00 0x00 0x1380d00 0x05 0x00 0x00 0x1430280 0x01 0x00 0x00 0x1430288 0x01 0x00 0x00 0x143028c 0x07 0x00 0x00 0xc201244 0x01 0x00 0x00 0xc202244 0x01 0x00>; + }; + + qcom,msm-core@780000 { + compatible = "qcom,apss-core-ea"; + reg = <0x780000 0x1000>; + }; + + qcom,icnss@18800000 { + compatible = "qcom,icnss"; + reg = <0x18800000 0x800000 0xa0000000 0x10000000 0xb0000000 0x10000>; + reg-names = "membase\0smmu_iova_base\0smmu_iova_ipa"; + iommus = <0x29 0x40 0x01>; + interrupts = <0x00 0x19e 0x00 0x00 0x19f 0x00 0x00 0x1a0 0x00 0x00 0x1a1 0x00 0x00 0x1a2 0x00 0x00 0x1a3 0x00 0x00 0x1a4 0x00 0x00 0x1a5 0x00 0x00 0x1a6 0x00 0x00 0x1a7 0x00 0x00 0x1a8 0x00 0x00 0x1a9 0x00>; + qcom,wlan-msa-memory = <0x100000>; + qcom,gpio-force-fatal-error = <0x140 0x00 0x00>; + qcom,gpio-early-crash-ind = <0x140 0x01 0x00>; + vdd-0.8-cx-mx-supply = <0x141>; + vdd-1.8-xo-supply = <0x142>; + vdd-1.3-rfa-supply = <0x143>; + vdd-3.3-ch0-supply = <0x144>; + qcom,vdd-0.8-cx-mx-config = <0xc3500 0xc3500>; + qcom,vdd-3.3-ch0-config = <0x2f5d00 0x328980>; + qcom,smmu-s1-bypass; + }; + + qmi-tmd-devices { + compatible = "qcom,qmi_cooling_devices"; + + modem { + qcom,instance-id = <0x00>; + + modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <0x02>; + }; + + modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <0x02>; + }; + + modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <0x02>; + }; + + modem_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <0x02>; + }; + + modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <0x02>; + phandle = <0x159>; + }; + }; + + adsp { + qcom,instance-id = <0x01>; + + adsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <0x02>; + phandle = <0x15a>; + }; + }; + + cdsp { + qcom,instance-id = <0x43>; + + cdsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <0x02>; + phandle = <0x15b>; + }; + }; + + slpi { + qcom,instance-id = <0x53>; + + slpi_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <0x02>; + phandle = <0x15c>; + }; + }; + }; + + thermal-zones { + + aoss0-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "user_space"; + thermal-sensors = <0x145 0x00>; + wake-capable-sensor; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + cpu0-silver-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "user_space"; + thermal-sensors = <0x145 0x01>; + wake-capable-sensor; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + cpu1-silver-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "user_space"; + thermal-sensors = <0x145 0x02>; + wake-capable-sensor; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + cpu2-silver-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "user_space"; + thermal-sensors = <0x145 0x03>; + wake-capable-sensor; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + cpu3-silver-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x04>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + kryo-l3-0-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x05>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + kryo-l3-1-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x06>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + cpu0-gold-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x07>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + cpu1-gold-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x08>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + cpu2-gold-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x09>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + cpu3-gold-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x0a>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + gpu0-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x0b>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + gpu1-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "user_space"; + thermal-sensors = <0x145 0x0c>; + wake-capable-sensor; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + aoss1-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x146 0x00>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + mdm-dsp-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x146 0x01>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + ddr-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x146 0x02>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + wlan-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x146 0x03>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + compute-hvx-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x146 0x04>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x146 0x05>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + mmss-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x146 0x06>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x146 0x07>; + wake-capable-sensor; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0x1e848>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + gpu-virt-max-step { + polling-delay-passive = <0x0a>; + polling-delay = <0x64>; + thermal-governor = "step_wise"; + wake-capable-sensor; + + trips { + + gpu-trip0 { + temperature = <0x17318>; + hysteresis = <0x00>; + type = "passive"; + phandle = <0x147>; + }; + }; + + cooling-maps { + + gpu_cdev0 { + trip = <0x147>; + cooling-device = <0xce 0x00 0xffffffff>; + }; + }; + }; + + silv-virt-max-step { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "step_wise"; + wake-capable-sensor; + + trips { + + silver-trip { + temperature = <0x1d4c0>; + hysteresis = <0x00>; + type = "passive"; + }; + }; + }; + + gold-virt-max-step { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "step_wise"; + wake-capable-sensor; + + trips { + + gold-trip { + temperature = <0x1d4c0>; + hysteresis = <0x00>; + type = "passive"; + }; + }; + }; + + pop-mem-step { + polling-delay-passive = <0x0a>; + polling-delay = <0x00>; + thermal-sensors = <0x146 0x02>; + wake-capable-sensor; + thermal-governor = "step_wise"; + + trips { + + pop-trip { + temperature = <0x17318>; + hysteresis = <0x00>; + type = "passive"; + phandle = <0x148>; + }; + }; + + cooling-maps { + + pop_cdev4 { + trip = <0x148>; + cooling-device = <0x15 0xffffffff 0xfffffffd>; + }; + + pop_cdev5 { + trip = <0x148>; + cooling-device = <0x16 0xffffffff 0xfffffffd>; + }; + + pop_cdev6 { + trip = <0x148>; + cooling-device = <0x17 0xffffffff 0xfffffffd>; + }; + + pop_cdev7 { + trip = <0x148>; + cooling-device = <0x18 0xffffffff 0xfffffffd>; + }; + }; + }; + + cpu0-silver-step { + polling-delay-passive = <0x64>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x01>; + wake-capable-sensor; + thermal-governor = "step_wise"; + + trips { + + emerg-config0 { + temperature = <0x1adb0>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x149>; + }; + }; + + cooling-maps { + + emerg_cdev0 { + trip = <0x149>; + cooling-device = <0x11 0xfffffffe 0xfffffffe>; + }; + }; + }; + + cpu1-silver-step { + polling-delay-passive = <0x64>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x02>; + wake-capable-sensor; + thermal-governor = "step_wise"; + + trips { + + emerg-config1 { + temperature = <0x1adb0>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x14a>; + }; + }; + + cooling-maps { + + emerg_cdev1 { + trip = <0x14a>; + cooling-device = <0x12 0xfffffffe 0xfffffffe>; + }; + }; + }; + + cpu2-silver-step { + polling-delay-passive = <0x64>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x03>; + wake-capable-sensor; + thermal-governor = "step_wise"; + + trips { + + emerg-config2 { + temperature = <0x1adb0>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x14b>; + }; + }; + + cooling-maps { + + emerg_cdev2 { + trip = <0x14b>; + cooling-device = <0x13 0xfffffffe 0xfffffffe>; + }; + }; + }; + + cpu3-silver-step { + polling-delay-passive = <0x64>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x04>; + wake-capable-sensor; + thermal-governor = "step_wise"; + + trips { + + emerg-config3 { + temperature = <0x1adb0>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x14c>; + }; + }; + + cooling-maps { + + emerg_cdev3 { + trip = <0x14c>; + cooling-device = <0x14 0xfffffffe 0xfffffffe>; + }; + }; + }; + + cpu0-gold-step { + polling-delay-passive = <0x64>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x07>; + wake-capable-sensor; + thermal-governor = "step_wise"; + + trips { + + emerg-config4 { + temperature = <0x1adb0>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x14d>; + }; + }; + + cooling-maps { + + emerg_cdev4 { + trip = <0x14d>; + cooling-device = <0x15 0xfffffffe 0xfffffffe>; + }; + }; + }; + + cpu1-gold-step { + polling-delay-passive = <0x64>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x08>; + wake-capable-sensor; + thermal-governor = "step_wise"; + + trips { + + emerg-config5 { + temperature = <0x1adb0>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x14e>; + }; + }; + + cooling-maps { + + emerg_cdev5 { + trip = <0x14e>; + cooling-device = <0x16 0xfffffffe 0xfffffffe>; + }; + }; + }; + + cpu2-gold-step { + polling-delay-passive = <0x64>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x09>; + wake-capable-sensor; + thermal-governor = "step_wise"; + + trips { + + emerg-config6 { + temperature = <0x1adb0>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x14f>; + }; + }; + + cooling-maps { + + emerg_cdev6 { + trip = <0x14f>; + cooling-device = <0x17 0xfffffffe 0xfffffffe>; + }; + }; + }; + + cpu3-gold-step { + polling-delay-passive = <0x64>; + polling-delay = <0x00>; + thermal-sensors = <0x145 0x0a>; + wake-capable-sensor; + thermal-governor = "step_wise"; + + trips { + + emerg-config7 { + temperature = <0x1adb0>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x150>; + }; + }; + + cooling-maps { + + emerg_cdev7 { + trip = <0x150>; + cooling-device = <0x18 0xfffffffe 0xfffffffe>; + }; + }; + }; + + lmh-dcvs-01 { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "user_space"; + thermal-sensors = <0x0a>; + wake-capable-sensor; + + trips { + + active-config { + temperature = <0x17318>; + hysteresis = <0x7530>; + type = "passive"; + }; + }; + }; + + lmh-dcvs-00 { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "user_space"; + thermal-sensors = <0x02>; + wake-capable-sensor; + + trips { + + active-config { + temperature = <0x17318>; + hysteresis = <0x7530>; + type = "passive"; + }; + }; + }; + + pm8998_tz { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "step_wise"; + thermal-sensors = <0x151>; + wake-capable-sensor; + + trips { + + pm8998-trip0 { + temperature = <0x19a28>; + hysteresis = <0x00>; + type = "passive"; + phandle = <0x152>; + }; + + pm8998-trip1 { + temperature = <0x1e848>; + hysteresis = <0x00>; + type = "passive"; + phandle = <0x153>; + }; + + pm8998-trip2 { + temperature = <0x23668>; + hysteresis = <0x00>; + type = "passive"; + }; + }; + + cooling-maps { + + trip0_cpu0 { + trip = <0x152>; + cooling-device = <0x11 0xfffffffd 0xfffffffd>; + }; + + trip0_cpu1 { + trip = <0x152>; + cooling-device = <0x12 0xfffffffd 0xfffffffd>; + }; + + trip0_cpu2 { + trip = <0x152>; + cooling-device = <0x13 0xfffffffd 0xfffffffd>; + }; + + trip0_cpu3 { + trip = <0x152>; + cooling-device = <0x14 0xfffffffd 0xfffffffd>; + }; + + trip0_cpu4 { + trip = <0x152>; + cooling-device = <0x15 0xfffffffd 0xfffffffd>; + }; + + trip0_cpu5 { + trip = <0x152>; + cooling-device = <0x16 0xfffffffd 0xfffffffd>; + }; + + trip0_cpu6 { + trip = <0x152>; + cooling-device = <0x17 0xfffffffd 0xfffffffd>; + }; + + trip0_cpu7 { + trip = <0x152>; + cooling-device = <0x18 0xfffffffd 0xfffffffd>; + }; + + trip1_cpu1 { + trip = <0x153>; + cooling-device = <0x12 0xfffffffe 0xfffffffe>; + }; + + trip1_cpu2 { + trip = <0x153>; + cooling-device = <0x13 0xfffffffe 0xfffffffe>; + }; + + trip1_cpu3 { + trip = <0x153>; + cooling-device = <0x14 0xfffffffe 0xfffffffe>; + }; + + trip1_cpu4 { + trip = <0x153>; + cooling-device = <0x15 0xfffffffe 0xfffffffe>; + }; + + trip1_cpu5 { + trip = <0x153>; + cooling-device = <0x16 0xfffffffe 0xfffffffe>; + }; + + trip1_cpu6 { + trip = <0x153>; + cooling-device = <0x17 0xfffffffe 0xfffffffe>; + }; + + trip1_cpu7 { + trip = <0x153>; + cooling-device = <0x18 0xfffffffe 0xfffffffe>; + }; + }; + }; + + pm8005_tz { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x154>; + + trips { + + pm8005-trip0 { + temperature = <0x19a28>; + hysteresis = <0x00>; + type = "passive"; + }; + + pm8005-trip1 { + temperature = <0x1e848>; + hysteresis = <0x00>; + type = "passive"; + }; + + pm8005-trip2 { + temperature = <0x23668>; + hysteresis = <0x00>; + type = "passive"; + }; + }; + }; + + aoss0-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x00>; + wake-capable-sensor; + tracks-low; + + trips { + + aoss0-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x155>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x155>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x155>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x155>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x155>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x155>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x155>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x155>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x155>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x155>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x155>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + cpu0-silver-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x01>; + wake-capable-sensor; + tracks-low; + + trips { + + cpu0-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x15d>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x15d>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x15d>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x15d>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x15d>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x15d>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x15d>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x15d>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x15d>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x15d>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x15d>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + cpu1-silver-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x02>; + wake-capable-sensor; + tracks-low; + + trips { + + cpu1-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x15e>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x15e>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x15e>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x15e>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x15e>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x15e>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x15e>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x15e>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x15e>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x15e>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x15e>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + cpu2-silver-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x03>; + wake-capable-sensor; + tracks-low; + + trips { + + cpu2-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x15f>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x15f>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x15f>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x15f>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x15f>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x15f>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x15f>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x15f>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x15f>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x15f>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x15f>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + cpu3-silver-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x04>; + wake-capable-sensor; + tracks-low; + + trips { + + cpu3-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x160>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x160>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x160>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x160>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x160>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x160>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x160>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x160>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x160>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x160>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x160>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + kryo-l3-0-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x05>; + wake-capable-sensor; + tracks-low; + + trips { + + l3-0-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x161>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x161>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x161>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x161>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x161>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x161>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x161>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x161>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x161>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x161>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x161>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + kryo-l3-1-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x06>; + wake-capable-sensor; + tracks-low; + + trips { + + l3-1-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x162>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x162>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x162>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x162>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x162>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x162>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x162>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x162>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x162>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x162>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x162>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + cpu0-gold-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x07>; + wake-capable-sensor; + tracks-low; + + trips { + + cpug0-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x163>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x163>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x163>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x163>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x163>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x163>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x163>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x163>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x163>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x163>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x163>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + cpu1-gold-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x08>; + wake-capable-sensor; + tracks-low; + + trips { + + cpug1-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x164>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x164>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x164>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x164>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x164>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x164>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x164>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x164>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x164>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x164>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x164>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + cpu2-gold-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x09>; + wake-capable-sensor; + tracks-low; + + trips { + + cpug2-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x165>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x165>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x165>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x165>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x165>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x165>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x165>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x165>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x165>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x165>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x165>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + cpu3-gold-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x0a>; + wake-capable-sensor; + tracks-low; + + trips { + + cpug3-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x166>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x166>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x166>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x166>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x166>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x166>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x166>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x166>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x166>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x166>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x166>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + gpu0-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x0b>; + wake-capable-sensor; + tracks-low; + + trips { + + gpu0-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x167>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x167>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x167>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x167>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x167>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x167>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x167>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x167>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x167>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x167>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x167>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + gpu1-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x145 0x0c>; + wake-capable-sensor; + tracks-low; + + trips { + + gpu1-trip_l { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x168>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x168>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x168>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x168>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x168>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x168>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x168>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x168>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x168>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x168>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x168>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + aoss1-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x146 0x00>; + wake-capable-sensor; + tracks-low; + + trips { + + aoss1-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x169>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x169>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x169>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x169>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x169>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x169>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x169>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x169>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x169>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x169>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x169>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + mdm-dsp-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x146 0x01>; + wake-capable-sensor; + tracks-low; + + trips { + + dsp-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x16a>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x16a>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x16a>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x16a>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x16a>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x16a>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x16a>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x16a>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x16a>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x16a>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x16a>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + ddr-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x146 0x02>; + wake-capable-sensor; + tracks-low; + + trips { + + ddr-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x16b>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x16b>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x16b>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x16b>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x16b>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x16b>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x16b>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x16b>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x16b>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x16b>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x16b>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + wlan-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x146 0x03>; + wake-capable-sensor; + tracks-low; + + trips { + + wlan-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x16c>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x16c>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x16c>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x16c>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x16c>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x16c>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x16c>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x16c>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x16c>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x16c>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x16c>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + compute-hvx-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x146 0x04>; + wake-capable-sensor; + tracks-low; + + trips { + + hvx-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x16d>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x16d>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x16d>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x16d>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x16d>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x16d>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x16d>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x16d>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x16d>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x16d>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x16d>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + camera-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x146 0x05>; + wake-capable-sensor; + tracks-low; + + trips { + + camera-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x16e>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x16e>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x16e>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x16e>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x16e>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x16e>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x16e>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x16e>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x16e>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x16e>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x16e>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + mmss-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x146 0x06>; + wake-capable-sensor; + tracks-low; + + trips { + + mmss-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x16f>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x16f>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x16f>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x16f>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x16f>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x16f>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x16f>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x16f>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x16f>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x16f>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x16f>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + mdm-core-lowf { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <0x146 0x07>; + wake-capable-sensor; + tracks-low; + + trips { + + mdm-trip { + temperature = <0x1388>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0x170>; + }; + }; + + cooling-maps { + + cpu0_vdd_cdev { + trip = <0x170>; + cooling-device = <0x11 0x04 0x04>; + }; + + cpu4_vdd_cdev { + trip = <0x170>; + cooling-device = <0x15 0x09 0x09>; + }; + + gpu_vdd_cdev { + trip = <0x170>; + cooling-device = <0xce 0x01 0x01>; + }; + + cx_vdd_cdev { + trip = <0x170>; + cooling-device = <0x156 0x00 0x00>; + }; + + mx_vdd_cdev { + trip = <0x170>; + cooling-device = <0x157 0x00 0x00>; + }; + + ebi_vdd_cdev { + trip = <0x170>; + cooling-device = <0x158 0x00 0x00>; + }; + + modem_vdd_cdev { + trip = <0x170>; + cooling-device = <0x159 0x00 0x00>; + }; + + adsp_vdd_cdev { + trip = <0x170>; + cooling-device = <0x15a 0x00 0x00>; + }; + + cdsp_vdd_cdev { + trip = <0x170>; + cooling-device = <0x15b 0x00 0x00>; + }; + + slpi_vdd_cdev { + trip = <0x170>; + cooling-device = <0x15c 0x00 0x00>; + }; + }; + }; + + ibat-high { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "step_wise"; + thermal-sensors = <0x171 0x00>; + wake-capable-sensor; + + trips { + + low-ibat { + temperature = <0x1388>; + hysteresis = <0xc8>; + type = "passive"; + }; + }; + }; + + ibat-vhigh { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "step_wise"; + thermal-sensors = <0x171 0x01>; + wake-capable-sensor; + + trips { + + ibat_vhigh { + temperature = <0x1770>; + hysteresis = <0x64>; + type = "passive"; + }; + }; + }; + + vbat { + polling-delay-passive = <0x64>; + polling-delay = <0x00>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <0x171 0x02>; + wake-capable-sensor; + tracks-low; + + trips { + + low-vbat { + temperature = <0xc80>; + hysteresis = <0x64>; + type = "passive"; + phandle = <0x172>; + }; + }; + + cooling-maps { + + vbat_cpu4 { + trip = <0x172>; + cooling-device = <0x15 0xfffffffe 0xfffffffe>; + }; + + vbat_cpu5 { + trip = <0x172>; + cooling-device = <0x16 0xfffffffe 0xfffffffe>; + }; + + vbat_map6 { + trip = <0x172>; + cooling-device = <0x17 0xfffffffe 0xfffffffe>; + }; + + vbat_map7 { + trip = <0x172>; + cooling-device = <0x18 0xfffffffe 0xfffffffe>; + }; + }; + }; + + vbat_low { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <0x171 0x03>; + wake-capable-sensor; + tracks-low; + + trips { + + low-vbat { + temperature = <0xaf0>; + hysteresis = <0x00>; + type = "passive"; + }; + }; + }; + + vbat_too_low { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <0x171 0x04>; + wake-capable-sensor; + tracks-low; + + trips { + + low-vbat { + temperature = <0xa28>; + hysteresis = <0x00>; + type = "passive"; + }; + }; + }; + + soc { + polling-delay-passive = <0x64>; + polling-delay = <0x00>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <0x171 0x05>; + wake-capable-sensor; + tracks-low; + + trips { + + low-soc { + temperature = <0x0a>; + hysteresis = <0x00>; + type = "passive"; + phandle = <0x173>; + }; + }; + + cooling-maps { + + soc_cpu4 { + trip = <0x173>; + cooling-device = <0x15 0xfffffffe 0xfffffffe>; + }; + + soc_cpu5 { + trip = <0x173>; + cooling-device = <0x16 0xfffffffe 0xfffffffe>; + }; + + soc_map6 { + trip = <0x173>; + cooling-device = <0x17 0xfffffffe 0xfffffffe>; + }; + + soc_map7 { + trip = <0x173>; + cooling-device = <0x18 0xfffffffe 0xfffffffe>; + }; + }; + }; + + pmi8998_tz { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x174>; + wake-capable-sensor; + + trips { + + pmi8998-trip0 { + temperature = <0x19a28>; + hysteresis = <0x00>; + type = "passive"; + }; + + pmi8998-trip1 { + temperature = <0x1e848>; + hysteresis = <0x00>; + type = "passive"; + }; + + pmi8998-trip2 { + temperature = <0x23668>; + hysteresis = <0x00>; + type = "passive"; + }; + }; + }; + + xo_therm { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x175 0x4c>; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0xfde8>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + cam_therm0 { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x175 0x4d>; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0xfde8>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + cam_therm1 { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x175 0x4e>; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0xfde8>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + pa_therm0 { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x175 0x4f>; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0xfde8>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + pa_therm1 { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x175 0x50>; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0xfde8>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + quiet_therm { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x175 0x51>; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0xfde8>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + + backlight_therm { + polling-delay-passive = <0x00>; + polling-delay = <0x00>; + thermal-sensors = <0x175 0x52>; + thermal-governor = "user_space"; + + trips { + + active-config0 { + temperature = <0xfde8>; + hysteresis = <0x3e8>; + type = "passive"; + }; + }; + }; + }; + + tsens@c222000 { + compatible = "qcom,sdm845-tsens"; + reg = <0xc222000 0x04 0xc263000 0x1ff>; + reg-names = "tsens_srot_physical\0tsens_tm_physical"; + interrupts = <0x00 0x1fa 0x00 0x00 0x1fc 0x00>; + interrupt-names = "tsens-upper-lower\0tsens-critical"; + #thermal-sensor-cells = <0x01>; + phandle = <0x145>; + }; + + tsens@c223000 { + compatible = "qcom,sdm845-tsens"; + reg = <0xc223000 0x04 0xc265000 0x1ff>; + reg-names = "tsens_srot_physical\0tsens_tm_physical"; + interrupts = <0x00 0x1fb 0x00 0x00 0x1fd 0x00>; + interrupt-names = "tsens-upper-lower\0tsens-critical"; + #thermal-sensor-cells = <0x01>; + phandle = <0x146>; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <0x176>; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + tmc_etf { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf0>; + }; + + tmc_etfswao { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xf1>; + }; + + tmc_etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + tmc_etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + tpdm_swao { + qcom,dump-size = <0x512>; + qcom,dump-id = <0xf2>; + }; + }; + + qcom,gpi-dma@0x800000 { + #dma-cells = <0x05>; + compatible = "qcom,gpi-dma"; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + interrupts = <0x00 0xf4 0x00 0x00 0xf5 0x00 0x00 0xf6 0x00 0x00 0xf7 0x00 0x00 0xf8 0x00 0x00 0xf9 0x00 0x00 0xfa 0x00 0x00 0xfb 0x00 0x00 0xfc 0x00 0x00 0xfd 0x00 0x00 0xfe 0x00 0x00 0xff 0x00 0x00 0x100 0x00>; + qcom,max-num-gpii = <0x0d>; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <0x02>; + iommus = <0x29 0x16 0x00>; + qcom,smmu-cfg = <0x01>; + qcom,iova-range = <0x00 0x100000 0x00 0x100000>; + status = "ok"; + phandle = <0x43>; + }; + + qcom,gpi-dma@0xa00000 { + #dma-cells = <0x05>; + compatible = "qcom,gpi-dma"; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + interrupts = <0x00 0x117 0x00 0x00 0x118 0x00 0x00 0x119 0x00 0x00 0x11a 0x00 0x00 0x11b 0x00 0x00 0x11c 0x00 0x00 0x125 0x00 0x00 0x126 0x00 0x00 0x127 0x00 0x00 0x128 0x00 0x00 0x129 0x00 0x00 0x12a 0x00 0x00 0x12b 0x00>; + qcom,max-num-gpii = <0x0d>; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <0x02>; + iommus = <0x29 0x6d6 0x00>; + qcom,smmu-cfg = <0x01>; + qcom,iova-range = <0x00 0x100000 0x00 0x100000>; + status = "ok"; + phandle = <0x6f>; + }; + + msm_tspp@0x8880000 { + compatible = "qcom,msm_tspp"; + reg = <0x88a7000 0x200 0x88a8000 0x200 0x88a9000 0x1000 0x8884000 0x23000>; + reg-names = "MSM_TSIF0_PHYS\0MSM_TSIF1_PHYS\0MSM_TSPP_PHYS\0MSM_TSPP_BAM_PHYS"; + interrupts = <0x00 0x79 0x00 0x00 0x77 0x00 0x00 0x78 0x00 0x00 0x7a 0x00>; + interrupt-names = "TSIF_TSPP_IRQ\0TSIF0_IRQ\0TSIF1_IRQ\0TSIF_BAM_IRQ"; + clock-names = "iface_clk\0ref_clk"; + clocks = <0x22 0x77 0x22 0x79>; + qcom,msm-bus,name = "tsif"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x52 0x200 0x00 0x00 0x52 0x200 0x3000 0x6000>; + pinctrl-names = "disabled\0tsif0-mode1\0tsif0-mode2\0tsif1-mode1\0tsif1-mode2\0dual-tsif-mode1\0dual-tsif-mode2"; + pinctrl-0; + pinctrl-1 = <0x177>; + pinctrl-2 = <0x177 0x178>; + pinctrl-3 = <0x179>; + pinctrl-4 = <0x179 0x17a>; + pinctrl-5 = <0x177 0x179>; + pinctrl-6 = <0x177 0x178 0x179 0x17a>; + qcom,smmu-s1-bypass; + iommus = <0x29 0x20 0x0f>; + }; + + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ebi.lvl"; + + regulator-s1 { + regulator-name = "pm8998_s1_level"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x01>; + regulator-max-microvolt = <0x10000>; + }; + + regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <0xa3 0x00>; + qcom,reg-resource-name = "ebi"; + #cooling-cells = <0x02>; + phandle = <0x158>; + }; + }; + + rpmh-regulator-smpa2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "smpa2"; + + regulator-s2 { + regulator-name = "pm8998_s2"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x10c8e0>; + regulator-max-microvolt = <0x10c8e0>; + qcom,init-voltage = <0x10c8e0>; + }; + }; + + rpmh-regulator-smpa3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "smpa3"; + + regulator-s3 { + regulator-name = "pm8998_s3"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x14a140>; + regulator-max-microvolt = <0x14a140>; + qcom,init-voltage = <0x14a140>; + phandle = <0x381>; + }; + }; + + rpmh-regulator-smpa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "smpa5"; + + regulator-s5 { + regulator-name = "pm8998_s5"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x1d0d80>; + regulator-max-microvolt = <0x1f20c0>; + qcom,init-voltage = <0x1d0d80>; + phandle = <0xd4>; + }; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "mx.lvl"; + + regulator-s6-level { + regulator-name = "pm8998_s6_level"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x01>; + regulator-max-microvolt = <0x10000>; + phandle = <0xbd>; + }; + + regulator-s6-level-ao { + regulator-name = "pm8998_s6_level_ao"; + qcom,set = <0x01>; + regulator-min-microvolt = <0x01>; + regulator-max-microvolt = <0x10000>; + phandle = <0xcf>; + }; + + mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <0xbd>; + regulator-levels = <0x101 0x01>; + #cooling-cells = <0x02>; + phandle = <0x157>; + }; + }; + + rpmh-regulator-smpa7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "smpa7"; + + regulator-s7 { + regulator-name = "pm8998_s7"; + qcom,set = <0x03>; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xfafa0>; + qcom,init-voltage = <0xdbba0>; + phandle = <0xd3>; + }; + }; + + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "cx.lvl"; + pm8998_s9_level-parent-supply = <0xbd>; + pm8998_s9_level_ao-parent-supply = <0xcf>; + + regulator-s9-level { + regulator-name = "pm8998_s9_level"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x11>; + regulator-max-microvolt = <0x10000>; + qcom,min-dropout-voltage-level = <0xffffffff>; + phandle = <0x1b>; + }; + + regulator-s9-level-ao { + regulator-name = "pm8998_s9_level_ao"; + qcom,set = <0x01>; + regulator-min-microvolt = <0x11>; + regulator-max-microvolt = <0x10000>; + qcom,min-dropout-voltage-level = <0xffffffff>; + phandle = <0xbc>; + }; + + regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <0xa3 0x00>; + qcom,reg-resource-name = "cx"; + #cooling-cells = <0x02>; + phandle = <0x156>; + }; + }; + + rpmh-regulator-ldoa1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa1"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + proxy-supply = <0x34>; + + regulator-l1 { + regulator-name = "pm8998_l1"; + qcom,set = <0x03>; + regulator-min-microvolt = <0xd6d80>; + regulator-max-microvolt = <0xd6d80>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <0x11940>; + qcom,init-voltage = <0xd6d80>; + qcom,init-mode = <0x02>; + phandle = <0x34>; + }; + + regulator-l1-ao { + regulator-name = "pm8998_l1_ao"; + qcom,set = <0x01>; + regulator-min-microvolt = <0xd6d80>; + regulator-max-microvolt = <0xd6d80>; + qcom,init-voltage = <0xd6d80>; + qcom,init-mode = <0x02>; + phandle = <0xd1>; + }; + + regulator-l1-so { + regulator-name = "pm8998_l1_so"; + qcom,set = <0x02>; + regulator-min-microvolt = <0xd6d80>; + regulator-max-microvolt = <0xd6d80>; + qcom,init-voltage = <0xd6d80>; + qcom,init-mode = <0x02>; + qcom,init-enable = <0x00>; + }; + }; + + rpmh-regulator-ldoa2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa2"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x7530>; + + regulator-l2 { + regulator-name = "pm8998_l2"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x124f80>; + regulator-max-microvolt = <0x124f80>; + qcom,init-voltage = <0x124f80>; + qcom,init-mode = <0x02>; + regulator-always-on; + phandle = <0xe0>; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l3 { + regulator-name = "pm8998_l3"; + qcom,set = <0x03>; + regulator-min-microvolt = <0xf4240>; + regulator-max-microvolt = <0xf4240>; + qcom,init-voltage = <0xf4240>; + qcom,init-mode = <0x02>; + }; + }; + + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "lmx.lvl"; + + regulator-l4-level { + regulator-name = "pm8998_l4_level"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x01>; + regulator-max-microvolt = <0x10000>; + phandle = <0xff>; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l5 { + regulator-name = "pm8998_l5"; + qcom,set = <0x03>; + regulator-min-microvolt = <0xc3500>; + regulator-max-microvolt = <0xc3500>; + qcom,init-voltage = <0xc3500>; + qcom,init-mode = <0x02>; + phandle = <0x141>; + }; + }; + + rpmh-regulator-ldoa6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa6"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l6 { + regulator-name = "pm8998_l6"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x1c5200>; + regulator-max-microvolt = <0x1c5200>; + qcom,init-voltage = <0x1c5200>; + qcom,init-mode = <0x02>; + }; + }; + + rpmh-regulator-ldoa7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa7"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x2710>; + + regulator-l7 { + regulator-name = "pm8998_l7"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + qcom,init-voltage = <0x1b7740>; + qcom,init-mode = <0x02>; + phandle = <0x142>; + }; + }; + + rpmh-regulator-ldoa8 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa8"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l8 { + regulator-name = "pm8998_l8"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x124f80>; + regulator-max-microvolt = <0x130b00>; + qcom,init-voltage = <0x124f80>; + qcom,init-mode = <0x02>; + }; + }; + + rpmh-regulator-ldoa9 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa9"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l9 { + regulator-name = "pm8998_l9"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x1a0040>; + regulator-max-microvolt = <0x2cad80>; + qcom,init-voltage = <0x1a0040>; + qcom,init-mode = <0x02>; + }; + }; + + rpmh-regulator-ldoa10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa10"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l10 { + regulator-name = "pm8998_l10"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x1a0040>; + regulator-max-microvolt = <0x2cad80>; + qcom,init-voltage = <0x1a0040>; + qcom,init-mode = <0x02>; + }; + }; + + rpmh-regulator-ldoa11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l11 { + regulator-name = "pm8998_l11"; + qcom,set = <0x03>; + regulator-min-microvolt = <0xf4240>; + regulator-max-microvolt = <0xffdc0>; + qcom,init-voltage = <0xf4240>; + qcom,init-mode = <0x02>; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l12 { + regulator-name = "pm8998_l12"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + qcom,init-voltage = <0x1b7740>; + qcom,init-mode = <0x02>; + phandle = <0x17b>; + }; + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x2710>; + + regulator-l13 { + regulator-name = "pm8998_l13"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x2d2a80>; + qcom,init-voltage = <0x1b7740>; + qcom,init-mode = <0x02>; + phandle = <0xe2>; + }; + }; + + rpmh-regulator-ldoa14 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa14"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x2710>; + proxy-supply = <0x89>; + + regulator-l14 { + regulator-name = "pm8998_l14"; + qcom,set = <0x03>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <0x1c138>; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1cafc0>; + qcom,init-voltage = <0x1b7740>; + qcom,init-mode = <0x04>; + phandle = <0x89>; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l15 { + regulator-name = "pm8998_l15"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + qcom,init-voltage = <0x1b7740>; + qcom,init-mode = <0x02>; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l16 { + regulator-name = "pm8998_l16"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x294280>; + regulator-max-microvolt = <0x294280>; + qcom,init-voltage = <0x294280>; + qcom,init-mode = <0x02>; + }; + }; + + rpmh-regulator-ldoa17 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa17"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x2710>; + + regulator-l17 { + regulator-name = "pm8998_l17"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x13e5c0>; + regulator-max-microvolt = <0x13e5c0>; + qcom,init-voltage = <0x13e5c0>; + qcom,init-mode = <0x02>; + phandle = <0x143>; + }; + }; + + rpmh-regulator-ldoa18 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa18"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l18 { + regulator-name = "pm8998_l18"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x294280>; + regulator-max-microvolt = <0x2d2a80>; + qcom,init-voltage = <0x294280>; + qcom,init-mode = <0x02>; + }; + }; + + rpmh-regulator-ldoa19 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa19"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l19 { + regulator-name = "pm8998_l19"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x2b9440>; + regulator-max-microvolt = <0x2f5d00>; + qcom,init-voltage = <0x2b9440>; + qcom,init-mode = <0x02>; + }; + }; + + rpmh-regulator-ldoa20 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa20"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x2710>; + + regulator-l20 { + regulator-name = "pm8998_l20"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x294280>; + regulator-max-microvolt = <0x2d2a80>; + qcom,init-voltage = <0x294280>; + qcom,init-mode = <0x04>; + phandle = <0xde>; + }; + }; + + rpmh-regulator-ldoa21 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa21"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x2710>; + + regulator-l21 { + regulator-name = "pm8998_l21"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x294280>; + regulator-max-microvolt = <0x2d2a80>; + qcom,init-voltage = <0x294280>; + qcom,init-mode = <0x02>; + phandle = <0xe1>; + }; + }; + + rpmh-regulator-ldoa22 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa22"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x2710>; + + regulator-l22 { + regulator-name = "pm8998_l22"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x2bb380>; + regulator-max-microvolt = <0x328980>; + qcom,init-voltage = <0x2bb380>; + qcom,init-mode = <0x02>; + phandle = <0x35e>; + }; + }; + + rpmh-regulator-ldoa23 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa23"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x2710>; + + regulator-l23 { + regulator-name = "pm8998_l23"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x2dc6c0>; + regulator-max-microvolt = <0x328980>; + qcom,init-voltage = <0x2dc6c0>; + qcom,init-mode = <0x02>; + }; + }; + + rpmh-regulator-ldoa24 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa24"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x2710>; + pm8998_l24-parent-supply = <0x17b>; + + regulator-l24 { + regulator-name = "pm8998_l24"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x2f1e80>; + regulator-max-microvolt = <0x2f1e80>; + qcom,init-voltage = <0x2f1e80>; + qcom,init-mode = <0x02>; + phandle = <0xa9>; + }; + }; + + rpmh-regulator-ldoa25 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa25"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x2710>; + + regulator-l25 { + regulator-name = "pm8998_l25"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x2dc6c0>; + regulator-max-microvolt = <0x328980>; + qcom,init-voltage = <0x2dc6c0>; + qcom,init-mode = <0x02>; + phandle = <0x144>; + }; + }; + + rpmh-regulator-ldoa26 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa26"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + proxy-supply = <0x33>; + + regulator-l26 { + regulator-name = "pm8998_l26"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x124f80>; + regulator-max-microvolt = <0x124f80>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <0xaa50>; + qcom,init-voltage = <0x124f80>; + qcom,init-mode = <0x02>; + phandle = <0x33>; + }; + }; + + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "lcx.lvl"; + + regulator-l27-level { + regulator-name = "pm8998_l27_level"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x01>; + regulator-max-microvolt = <0x10000>; + phandle = <0xfe>; + }; + }; + + rpmh-regulator-ldoa28 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "ldoa28"; + qcom,regulator-type = "pmic4-ldo"; + qcom,supported-modes = <0x02 0x04>; + qcom,mode-threshold-currents = <0x00 0x01>; + + regulator-l28 { + regulator-name = "pm8998_l28"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + qcom,init-voltage = <0x325aa0>; + qcom,init-mode = <0x02>; + phandle = <0x35c>; + }; + }; + + rpmh-regulator-vsa1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "vsa1"; + + regulator-lvs1 { + regulator-name = "pm8998_lvs1"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + }; + }; + + rpmh-regulator-vsa2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "vsa2"; + + regulator-lvs2 { + regulator-name = "pm8998_lvs2"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + }; + }; + + rpmh-regulator-bobb1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "bobb1"; + qcom,regulator-type = "pmic4-bob"; + qcom,send-defaults; + + regulator-bob { + regulator-name = "pmi8998_bob"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x328980>; + regulator-max-microvolt = <0x36ee80>; + qcom,init-voltage = <0x328980>; + qcom,init-mode = <0x00>; + phandle = <0x21c>; + }; + + regulator-bob-ao { + regulator-name = "pmi8998_bob_ao"; + qcom,set = <0x01>; + regulator-min-microvolt = <0x328980>; + regulator-max-microvolt = <0x36ee80>; + qcom,init-voltage = <0x328980>; + qcom,init-mode = <0x03>; + }; + }; + + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "gfx.lvl"; + + regulator-s1-level { + regulator-name = "pm8005_s1_level"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x31>; + regulator-max-microvolt = <0x10000>; + qcom,init-voltage-level = <0x31>; + phandle = <0x1d>; + }; + }; + + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "mss.lvl"; + + regulator-s2-level { + regulator-name = "pm8005_s2_level"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x01>; + regulator-max-microvolt = <0x10000>; + phandle = <0xf6>; + }; + }; + + rpmh-regulator-smpc3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <0xbb 0x00>; + qcom,resource-name = "smpc3"; + + regulator-s3 { + regulator-name = "pm8005_s3"; + qcom,set = <0x03>; + regulator-min-microvolt = <0x927c0>; + regulator-max-microvolt = <0x927c0>; + qcom,init-voltage = <0x927c0>; + }; + }; + + refgen-regulator@ff1000 { + compatible = "qcom,refgen-regulator"; + reg = <0xff1000 0x60>; + regulator-name = "refgen"; + regulator-enable-ramp-delay = <0x05>; + status = "ok"; + proxy-supply = <0x17c>; + qcom,proxy-consumer-enable; + phandle = <0x17c>; + }; + + csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + qcom,blk-size = <0x01>; + phandle = <0x182>; + }; + + csr@6b0e000 { + compatible = "qcom,coresight-csr"; + reg = <0x6b0e000 0x1000>; + reg-names = "csr-base"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + qcom,blk-size = <0x01>; + }; + + replicator@6046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b909>; + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + coresight-name = "coresight-replicator"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x17d>; + phandle = <0x18f>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x17e>; + phandle = <0x190>; + }; + }; + }; + }; + + replicator@6b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b909>; + reg = <0x6b0a000 0x1000>; + reg-names = "replicator-base"; + coresight-name = "coresight-replicator-swao"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x17f>; + phandle = <0x183>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x180>; + phandle = <0x1e1>; + }; + }; + + port@2 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x181>; + phandle = <0x19c>; + }; + }; + }; + }; + + tmc@6b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b961>; + reg = <0x6b09000 0x1000>; + reg-names = "tmc-base"; + coresight-name = "coresight-tmc-etf-swao"; + coresight-csr = <0x182>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x183>; + phandle = <0x17f>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x184>; + phandle = <0x185>; + }; + }; + }; + }; + + funnel@0x6b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6b08000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-swao"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x185>; + phandle = <0x184>; + }; + }; + + port@1 { + reg = <0x06>; + + endpoint { + slave-mode; + remote-endpoint = <0x186>; + phandle = <0x1e2>; + }; + }; + + port@2 { + reg = <0x07>; + + endpoint { + slave-mode; + remote-endpoint = <0x187>; + phandle = <0x188>; + }; + }; + }; + }; + + tpda@6b01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b969>; + reg = <0x6b01000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-swao"; + qcom,tpda-atid = <0x47>; + qcom,dsb-elem-size = <0x01 0x20>; + qcom,cmb-elem-size = <0x00 0x40>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x188>; + phandle = <0x187>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x189>; + phandle = <0x18b>; + }; + }; + + port@2 { + reg = <0x01>; + + endpoint { + slave-mode; + remote-endpoint = <0x18a>; + phandle = <0x18c>; + }; + }; + }; + }; + + tpdm@6b02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x6b02000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-swao-0"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x18b>; + phandle = <0x189>; + }; + }; + }; + + tpdm@6b03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x6b03000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-swao-1"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + qcom,msr-fix-req; + + port { + + endpoint { + remote-endpoint = <0x18c>; + phandle = <0x18a>; + }; + }; + }; + + tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b961>; + reg = <0x6048000 0x1000 0x6064000 0x15000>; + reg-names = "tmc-base\0bam-base"; + arm,buffer-size = <0x400000>; + arm,sg-enable; + coresight-name = "coresight-tmc-etr"; + coresight-ctis = <0x18d 0x18e>; + coresight-csr = <0x182>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + interrupts = <0x00 0x10e 0x01>; + interrupt-names = "byte-cntr-irq"; + + port { + + endpoint { + slave-mode; + remote-endpoint = <0x18f>; + phandle = <0x17d>; + }; + }; + }; + + tmc@6047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b961>; + reg = <0x6047000 0x1000>; + reg-names = "tmc-base"; + coresight-name = "coresight-tmc-etf"; + coresight-ctis = <0x18d 0x18e>; + coresight-csr = <0x182>; + arm,default-sink; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x190>; + phandle = <0x17e>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + slave-mode; + remote-endpoint = <0x191>; + phandle = <0x192>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-merg"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x192>; + phandle = <0x191>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x193>; + phandle = <0x196>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + slave-mode; + remote-endpoint = <0x194>; + phandle = <0x19a>; + }; + }; + }; + }; + + stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b962>; + reg = <0x6002000 0x1000 0x16280000 0x180000>; + reg-names = "stm-base\0stm-stimulus-base"; + coresight-name = "coresight-stm"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x195>; + phandle = <0x199>; + }; + }; + }; + + hwevent@0x014066f0 { + compatible = "qcom,coresight-hwevent"; + reg = <0x14066f0 0x04 0x14166f0 0x04 0x1406038 0x04 0x1416038 0x04>; + reg-names = "ddr-ch0-cfg\0ddr-ch23-cfg\0ddr-ch0-ctrl\0ddr-ch23-ctrl"; + coresight-name = "coresight-hwevent"; + coresight-csr = <0x182>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + funnel@0x6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-in0"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x196>; + phandle = <0x193>; + }; + }; + + port@1 { + reg = <0x03>; + + endpoint { + slave-mode; + remote-endpoint = <0x197>; + phandle = <0x1d8>; + }; + }; + + port@2 { + reg = <0x06>; + + endpoint { + slave-mode; + remote-endpoint = <0x198>; + phandle = <0x1db>; + }; + }; + + port@3 { + reg = <0x07>; + + endpoint { + slave-mode; + remote-endpoint = <0x199>; + phandle = <0x195>; + }; + }; + }; + }; + + funnel@0x6043000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6043000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-in2"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x19a>; + phandle = <0x194>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x19b>; + phandle = <0x1e3>; + }; + }; + + port@2 { + reg = <0x01>; + + endpoint { + slave-mode; + remote-endpoint = <0x19c>; + phandle = <0x181>; + }; + }; + + port@3 { + reg = <0x02>; + + endpoint { + slave-mode; + remote-endpoint = <0x19d>; + phandle = <0x1ae>; + }; + }; + + port@4 { + reg = <0x05>; + + endpoint { + slave-mode; + remote-endpoint = <0x19e>; + phandle = <0x1e6>; + }; + }; + + port@5 { + reg = <0x06>; + + endpoint { + slave-mode; + remote-endpoint = <0x19f>; + phandle = <0x1a0>; + }; + }; + }; + }; + + funnel@0x6943000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6943000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-gfx"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + status = "disabled"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1a0>; + phandle = <0x19f>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1a1>; + phandle = <0x336>; + }; + }; + + port@2 { + reg = <0x01>; + + endpoint { + slave-mode; + remote-endpoint = <0x1a2>; + phandle = <0x337>; + }; + }; + }; + }; + + tpda@6004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b969>; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda"; + qcom,tpda-atid = <0x41>; + qcom,bc-elem-size = <0x0a 0x20 0x0d 0x20>; + qcom,tc-elem-size = <0x0d 0x20>; + qcom,dsb-elem-size = <0x00 0x20 0x02 0x20 0x03 0x20 0x05 0x20 0x06 0x20 0x0a 0x20 0x0b 0x20 0x0d 0x20>; + qcom,cmb-elem-size = <0x03 0x40 0x07 0x40 0x09 0x40 0x0d 0x40>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1a3>; + phandle = <0x1dc>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1a4>; + phandle = <0x1b8>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + slave-mode; + remote-endpoint = <0x1a5>; + phandle = <0x1c4>; + }; + }; + + port@3 { + reg = <0x03>; + + endpoint { + slave-mode; + remote-endpoint = <0x1a6>; + phandle = <0x1cc>; + }; + }; + + port@4 { + reg = <0x05>; + + endpoint { + slave-mode; + remote-endpoint = <0x1a7>; + phandle = <0x1b3>; + }; + }; + + port@5 { + reg = <0x06>; + + endpoint { + slave-mode; + remote-endpoint = <0x1a8>; + phandle = <0x1c7>; + }; + }; + + port@6 { + reg = <0x07>; + + endpoint { + slave-mode; + remote-endpoint = <0x1a9>; + phandle = <0x1d1>; + }; + }; + + port@7 { + reg = <0x09>; + + endpoint { + slave-mode; + remote-endpoint = <0x1aa>; + phandle = <0x1d0>; + }; + }; + + port@8 { + reg = <0x0a>; + + endpoint { + slave-mode; + remote-endpoint = <0x1ab>; + phandle = <0x1ba>; + }; + }; + + port@9 { + reg = <0x0b>; + + endpoint { + slave-mode; + remote-endpoint = <0x1ac>; + phandle = <0x1b9>; + }; + }; + + port@10 { + reg = <0x0d>; + + endpoint { + slave-mode; + remote-endpoint = <0x1ad>; + phandle = <0x1cf>; + }; + }; + }; + }; + + funnel@6832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6832000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-modem"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1ae>; + phandle = <0x19d>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1af>; + phandle = <0x1b0>; + }; + }; + }; + }; + + tpda@6831000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b969>; + reg = <0x6831000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-modem"; + qcom,tpda-atid = <0x43>; + qcom,dsb-elem-size = <0x00 0x20>; + qcom,cmb-elem-size = <0x00 0x40>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1b0>; + phandle = <0x1af>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1b1>; + phandle = <0x1b2>; + }; + }; + }; + }; + + tpdm@6830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x6830000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-modem"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1b2>; + phandle = <0x1b1>; + }; + }; + }; + + funnel@6845000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6845000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-lpass"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1b3>; + phandle = <0x1a7>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1b4>; + phandle = <0x1b7>; + }; + }; + }; + }; + + funnel_1@6845000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6867010 0x10 0x6845000 0x1000>; + reg-names = "funnel-base-dummy\0funnel-base-real"; + coresight-name = "coresight-funnel-lpass-1"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1b5>; + phandle = <0x1dd>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + slave-mode; + remote-endpoint = <0x1b6>; + phandle = <0x1e4>; + }; + }; + }; + }; + + tpdm@6844000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x6844000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-lpass"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + qcom,msr-fix-req; + + port { + + endpoint { + remote-endpoint = <0x1b7>; + phandle = <0x1b4>; + }; + }; + }; + + tpdm@6c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x6c28000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-center"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + qcom,msr-fix-req; + + port { + + endpoint { + remote-endpoint = <0x1b8>; + phandle = <0x1a4>; + }; + }; + }; + + tpdm@6a24000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x6a24000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-north"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + qcom,msr-fix-req; + + port { + + endpoint { + remote-endpoint = <0x1b9>; + phandle = <0x1ac>; + }; + }; + }; + + tpdm@69d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x69d0000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-qm"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1ba>; + phandle = <0x1ab>; + }; + }; + }; + + tpda@7862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b969>; + reg = <0x7862000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-apss"; + qcom,tpda-atid = <0x42>; + qcom,dsb-elem-size = <0x00 0x20>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1bb>; + phandle = <0x1e9>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1bc>; + phandle = <0x1bd>; + }; + }; + }; + }; + + tpdm@7860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x7860000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-apss"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1bd>; + phandle = <0x1bc>; + }; + }; + }; + + tpda@78c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b969>; + reg = <0x78c0000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-llm-silver"; + qcom,tpda-atid = <0x48>; + qcom,cmb-elem-size = <0x00 0x20>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1be>; + phandle = <0x1ea>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1bf>; + phandle = <0x1c0>; + }; + }; + }; + }; + + tpdm@78a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x78a0000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-llm-silver"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1c0>; + phandle = <0x1bf>; + }; + }; + }; + + tpda@78d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b969>; + reg = <0x78d0000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-llm-gold"; + qcom,tpda-atid = <0x49>; + qcom,cmb-elem-size = <0x00 0x20>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1c1>; + phandle = <0x1eb>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1c2>; + phandle = <0x1c3>; + }; + }; + }; + }; + + tpdm@78b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x78b0000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-llm-gold"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1c3>; + phandle = <0x1c2>; + }; + }; + }; + + funnel@6c0b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6c0b000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-dl-mm"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1c4>; + phandle = <0x1a5>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + slave-mode; + remote-endpoint = <0x1c5>; + phandle = <0x1c6>; + }; + }; + }; + }; + + tpdm@6c08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x6c08000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-mm"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + qcom,msr-fix-req; + + port { + + endpoint { + remote-endpoint = <0x1c6>; + phandle = <0x1c5>; + }; + }; + }; + + funnel@6861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6861000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-turing"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1c7>; + phandle = <0x1a8>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1c8>; + phandle = <0x1cb>; + }; + }; + }; + }; + + funnel_1@6861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6867000 0x10 0x6861000 0x1000>; + reg-names = "funnel-base-dummy\0funnel-base-real"; + coresight-name = "coresight-funnel-turing-1"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1c9>; + phandle = <0x1de>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + slave-mode; + remote-endpoint = <0x1ca>; + phandle = <0x1e0>; + }; + }; + }; + }; + + tpdm@6860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x6860000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-turing"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + qcom,msr-fix-req; + + port { + + endpoint { + remote-endpoint = <0x1cb>; + phandle = <0x1c8>; + }; + }; + }; + + funnel@69e2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x69e2000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-ddr-0"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1cc>; + phandle = <0x1a6>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1cd>; + phandle = <0x1ce>; + }; + }; + }; + }; + + tpdm@69e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x69e0000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-ddr"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + qcom,msr-fix-req; + + port { + + endpoint { + remote-endpoint = <0x1ce>; + phandle = <0x1cd>; + }; + }; + }; + + tpdm@6850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x6850000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-pimem"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1cf>; + phandle = <0x1ad>; + }; + }; + }; + + tpdm@684c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x684c000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-prng"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1d0>; + phandle = <0x1aa>; + }; + }; + }; + + tpdm@6840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x6840000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-vsense"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1d1>; + phandle = <0x1a9>; + }; + }; + }; + + tpda@7832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b969>; + reg = <0x7832000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-olc"; + qcom,tpda-atid = <0x45>; + qcom,cmb-elem-size = <0x00 0x40>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1d2>; + phandle = <0x1e8>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1d3>; + phandle = <0x1d4>; + }; + }; + }; + }; + + tpdm@7830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x7830000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-olc"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1d4>; + phandle = <0x1d3>; + }; + }; + }; + + tpda@6882000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b969>; + reg = <0x6882000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-spss"; + qcom,tpda-atid = <0x46>; + qcom,dsb-elem-size = <0x00 0x20>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1d5>; + phandle = <0x1d9>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1d6>; + phandle = <0x1d7>; + }; + }; + }; + }; + + tpdm@6880000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b968>; + reg = <0x6880000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-spss"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1d7>; + phandle = <0x1d6>; + }; + }; + }; + + funnel@6883000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6883000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-spss"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1d8>; + phandle = <0x197>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1d9>; + phandle = <0x1d5>; + }; + }; + + port@2 { + reg = <0x01>; + + endpoint { + slave-mode; + remote-endpoint = <0x1da>; + phandle = <0x1e5>; + }; + }; + }; + }; + + funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-qatb"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1db>; + phandle = <0x198>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1dc>; + phandle = <0x1a3>; + }; + }; + + port@2 { + reg = <0x06>; + + endpoint { + slave-mode; + remote-endpoint = <0x1dd>; + phandle = <0x1b5>; + }; + }; + + port@3 { + reg = <0x07>; + + endpoint { + slave-mode; + remote-endpoint = <0x1de>; + phandle = <0x1c9>; + }; + }; + }; + }; + + cti@69e1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x69e1000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-ddr_dl_0_cti"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@69e4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x69e4000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-ddr_dl_1_cti0"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@69e5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x69e5000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-ddr_dl_1_cti1"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@6c09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6c09000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-dlmm_cti0"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@6c0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6c0a000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-dlmm_cti1"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@78e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x78e0000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-apss_cti0"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@78f0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x78f0000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-apss_cti1"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@7900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x7900000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-apss_cti2"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@6010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti0"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + phandle = <0x18d>; + }; + + cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti1"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti2"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + qcom,cti-gpio-trigout = <0x04>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <0x1df>; + }; + + cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti3"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti4"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti5"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti6"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti7"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti8"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + phandle = <0x18e>; + }; + + cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti9"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti10"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti11"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti12"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti13"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti14"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti15"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@7020000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x7020000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu0"; + cpu = <0x11>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@7120000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x7120000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu1"; + cpu = <0x12>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@7220000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x7220000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu2"; + cpu = <0x13>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@7320000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x7320000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu3"; + cpu = <0x14>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@7420000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x7420000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu4"; + cpu = <0x15>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@7520000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x7520000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu5"; + cpu = <0x16>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@7620000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x7620000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu6"; + cpu = <0x17>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@7720000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x7720000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu7"; + cpu = <0x18>; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + cti@6b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b966>; + reg = <0x6b04000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-swao_cti0"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + tgu@6b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b999>; + reg = <0x6b0c000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <0x03>; + tgu-conditions = <0x04>; + tgu-regs = <0x04>; + tgu-timer-counters = <0x08>; + coresight-name = "coresight-tgu-ipcb"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + }; + + turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-turing-etm0"; + qcom,inst-id = <0x0d>; + + port { + + endpoint { + remote-endpoint = <0x1e0>; + phandle = <0x1ca>; + }; + }; + }; + + dummy_sink { + compatible = "qcom,coresight-dummy"; + coresight-name = "coresight-eud"; + qcom,dummy-sink; + + port { + + endpoint { + slave-mode; + remote-endpoint = <0x1e1>; + phandle = <0x180>; + }; + }; + }; + + sensor_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-sensor-etm0"; + qcom,inst-id = <0x08>; + + port { + + endpoint { + remote-endpoint = <0x1e2>; + phandle = <0x186>; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <0x02>; + + port { + + endpoint { + remote-endpoint = <0x1e3>; + phandle = <0x19b>; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <0x05>; + + port { + + endpoint { + remote-endpoint = <0x1e4>; + phandle = <0x1b6>; + }; + }; + }; + + spss_etm0 { + compatible = "qcom,coresight-dummy"; + coresight-name = "coresight-spss-etm0"; + qcom,dummy-source; + + port { + + endpoint { + remote-endpoint = <0x1e5>; + phandle = <0x1da>; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x7810000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-apss-merg"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1e6>; + phandle = <0x19e>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1e7>; + phandle = <0x1f4>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + slave-mode; + remote-endpoint = <0x1e8>; + phandle = <0x1d2>; + }; + }; + + port@3 { + reg = <0x04>; + + endpoint { + slave-mode; + remote-endpoint = <0x1e9>; + phandle = <0x1bb>; + }; + }; + + port@4 { + reg = <0x05>; + + endpoint { + slave-mode; + remote-endpoint = <0x1ea>; + phandle = <0x1be>; + }; + }; + + port@5 { + reg = <0x06>; + + endpoint { + slave-mode; + remote-endpoint = <0x1eb>; + phandle = <0x1c1>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb95d>; + reg = <0x7040000 0x1000>; + cpu = <0x11>; + coresight-name = "coresight-etm0"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1ec>; + phandle = <0x1f5>; + }; + }; + }; + + etm@7140000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb95d>; + reg = <0x7140000 0x1000>; + cpu = <0x12>; + coresight-name = "coresight-etm1"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1ed>; + phandle = <0x1f6>; + }; + }; + }; + + etm@7240000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb95d>; + reg = <0x7240000 0x1000>; + cpu = <0x13>; + coresight-name = "coresight-etm2"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1ee>; + phandle = <0x1f7>; + }; + }; + }; + + etm@7340000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb95d>; + reg = <0x7340000 0x1000>; + cpu = <0x14>; + coresight-name = "coresight-etm3"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1ef>; + phandle = <0x1f8>; + }; + }; + }; + + etm@7440000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb95d>; + reg = <0x7440000 0x1000>; + cpu = <0x15>; + coresight-name = "coresight-etm4"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1f0>; + phandle = <0x1f9>; + }; + }; + }; + + etm@7540000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb95d>; + reg = <0x7540000 0x1000>; + cpu = <0x16>; + coresight-name = "coresight-etm5"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1f1>; + phandle = <0x1fa>; + }; + }; + }; + + etm@7640000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb95d>; + reg = <0x7640000 0x1000>; + cpu = <0x17>; + coresight-name = "coresight-etm6"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1f2>; + phandle = <0x1fb>; + }; + }; + }; + + etm@7740000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb95d>; + reg = <0x7740000 0x1000>; + cpu = <0x18>; + coresight-name = "coresight-etm7"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + port { + + endpoint { + remote-endpoint = <0x1f3>; + phandle = <0x1fc>; + }; + }; + }; + + funnel@7800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x3b908>; + reg = <0x7800000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-apss"; + clocks = <0xa1 0x00>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x1f4>; + phandle = <0x1e7>; + }; + }; + + port@1 { + reg = <0x00>; + + endpoint { + slave-mode; + remote-endpoint = <0x1f5>; + phandle = <0x1ec>; + }; + }; + + port@2 { + reg = <0x01>; + + endpoint { + slave-mode; + remote-endpoint = <0x1f6>; + phandle = <0x1ed>; + }; + }; + + port@3 { + reg = <0x02>; + + endpoint { + slave-mode; + remote-endpoint = <0x1f7>; + phandle = <0x1ee>; + }; + }; + + port@4 { + reg = <0x03>; + + endpoint { + slave-mode; + remote-endpoint = <0x1f8>; + phandle = <0x1ef>; + }; + }; + + port@5 { + reg = <0x04>; + + endpoint { + slave-mode; + remote-endpoint = <0x1f9>; + phandle = <0x1f0>; + }; + }; + + port@6 { + reg = <0x05>; + + endpoint { + slave-mode; + remote-endpoint = <0x1fa>; + phandle = <0x1f1>; + }; + }; + + port@7 { + reg = <0x06>; + + endpoint { + slave-mode; + remote-endpoint = <0x1fb>; + phandle = <0x1f2>; + }; + }; + + port@8 { + reg = <0x07>; + + endpoint { + slave-mode; + remote-endpoint = <0x1fc>; + phandle = <0x1f3>; + }; + }; + }; + }; + + arm,smmu-kgsl@5040000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <0x01>; + qcom,dynamic; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <0x02>; + qcom,regulator-names = "vdd"; + vdd-supply = <0x1fd>; + interrupts = <0x00 0xe5 0x04 0x00 0xe7 0x04 0x00 0x16c 0x04 0x00 0x16d 0x04 0x00 0x16e 0x04 0x00 0x16f 0x04 0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04 0x00 0x173 0x04>; + clock-names = "gcc_gpu_memnoc_gfx_clk"; + clocks = <0x22 0x29>; + attach-impl-defs = <0x6000 0x2378 0x6060 0x1055 0x678c 0x08 0x6794 0x28 0x6800 0x06 0x6900 0x3ff 0x6924 0x204 0x6928 0x11000 0x6930 0x800 0x6960 0xffffffff 0x6b64 0x1a5551 0x6b68 0x9a82a382>; + phandle = <0x205>; + }; + + apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x80000 0x150c2000 0x20>; + reg-names = "base\0tcu-base"; + #iommu-cells = <0x02>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <0x01>; + #size-cells = <0x01>; + #address-cells = <0x01>; + ranges; + interrupts = <0x00 0x41 0x04 0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0xb5 0x04 0x00 0xb6 0x04 0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x13e 0x04 0x00 0x13f 0x04 0x00 0x140 0x04 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; + qcom,actlr = <0x880 0x08 0x103 0x881 0x08 0x103 0xc80 0x08 0x103 0xc81 0x08 0x103 0x1090 0x00 0x103 0x1091 0x00 0x103 0x10a0 0x08 0x103 0x10b0 0x00 0x103 0x10a1 0x08 0x103 0x10a3 0x08 0x103 0x10a4 0x08 0x103 0x10b4 0x00 0x103 0x10a5 0x08 0x103>; + qcom,mmu500-errata-1 = <0x800 0x3ff 0xc00 0x3ff>; + phandle = <0x29>; + + anoc_1_tbu@0x150c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150c5000 0x1000 0x150c2200 0x08>; + reg-names = "base\0status-reg"; + qcom,stream-id-range = <0x00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <0x1fe>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; + }; + + anoc_2_tbu@0x150c9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150c9000 0x1000 0x150c2208 0x08>; + reg-names = "base\0status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <0x1ff>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; + }; + + mnoc_hf_0_tbu@0x150cd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150cd000 0x1000 0x150c2210 0x08>; + reg-names = "base\0status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <0x200>; + qcom,msm-bus,name = "mnoc_hf_0_tbu"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8>; + }; + + mnoc_hf_1_tbu@0x150d1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d1000 0x1000 0x150c2218 0x08>; + reg-names = "base\0status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <0x201>; + qcom,msm-bus,name = "mnoc_hf_1_tbu"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8>; + }; + + mnoc_sf_0_tbu@0x150d5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d5000 0x1000 0x150c2220 0x08>; + reg-names = "base\0status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <0x202>; + qcom,msm-bus,name = "mnoc_sf_0_tbu"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x89 0x304 0x00 0x00 0x89 0x304 0x00 0x3e8>; + }; + + compute_dsp_tbu@0x150d9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d9000 0x1000 0x150c2228 0x08>; + reg-names = "base\0status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; + }; + + adsp_tbu@0x150dd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150dd000 0x1000 0x150c2230 0x08>; + reg-names = "base\0status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <0x203>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; + }; + + anoc_1_pcie_tbu@0x150e1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150e1000 0x1000 0x150c2238 0x08>; + reg-names = "base\0status-reg"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <0x204>; + clock-names = "gcc_aggre_noc_pcie_tbu_clk"; + clocks = <0x22 0x06>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; + }; + }; + + kgsl_iommu_test_device { + status = "disabled"; + compatible = "iommu-debug-test"; + iommus = <0x205 0x07>; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <0x29 0x20 0x00>; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <0x29 0x20 0x00>; + dma-coherent; + }; + + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,ion-heap@25 { + reg = <0x19>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@22 { + reg = <0x16>; + memory-region = <0x116>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { + reg = <0x1b>; + memory-region = <0x206>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { + reg = <0x13>; + memory-region = <0x207>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@13 { + reg = <0x0d>; + memory-region = <0x208>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@10 { + reg = <0x0a>; + memory-region = <0x209>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@9 { + reg = <0x09>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; + + qcom,smp2p-modem@1799000c { + compatible = "qcom,smp2p"; + reg = <0x1799000c 0x04>; + qcom,remote-pid = <0x01>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0x00 0x1c3 0x01>; + }; + + qcom,smp2p-adsp@1799000c { + compatible = "qcom,smp2p"; + reg = <0x1799000c 0x04>; + qcom,remote-pid = <0x02>; + qcom,irq-bitmask = <0x400>; + interrupts = <0x00 0x9e 0x01>; + }; + + qcom,smp2p-dsps@1799000c { + compatible = "qcom,smp2p"; + reg = <0x1799000c 0x04>; + qcom,remote-pid = <0x03>; + qcom,irq-bitmask = <0x4000000>; + interrupts = <0x00 0xac 0x01>; + }; + + qcom,smp2p-cdsp@1799000c { + compatible = "qcom,smp2p"; + reg = <0x1799000c 0x04>; + qcom,remote-pid = <0x05>; + qcom,irq-bitmask = <0x40>; + interrupts = <0x00 0x240 0x01>; + }; + + qcom,smp2pgpio-smp2p-15-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <0x0f>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x20a>; + }; + + qcom,smp2pgpio_test_smp2p_15_in { + compatible = "qcom,smp2pgpio_test_smp2p_15_in"; + gpios = <0x20a 0x00 0x00>; + }; + + qcom,smp2pgpio-smp2p-15-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <0x0f>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x20b>; + }; + + qcom,smp2pgpio_test_smp2p_15_out { + compatible = "qcom,smp2pgpio_test_smp2p_15_out"; + gpios = <0x20b 0x00 0x00>; + }; + + qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <0x01>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x20c>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <0x20c 0x00 0x00>; + }; + + qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <0x01>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x20d>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <0x20d 0x00 0x00>; + }; + + qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <0x02>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x20e>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <0x20e 0x00 0x00>; + }; + + qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <0x02>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x20f>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <0x20f 0x00 0x00>; + }; + + qcom,smp2pgpio-smp2p-3-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <0x03>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x210>; + }; + + qcom,smp2pgpio_test_smp2p_3_in { + compatible = "qcom,smp2pgpio_test_smp2p_3_in"; + gpios = <0x210 0x00 0x00>; + }; + + qcom,smp2pgpio-smp2p-3-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <0x03>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x211>; + }; + + qcom,smp2pgpio_test_smp2p_3_out { + compatible = "qcom,smp2pgpio_test_smp2p_3_out"; + gpios = <0x211 0x00 0x00>; + }; + + qcom,smp2pgpio-smp2p-5-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <0x05>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x212>; + }; + + qcom,smp2pgpio_test_smp2p_5_in { + compatible = "qcom,smp2pgpio_test_smp2p_5_in"; + gpios = <0x212 0x00 0x00>; + }; + + qcom,smp2pgpio-smp2p-5-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <0x05>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x213>; + }; + + qcom,smp2pgpio_test_smp2p_5_out { + compatible = "qcom,smp2pgpio_test_smp2p_5_out"; + gpios = <0x213 0x00 0x00>; + }; + + qcom,smp2pgpio-sleepstate-gpio-3-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "sleepstate"; + qcom,remote-pid = <0x03>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x214>; + }; + + qcom,smp2pgpio-sleepstate-3-out { + compatible = "qcom,smp2pgpio_sleepstate_3_out"; + gpios = <0x214 0x00 0x00>; + }; + + qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <0x01>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xf8>; + }; + + qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <0x01>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xf9>; + }; + + qcom,smp2pgpio-ssr-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <0x02>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xfc>; + }; + + qcom,smp2pgpio-ssr-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <0x02>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xfd>; + }; + + qcom,smp2pgpio-ssr-smp2p-3-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <0x03>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x101>; + }; + + qcom,smp2pgpio-ssr-smp2p-3-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <0x03>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x102>; + }; + + qcom,smp2pgpio-ssr-smp2p-5-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <0x05>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x114>; + }; + + qcom,smp2pgpio-ssr-smp2p-5-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <0x05>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x115>; + }; + + qcom,smp2pgpio-ipa-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "ipa"; + qcom,remote-pid = <0x01>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x13d>; + }; + + qcom,smp2pgpio-ipa-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "ipa"; + qcom,remote-pid = <0x01>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x13e>; + }; + + qcom,smp2pgpio-wlan-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "wlan"; + qcom,remote-pid = <0x01>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x140>; + }; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,csiphy@ac65000 { + cell-index = <0x00>; + compatible = "qcom,csiphy-v1.0\0qcom,csiphy"; + reg = <0xac65000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x65000>; + interrupts = <0x00 0x1dd 0x00>; + interrupt-names = "csiphy"; + gdscr-supply = <0x215>; + regulator-names = "gdscr\0refgen"; + csi-vdd-voltage = <0x124f80>; + mipi-csi-vdd-supply = <0x34>; + clocks = <0xd6 0x06 0xd6 0x55 0xd6 0x54 0xd6 0x09 0xd6 0x0a 0xd6 0x13 0xd6 0x0c 0xd6 0x0b>; + clock-names = "camnoc_axi_clk\0soc_ahb_clk\0slow_ahb_src_clk\0cpas_ahb_clk\0cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = <0x00 0x00 0x00 0x00 0x16e36000 0x00 0x100db355 0x00>; + status = "ok"; + refgen-supply = <0x17c>; + phandle = <0xbe>; + }; + + qcom,csiphy@ac66000 { + cell-index = <0x01>; + compatible = "qcom,csiphy-v1.0\0qcom,csiphy"; + reg = <0xac66000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x66000>; + interrupts = <0x00 0x1de 0x00>; + interrupt-names = "csiphy"; + gdscr-supply = <0x215>; + regulator-names = "gdscr\0refgen"; + csi-vdd-voltage = <0x124f80>; + mipi-csi-vdd-supply = <0x34>; + clocks = <0xd6 0x06 0xd6 0x55 0xd6 0x54 0xd6 0x09 0xd6 0x0a 0xd6 0x14 0xd6 0x0e 0xd6 0x0d>; + clock-names = "camnoc_axi_clk\0soc_ahb_clk\0slow_ahb_src_clk\0cpas_ahb_clk\0cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = <0x00 0x00 0x00 0x00 0x16e36000 0x00 0x100db355 0x00>; + status = "ok"; + refgen-supply = <0x17c>; + phandle = <0xbf>; + }; + + qcom,csiphy@ac67000 { + cell-index = <0x02>; + compatible = "qcom,csiphy-v1.0\0qcom,csiphy"; + reg = <0xac67000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x67000>; + interrupts = <0x00 0x1df 0x00>; + interrupt-names = "csiphy"; + gdscr-supply = <0x215>; + regulator-names = "gdscr\0refgen"; + csi-vdd-voltage = <0x124f80>; + mipi-csi-vdd-supply = <0x34>; + clocks = <0xd6 0x06 0xd6 0x55 0xd6 0x54 0xd6 0x09 0xd6 0x0a 0xd6 0x15 0xd6 0x10 0xd6 0x0f>; + clock-names = "camnoc_axi_clk\0soc_ahb_clk\0slow_ahb_src_clk\0cpas_ahb_clk\0cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = <0x00 0x00 0x00 0x00 0x16e36000 0x00 0x100db355 0x00>; + status = "ok"; + refgen-supply = <0x17c>; + phandle = <0xc0>; + }; + + qcom,cci@ac4a000 { + cell-index = <0x00>; + compatible = "qcom,cci"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0xac4a000 0x4000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupt-names = "cci"; + interrupts = <0x00 0x1cc 0x00>; + status = "ok"; + gdscr-supply = <0x215>; + regulator-names = "gdscr"; + clocks = <0xd6 0x06 0xd6 0x55 0xd6 0x54 0xd6 0x09 0xd6 0x07 0xd6 0x08>; + clock-names = "camnoc_axi_clk\0soc_ahb_clk\0slow_ahb_src_clk\0cpas_ahb_clk\0cci_clk\0cci_clk_src"; + src-clock-name = "cci_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0x23c3460>; + pinctrl-names = "cam_default\0cam_suspend"; + pinctrl-0 = <0x216 0x217>; + pinctrl-1 = <0x218 0x219>; + gpios = <0x3c 0x11 0x00 0x3c 0x12 0x00 0x3c 0x13 0x00 0x3c 0x14 0x00>; + gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; + gpio-req-tbl-flags = <0x01 0x01 0x01 0x01>; + gpio-req-tbl-label = "CCI_I2C_DATA0\0CCI_I2C_CLK0\0CCI_I2C_DATA1\0CCI_I2C_CLK1"; + phandle = <0xc1>; + + qcom,i2c_standard_mode { + hw-thigh = <0xc9>; + hw-tlow = <0xae>; + hw-tsu-sto = <0xcc>; + hw-tsu-sta = <0xe7>; + hw-thd-dat = <0x16>; + hw-thd-sta = <0xa2>; + hw-tbuf = <0xe3>; + hw-scl-stretch-en = <0x01>; + hw-trdhld = <0x06>; + hw-tsp = <0x03>; + cci-clk-src = <0x23c3460>; + status = "ok"; + }; + + qcom,i2c_fast_mode { + hw-thigh = <0x26>; + hw-tlow = <0x38>; + hw-tsu-sto = <0x28>; + hw-tsu-sta = <0x28>; + hw-thd-dat = <0x16>; + hw-thd-sta = <0x23>; + hw-tbuf = <0x3e>; + hw-scl-stretch-en = <0x01>; + hw-trdhld = <0x06>; + hw-tsp = <0x03>; + cci-clk-src = <0x23c3460>; + status = "ok"; + }; + + qcom,i2c_custom_mode { + hw-thigh = <0x26>; + hw-tlow = <0x38>; + hw-tsu-sto = <0x28>; + hw-tsu-sta = <0x28>; + hw-thd-dat = <0x16>; + hw-thd-sta = <0x23>; + hw-tbuf = <0x3e>; + hw-scl-stretch-en = <0x01>; + hw-trdhld = <0x06>; + hw-tsp = <0x03>; + cci-clk-src = <0x23c3460>; + status = "ok"; + }; + + qcom,i2c_fast_plus_mode { + hw-thigh = <0x10>; + hw-tlow = <0x16>; + hw-tsu-sto = <0x11>; + hw-tsu-sta = <0x12>; + hw-thd-dat = <0x10>; + hw-thd-sta = <0x0f>; + hw-tbuf = <0x18>; + hw-scl-stretch-en = <0x01>; + hw-trdhld = <0x03>; + hw-tsp = <0x03>; + cci-clk-src = <0x23c3460>; + status = "ok"; + }; + + qcom,actuator@0 { + cell-index = <0x00>; + reg = <0x00>; + compatible = "qcom,actuator"; + cci-master = <0x00>; + cam_vaf-supply = <0x21a>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0x2ab980>; + rgltr-max-voltage = <0x2ab980>; + rgltr-load-current = <0x00>; + phandle = <0x234>; + }; + + qcom,eeprom@2 { + cell-index = <0x02>; + reg = <0x02>; + compatible = "qcom,eeprom"; + slave-addr = <0x5a>; + i2c-freq-mode = <0x01>; + num-blocks = <0x01>; + page0 = <0x00 0x00 0x00 0x00 0x00 0x00>; + poll0 = <0x00 0x00 0x00 0x00 0x00 0x00>; + mem0 = <0x2000 0x00 0x02 0x00 0x01 0x00>; + qcom,cam-power-seq-type = "cam_vio"; + qcom,cam-power-seq-cfg-val = <0x01>; + qcom,cam-power-seq-delay = <0x01>; + cam_vio-supply = <0x21b>; + cam_vana-supply = <0x21c>; + cam_vdig-supply = <0x21b>; + cam_clk-supply = <0x215>; + regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0x1b7740 0x328980 0x149970 0x00>; + rgltr-max-voltage = <0x1b7740 0x36ee80 0x149970 0x00>; + rgltr-load-current = <0x2bf20 0x13880 0x20f58 0x00>; + gpio-no-mux = <0x00>; + pinctrl-names = "cam_default\0cam_suspend"; + pinctrl-0 = <0x21d 0x21e>; + pinctrl-1 = <0x21f 0x220>; + gpios = <0x3c 0x0f 0x00 0x3c 0x68 0x00 0x3c 0x1d 0x00 0x4c 0x09 0x00>; + gpio-reset = <0x01>; + gpio-vana = <0x02>; + gpio-vdig = <0x03>; + gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; + gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; + gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAM_VANA2\0CAM_VDIG2"; + cci-master = <0x00>; + status = "ok"; + clocks = <0xd6 0x46>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <0x16e3600>; + phandle = <0x237>; + }; + + qcom,eeprom@0 { + cell-index = <0x00>; + reg = <0x00>; + compatible = "qcom,eeprom"; + slave-addr = <0xa8>; + i2c-freq-mode = <0x01>; + num-blocks = <0x01>; + page0 = <0x00 0x00 0x00 0x00 0x00 0x00>; + poll0 = <0x00 0x00 0x00 0x00 0x00 0x00>; + mem0 = <0x2000 0x00 0x02 0x00 0x01 0x00>; + cam_vio-supply = <0x21b>; + cam_vana-supply = <0x21c>; + cam_vdig-supply = <0x221>; + cam_clk-supply = <0x215>; + regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0x1b7740 0x328980 0x149970 0x00>; + rgltr-max-voltage = <0x1b7740 0x36ee80 0x149970 0x00>; + rgltr-load-current = <0x2bf20 0x13880 0x19a28 0x00>; + gpio-no-mux = <0x00>; + pinctrl-names = "cam_default\0cam_suspend"; + pinctrl-0 = <0x222 0x223>; + pinctrl-1 = <0x224 0x225>; + gpios = <0x3c 0x0d 0x00 0x3c 0x50 0x00 0x3c 0x28 0x00 0x4c 0x0b 0x00>; + gpio-reset = <0x01>; + gpio-vana = <0x02>; + gpio-vdig = <0x03>; + gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; + gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; + gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET0\0CAM_VANA0\0CAM_VDIG0"; + cci-master = <0x00>; + status = "ok"; + clocks = <0xd6 0x42>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <0x16e3600>; + phandle = <0x235>; + }; + + qcom,eeprom@1 { + cell-index = <0x01>; + reg = <0x01>; + compatible = "qcom,eeprom"; + slave-addr = <0x30>; + i2c-freq-mode = <0x01>; + cam_vio-supply = <0x21b>; + cam_vana-supply = <0x21c>; + cam_vdig-supply = <0x221>; + cam_clk-supply = <0x215>; + regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0x1b7740 0x328980 0x149970 0x00>; + rgltr-max-voltage = <0x1b7740 0x36ee80 0x149970 0x00>; + rgltr-load-current = <0x2bf20 0x13880 0x19a28 0x00>; + gpio-no-mux = <0x00>; + pinctrl-names = "cam_default\0cam_suspend"; + pinctrl-0 = <0x226 0x227 0x228>; + pinctrl-1 = <0x229 0x22a 0x22b>; + gpios = <0x3c 0x0e 0x00 0x3c 0x1c 0x00 0x3c 0x4f 0x00 0x3c 0x5c 0x00>; + gpio-reset = <0x01>; + gpio-vana = <0x02>; + gpio-vdig = <0x03>; + gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; + gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; + gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET1\0CAM_VANA1\0CAM_VDIG1"; + sensor-mode = <0x00>; + cci-master = <0x01>; + status = "ok"; + clocks = <0xd6 0x44>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <0x16e3600>; + phandle = <0x236>; + }; + + qcom,eeprom@3 { + cell-index = <0x03>; + compatible = "qcom,eeprom"; + reg = <0x03>; + slave-addr = <0xc0>; + i2c-freq-mode = <0x01>; + cam_vio-supply = <0x21b>; + cam_vana-supply = <0x21c>; + cam_vdig-supply = <0x221>; + cam_clk-supply = <0x215>; + regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0x00 0x328980 0x149970 0x00>; + rgltr-max-voltage = <0x00 0x36ee80 0x149970 0x00>; + rgltr-load-current = <0x00 0x13880 0x13880 0x00>; + gpio-no-mux = <0x00>; + pinctrl-names = "cam_default\0cam_suspend"; + pinctrl-0 = <0x22c 0x22d 0x22e 0x22f>; + pinctrl-1 = <0x230 0x231 0x232>; + gpios = <0x3c 0x10 0x00 0x3c 0x19 0x00 0x3c 0x5b 0x00 0x3c 0x07 0x00>; + gpio-reset = <0x01>; + gpio-vana = <0x02>; + gpio-vdig = <0x03>; + gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; + gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; + gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3\0CAM_VANA3\0CAM_VDIG3"; + sensor-mode = <0x00>; + cci-master = <0x01>; + status = "ok"; + clocks = <0xd6 0x48>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <0x16e3600>; + phandle = <0x238>; + }; + + qcom,cam-sensor@0 { + cell-index = <0x00>; + compatible = "qcom,cam-sensor"; + reg = <0x00>; + csiphy-sd-index = <0x00>; + sensor-position-roll = <0x5a>; + sensor-position-pitch = <0x00>; + sensor-position-yaw = <0xb4>; + led-flash-src = <0x233>; + actuator-src = <0x234>; + eeprom-src = <0x235>; + cam_vio-supply = <0x21b>; + cam_vana-supply = <0x21c>; + cam_vdig-supply = <0x221>; + cam_clk-supply = <0x215>; + regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0x1b7740 0x328980 0x149970 0x00>; + rgltr-max-voltage = <0x1b7740 0x36ee80 0x149970 0x00>; + rgltr-load-current = <0x2bf20 0x13880 0x19a28 0x00>; + gpio-no-mux = <0x00>; + pinctrl-names = "cam_default\0cam_suspend"; + pinctrl-0 = <0x222 0x223>; + pinctrl-1 = <0x224 0x225>; + gpios = <0x3c 0x0d 0x00 0x3c 0x50 0x00 0x3c 0x28 0x00 0x4c 0x0b 0x00>; + gpio-reset = <0x01>; + gpio-vana = <0x02>; + gpio-vdig = <0x03>; + gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; + gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; + gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET0\0CAM_VANA0\0CAM_VDIG0"; + sensor-mode = <0x00>; + cci-master = <0x00>; + status = "ok"; + clocks = <0xd6 0x42>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <0x16e3600>; + }; + + qcom,cam-sensor@1 { + cell-index = <0x01>; + compatible = "qcom,cam-sensor"; + reg = <0x01>; + csiphy-sd-index = <0x01>; + sensor-position-roll = <0x5a>; + sensor-position-pitch = <0x00>; + sensor-position-yaw = <0xb4>; + led-flash-src = <0x233>; + eeprom-src = <0x236>; + cam_vio-supply = <0x21b>; + cam_vana-supply = <0x21c>; + cam_vdig-supply = <0x221>; + cam_clk-supply = <0x215>; + regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0x1b7740 0x328980 0x149970 0x00>; + rgltr-max-voltage = <0x1b7740 0x36ee80 0x149970 0x00>; + rgltr-load-current = <0x2bf20 0x13880 0x19a28 0x00>; + gpio-no-mux = <0x00>; + pinctrl-names = "cam_default\0cam_suspend"; + pinctrl-0 = <0x226 0x227 0x228>; + pinctrl-1 = <0x229 0x22a 0x22b>; + gpios = <0x3c 0x0e 0x00 0x3c 0x1c 0x00 0x3c 0x4f 0x00 0x3c 0x5c 0x00>; + gpio-reset = <0x01>; + gpio-vana = <0x02>; + gpio-vdig = <0x03>; + gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; + gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; + gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET1\0CAM_VANA1\0CAM_VDIG1"; + sensor-mode = <0x00>; + cci-master = <0x01>; + status = "ok"; + clocks = <0xd6 0x44>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <0x16e3600>; + }; + + qcom,cam-sensor@2 { + cell-index = <0x02>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <0x02>; + sensor-position-roll = <0x10e>; + sensor-position-pitch = <0x00>; + sensor-position-yaw = <0x00>; + eeprom-src = <0x237>; + cam_vio-supply = <0x21b>; + cam_vana-supply = <0x21c>; + cam_vdig-supply = <0x221>; + cam_clk-supply = <0x215>; + regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0x1b7740 0x328980 0x149970 0x00>; + rgltr-max-voltage = <0x1b7740 0x36ee80 0x149970 0x00>; + rgltr-load-current = <0x2bf20 0x13880 0x20f58 0x00>; + gpio-no-mux = <0x00>; + pinctrl-names = "cam_default\0cam_suspend"; + pinctrl-0 = <0x21d 0x21e>; + pinctrl-1 = <0x21f 0x220>; + gpios = <0x3c 0x0f 0x00 0x3c 0x68 0x00 0x3c 0x1d 0x00 0x4c 0x09 0x00>; + gpio-reset = <0x01>; + gpio-vana = <0x02>; + gpio-vdig = <0x03>; + gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; + gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; + gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAM_VANA2\0CAM_VDIG2"; + sensor-mode = <0x00>; + cci-master = <0x00>; + status = "ok"; + clocks = <0xd6 0x46>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <0x16e3600>; + }; + + qcom,cam-sensor@3 { + cell-index = <0x03>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <0x01>; + sensor-position-roll = <0x10e>; + sensor-position-pitch = <0x00>; + sensor-position-yaw = <0x00>; + eeprom-src = <0x238>; + cam_vio-supply = <0x21b>; + cam_vana-supply = <0x21c>; + cam_vdig-supply = <0x221>; + cam_clk-supply = <0x215>; + regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0x00 0x328980 0x149970 0x00>; + rgltr-max-voltage = <0x00 0x36ee80 0x149970 0x00>; + rgltr-load-current = <0x00 0x13880 0x13880 0x00>; + gpio-no-mux = <0x00>; + pinctrl-names = "cam_default\0cam_suspend"; + pinctrl-0 = <0x22c 0x22d 0x22e 0x22f>; + pinctrl-1 = <0x230 0x231 0x232>; + gpios = <0x3c 0x10 0x00 0x3c 0x19 0x00 0x3c 0x5b 0x00 0x3c 0x07 0x00>; + gpio-reset = <0x01>; + gpio-vana = <0x02>; + gpio-vdig = <0x03>; + gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; + gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; + gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3\0CAM_VANA3\0CAM_VDIG3"; + sensor-mode = <0x00>; + cci-master = <0x01>; + status = "ok"; + clocks = <0xd6 0x48>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <0x16e3600>; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + non-fatal-fault-disabled; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <0x29 0x808 0x00 0x29 0x810 0x08 0x29 0xc08 0x00 0x29 0xc10 0x08>; + label = "ife"; + + iova-mem-map { + + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x03>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <0x29 0x1060 0x08 0x29 0x1068 0x08>; + label = "jpeg"; + + iova-mem-map { + + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x03>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label = "icp"; + memory-region = <0x239>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <0x29 0x107a 0x02 0x29 0x1020 0x08 0x29 0x1040 0x08 0x29 0x1030 0x00 0x29 0x1050 0x00>; + label = "icp"; + + iova-mem-map { + + iova-mem-region-firmware { + iova-region-name = "firmware"; + iova-region-start = <0x00>; + iova-region-len = <0x500000>; + iova-region-id = <0x00>; + status = "ok"; + }; + + iova-mem-region-shared { + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x01>; + status = "ok"; + iova-granularity = <0x15>; + }; + + iova-mem-region-secondary-heap { + iova-region-name = "secheap"; + iova-region-start = <0x10a00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x04>; + status = "ok"; + }; + + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xcf300000>; + iova-region-id = <0x03>; + status = "ok"; + }; + + iova-mem-qdss-region { + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x05>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <0x29 0x1000 0x00>; + label = "cpas-cdm0"; + + iova-mem-map { + + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x03>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + label = "cam-secure"; + qcom,secure-cb; + }; + + msm_cam_smmu_fd { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <0x29 0x1070 0x00>; + label = "fd"; + + iova-mem-map { + + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x03>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <0x29 0x1038 0x00 0x29 0x1058 0x00>; + label = "lrme"; + + iova-mem-map { + + iova-mem-region-shared { + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x01>; + status = "ok"; + }; + + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0xd800000>; + iova-region-len = <0xd2800000>; + iova-region-id = <0x03>; + status = "ok"; + }; + }; + }; + }; + + qcom,cam-cpas@ac40000 { + cell-index = <0x00>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top\0cam_camnoc"; + reg = <0xac40000 0x1000 0xac42000 0x5000>; + reg-cam-base = <0x40000 0x42000>; + interrupt-names = "cpas_camnoc"; + interrupts = <0x00 0x1cb 0x00>; + qcom,cpas-hw-ver = <0x170110>; + camnoc-axi-min-ib-bw = <0xb2d05e00>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <0x215>; + clock-names = "gcc_ahb_clk\0gcc_axi_clk\0soc_ahb_clk\0slow_ahb_clk_src\0cpas_ahb_clk\0camnoc_axi_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x54 0xd6 0x09 0xd6 0x06>; + src-clock-name = "slow_ahb_clk_src"; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00>; + clock-cntl-level = "suspend\0minsvs\0lowsvs\0svs\0svs_l1\0nominal\0turbo"; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <0x07>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x12ad4 0x01 0x24d 0x00 0x12ad4 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x493e0 0x01 0x24d 0x00 0x493e0>; + vdd-corners = <0x01 0x11 0x31 0x41 0x81 0xc1 0x101 0x141 0x151 0x181 0x1a1>; + vdd-corner-ahb-mapping = "suspend\0suspend\0minsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; + client-id-based; + client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0cci0\0csid0\0csid1\0csid2\0ife0\0ife1\0ife2\0ipe0\0ipe1\0cam-cdm-intf0\0cpas-cdm0\0bps0\0icp0\0jpeg-dma0\0jpeg-enc0\0fd0\0lrmecpas0"; + client-axi-port-names = "cam_hf_1\0cam_hf_2\0cam_hf_2\0cam_hf_2\0cam_sf_1\0cam_hf_1\0cam_hf_2\0cam_hf_2\0cam_hf_1\0cam_hf_2\0cam_hf_2\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1"; + client-bus-camnoc-based; + + qcom,axi-port-list { + + qcom,axi-port1 { + qcom,axi-port-name = "cam_hf_1"; + + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_hf_1_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x88 0x200 0x00 0x00 0x88 0x200 0x00 0x00>; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_hf_1_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x92 0x30a 0x00 0x00 0x92 0x30a 0x00 0x00>; + }; + }; + + qcom,axi-port2 { + qcom,axi-port-name = "cam_hf_2"; + + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_hf_2_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x91 0x200 0x00 0x00 0x91 0x200 0x00 0x00>; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_hf_2_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x93 0x30a 0x00 0x00 0x93 0x30a 0x00 0x00>; + }; + }; + + qcom,axi-port3 { + qcom,axi-port-name = "cam_sf_1"; + + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_sf_1_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x89 0x200 0x00 0x00 0x89 0x200 0x00 0x00>; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_sf_1_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x94 0x30a 0x00 0x00 0x94 0x30a 0x00 0x00>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0x00>; + label = "cam-cdm-intf"; + num-hw-cdm = <0x01>; + cdm-client-names = "vfe\0jpegdma\0jpegenc\0fd\0lrmecdm"; + status = "ok"; + }; + + qcom,cpas-cdm0@ac48000 { + cell-index = <0x00>; + compatible = "qcom,cam170-cpas-cdm0"; + label = "cpas-cdm"; + reg = <0xac48000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x48000>; + interrupts = <0x00 0x1cd 0x00>; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <0x215>; + clock-names = "gcc_camera_ahb\0gcc_camera_axi\0cam_cc_soc_ahb_clk\0cam_cc_cpas_ahb_clk\0cam_cc_camnoc_axi_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x09 0xd6 0x06>; + clock-rates = <0x00 0x00 0x00 0x00 0x00>; + clock-cntl-level = "svs"; + cdm-client-names = "ife"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + qcom,csid0@acb3000 { + cell-index = <0x00>; + compatible = "qcom,csid170"; + reg-names = "csid"; + reg = <0xacb3000 0x1000>; + reg-cam-base = <0xb3000>; + interrupt-names = "csid"; + interrupts = <0x00 0x1d0 0x00>; + regulator-names = "camss\0ife0"; + camss-supply = <0x215>; + ife0-supply = <0x23a>; + clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_csid_clk\0ife_csid_clk_src\0ife_cphy_rx_clk\0cphy_rx_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk\0ife_axi_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x09 0xd6 0x54 0xd6 0x25 0xd6 0x26 0xd6 0x24 0xd6 0x0a 0xd6 0x22 0xd6 0x23 0xd6 0x06 0xd6 0x21>; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x23c34600 0x00 0x00>; + clock-cntl-level = "svs\0turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + phandle = <0xc2>; + }; + + qcom,vfe0@acaf000 { + cell-index = <0x00>; + compatible = "qcom,vfe170"; + reg-names = "ife"; + reg = <0xacaf000 0x4000>; + reg-cam-base = <0xaf000>; + interrupt-names = "ife"; + interrupts = <0x00 0x1d1 0x00>; + regulator-names = "camss\0ife0"; + camss-supply = <0x215>; + ife0-supply = <0x23a>; + clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk\0ife_axi_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x09 0xd6 0x54 0xd6 0x22 0xd6 0x23 0xd6 0x06 0xd6 0x21>; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00>; + clock-cntl-level = "svs\0svs_l1\0turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <0xd6 0x27>; + clock-rates-option = <0x23c34600>; + status = "ok"; + phandle = <0xc3>; + }; + + qcom,csid1@acba000 { + cell-index = <0x01>; + compatible = "qcom,csid170"; + reg-names = "csid"; + reg = <0xacba000 0x1000>; + reg-cam-base = <0xba000>; + interrupt-names = "csid"; + interrupts = <0x00 0x1d2 0x00>; + regulator-names = "camss\0ife1"; + camss-supply = <0x215>; + ife1-supply = <0x23b>; + clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_csid_clk\0ife_csid_clk_src\0ife_cphy_rx_clk\0cphy_rx_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk\0ife_axi_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x09 0xd6 0x54 0xd6 0x2c 0xd6 0x2d 0xd6 0x2b 0xd6 0x0a 0xd6 0x29 0xd6 0x2a 0xd6 0x06 0xd6 0x28>; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x23c34600 0x00 0x00>; + clock-cntl-level = "svs\0turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + phandle = <0xc4>; + }; + + qcom,vfe1@acb6000 { + cell-index = <0x01>; + compatible = "qcom,vfe170"; + reg-names = "ife"; + reg = <0xacb6000 0x4000>; + reg-cam-base = <0xb6000>; + interrupt-names = "ife"; + interrupts = <0x00 0x1d3 0x00>; + regulator-names = "camss\0ife1"; + camss-supply = <0x215>; + ife1-supply = <0x23b>; + clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk\0ife_axi_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x09 0xd6 0x54 0xd6 0x29 0xd6 0x2a 0xd6 0x06 0xd6 0x28>; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00>; + clock-cntl-level = "svs\0svs_l1\0turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <0xd6 0x2e>; + clock-rates-option = <0x23c34600>; + status = "ok"; + phandle = <0xc5>; + }; + + qcom,csid-lite@acc8000 { + cell-index = <0x02>; + compatible = "qcom,csid-lite170"; + reg-names = "csid-lite"; + reg = <0xacc8000 0x1000>; + reg-cam-base = <0xc8000>; + interrupt-names = "csid-lite"; + interrupts = <0x00 0x1d4 0x00>; + regulator-names = "camss"; + camss-supply = <0x215>; + clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_csid_clk\0ife_csid_clk_src\0ife_cphy_rx_clk\0cphy_rx_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x09 0xd6 0x54 0xd6 0x32 0xd6 0x33 0xd6 0x31 0xd6 0x0a 0xd6 0x2f 0xd6 0x30 0xd6 0x06>; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x23c34600 0x00>; + clock-cntl-level = "svs\0turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + phandle = <0xc6>; + }; + + qcom,vfe-lite@acc4000 { + cell-index = <0x02>; + compatible = "qcom,vfe-lite170"; + reg-names = "ife-lite"; + reg = <0xacc4000 0x4000>; + reg-cam-base = <0xc4000>; + interrupt-names = "ife-lite"; + interrupts = <0x00 0x1d5 0x00>; + regulator-names = "camss"; + camss-supply = <0x215>; + clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x09 0xd6 0x54 0xd6 0x2f 0xd6 0x30 0xd6 0x06>; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00>; + clock-cntl-level = "svs\0svs_l1\0turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + phandle = <0xc7>; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,a5\0qcom,ipe0\0qcom,ipe1\0qcom,bps"; + num-a5 = <0x01>; + num-ipe = <0x02>; + num-bps = <0x01>; + status = "ok"; + }; + + qcom,a5@ac00000 { + cell-index = <0x00>; + compatible = "qcom,cam-a5"; + reg = <0xac00000 0x6000 0xac10000 0x8000 0xac18000 0x3000>; + reg-names = "a5_qgic\0a5_sierra\0a5_csr"; + reg-cam-base = <0x00 0x10000 0x18000>; + interrupts = <0x00 0x1cf 0x00>; + interrupt-names = "a5"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <0x215>; + clock-names = "gcc_cam_ahb_clk\0gcc_cam_axi_clk\0soc_fast_ahb\0soc_ahb_clk\0cpas_ahb_clk\0camnoc_axi_clk\0icp_clk\0icp_clk_src"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x17 0xd6 0x55 0xd6 0x09 0xd6 0x06 0xd6 0x1d 0xd6 0x1e>; + clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x23c34600>; + clock-cntl-level = "svs\0turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-cfg = <0x7b 0x1ef>; + status = "ok"; + phandle = <0xc8>; + }; + + qcom,ipe0 { + cell-index = <0x00>; + compatible = "qcom,cam-ipe"; + reg = <0xac87000 0x3000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <0x23c>; + clock-names = "ipe_0_ahb_clk\0ipe_0_areg_clk\0ipe_0_axi_clk\0ipe_0_clk\0ipe_0_clk_src"; + src-clock-name = "ipe_0_clk_src"; + clock-control-debugfs = "true"; + clocks = <0xd6 0x34 0xd6 0x35 0xd6 0x36 0xd6 0x37 0xd6 0x38>; + clock-rates = <0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x00 0x23c34600>; + clock-cntl-level = "svs\0svs_l1\0nominal\0turbo"; + status = "ok"; + phandle = <0xc9>; + }; + + qcom,ipe1 { + cell-index = <0x01>; + compatible = "qcom,cam-ipe"; + reg = <0xac91000 0x3000>; + reg-names = "ipe1_top"; + reg-cam-base = <0x91000>; + regulator-names = "ipe1-vdd"; + ipe1-vdd-supply = <0x23d>; + clock-names = "ipe_1_ahb_clk\0ipe_1_areg_clk\0ipe_1_axi_clk\0ipe_1_clk\0ipe_1_clk_src"; + src-clock-name = "ipe_1_clk_src"; + clock-control-debugfs = "true"; + clocks = <0xd6 0x39 0xd6 0x3a 0xd6 0x3b 0xd6 0x3c 0xd6 0x3d>; + clock-rates = <0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x00 0x23c34600>; + clock-cntl-level = "svs\0svs_l1\0nominal\0turbo"; + status = "ok"; + phandle = <0xca>; + }; + + qcom,bps { + cell-index = <0x00>; + compatible = "qcom,cam-bps"; + reg = <0xac6f000 0x3000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <0x23e>; + clock-names = "bps_ahb_clk\0bps_areg_clk\0bps_axi_clk\0bps_clk\0bps_clk_src"; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + clocks = <0xd6 0x00 0xd6 0x01 0xd6 0x02 0xd6 0x03 0xd6 0x04>; + clock-rates = <0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600>; + clock-cntl-level = "svs\0svs_l1\0nominal\0turbo"; + status = "ok"; + phandle = <0xcb>; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc\0qcom,jpegdma"; + num-jpeg-enc = <0x01>; + num-jpeg-dma = <0x01>; + status = "ok"; + }; + + qcom,jpegenc@ac4e000 { + cell-index = <0x00>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac4e000 0x4000>; + reg-cam-base = <0x4e000>; + interrupt-names = "jpeg"; + interrupts = <0x00 0x1da 0x00>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <0x215>; + clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0camnoc_axi_clk\0jpegenc_clk_src\0jpegenc_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x09 0xd6 0x06 0xd6 0x3f 0xd6 0x3e>; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + qcom,jpegdma@0xac52000 { + cell-index = <0x00>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac52000 0x4000>; + reg-cam-base = <0x52000>; + interrupt-names = "jpegdma"; + interrupts = <0x00 0x1db 0x00>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <0x215>; + clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0camnoc_axi_clk\0jpegdma_clk_src\0jpegdma_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x09 0xd6 0x06 0xd6 0x3f 0xd6 0x3e>; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + qcom,cam-fd { + compatible = "qcom,cam-fd"; + compat-hw-name = "qcom,fd"; + num-fd = <0x01>; + status = "ok"; + }; + + qcom,fd@ac5a000 { + cell-index = <0x00>; + compatible = "qcom,fd41"; + reg-names = "fd_core\0fd_wrapper"; + reg = <0xac5a000 0x1000 0xac5b000 0x400>; + reg-cam-base = <0x5a000 0x5b000>; + interrupt-names = "fd"; + interrupts = <0x00 0x1ce 0x00>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <0x215>; + clock-names = "gcc_ahb_clk\0gcc_axi_clk\0soc_ahb_clk\0cpas_ahb_clk\0camnoc_axi_clk\0fd_core_clk_src\0fd_core_clk\0fd_core_uar_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x09 0xd6 0x06 0xd6 0x19 0xd6 0x18 0xd6 0x1a>; + src-clock-name = "fd_core_clk_src"; + clock-control-debugfs = "true"; + clock-cntl-level = "svs\0svs_l1\0turbo"; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00>; + status = "ok"; + }; + + ad-hoc-bus { + compatible = "qcom,msm-bus-device"; + reg = <0x16e0000 0x40000 0x1700000 0x40000 0x1500000 0x40000 0x14e0000 0x40000 0x17900000 0x40000 0x1380000 0x40000 0x1380000 0x40000 0x1740000 0x40000 0x1620000 0x40000 0x1620000 0x40000 0x1620000 0x40000>; + reg-names = "aggre1_noc-base\0aggre2_noc-base\0config_noc-base\0dc_noc-base\0gladiator_noc-base\0mc_virt-base\0mem_noc-base\0mmss_noc-base\0system_noc-base\0ipa_virt-base\0camnoc_virt-base"; + mbox-names = "apps_rsc\0disp_rsc"; + mboxes = <0xbb 0x00 0x30 0x00>; + + rsc-apps { + cell-id = <0x1f40>; + label = "apps_rsc"; + qcom,rsc-dev; + qcom,req_state = <0x02>; + phandle = <0x23f>; + }; + + rsc-disp { + cell-id = <0x1f41>; + label = "disp_rsc"; + qcom,rsc-dev; + qcom,req_state = <0x03>; + phandle = <0x240>; + }; + + bcm-acv { + cell-id = <0x1b7d>; + label = "ACV"; + qcom,bcm-name = "ACV"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2bd>; + }; + + bcm-alc { + cell-id = <0x1b7e>; + label = "ALC"; + qcom,bcm-name = "ALC"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2a5>; + }; + + bcm-mc0 { + cell-id = <0x1b58>; + label = "MC0"; + qcom,bcm-name = "MC0"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2bc>; + }; + + bcm-sh0 { + cell-id = <0x1b5b>; + label = "SH0"; + qcom,bcm-name = "SH0"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2c0>; + }; + + bcm-mm0 { + cell-id = <0x1b63>; + label = "MM0"; + qcom,bcm-name = "MM0"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2c6>; + }; + + bcm-sh1 { + cell-id = <0x1b5c>; + label = "SH1"; + qcom,bcm-name = "SH1"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2be>; + }; + + bcm-mm1 { + cell-id = <0x1b64>; + label = "MM1"; + qcom,bcm-name = "MM1"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x24d>; + }; + + bcm-sh2 { + cell-id = <0x1b5d>; + label = "SH2"; + qcom,bcm-name = "SH2"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2c2>; + }; + + bcm-mm2 { + cell-id = <0x1b65>; + label = "MM2"; + qcom,bcm-name = "MM2"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2c4>; + }; + + bcm-sh3 { + cell-id = <0x1b5e>; + label = "SH3"; + qcom,bcm-name = "SH3"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x28a>; + }; + + bcm-mm3 { + cell-id = <0x1b66>; + label = "MM3"; + qcom,bcm-name = "MM3"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x292>; + }; + + bcm-sh4 { + cell-id = <0x1b5f>; + label = "SH4"; + qcom,bcm-name = "SH4"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + }; + + bcm-sh5 { + cell-id = <0x1b60>; + label = "SH5"; + qcom,bcm-name = "SH5"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x28d>; + }; + + bcm-sn0 { + cell-id = <0x1b6a>; + label = "SN0"; + qcom,bcm-name = "SN0"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2cd>; + }; + + bcm-ce0 { + cell-id = <0x1b7a>; + label = "CE0"; + qcom,bcm-name = "CE0"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x249>; + }; + + bcm-ip0 { + cell-id = <0x1b7b>; + label = "IP0"; + qcom,bcm-name = "IP0"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2bb>; + }; + + bcm-cn0 { + cell-id = <0x1b7c>; + label = "CN0"; + qcom,bcm-name = "CN0"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x250>; + }; + + bcm-qup0 { + cell-id = <0x1b7f>; + label = "QUP0"; + qcom,bcm-name = "QUP0"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x244>; + }; + + bcm-sn1 { + cell-id = <0x1b6b>; + label = "SN1"; + qcom,bcm-name = "SN1"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2ce>; + }; + + bcm-sn2 { + cell-id = <0x1b6c>; + label = "SN2"; + qcom,bcm-name = "SN2"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2cb>; + }; + + bcm-sn3 { + cell-id = <0x1b6d>; + label = "SN3"; + qcom,bcm-name = "SN3"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2c9>; + }; + + bcm-sn4 { + cell-id = <0x1b6e>; + label = "SN4"; + qcom,bcm-name = "SN4"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2a4>; + }; + + bcm-sn5 { + cell-id = <0x1b6f>; + label = "SN5"; + qcom,bcm-name = "SN5"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2d1>; + }; + + bcm-sn6 { + cell-id = <0x1b70>; + label = "SN6"; + qcom,bcm-name = "SN6"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2c7>; + }; + + bcm-sn7 { + cell-id = <0x1b71>; + label = "SN7"; + qcom,bcm-name = "SN7"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2cf>; + }; + + bcm-sn8 { + cell-id = <0x1b72>; + label = "SN8"; + qcom,bcm-name = "SN8"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2d0>; + }; + + bcm-sn9 { + cell-id = <0x1b73>; + label = "SN9"; + qcom,bcm-name = "SN9"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x29b>; + }; + + bcm-sn11 { + cell-id = <0x1b75>; + label = "SN11"; + qcom,bcm-name = "SN11"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x29f>; + }; + + bcm-sn12 { + cell-id = <0x1b76>; + label = "SN12"; + qcom,bcm-name = "SN12"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2a0>; + }; + + bcm-sn14 { + cell-id = <0x1b78>; + label = "SN14"; + qcom,bcm-name = "SN14"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2a2>; + }; + + bcm-sn15 { + cell-id = <0x1b79>; + label = "SN15"; + qcom,bcm-name = "SN15"; + qcom,rscs = <0x23f>; + qcom,bcm-dev; + phandle = <0x2a1>; + }; + + bcm-mc0_display { + cell-id = <0x6978>; + label = "MC0_DISPLAY"; + qcom,bcm-name = "MC0"; + qcom,rscs = <0x240>; + qcom,bcm-dev; + phandle = <0x2d2>; + }; + + bcm-sh0_display { + cell-id = <0x6979>; + label = "SH0_DISPLAY"; + qcom,bcm-name = "SH0"; + qcom,rscs = <0x240>; + qcom,bcm-dev; + phandle = <0x2d4>; + }; + + bcm-mm0_display { + cell-id = <0x697a>; + label = "MM0_DISPLAY"; + qcom,bcm-name = "MM0"; + qcom,rscs = <0x240>; + qcom,bcm-dev; + phandle = <0x2d8>; + }; + + bcm-mm1_display { + cell-id = <0x697b>; + label = "MM1_DISPLAY"; + qcom,bcm-name = "MM1"; + qcom,rscs = <0x240>; + qcom,bcm-dev; + phandle = <0x2ac>; + }; + + bcm-mm2_display { + cell-id = <0x697c>; + label = "MM2_DISPLAY"; + qcom,bcm-name = "MM2"; + qcom,rscs = <0x240>; + qcom,bcm-dev; + phandle = <0x2d6>; + }; + + bcm-mm3_display { + cell-id = <0x697d>; + label = "MM3_DISPLAY"; + qcom,bcm-name = "MM3"; + qcom,rscs = <0x240>; + qcom,bcm-dev; + phandle = <0x2ae>; + }; + + fab-aggre1_noc { + cell-id = <0x1802>; + label = "fab-aggre1_noc"; + qcom,fab-dev; + qcom,base-name = "aggre1_noc-base"; + qcom,qos-off = <0x1000>; + qcom,base-offset = <0x4000>; + qcom,bus-type = <0x01>; + clocks; + phandle = <0x242>; + }; + + fab-aggre2_noc { + cell-id = <0x1803>; + label = "fab-aggre2_noc"; + qcom,fab-dev; + qcom,base-name = "aggre2_noc-base"; + qcom,qos-off = <0x1000>; + qcom,base-offset = <0x4000>; + qcom,bus-type = <0x01>; + clocks; + phandle = <0x247>; + }; + + fab-camnoc_virt { + cell-id = <0x180a>; + label = "fab-camnoc_virt"; + qcom,fab-dev; + qcom,base-name = "camnoc_virt-base"; + qcom,bypass-qos-prg; + clocks; + phandle = <0x24c>; + }; + + fab-config_noc { + cell-id = <0x1400>; + label = "fab-config_noc"; + qcom,fab-dev; + qcom,base-name = "config_noc-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <0x01>; + clocks; + phandle = <0x24f>; + }; + + fab-dc_noc { + cell-id = <0x1806>; + label = "fab-dc_noc"; + qcom,fab-dev; + qcom,base-name = "dc_noc-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <0x01>; + clocks; + phandle = <0x27d>; + }; + + fab-gladiator_noc { + cell-id = <0x1804>; + label = "fab-gladiator_noc"; + qcom,fab-dev; + qcom,base-name = "gladiator_noc-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <0x01>; + clocks; + phandle = <0x281>; + }; + + fab-ipa_virt { + cell-id = <0x1809>; + label = "fab-ipa_virt"; + qcom,fab-dev; + qcom,base-name = "ipa_virt-base"; + qcom,bypass-qos-prg; + clocks; + phandle = <0x283>; + }; + + fab-mc_virt { + cell-id = <0x1807>; + label = "fab-mc_virt"; + qcom,fab-dev; + qcom,base-name = "mc_virt-base"; + qcom,bypass-qos-prg; + clocks; + phandle = <0x285>; + }; + + fab-mem_noc { + cell-id = <0x1808>; + label = "fab-mem_noc"; + qcom,fab-dev; + qcom,base-name = "mem_noc-base"; + qcom,qos-off = <0x1000>; + qcom,base-offset = <0x10000>; + qcom,bus-type = <0x01>; + clocks; + phandle = <0x289>; + }; + + fab-mmss_noc { + cell-id = <0x800>; + label = "fab-mmss_noc"; + qcom,fab-dev; + qcom,base-name = "mmss_noc-base"; + qcom,qos-off = <0x1000>; + qcom,base-offset = <0x9000>; + qcom,bus-type = <0x01>; + clocks; + phandle = <0x28f>; + }; + + fab-system_noc { + cell-id = <0x400>; + label = "fab-system_noc"; + qcom,fab-dev; + qcom,base-name = "system_noc-base"; + qcom,qos-off = <0x1000>; + qcom,base-offset = <0x9000>; + qcom,bus-type = <0x01>; + clocks; + phandle = <0x294>; + }; + + fab-mc_virt_display { + cell-id = <0x6590>; + label = "fab-mc_virt_display"; + qcom,fab-dev; + qcom,base-name = "mc_virt-base"; + qcom,bypass-qos-prg; + clocks; + phandle = <0x2a7>; + }; + + fab-mem_noc_display { + cell-id = <0x6591>; + label = "fab-mem_noc_display"; + qcom,fab-dev; + qcom,base-name = "mem_noc-base"; + qcom,qos-off = <0x1000>; + qcom,base-offset = <0x10000>; + qcom,bypass-qos-prg; + qcom,bus-type = <0x01>; + clocks; + phandle = <0x2a9>; + }; + + fab-mmss_noc_display { + cell-id = <0x6592>; + label = "fab-mmss_noc_display"; + qcom,fab-dev; + qcom,base-name = "mmss_noc-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <0x01>; + clocks; + phandle = <0x2ab>; + }; + + mas-qhm-a1noc-cfg { + cell-id = <0x79>; + label = "mas-qhm-a1noc-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x241>; + qcom,bus-dev = <0x242>; + phandle = <0x2b2>; + }; + + mas-qhm-qup1 { + cell-id = <0x56>; + label = "mas-qhm-qup1"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x243>; + qcom,bus-dev = <0x242>; + qcom,bcms = <0x244>; + }; + + mas-qhm-tsif { + cell-id = <0x52>; + label = "mas-qhm-tsif"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x243>; + qcom,bus-dev = <0x242>; + }; + + mas-xm-sdc2 { + cell-id = <0x51>; + label = "mas-xm-sdc2"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x01>; + qcom,connections = <0x243>; + qcom,bus-dev = <0x242>; + qcom,ap-owned; + qcom,prio = <0x01>; + }; + + mas-xm-sdc4 { + cell-id = <0x50>; + label = "mas-xm-sdc4"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x02>; + qcom,connections = <0x243>; + qcom,bus-dev = <0x242>; + qcom,ap-owned; + qcom,prio = <0x01>; + }; + + mas-xm-ufs-card { + cell-id = <0x7a>; + label = "mas-xm-ufs-card"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x03>; + qcom,connections = <0x243>; + qcom,bus-dev = <0x242>; + qcom,ap-owned; + qcom,prio = <0x02>; + }; + + mas-xm-ufs-mem { + cell-id = <0x7b>; + label = "mas-xm-ufs-mem"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x04>; + qcom,connections = <0x243>; + qcom,bus-dev = <0x242>; + qcom,ap-owned; + qcom,prio = <0x02>; + }; + + mas-xm-pcie-0 { + cell-id = <0x2d>; + label = "mas-xm-pcie-0"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x05>; + qcom,connections = <0x245>; + qcom,bus-dev = <0x242>; + qcom,ap-owned; + qcom,prio = <0x02>; + }; + + mas-qhm-a2noc-cfg { + cell-id = <0x7c>; + label = "mas-qhm-a2noc-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x246>; + qcom,bus-dev = <0x247>; + phandle = <0x2b3>; + }; + + mas-qhm-qdss-bam { + cell-id = <0x35>; + label = "mas-qhm-qdss-bam"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x248>; + qcom,bus-dev = <0x247>; + }; + + mas-qhm-qup2 { + cell-id = <0x54>; + label = "mas-qhm-qup2"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x248>; + qcom,bus-dev = <0x247>; + qcom,bcms = <0x244>; + }; + + mas-qnm-cnoc { + cell-id = <0x76>; + label = "mas-qnm-cnoc"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x00>; + qcom,connections = <0x248>; + qcom,bus-dev = <0x247>; + qcom,ap-owned; + qcom,prio = <0x01>; + phandle = <0x2b7>; + }; + + mas-qxm-crypto { + cell-id = <0x7d>; + label = "mas-qxm-crypto"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x01>; + qcom,connections = <0x248>; + qcom,bus-dev = <0x247>; + qcom,bcms = <0x249>; + qcom,ap-owned; + qcom,prio = <0x02>; + }; + + mas-qxm-ipa { + cell-id = <0x5a>; + label = "mas-qxm-ipa"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x02>; + qcom,connections = <0x248>; + qcom,bus-dev = <0x247>; + qcom,ap-owned; + qcom,prio = <0x02>; + qcom,defer-init-qos; + qcom,node-qos-bcms = <0x1b7b 0x00 0x01>; + }; + + mas-xm-pcie3-1 { + cell-id = <0x64>; + label = "mas-xm-pcie3-1"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x06>; + qcom,connections = <0x24a>; + qcom,bus-dev = <0x247>; + qcom,ap-owned; + qcom,prio = <0x02>; + }; + + mas-xm-qdss-etr { + cell-id = <0x3c>; + label = "mas-xm-qdss-etr"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x07>; + qcom,connections = <0x248>; + qcom,bus-dev = <0x247>; + qcom,ap-owned; + qcom,prio = <0x02>; + }; + + mas-xm-usb3-0 { + cell-id = <0x3d>; + label = "mas-xm-usb3-0"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x0a>; + qcom,connections = <0x248>; + qcom,bus-dev = <0x247>; + qcom,ap-owned; + qcom,prio = <0x02>; + + qcom,node-qos-clks { + clocks = <0x22 0x09>; + clock-names = "clk-usb3-prim-axi-no-rate"; + }; + }; + + mas-xm-usb3-1 { + cell-id = <0x65>; + label = "mas-xm-usb3-1"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x0b>; + qcom,connections = <0x248>; + qcom,bus-dev = <0x247>; + qcom,ap-owned; + qcom,prio = <0x02>; + + qcom,node-qos-clks { + clocks = <0x22 0x0a>; + clock-names = "clk-usb3-sec-axi-no-rate"; + }; + }; + + mas-qxm-camnoc-hf0-uncomp { + cell-id = <0x92>; + label = "mas-qxm-camnoc-hf0-uncomp"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x24b>; + qcom,bus-dev = <0x24c>; + qcom,bcms = <0x24d>; + }; + + mas-qxm-camnoc-hf1-uncomp { + cell-id = <0x93>; + label = "mas-qxm-camnoc-hf1-uncomp"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x24b>; + qcom,bus-dev = <0x24c>; + qcom,bcms = <0x24d>; + }; + + mas-qxm-camnoc-sf-uncomp { + cell-id = <0x94>; + label = "mas-qxm-camnoc-sf-uncomp"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x24b>; + qcom,bus-dev = <0x24c>; + qcom,bcms = <0x24d>; + }; + + mas-qhm-spdm { + cell-id = <0x24>; + label = "mas-qhm-spdm"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x24e>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + }; + + mas-qnm-snoc { + cell-id = <0x2733>; + label = "mas-qnm-snoc"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x251 0x252 0x253 0x254 0x255 0x256 0x257 0x258 0x259 0x25a 0x25b 0x25c 0x25d 0x25e 0x25f 0x260 0x261 0x262 0x263 0x264 0x265 0x266 0x267 0x268 0x269 0x26a 0x26b 0x26c 0x26d 0x26e 0x26f 0x270 0x271 0x272 0x273 0x274 0x275 0x276 0x277 0x278 0x279 0x27a>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x2c8>; + }; + + mas-qhm-cnoc { + cell-id = <0x7e>; + label = "mas-qhm-cnoc"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x27b 0x27c>; + qcom,bus-dev = <0x27d>; + phandle = <0x2b4>; + }; + + mas-acm-l3 { + cell-id = <0x01>; + label = "mas-acm-l3"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x27e 0x27f 0x280>; + qcom,bus-dev = <0x281>; + }; + + mas-pm-gnoc-cfg { + cell-id = <0x7f>; + label = "mas-pm-gnoc-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x27e>; + qcom,bus-dev = <0x281>; + }; + + mas-ipa-core-master { + cell-id = <0x8f>; + label = "mas-ipa-core-master"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x282>; + qcom,bus-dev = <0x283>; + }; + + mas-llcc-mc { + cell-id = <0x81>; + label = "mas-llcc-mc"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x04>; + qcom,connections = <0x284>; + qcom,bus-dev = <0x285>; + phandle = <0x2bf>; + }; + + mas-acm-tcu { + cell-id = <0x68>; + label = "mas-acm-tcu"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x00>; + qcom,connections = <0x286 0x287 0x288>; + qcom,bus-dev = <0x289>; + qcom,bcms = <0x28a>; + qcom,ap-owned; + qcom,prio = <0x07>; + }; + + mas-qhm-memnoc-cfg { + cell-id = <0x82>; + label = "mas-qhm-memnoc-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x28b 0x28c>; + qcom,bus-dev = <0x289>; + phandle = <0x2b8>; + }; + + mas-qnm-apps { + cell-id = <0x83>; + label = "mas-qnm-apps"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x02>; + qcom,qport = <0x02 0x03>; + qcom,connections = <0x287>; + qcom,bus-dev = <0x289>; + qcom,bcms = <0x28d>; + qcom,ap-owned; + qcom,prio = <0x00>; + phandle = <0x2ba>; + }; + + mas-qnm-mnoc-hf { + cell-id = <0x84>; + label = "mas-qnm-mnoc-hf"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x02>; + qcom,qport = <0x04 0x05>; + qcom,connections = <0x286 0x287>; + qcom,bus-dev = <0x289>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + qcom,node-qos-bcms = <0x1b64 0x00 0x01>; + phandle = <0x2c5>; + }; + + mas-qnm-mnoc-sf { + cell-id = <0x85>; + label = "mas-qnm-mnoc-sf"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x07>; + qcom,connections = <0x286 0x287 0x288>; + qcom,bus-dev = <0x289>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + qcom,node-qos-bcms = <0x1b64 0x00 0x01>; + phandle = <0x2c3>; + }; + + mas-qnm-snoc-gc { + cell-id = <0x86>; + label = "mas-qnm-snoc-gc"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x08>; + qcom,connections = <0x287>; + qcom,bus-dev = <0x289>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + phandle = <0x2ca>; + }; + + mas-qnm-snoc-sf { + cell-id = <0x87>; + label = "mas-qnm-snoc-sf"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x09>; + qcom,connections = <0x286 0x287>; + qcom,bus-dev = <0x289>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + phandle = <0x2cc>; + }; + + mas-qxm-gpu { + cell-id = <0x1a>; + label = "mas-qxm-gpu"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x02>; + qcom,qport = <0x0a 0x0b>; + qcom,connections = <0x286 0x287 0x288>; + qcom,bus-dev = <0x289>; + qcom,ap-owned; + qcom,prio = <0x00>; + }; + + mas-qhm-mnoc-cfg { + cell-id = <0x67>; + label = "mas-qhm-mnoc-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x28e>; + qcom,bus-dev = <0x28f>; + phandle = <0x2b5>; + }; + + mas-qxm-camnoc-hf0 { + cell-id = <0x88>; + label = "mas-qxm-camnoc-hf0"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x01>; + qcom,connections = <0x290>; + qcom,bus-dev = <0x28f>; + qcom,bcms = <0x24d>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + qcom,node-qos-bcms = <0x1b64 0x00 0x01>; + }; + + mas-qxm-camnoc-hf1 { + cell-id = <0x91>; + label = "mas-qxm-camnoc-hf1"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x02>; + qcom,connections = <0x290>; + qcom,bus-dev = <0x28f>; + qcom,bcms = <0x24d>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + qcom,node-qos-bcms = <0x1b64 0x00 0x01>; + }; + + mas-qxm-camnoc-sf { + cell-id = <0x89>; + label = "mas-qxm-camnoc-sf"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x00>; + qcom,connections = <0x291>; + qcom,bus-dev = <0x28f>; + qcom,bcms = <0x292>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + qcom,node-qos-bcms = <0x1b64 0x00 0x01>; + }; + + mas-qxm-mdp0 { + cell-id = <0x16>; + label = "mas-qxm-mdp0"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x03>; + qcom,connections = <0x290>; + qcom,bus-dev = <0x28f>; + qcom,bcms = <0x24d>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + qcom,node-qos-bcms = <0x1b64 0x00 0x01>; + }; + + mas-qxm-mdp1 { + cell-id = <0x17>; + label = "mas-qxm-mdp1"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x04>; + qcom,connections = <0x290>; + qcom,bus-dev = <0x28f>; + qcom,bcms = <0x24d>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + qcom,node-qos-bcms = <0x1b64 0x00 0x01>; + }; + + mas-qxm-rot { + cell-id = <0x19>; + label = "mas-qxm-rot"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x05>; + qcom,connections = <0x291>; + qcom,bus-dev = <0x28f>; + qcom,bcms = <0x292>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + qcom,node-qos-bcms = <0x1b64 0x00 0x01>; + }; + + mas-qxm-venus0 { + cell-id = <0x3f>; + label = "mas-qxm-venus0"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x06>; + qcom,connections = <0x291>; + qcom,bus-dev = <0x28f>; + qcom,bcms = <0x292>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + qcom,node-qos-bcms = <0x1b64 0x00 0x01>; + }; + + mas-qxm-venus1 { + cell-id = <0x40>; + label = "mas-qxm-venus1"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x07>; + qcom,connections = <0x291>; + qcom,bus-dev = <0x28f>; + qcom,bcms = <0x292>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + qcom,node-qos-bcms = <0x1b64 0x00 0x01>; + }; + + mas-qxm-venus-arm9 { + cell-id = <0x8a>; + label = "mas-qxm-venus-arm9"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x08>; + qcom,connections = <0x291>; + qcom,bus-dev = <0x28f>; + qcom,bcms = <0x292>; + qcom,ap-owned; + qcom,prio = <0x00>; + qcom,forwarding; + qcom,node-qos-bcms = <0x1b64 0x00 0x01>; + }; + + mas-qhm-snoc-cfg { + cell-id = <0x36>; + label = "mas-qhm-snoc-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x293>; + qcom,bus-dev = <0x294>; + phandle = <0x2b6>; + }; + + mas-qnm-aggre1-noc { + cell-id = <0x274f>; + label = "mas-qnm-aggre1-noc"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x295 0x296 0x297 0x298 0x299 0x29a>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x29b>; + phandle = <0x2af>; + }; + + mas-qnm-aggre2-noc { + cell-id = <0x2750>; + label = "mas-qnm-aggre2-noc"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x295 0x296 0x29c 0x297 0x298 0x299 0x29d 0x29e 0x29a>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x29f>; + phandle = <0x2b1>; + }; + + mas-qnm-gladiator-sodv { + cell-id = <0x8b>; + label = "mas-qnm-gladiator-sodv"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x295 0x29c 0x297 0x298 0x299 0x29d 0x29e 0x29a>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2a0>; + phandle = <0x2b9>; + }; + + mas-qnm-memnoc { + cell-id = <0x8e>; + label = "mas-qnm-memnoc"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x297 0x298 0x295 0x299 0x29a>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2a1>; + phandle = <0x2c1>; + }; + + mas-qnm-pcie-anoc { + cell-id = <0x8c>; + label = "mas-qnm-pcie-anoc"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x01>; + qcom,connections = <0x297 0x298 0x299 0x296 0x29a>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2a2>; + phandle = <0x2b0>; + }; + + mas-qxm-pimem { + cell-id = <0x8d>; + label = "mas-qxm-pimem"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x03>; + qcom,connections = <0x297 0x2a3>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2a4>; + qcom,ap-owned; + qcom,prio = <0x02>; + }; + + mas-xm-gic { + cell-id = <0x95>; + label = "mas-xm-gic"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x00>; + qcom,connections = <0x297 0x2a3>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2a0>; + qcom,ap-owned; + qcom,prio = <0x01>; + }; + + mas-alc { + cell-id = <0x90>; + label = "mas-alc"; + qcom,buswidth = <0x01>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x285>; + qcom,bcms = <0x2a5>; + }; + + mas-llcc-mc_display { + cell-id = <0x4e20>; + label = "mas-llcc-mc_display"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x04>; + qcom,connections = <0x2a6>; + qcom,bus-dev = <0x2a7>; + phandle = <0x2d3>; + }; + + mas-qnm-mnoc-hf_display { + cell-id = <0x4e21>; + label = "mas-qnm-mnoc-hf_display"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x02>; + qcom,qport = <0x04 0x05>; + qcom,connections = <0x2a8>; + qcom,bus-dev = <0x2a9>; + phandle = <0x2d7>; + }; + + mas-qnm-mnoc-sf_display { + cell-id = <0x4e22>; + label = "mas-qnm-mnoc-sf_display"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x07>; + qcom,connections = <0x2a8>; + qcom,bus-dev = <0x2a9>; + phandle = <0x2d5>; + }; + + mas-qxm-mdp0_display { + cell-id = <0x4e23>; + label = "mas-qxm-mdp0_display"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x03>; + qcom,connections = <0x2aa>; + qcom,bus-dev = <0x2ab>; + qcom,bcms = <0x2ac>; + }; + + mas-qxm-mdp1_display { + cell-id = <0x4e24>; + label = "mas-qxm-mdp1_display"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x04>; + qcom,connections = <0x2aa>; + qcom,bus-dev = <0x2ab>; + qcom,bcms = <0x2ac>; + }; + + mas-qxm-rot_display { + cell-id = <0x4e25>; + label = "mas-qxm-rot_display"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,qport = <0x05>; + qcom,connections = <0x2ad>; + qcom,bus-dev = <0x2ab>; + qcom,bcms = <0x2ae>; + }; + + slv-qns-a1noc-snoc { + cell-id = <0x274e>; + label = "slv-qns-a1noc-snoc"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x242>; + qcom,connections = <0x2af>; + phandle = <0x243>; + }; + + slv-srvc-aggre1-noc { + cell-id = <0x2e8>; + label = "slv-srvc-aggre1-noc"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x242>; + qcom,bcms = <0x29b>; + phandle = <0x241>; + }; + + slv-qns-pcie-a1noc-snoc { + cell-id = <0x2754>; + label = "slv-qns-pcie-a1noc-snoc"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x242>; + qcom,connections = <0x2b0>; + phandle = <0x245>; + }; + + slv-qns-a2noc-snoc { + cell-id = <0x2751>; + label = "slv-qns-a2noc-snoc"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x247>; + qcom,connections = <0x2b1>; + phandle = <0x248>; + }; + + slv-qns-pcie-snoc { + cell-id = <0x2e9>; + label = "slv-qns-pcie-snoc"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x247>; + qcom,connections = <0x2b0>; + phandle = <0x24a>; + }; + + slv-srvc-aggre2-noc { + cell-id = <0x2ea>; + label = "slv-srvc-aggre2-noc"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x247>; + qcom,bcms = <0x29f>; + phandle = <0x246>; + }; + + slv-qns-camnoc-uncomp { + cell-id = <0x30a>; + label = "slv-qns-camnoc-uncomp"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24c>; + phandle = <0x24b>; + }; + + slv-qhs-a1-noc-cfg { + cell-id = <0x2af>; + label = "slv-qhs-a1-noc-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,connections = <0x2b2>; + qcom,bcms = <0x250>; + phandle = <0x270>; + }; + + slv-qhs-a2-noc-cfg { + cell-id = <0x2b0>; + label = "slv-qhs-a2-noc-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,connections = <0x2b3>; + qcom,bcms = <0x250>; + phandle = <0x25b>; + }; + + slv-qhs-aop { + cell-id = <0x2eb>; + label = "slv-qhs-aop"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x268>; + }; + + slv-qhs-aoss { + cell-id = <0x2ec>; + label = "slv-qhs-aoss"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x271>; + }; + + slv-qhs-camera-cfg { + cell-id = <0x24d>; + label = "slv-qhs-camera-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x253>; + }; + + slv-qhs-clk-ctl { + cell-id = <0x26c>; + label = "slv-qhs-clk-ctl"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x279>; + }; + + slv-qhs-compute-dsp-cfg { + cell-id = <0x2ed>; + label = "slv-qhs-compute-dsp-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x267>; + }; + + slv-qhs-cpr-cx { + cell-id = <0x28b>; + label = "slv-qhs-cpr-cx"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x26f>; + }; + + slv-qhs-crypto0-cfg { + cell-id = <0x271>; + label = "slv-qhs-crypto0-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x276>; + }; + + slv-qhs-dcc-cfg { + cell-id = <0x2aa>; + label = "slv-qhs-dcc-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,connections = <0x2b4>; + qcom,bcms = <0x250>; + phandle = <0x25f>; + }; + + slv-qhs-ddrss-cfg { + cell-id = <0x2ee>; + label = "slv-qhs-ddrss-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x260>; + }; + + slv-qhs-display-cfg { + cell-id = <0x24e>; + label = "slv-qhs-display-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x25d>; + }; + + slv-qhs-glm { + cell-id = <0x2d6>; + label = "slv-qhs-glm"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x259>; + }; + + slv-qhs-gpuss-cfg { + cell-id = <0x256>; + label = "slv-qhs-gpuss-cfg"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x264>; + }; + + slv-qhs-imem-cfg { + cell-id = <0x273>; + label = "slv-qhs-imem-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x27a>; + }; + + slv-qhs-ipa { + cell-id = <0x2a4>; + label = "slv-qhs-ipa"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x26e>; + }; + + slv-qhs-mnoc-cfg { + cell-id = <0x280>; + label = "slv-qhs-mnoc-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,connections = <0x2b5>; + qcom,bcms = <0x250>; + phandle = <0x256>; + }; + + slv-qhs-pcie0-cfg { + cell-id = <0x29b>; + label = "slv-qhs-pcie0-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x263>; + }; + + slv-qhs-pcie-gen3-cfg { + cell-id = <0x29c>; + label = "slv-qhs-pcie-gen3-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x262>; + }; + + slv-qhs-pdm { + cell-id = <0x267>; + label = "slv-qhs-pdm"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x25a>; + }; + + slv-qhs-phy-refgen-south { + cell-id = <0x2f0>; + label = "slv-qhs-phy-refgen-south"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x261>; + }; + + slv-qhs-pimem-cfg { + cell-id = <0x2a9>; + label = "slv-qhs-pimem-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x277>; + }; + + slv-qhs-prng { + cell-id = <0x26a>; + label = "slv-qhs-prng"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x272>; + }; + + slv-qhs-qdss-cfg { + cell-id = <0x27b>; + label = "slv-qhs-qdss-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x25c>; + }; + + slv-qhs-qupv3-north { + cell-id = <0x263>; + label = "slv-qhs-qupv3-north"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x269>; + }; + + slv-qhs-qupv3-south { + cell-id = <0x265>; + label = "slv-qhs-qupv3-south"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x274>; + }; + + slv-qhs-sdc2 { + cell-id = <0x260>; + label = "slv-qhs-sdc2"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x255>; + }; + + slv-qhs-sdc4 { + cell-id = <0x261>; + label = "slv-qhs-sdc4"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x254>; + }; + + slv-qhs-snoc-cfg { + cell-id = <0x282>; + label = "slv-qhs-snoc-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,connections = <0x2b6>; + qcom,bcms = <0x250>; + phandle = <0x258>; + }; + + slv-qhs-spdm { + cell-id = <0x279>; + label = "slv-qhs-spdm"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x275>; + }; + + slv-qhs-spss-cfg { + cell-id = <0x2f1>; + label = "slv-qhs-spss-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x252>; + }; + + slv-qhs-tcsr { + cell-id = <0x26f>; + label = "slv-qhs-tcsr"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x25e>; + }; + + slv-qhs-tlmm-north { + cell-id = <0x2db>; + label = "slv-qhs-tlmm-north"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x278>; + }; + + slv-qhs-tlmm-south { + cell-id = <0x2f3>; + label = "slv-qhs-tlmm-south"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x251>; + }; + + slv-qhs-tsif { + cell-id = <0x23f>; + label = "slv-qhs-tsif"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x266>; + }; + + slv-qhs-ufs-card-cfg { + cell-id = <0x2f4>; + label = "slv-qhs-ufs-card-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x26c>; + }; + + slv-qhs-ufs-mem-cfg { + cell-id = <0x2f5>; + label = "slv-qhs-ufs-mem-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x257>; + }; + + slv-qhs-usb3-0 { + cell-id = <0x247>; + label = "slv-qhs-usb3-0"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x26a>; + }; + + slv-qhs-usb3-1 { + cell-id = <0x2ef>; + label = "slv-qhs-usb3-1"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x26d>; + }; + + slv-qhs-venus-cfg { + cell-id = <0x254>; + label = "slv-qhs-venus-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x265>; + }; + + slv-qhs-vsense-ctrl-cfg { + cell-id = <0x2f6>; + label = "slv-qhs-vsense-ctrl-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x273>; + }; + + slv-qns-cnoc-a2noc { + cell-id = <0x2d5>; + label = "slv-qns-cnoc-a2noc"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,connections = <0x2b7>; + qcom,bcms = <0x250>; + phandle = <0x24e>; + }; + + slv-srvc-cnoc { + cell-id = <0x286>; + label = "slv-srvc-cnoc"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x24f>; + qcom,bcms = <0x250>; + phandle = <0x26b>; + }; + + slv-qhs-llcc { + cell-id = <0x2f8>; + label = "slv-qhs-llcc"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x27d>; + phandle = <0x27c>; + }; + + slv-qhs-memnoc { + cell-id = <0x2f9>; + label = "slv-qhs-memnoc"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x27d>; + qcom,connections = <0x2b8>; + phandle = <0x27b>; + }; + + slv-qns-gladiator-sodv { + cell-id = <0x2d8>; + label = "slv-qns-gladiator-sodv"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x281>; + qcom,connections = <0x2b9>; + phandle = <0x27f>; + }; + + slv-qns-gnoc-memnoc { + cell-id = <0x2fb>; + label = "slv-qns-gnoc-memnoc"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x02>; + qcom,bus-dev = <0x281>; + qcom,connections = <0x2ba>; + phandle = <0x280>; + }; + + slv-srvc-gnoc { + cell-id = <0x2fc>; + label = "slv-srvc-gnoc"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x281>; + phandle = <0x27e>; + }; + + slv-ipa-core-slave { + cell-id = <0x309>; + label = "slv-ipa-core-slave"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x283>; + qcom,bcms = <0x2bb>; + phandle = <0x282>; + }; + + slv-ebi { + cell-id = <0x200>; + label = "slv-ebi"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x04>; + qcom,bus-dev = <0x285>; + qcom,bcms = <0x2bc 0x2bd>; + phandle = <0x284>; + }; + + slv-qhs-mdsp-ms-mpu-cfg { + cell-id = <0x2fd>; + label = "slv-qhs-mdsp-ms-mpu-cfg"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x289>; + phandle = <0x28c>; + }; + + slv-qns-apps-io { + cell-id = <0x2fe>; + label = "slv-qns-apps-io"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x289>; + qcom,bcms = <0x2be>; + phandle = <0x286>; + }; + + slv-qns-llcc { + cell-id = <0x302>; + label = "slv-qns-llcc"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x04>; + qcom,bus-dev = <0x289>; + qcom,connections = <0x2bf>; + qcom,bcms = <0x2c0>; + phandle = <0x287>; + }; + + slv-qns-memnoc-snoc { + cell-id = <0x308>; + label = "slv-qns-memnoc-snoc"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x289>; + qcom,connections = <0x2c1>; + qcom,bcms = <0x2c2>; + phandle = <0x288>; + }; + + slv-srvc-memnoc { + cell-id = <0x303>; + label = "slv-srvc-memnoc"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x289>; + phandle = <0x28b>; + }; + + slv-qns2-mem-noc { + cell-id = <0x304>; + label = "slv-qns2-mem-noc"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x28f>; + qcom,connections = <0x2c3>; + qcom,bcms = <0x2c4>; + phandle = <0x291>; + }; + + slv-qns-mem-noc-hf { + cell-id = <0x305>; + label = "slv-qns-mem-noc-hf"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x02>; + qcom,bus-dev = <0x28f>; + qcom,connections = <0x2c5>; + qcom,bcms = <0x2c6>; + phandle = <0x290>; + }; + + slv-srvc-mnoc { + cell-id = <0x25b>; + label = "slv-srvc-mnoc"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x28f>; + phandle = <0x28e>; + }; + + slv-qhs-apss { + cell-id = <0x2a1>; + label = "slv-qhs-apss"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2c7>; + phandle = <0x298>; + }; + + slv-qns-cnoc { + cell-id = <0x2734>; + label = "slv-qns-cnoc"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x294>; + qcom,connections = <0x2c8>; + qcom,bcms = <0x2c9>; + phandle = <0x299>; + }; + + slv-qns-memnoc-gc { + cell-id = <0x306>; + label = "slv-qns-memnoc-gc"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x294>; + qcom,connections = <0x2ca>; + qcom,bcms = <0x2cb>; + phandle = <0x2a3>; + }; + + slv-qns-memnoc-sf { + cell-id = <0x307>; + label = "slv-qns-memnoc-sf"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x294>; + qcom,connections = <0x2cc>; + qcom,bcms = <0x2cd>; + phandle = <0x296>; + }; + + slv-qxs-imem { + cell-id = <0x249>; + label = "slv-qxs-imem"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2ce>; + phandle = <0x297>; + }; + + slv-qxs-pcie { + cell-id = <0x299>; + label = "slv-qxs-pcie"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2cf>; + phandle = <0x29d>; + }; + + slv-qxs-pcie-gen3 { + cell-id = <0x29a>; + label = "slv-qxs-pcie-gen3"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2d0>; + phandle = <0x29c>; + }; + + slv-qxs-pimem { + cell-id = <0x2c8>; + label = "slv-qxs-pimem"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x294>; + phandle = <0x295>; + }; + + slv-srvc-snoc { + cell-id = <0x24b>; + label = "slv-srvc-snoc"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2c7>; + phandle = <0x293>; + }; + + slv-xs-qdss-stm { + cell-id = <0x24c>; + label = "slv-xs-qdss-stm"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2d1>; + phandle = <0x29a>; + }; + + slv-xs-sys-tcu-cfg { + cell-id = <0x2a0>; + label = "slv-xs-sys-tcu-cfg"; + qcom,buswidth = <0x08>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x294>; + qcom,bcms = <0x2c7>; + phandle = <0x29e>; + }; + + slv-ebi_display { + cell-id = <0x5020>; + label = "slv-ebi_display"; + qcom,buswidth = <0x04>; + qcom,agg-ports = <0x04>; + qcom,bus-dev = <0x2a7>; + qcom,bcms = <0x2d2>; + phandle = <0x2a6>; + }; + + slv-qns-llcc_display { + cell-id = <0x5021>; + label = "slv-qns-llcc_display"; + qcom,buswidth = <0x10>; + qcom,agg-ports = <0x04>; + qcom,bus-dev = <0x2a9>; + qcom,connections = <0x2d3>; + qcom,bcms = <0x2d4>; + phandle = <0x2a8>; + }; + + slv-qns2-mem-noc_display { + cell-id = <0x5022>; + label = "slv-qns2-mem-noc_display"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x01>; + qcom,bus-dev = <0x2ab>; + qcom,connections = <0x2d5>; + qcom,bcms = <0x2d6>; + phandle = <0x2ad>; + }; + + slv-qns-mem-noc-hf_display { + cell-id = <0x5023>; + label = "slv-qns-mem-noc-hf_display"; + qcom,buswidth = <0x20>; + qcom,agg-ports = <0x02>; + qcom,bus-dev = <0x2ab>; + qcom,connections = <0x2d7>; + qcom,bcms = <0x2d8>; + phandle = <0x2aa>; + }; + }; + + qcom,vidc@aa00000 { + compatible = "qcom,msm-vidc\0qcom,sdm845-vidc"; + status = "ok"; + reg = <0xaa00000 0x200000>; + interrupts = <0x00 0xae 0x04>; + cache-slice-names = "vidsc0\0vidsc1"; + cache-slices = <0x32 0x02 0x32 0x03>; + venus-supply = <0x117>; + venus-core0-supply = <0x2d9>; + venus-core1-supply = <0x2da>; + clock-names = "core_clk\0iface_clk\0bus_clk\0core0_clk\0core0_bus_clk\0core1_clk\0core1_bus_clk"; + clocks = <0xd5 0x0b 0xd5 0x08 0xd5 0x0a 0xd5 0x05 0xd5 0x04 0xd5 0x07 0xd5 0x06>; + qcom,proxy-clock-names = "core_clk\0iface_clk\0bus_clk\0core0_clk\0core0_bus_clk\0core1_clk\0core1_bus_clk"; + qcom,clock-configs = <0x01 0x00 0x00 0x01 0x00 0x01 0x00>; + qcom,allowed-clock-rates = <0x5f5e100 0xbebc200 0x13ab6680 0x18148d00 0x1a76e700 0x1fc4ef40>; + + bus_cnoc { + compatible = "qcom,msm-vidc,bus"; + label = "cnoc"; + qcom,bus-master = <0x01>; + qcom,bus-slave = <0x254>; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <0x3e8 0x3e8>; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = <0x81>; + qcom,bus-slave = <0x200>; + qcom,bus-governor = "msm-vidc-ddr"; + qcom,bus-range-kbps = <0x3e8 0x33b260>; + }; + + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = <0x3f>; + qcom,bus-slave = <0x200>; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <0x3e8 0x3e8>; + }; + + venus_bus_llcc { + compatible = "qcom,msm-vidc,bus"; + label = "venus-llcc"; + qcom,bus-master = <0x3f>; + qcom,bus-slave = <0x302>; + qcom,bus-governor = "msm-vidc-llcc"; + qcom,bus-range-kbps = <0x4268 0x33b260>; + }; + + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = <0x29 0x10a0 0x08 0x29 0x10b0 0x00>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x70800000 0x6f800000>; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <0x29 0x10a1 0x08 0x29 0x10a5 0x08>; + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <0x29 0x10a3 0x08>; + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <0x29 0x10a4 0x08 0x29 0x10b4 0x00>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,pm-cluster@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + label = "L3"; + qcom,clstr-tmr-add = <0x3e8>; + qcom,psci-mode-shift = <0x04>; + qcom,psci-mode-mask = <0xfff>; + + qcom,pm-cluster-level@0 { + reg = <0x00>; + label = "l3-wfi"; + qcom,psci-mode = <0x01>; + qcom,latency-us = <0x33>; + qcom,ss-power = <0x1c4>; + qcom,energy-overhead = <0x10eeb>; + qcom,time-overhead = <0x63>; + }; + + qcom,pm-cluster-level@1 { + reg = <0x01>; + label = "llcc-off"; + qcom,psci-mode = <0xc24>; + qcom,latency-us = <0x19a2>; + qcom,ss-power = <0x6c>; + qcom,energy-overhead = <0x3d0900>; + qcom,time-overhead = <0x1388>; + qcom,min-child-idx = <0x02>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cpu@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + qcom,psci-mode-shift = <0x00>; + qcom,psci-mode-mask = <0x0f>; + qcom,ref-stddev = <0x1f4>; + qcom,tmr-add = <0x3e8>; + qcom,ref-premature-cnt = <0x01>; + qcom,cpu = <0x11 0x12 0x13 0x14>; + + qcom,pm-cpu-level@0 { + reg = <0x00>; + label = "wfi"; + qcom,psci-cpu-mode = <0x01>; + qcom,latency-us = <0x2b>; + qcom,ss-power = <0x96>; + qcom,energy-overhead = <0x2710>; + qcom,time-overhead = <0x64>; + }; + + qcom,pm-cpu-level@1 { + reg = <0x01>; + label = "pc"; + qcom,psci-cpu-mode = <0x03>; + qcom,latency-us = <0x1cd>; + qcom,ss-power = <0x64>; + qcom,energy-overhead = <0x61a80>; + qcom,time-overhead = <0x1f4>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + qcom,pm-cpu-level@2 { + reg = <0x02>; + label = "rail-pc"; + qcom,psci-cpu-mode = <0x04>; + qcom,latency-us = <0x213>; + qcom,ss-power = <0x49>; + qcom,energy-overhead = <0x7a120>; + qcom,time-overhead = <0x258>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + + qcom,pm-cpu@1 { + #address-cells = <0x01>; + #size-cells = <0x00>; + qcom,psci-mode-shift = <0x00>; + qcom,psci-mode-mask = <0x0f>; + qcom,ref-stddev = <0x64>; + qcom,tmr-add = <0x64>; + qcom,ref-premature-cnt = <0x03>; + qcom,cpu = <0x15 0x16 0x17 0x18>; + + qcom,pm-cpu-level@0 { + reg = <0x00>; + label = "wfi"; + qcom,psci-cpu-mode = <0x01>; + qcom,latency-us = <0x2b>; + qcom,ss-power = <0x1c6>; + qcom,energy-overhead = <0x96ef>; + qcom,time-overhead = <0x53>; + }; + + qcom,pm-cpu-level@1 { + reg = <0x01>; + label = "pc"; + qcom,psci-cpu-mode = <0x03>; + qcom,latency-us = <0x26d>; + qcom,ss-power = <0x1b4>; + qcom,energy-overhead = <0x661b1>; + qcom,time-overhead = <0x375>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + qcom,pm-cpu-level@2 { + reg = <0x02>; + label = "rail-pc"; + qcom,psci-cpu-mode = <0x04>; + qcom,latency-us = <0x425>; + qcom,ss-power = <0x190>; + qcom,energy-overhead = <0x688c1>; + qcom,time-overhead = <0x3e8>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + qcom,rpm-stats@c300000 { + compatible = "qcom,rpm-stats"; + reg = <0xc300000 0x1000 0xc3f0004 0x04>; + reg-names = "phys_addr_base\0offset_addr"; + }; + + qcom,rpmh-master-stats@b221200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb221200 0x60>; + qcom,use-alt-unit = <0x03>; + }; + + pinctrl@03400000 { + compatible = "qcom,sdm845-pinctrl-v2"; + reg = <0x3400000 0xc00000 0x179900f0 0x60>; + reg-names = "pinctrl_regs\0spi_cfg_regs"; + interrupts = <0x00 0xd0 0x00>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + interrupt-parent = <0x01>; + phandle = <0x3c>; + + ufs_dev_reset_assert { + phandle = <0xdc>; + + config { + pins = "ufs_reset"; + bias-pull-down; + drive-strength = <0x08>; + output-low; + }; + }; + + ufs_dev_reset_deassert { + phandle = <0xdd>; + + config { + pins = "ufs_reset"; + bias-pull-down; + drive-strength = <0x08>; + output-high; + }; + }; + + flash_led3_front { + + flash_led3_front_en { + + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive_strength = <0x02>; + output-high; + bias-disable; + }; + }; + + flash_led3_front_dis { + + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive_strength = <0x02>; + output-low; + bias-disable; + }; + }; + }; + + flash_led3_iris { + + flash_led3_iris_en { + phandle = <0xb0>; + + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive_strength = <0x02>; + output-high; + bias-disable; + }; + }; + + flash_led3_iris_dis { + phandle = <0xb1>; + + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive_strength = <0x02>; + output-low; + bias-disable; + }; + }; + }; + + wcd9xxx_intr { + + wcd_intr_default { + phandle = <0x379>; + + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + }; + + storage_cd { + phandle = <0xe6>; + + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + bias-pull-up; + drive-strength = <0x02>; + }; + }; + + sdc2_clk_on { + phandle = <0xe3>; + + config { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <0x10>; + }; + }; + + sdc2_clk_off { + phandle = <0xe7>; + + config { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <0x02>; + }; + }; + + sdc2_clk_ds_400KHz { + phandle = <0xea>; + + config { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <0x10>; + }; + }; + + sdc2_clk_ds_50MHz { + phandle = <0xed>; + + config { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <0x10>; + }; + }; + + sdc2_clk_ds_100MHz { + phandle = <0xf0>; + + config { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <0x10>; + }; + }; + + sdc2_clk_ds_200MHz { + phandle = <0xf3>; + + config { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <0x10>; + }; + }; + + sdc2_cmd_on { + phandle = <0xe4>; + + config { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <0x0a>; + }; + }; + + sdc2_cmd_off { + phandle = <0xe8>; + + config { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <0x02>; + }; + }; + + sdc2_cmd_ds_400KHz { + phandle = <0xeb>; + + config { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <0x0a>; + }; + }; + + sdc2_cmd_ds_50MHz { + phandle = <0xee>; + + config { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <0x0a>; + }; + }; + + sdc2_cmd_ds_100MHz { + phandle = <0xf1>; + + config { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <0x0a>; + }; + }; + + sdc2_cmd_ds_200MHz { + phandle = <0xf4>; + + config { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <0x0a>; + }; + }; + + sdc2_data_on { + phandle = <0xe5>; + + config { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <0x0a>; + }; + }; + + sdc2_data_off { + phandle = <0xe9>; + + config { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <0x02>; + }; + }; + + sdc2_data_ds_400KHz { + phandle = <0xec>; + + config { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <0x0a>; + }; + }; + + sdc2_data_ds_50MHz { + phandle = <0xef>; + + config { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <0x0a>; + }; + }; + + sdc2_data_ds_100MHz { + phandle = <0xf2>; + + config { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <0x0a>; + }; + }; + + sdc2_data_ds_200MHz { + phandle = <0xf5>; + + config { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <0x0a>; + }; + }; + + pcie0 { + + pcie0_clkreq_default { + phandle = <0x2db>; + + mux { + pins = "gpio36"; + function = "pci_e0"; + }; + + config { + pins = "gpio36"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + + pcie0_perst_default { + phandle = <0x2dc>; + + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + + pcie0_wake_default { + phandle = <0x2dd>; + + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + + pcie0_3v3_on { + + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive_strength = <0x02>; + bias-disable; + output-high; + }; + }; + + pcie0_1v5_on { + + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive_strength = <0x02>; + bias-disable; + output-high; + }; + }; + }; + + pcie1 { + + pcie1_clkreq_default { + phandle = <0x2e0>; + + mux { + pins = "gpio103"; + function = "pci_e1"; + }; + + config { + pins = "gpio103"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + + pcie1_perst_default { + phandle = <0x2e1>; + + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + + pcie1_wake_default { + phandle = <0x2e2>; + + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + }; + + cdc_reset_ctrl { + + cdc_reset_sleep { + phandle = <0x37b>; + + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <0x02>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active { + phandle = <0x37a>; + + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <0x08>; + bias-pull-down; + output-high; + }; + }; + }; + + spkr_i2s_clk_pin { + + spkr_i2s_clk_sleep { + + mux { + pins = "gpio69"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio69"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + + spkr_i2s_clk_active { + + mux { + pins = "gpio69"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio69"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + wcd_gnd_mic_swap { + + wcd_gnd_mic_swap_idle { + + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + drive-strength = <0x02>; + bias-pull-down; + output-low; + }; + }; + + wcd_gnd_mic_swap_active { + + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + drive-strength = <0x02>; + bias-disable; + output-high; + }; + }; + }; + + wcd_usbc_analog_en1 { + + wcd_usbc_ana_en1_idle { + + mux { + pins = "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio49"; + drive-strength = <0x02>; + bias-pull-down; + output-low; + }; + }; + + wcd_usbc_ana_en1_active { + + mux { + pins = "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio49"; + drive-strength = <0x02>; + bias-disable; + output-high; + }; + }; + }; + + wcd_usbc_analog_en2 { + + wcd_usbc_ana_en2_idle { + phandle = <0x324>; + + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + drive-strength = <0x02>; + bias-pull-down; + output-low; + }; + }; + + wcd_usbc_ana_en2_active { + phandle = <0x323>; + + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + drive-strength = <0x02>; + bias-disable; + output-high; + }; + }; + }; + + pri_aux_pcm_clk { + + pri_aux_pcm_clk_sleep { + + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + pri_aux_pcm_clk_active { + + mux { + pins = "gpio65"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio65"; + drive-strength = <0x08>; + bias-disable; + output-high; + }; + }; + }; + + pri_aux_pcm_sync { + + pri_aux_pcm_sync_sleep { + + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + pri_aux_pcm_sync_active { + + mux { + pins = "gpio66"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio66"; + drive-strength = <0x08>; + bias-disable; + output-high; + }; + }; + }; + + pri_aux_pcm_din { + + pri_aux_pcm_din_sleep { + + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + pri_aux_pcm_din_active { + + mux { + pins = "gpio67"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio67"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + pri_aux_pcm_dout { + + pri_aux_pcm_dout_sleep { + + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + pri_aux_pcm_dout_active { + + mux { + pins = "gpio68"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio68"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + pmx_sde { + + sde_dsi_active { + phandle = <0x346>; + + mux { + pins = "gpio6\0gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio6\0gpio10"; + drive-strength = <0x08>; + bias-disable = <0x00>; + }; + }; + + sde_dsi_suspend { + phandle = <0x348>; + + mux { + pins = "gpio6\0gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio6\0gpio10"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + }; + + pmx_sde_te { + + sde_te_active { + phandle = <0x347>; + + mux { + pins = "gpio10"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio10"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + + sde_te_suspend { + phandle = <0x349>; + + mux { + pins = "gpio10"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio10"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + }; + + sde_dp_aux_active { + phandle = <0x38>; + + mux { + pins = "gpio43\0gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio43\0gpio51"; + bias-disable = <0x00>; + drive-strength = <0x08>; + }; + }; + + sde_dp_aux_suspend { + phandle = <0x3a>; + + mux { + pins = "gpio43\0gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio43\0gpio51"; + bias-pull-down; + drive-strength = <0x02>; + }; + }; + + sde_dp_usbplug_cc_active { + phandle = <0x39>; + + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-disable; + drive-strength = <0x10>; + }; + }; + + sde_dp_usbplug_cc_suspend { + phandle = <0x3b>; + + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-down; + drive-strength = <0x02>; + }; + }; + + pmx_ts_int_active { + + ts_int_active { + + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <0x08>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + + ts_int_suspend1 { + + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + + ts_reset_active { + + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <0x08>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + + ts_reset_suspend1 { + + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + + ts_release { + + mux { + pins = "gpio122\0gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio122\0gpio99"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + }; + + ts_mux { + + ts_active { + + mux { + pins = "gpio99\0gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio99\0gpio122"; + drive-strength = <0x10>; + bias-pull-up; + }; + }; + + ts_reset_suspend { + phandle = <0x8f>; + + mux { + pins = "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio32"; + drive-strength = <0x02>; + bias-pull-down; + bias-disable; + output-low; + }; + }; + + ts_int_suspend { + phandle = <0x8e>; + + mux { + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + drive-strength = <0x02>; + bias-disable; + bias-pull-down; + input-enable; + }; + }; + + ts_int_active { + phandle = <0x8c>; + + mux { + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + drive-strength = <0x10>; + bias-pull-down; + input-enable; + }; + }; + + ts_reset_active { + phandle = <0x8d>; + + mux { + pins = "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio32"; + drive-strength = <0x10>; + output-high; + }; + }; + }; + + ext_bridge_mux { + + lt9611_pins { + + mux { + pins = "gpio84\0gpio128\0gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio84\0gpio128\0gpio89"; + bias-disable = <0x00>; + drive-strength = <0x08>; + }; + }; + }; + + sec_aux_pcm { + + sec_aux_pcm_sleep { + + mux { + pins = "gpio80\0gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio80\0gpio81"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + sec_aux_pcm_active { + + mux { + pins = "gpio80\0gpio81"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio80\0gpio81"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + sec_aux_pcm_din { + + sec_aux_pcm_din_sleep { + + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + sec_aux_pcm_din_active { + + mux { + pins = "gpio82"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio82"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + sec_aux_pcm_dout { + + sec_aux_pcm_dout_sleep { + + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + sec_aux_pcm_dout_active { + + mux { + pins = "gpio83"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio83"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + tert_aux_pcm { + + tert_aux_pcm_sleep { + + mux { + pins = "gpio75\0gpio76"; + function = "gpio"; + }; + + config { + pins = "gpio75\0gpio76"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + tert_aux_pcm_active { + + mux { + pins = "gpio75\0gpio76"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio75\0gpio76"; + drive-strength = <0x08>; + bias-disable; + output-high; + }; + }; + }; + + tert_aux_pcm_din { + + tert_aux_pcm_din_sleep { + + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + tert_aux_pcm_din_active { + + mux { + pins = "gpio77"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio77"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + tert_aux_pcm_dout { + + tert_aux_pcm_dout_sleep { + + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + tert_aux_pcm_dout_active { + + mux { + pins = "gpio78"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio78"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + quat_aux_pcm { + + quat_aux_pcm_sleep { + + mux { + pins = "gpio58\0gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio58\0gpio59"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + quat_aux_pcm_active { + + mux { + pins = "gpio58\0gpio59"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio58\0gpio59"; + drive-strength = <0x08>; + bias-disable; + output-high; + }; + }; + }; + + quat_aux_pcm_din { + + quat_aux_pcm_din_sleep { + + mux { + pins = "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio60"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + quat_aux_pcm_din_active { + + mux { + pins = "gpio60"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio60"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + quat_aux_pcm_dout { + + quat_aux_pcm_dout_sleep { + + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + quat_aux_pcm_dout_active { + + mux { + pins = "gpio61"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio61"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + pri_mi2s_mclk { + + pri_mi2s_mclk_sleep { + + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + pri_mi2s_mclk_active { + + mux { + pins = "gpio64"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio64"; + drive-strength = <0x08>; + bias-disable; + output-high; + }; + }; + }; + + pri_mi2s_sck { + + pri_mi2s_sck_sleep { + + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + pri_mi2s_sck_active { + + mux { + pins = "gpio65"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio65"; + drive-strength = <0x08>; + bias-disable; + output-high; + }; + }; + }; + + pri_mi2s_ws { + + pri_mi2s_ws_sleep { + + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + pri_mi2s_ws_active { + + mux { + pins = "gpio66"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio66"; + drive-strength = <0x08>; + bias-disable; + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + + pri_mi2s_sd0_sleep { + + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + pri_mi2s_sd0_active { + + mux { + pins = "gpio67"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio67"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + pri_mi2s_sd1 { + + pri_mi2s_sd1_sleep { + + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + pri_mi2s_sd1_active { + + mux { + pins = "gpio68"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio68"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + sec_mi2s_mclk { + + sec_mi2s_mclk_sleep { + + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + sec_mi2s_mclk_active { + + mux { + pins = "gpio79"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio79"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + sec_mi2s { + + sec_mi2s_sleep { + + mux { + pins = "gpio80\0gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio80\0gpio81"; + drive-strength = <0x02>; + bias-disable; + input-enable; + }; + }; + + sec_mi2s_active { + + mux { + pins = "gpio80\0gpio81"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio80\0gpio81"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + sec_mi2s_sd0 { + + sec_mi2s_sd0_sleep { + + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + sec_mi2s_sd0_active { + + mux { + pins = "gpio82"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio82"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + sec_mi2s_sd1 { + + sec_mi2s_sd1_sleep { + + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + sec_mi2s_sd1_active { + + mux { + pins = "gpio83"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio83"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + tert_mi2s_mclk { + + tert_mi2s_mclk_sleep { + + mux { + pins = "gpio74"; + function = "gpio"; + }; + + config { + pins = "gpio74"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + tert_mi2s_mclk_active { + + mux { + pins = "gpio74"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio74"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + tert_mi2s { + + tert_mi2s_sleep { + + mux { + pins = "gpio75\0gpio76"; + function = "gpio"; + }; + + config { + pins = "gpio75\0gpio76"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + tert_mi2s_active { + + mux { + pins = "gpio75\0gpio76"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio75\0gpio76"; + drive-strength = <0x08>; + bias-disable; + output-high; + }; + }; + }; + + tert_mi2s_sd0 { + + tert_mi2s_sd0_sleep { + + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + tert_mi2s_sd0_active { + + mux { + pins = "gpio77"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio77"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + tert_mi2s_sd1 { + + tert_mi2s_sd1_sleep { + + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + tert_mi2s_sd1_active { + + mux { + pins = "gpio78"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio78"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + quat_mi2s_mclk { + + quat_mi2s_mclk_sleep { + + mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio57"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + quat_mi2s_mclk_active { + + mux { + pins = "gpio57"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio57"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + quat_mi2s { + + quat_mi2s_sleep { + phandle = <0x32c>; + + mux { + pins = "gpio58\0gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio58\0gpio59"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + quat_mi2s_active { + phandle = <0x329>; + + mux { + pins = "gpio58\0gpio59"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio58\0gpio59"; + drive-strength = <0x08>; + bias-disable; + output-high; + }; + }; + }; + + quat_mi2s_sd0 { + + quat_mi2s_sd0_sleep { + phandle = <0x32d>; + + mux { + pins = "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio60"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + quat_mi2s_sd0_active { + phandle = <0x32a>; + + mux { + pins = "gpio60"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio60"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + quat_mi2s_sd1 { + + quat_mi2s_sd1_sleep { + phandle = <0x32e>; + + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + quat_mi2s_sd1_active { + phandle = <0x32b>; + + mux { + pins = "gpio61"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio61"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + quat_mi2s_sd2 { + + quat_mi2s_sd2_sleep { + + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + quat_mi2s_sd2_active { + + mux { + pins = "gpio62"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio62"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + quat_mi2s_sd3 { + + quat_mi2s_sd3_sleep { + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <0x02>; + bias-pull-down; + input-enable; + }; + }; + + quat_mi2s_sd3_active { + + mux { + pins = "gpio63"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio63"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + quat_tdm { + + quat_tdm_sleep { + phandle = <0x331>; + + mux { + pins = "gpio58\0gpio59"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio58\0gpio59"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + + quat_tdm_active { + phandle = <0x32f>; + + mux { + pins = "gpio58\0gpio59"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio58\0gpio59"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + quat_tdm_dout { + + quat_tdm_dout_sleep { + phandle = <0x332>; + + mux { + pins = "gpio61"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio61"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + + quat_tdm_dout_active { + phandle = <0x330>; + + mux { + pins = "gpio61"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio61"; + drive-strength = <0x02>; + bias-disable; + }; + }; + }; + + quat_tdm_din { + + quat_tdm_din_sleep { + + mux { + pins = "gpio60"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio60"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + + quat_tdm_din_active { + + mux { + pins = "gpio60"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio60"; + drive-strength = <0x02>; + bias-disable; + }; + }; + }; + + qupv3_se0_i2c_pins { + + qupv3_se0_i2c_active { + phandle = <0x44>; + + mux { + pins = "gpio0\0gpio1"; + function = "qup0"; + }; + + config { + pins = "gpio0\0gpio1"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se0_i2c_sleep { + phandle = <0x45>; + + mux { + pins = "gpio0\0gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0\0gpio1"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se0_spi_pins { + + qupv3_se0_spi_active { + phandle = <0x5a>; + + mux { + pins = "gpio0\0gpio1\0gpio2\0gpio3"; + function = "qup0"; + }; + + config { + pins = "gpio0\0gpio1\0gpio2\0gpio3"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep { + phandle = <0x5b>; + + mux { + pins = "gpio0\0gpio1\0gpio2\0gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0\0gpio1\0gpio2\0gpio3"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins { + + qupv3_se1_i2c_active { + phandle = <0x46>; + + mux { + pins = "gpio17\0gpio18"; + function = "qup1"; + }; + + config { + pins = "gpio17\0gpio18"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se1_i2c_sleep { + phandle = <0x47>; + + mux { + pins = "gpio17\0gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio17\0gpio18"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se1_spi_pins { + + qupv3_se1_spi_active { + phandle = <0x5c>; + + mux { + pins = "gpio17\0gpio18\0gpio19\0gpio20"; + function = "qup1"; + }; + + config { + pins = "gpio17\0gpio18\0gpio19\0gpio20"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep { + phandle = <0x5d>; + + mux { + pins = "gpio17\0gpio18\0gpio19\0gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio17\0gpio18\0gpio19\0gpio20"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins { + + qupv3_se2_i2c_active { + phandle = <0x48>; + + mux { + pins = "gpio27\0gpio28"; + function = "qup2"; + }; + + config { + pins = "gpio27\0gpio28"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se2_i2c_sleep { + phandle = <0x49>; + + mux { + pins = "gpio27\0gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio27\0gpio28"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se2_spi_pins { + + qupv3_se2_spi_active { + phandle = <0x5e>; + + mux { + pins = "gpio27\0gpio28\0gpio29\0gpio30"; + function = "qup2"; + }; + + config { + pins = "gpio27\0gpio28\0gpio29\0gpio30"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep { + phandle = <0x5f>; + + mux { + pins = "gpio27\0gpio28\0gpio29\0gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio27\0gpio28\0gpio29\0gpio30"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se3_i2c_pins { + + qupv3_se3_i2c_active { + phandle = <0x4a>; + + mux { + pins = "gpio41\0gpio42"; + function = "qup3"; + }; + + config { + pins = "gpio41\0gpio42"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se3_i2c_sleep { + phandle = <0x4b>; + + mux { + pins = "gpio41\0gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio41\0gpio42"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + nfc { + + nfc_int_active { + phandle = <0x4d>; + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + + nfc_int_suspend { + phandle = <0x50>; + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + + nfc_enable_active { + phandle = <0x4e>; + + mux { + pins = "gpio12\0gpio88\0gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio12\0gpio88\0gpio116"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + + nfc_enable_suspend { + phandle = <0x51>; + + mux { + pins = "gpio12\0gpio62\0gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio12\0gpio62\0gpio116"; + drive-strength = <0x02>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins { + + qupv3_se3_spi_active { + phandle = <0x60>; + + mux { + pins = "gpio41\0gpio42\0gpio43\0gpio44"; + function = "qup3"; + }; + + config { + pins = "gpio41\0gpio42\0gpio43\0gpio44"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep { + phandle = <0x61>; + + mux { + pins = "gpio41\0gpio42\0gpio43\0gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio41\0gpio42\0gpio43\0gpio44"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins { + + qupv3_se4_i2c_active { + phandle = <0x52>; + + mux { + pins = "gpio89\0gpio90"; + function = "qup4"; + }; + + config { + pins = "gpio89\0gpio90"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se4_i2c_sleep { + phandle = <0x53>; + + mux { + pins = "gpio89\0gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio89\0gpio90"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se4_spi_pins { + + qupv3_se4_spi_active { + phandle = <0x62>; + + mux { + pins = "gpio89\0gpio90\0gpio91\0gpio92"; + function = "qup4"; + }; + + config { + pins = "gpio89\0gpio90\0gpio91\0gpio92"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep { + phandle = <0x63>; + + mux { + pins = "gpio89\0gpio90\0gpio91\0gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio89\0gpio90\0gpio91\0gpio92"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se5_i2c_pins { + + qupv3_se5_i2c_active { + phandle = <0x54>; + + mux { + pins = "gpio85\0gpio86"; + function = "qup5"; + }; + + config { + pins = "gpio85\0gpio86"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se5_i2c_sleep { + phandle = <0x55>; + + mux { + pins = "gpio85\0gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio85\0gpio86"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se5_spi_pins { + + qupv3_se5_spi_active { + phandle = <0x64>; + + mux { + pins = "gpio85\0gpio86\0gpio87\0gpio88"; + function = "qup5"; + }; + + config { + pins = "gpio85\0gpio86\0gpio87\0gpio88"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep { + phandle = <0x65>; + + mux { + pins = "gpio85\0gpio86\0gpio87\0gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio85\0gpio86\0gpio87\0gpio88"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins { + + qupv3_se6_i2c_active { + phandle = <0x56>; + + mux { + pins = "gpio45\0gpio46"; + function = "qup6"; + }; + + config { + pins = "gpio45\0gpio46"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se6_i2c_sleep { + phandle = <0x57>; + + mux { + pins = "gpio45\0gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio45\0gpio46"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se6_4uart_pins { + + qupv3_se6_ctsrx { + phandle = <0x3d>; + + mux { + pins = "gpio45\0gpio48"; + function = "qup6"; + }; + + config { + pins = "gpio45\0gpio48"; + drive-strength = <0x02>; + bias-no-pull; + }; + }; + + qupv3_se6_rts { + phandle = <0x3e>; + + mux { + pins = "gpio46"; + function = "qup6"; + }; + + config { + pins = "gpio46"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + + qupv3_se6_tx { + phandle = <0x3f>; + + mux { + pins = "gpio47"; + function = "qup6"; + }; + + config { + pins = "gpio47"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se6_spi_pins { + + qupv3_se6_spi_active { + phandle = <0x66>; + + mux { + pins = "gpio45\0gpio46\0gpio47\0gpio48"; + function = "qup6"; + }; + + config { + pins = "gpio45\0gpio46\0gpio47\0gpio48"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep { + phandle = <0x67>; + + mux { + pins = "gpio45\0gpio46\0gpio47\0gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio45\0gpio46\0gpio47\0gpio48"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se7_i2c_pins { + + qupv3_se7_i2c_active { + phandle = <0x58>; + + mux { + pins = "gpio93\0gpio94"; + function = "qup7"; + }; + + config { + pins = "gpio93\0gpio94"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se7_i2c_sleep { + phandle = <0x59>; + + mux { + pins = "gpio93\0gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio93\0gpio94"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se7_4uart_pins { + + qupv3_se7_4uart_active { + phandle = <0x41>; + + mux { + pins = "gpio93\0gpio94\0gpio95\0gpio96"; + function = "qup7"; + }; + + config { + pins = "gpio93\0gpio94\0gpio95\0gpio96"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se7_4uart_sleep { + phandle = <0x42>; + + mux { + pins = "gpio93\0gpio94\0gpio95\0gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio93\0gpio94\0gpio95\0gpio96"; + drive-strength = <0x02>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins { + + qupv3_se7_spi_active { + phandle = <0x68>; + + mux { + pins = "gpio93\0gpio94\0gpio95\0gpio96"; + function = "qup7"; + }; + + config { + pins = "gpio93\0gpio94\0gpio95\0gpio96"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep { + phandle = <0x69>; + + mux { + pins = "gpio93\0gpio94\0gpio95\0gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio93\0gpio94\0gpio95\0gpio96"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se8_i2c_pins { + + qupv3_se8_i2c_active { + phandle = <0x70>; + + mux { + pins = "gpio65\0gpio66"; + function = "qup8"; + }; + + config { + pins = "gpio65\0gpio66"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se8_i2c_sleep { + phandle = <0x71>; + + mux { + pins = "gpio65\0gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio65\0gpio66"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se8_spi_pins { + + qupv3_se8_spi_active { + phandle = <0x92>; + + mux { + pins = "gpio65\0gpio66\0gpio67\0gpio68"; + function = "qup8"; + }; + + config { + pins = "gpio65\0gpio66\0gpio67\0gpio68"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep { + + mux { + pins = "gpio65\0gpio66\0gpio67\0gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio65\0gpio66\0gpio67\0gpio68"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins { + + qupv3_se9_i2c_active { + phandle = <0x72>; + + mux { + pins = "gpio6\0gpio7"; + function = "qup9"; + }; + + config { + pins = "gpio6\0gpio7"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se9_i2c_sleep { + phandle = <0x73>; + + mux { + pins = "gpio6\0gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6\0gpio7"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se9_2uart_pins { + + qupv3_se9_2uart_active { + phandle = <0x6a>; + + mux { + pins = "gpio4\0gpio5"; + function = "qup9"; + }; + + config { + pins = "gpio4\0gpio5"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se9_2uart_sleep { + phandle = <0x6b>; + + mux { + pins = "gpio4\0gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4\0gpio5"; + drive-strength = <0x02>; + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins { + + qupv3_se9_spi_active { + phandle = <0x93>; + + mux { + pins = "gpio4\0gpio5\0gpio6\0gpio7"; + function = "qup9"; + }; + + config { + pins = "gpio4\0gpio5\0gpio6\0gpio7"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep { + phandle = <0x94>; + + mux { + pins = "gpio4\0gpio5\0gpio6\0gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4\0gpio5\0gpio6\0gpio7"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se10_i2c_pins { + + qupv3_se10_i2c_active { + phandle = <0x74>; + + mux { + pins = "gpio55\0gpio56"; + function = "qup10"; + }; + + config { + pins = "gpio55\0gpio56"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se10_i2c_sleep { + phandle = <0x75>; + + mux { + pins = "gpio55\0gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio55\0gpio56"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se10_2uart_pins { + + qupv3_se10_2uart_active { + phandle = <0x6d>; + + mux { + pins = "gpio53\0gpio54"; + function = "qup10"; + }; + + config { + pins = "gpio53\0gpio54"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se10_2uart_sleep { + phandle = <0x6e>; + + mux { + pins = "gpio53\0gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio53\0gpio54"; + drive-strength = <0x02>; + bias-disable; + }; + }; + }; + + qupv3_se10_spi_pins { + + qupv3_se10_spi_active { + phandle = <0x95>; + + mux { + pins = "gpio53\0gpio54\0gpio55\0gpio56"; + function = "qup10"; + }; + + config { + pins = "gpio53\0gpio54\0gpio55\0gpio56"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep { + phandle = <0x96>; + + mux { + pins = "gpio53\0gpio54\0gpio55\0gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio53\0gpio54\0gpio55\0gpio56"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se11_i2c_pins { + + qupv3_se11_i2c_active { + phandle = <0x81>; + + mux { + pins = "gpio31\0gpio32"; + function = "qup11"; + }; + + config { + pins = "gpio31\0gpio32"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se11_i2c_sleep { + phandle = <0x82>; + + mux { + pins = "gpio31\0gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio31\0gpio32"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se11_spi_pins { + + qupv3_se11_spi_active { + phandle = <0x97>; + + mux { + pins = "gpio31\0gpio32\0gpio33\0gpio34"; + function = "qup11"; + }; + + config { + pins = "gpio31\0gpio32\0gpio33\0gpio34"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep { + phandle = <0x98>; + + mux { + pins = "gpio31\0gpio32\0gpio33\0gpio34"; + function = "gpio"; + }; + + config { + pins = "gpio31\0gpio32\0gpio33\0gpio34"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se12_i2c_pins { + + qupv3_se12_i2c_active { + phandle = <0x83>; + + mux { + pins = "gpio49\0gpio50"; + function = "qup12"; + }; + + config { + pins = "gpio49\0gpio50"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se12_i2c_sleep { + phandle = <0x84>; + + mux { + pins = "gpio49\0gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio49\0gpio50"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se12_spi_pins { + + qupv3_se12_spi_active { + phandle = <0x99>; + + mux { + pins = "gpio49\0gpio50\0gpio51\0gpio52"; + function = "qup12"; + }; + + config { + pins = "gpio49\0gpio50\0gpio51\0gpio52"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep { + phandle = <0x9a>; + + mux { + pins = "gpio49\0gpio50\0gpio51\0gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio49\0gpio50\0gpio51\0gpio52"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se13_i2c_pins { + + qupv3_se13_i2c_active { + phandle = <0x85>; + + mux { + pins = "gpio105\0gpio106"; + function = "qup13"; + }; + + config { + pins = "gpio105\0gpio106"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se13_i2c_sleep { + phandle = <0x86>; + + mux { + pins = "gpio105\0gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio105\0gpio106"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se13_spi_pins { + + qupv3_se13_spi_active { + phandle = <0x9b>; + + mux { + pins = "gpio105\0gpio106\0gpio107\0gpio108"; + function = "qup13"; + }; + + config { + pins = "gpio105\0gpio106\0gpio107\0gpio108"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep { + phandle = <0x9c>; + + mux { + pins = "gpio105\0gpio106\0gpio107\0gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio105\0gpio106\0gpio107\0gpio108"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se14_i2c_pins { + + qupv3_se14_i2c_active { + phandle = <0x87>; + + mux { + pins = "gpio33\0gpio34"; + function = "qup14"; + }; + + config { + pins = "gpio33\0gpio34"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se14_i2c_sleep { + phandle = <0x88>; + + mux { + pins = "gpio33\0gpio34"; + function = "gpio"; + }; + + config { + pins = "gpio33\0gpio34"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se14_spi_pins { + + qupv3_se14_spi_active { + phandle = <0x9d>; + + mux { + pins = "gpio31\0gpio32\0gpio33\0gpio34"; + function = "qup14"; + }; + + config { + pins = "gpio31\0gpio32\0gpio33\0gpio34"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep { + phandle = <0x9e>; + + mux { + pins = "gpio31\0gpio32\0gpio33\0gpio34"; + function = "gpio"; + }; + + config { + pins = "gpio31\0gpio32\0gpio33\0gpio34"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + qupv3_se15_i2c_pins { + + qupv3_se15_i2c_active { + phandle = <0x90>; + + mux { + pins = "gpio81\0gpio82"; + function = "qup15"; + }; + + config { + pins = "gpio81\0gpio82"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + qupv3_se15_i2c_sleep { + phandle = <0x91>; + + mux { + pins = "gpio81\0gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio81\0gpio82"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + }; + + qupv3_se15_spi_pins { + + qupv3_se15_spi_active { + phandle = <0x9f>; + + mux { + pins = "gpio81\0gpio82\0gpio83\0gpio84"; + function = "qup15"; + }; + + config { + pins = "gpio81\0gpio82\0gpio83\0gpio84"; + drive-strength = <0x06>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep { + phandle = <0xa0>; + + mux { + pins = "gpio81\0gpio82\0gpio83\0gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio81\0gpio82\0gpio83\0gpio84"; + drive-strength = <0x06>; + bias-disable; + }; + }; + }; + + cci0_active { + phandle = <0x216>; + + mux { + pins = "gpio17\0gpio18"; + function = "cci_i2c"; + }; + + config { + pins = "gpio17\0gpio18"; + bias-pull-up; + drive-strength = <0x02>; + }; + }; + + cci0_suspend { + phandle = <0x218>; + + mux { + pins = "gpio17\0gpio18"; + function = "cci_i2c"; + }; + + config { + pins = "gpio17\0gpio18"; + bias-pull-down; + drive-strength = <0x02>; + }; + }; + + cci1_active { + phandle = <0x217>; + + mux { + pins = "gpio19\0gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19\0gpio20"; + bias-pull-up; + drive-strength = <0x02>; + }; + }; + + cci1_suspend { + phandle = <0x219>; + + mux { + pins = "gpio19\0gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19\0gpio20"; + bias-pull-down; + drive-strength = <0x02>; + }; + }; + + cam_sensor_fisheye_active { + + mux { + pins = "gpio76\0gpio75"; + function = "gpio"; + }; + + config { + pins = "gpio76\0gpio75"; + bias-disable; + drive-strength = <0x02>; + }; + }; + + cam_sensor_fisheye_suspend { + + mux { + pins = "gpio76\0gpio75"; + function = "gpio"; + }; + + config { + pins = "gpio76\0gpio75"; + bias-pull-down; + drive-strength = <0x02>; + output-low; + }; + }; + + cam_sensor_depth_active { + + mux { + pins = "gpio28\0gpio23\0gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio28\0gpio23\0gpio24"; + bias-disable; + drive-strength = <0x02>; + }; + }; + + cam_sensor_depth_suspend { + + mux { + pins = "gpio28\0gpio23\0gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio28\0gpio23\0gpio24"; + bias-pull-down; + drive-strength = <0x02>; + }; + }; + + max_rst_active { + + mux { + pins = "gpio31\0gpio77\0gpio78\0gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio31\0gpio77\0gpio78\0gpio32"; + bias-disable; + drive-strength = <0x08>; + }; + }; + + max_rst_suspend { + + mux { + pins = "gpio31\0gpio77\0gpio78\0gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio31\0gpio77\0gpio78\0gpio32"; + bias-pull-down; + drive-strength = <0x08>; + }; + }; + + max_6dof_active { + + mux { + pins = "gpio30\0gpio95\0gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio30\0gpio95\0gpio94"; + bias-disable; + drive-strength = <0x08>; + }; + }; + + max_6dof_suspend { + + mux { + pins = "gpio30\0gpio95\0gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio30\0gpio95\0gpio94"; + bias-pull-down; + drive-strength = <0x08>; + }; + }; + + cam_sensor_mclk0_active { + phandle = <0x222>; + + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; + drive-strength = <0x02>; + }; + }; + + cam_sensor_mclk0_suspend { + phandle = <0x224>; + + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; + drive-strength = <0x02>; + }; + }; + + cam_sensor_rear_active { + phandle = <0x223>; + + mux { + pins = "gpio40\0gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio40\0gpio80"; + bias-disable; + drive-strength = <0x02>; + }; + }; + + cam_sensor_rear_suspend { + phandle = <0x225>; + + mux { + pins = "gpio40\0gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio40\0gpio80"; + bias-pull-down; + drive-strength = <0x02>; + output-low; + }; + }; + + cam_sensor_mclk1_active { + phandle = <0x226>; + + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; + drive-strength = <0x04>; + }; + }; + + cam_sensor_mclk1_suspend { + phandle = <0x229>; + + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; + drive-strength = <0x04>; + output-low; + }; + }; + + cam_sensor_mclk3_active { + phandle = <0x22c>; + + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; + drive-strength = <0x04>; + }; + }; + + cam_sensor_mclk3_suspend { + phandle = <0x230>; + + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; + drive-strength = <0x04>; + output-low; + }; + }; + + cam_sensor_front_active { + phandle = <0x21e>; + + mux { + pins = "gpio104\0gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio104\0gpio29"; + bias-disable; + drive-strength = <0x02>; + }; + }; + + cam_sensor_front_suspend { + phandle = <0x220>; + + mux { + pins = "gpio104\0gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio104\0gpio29"; + bias-pull-down; + drive-strength = <0x02>; + output-low; + }; + }; + + cam_sensor_iris_active { + + mux { + pins = "gpio9\0gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio9\0gpio8"; + bias-disable; + drive-strength = <0x02>; + }; + }; + + cam_sensor_iris_suspend { + + mux { + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + bias-pull-down; + drive-strength = <0x02>; + output-low; + bias-disable; + }; + }; + + cam_sensor_mclk2_active { + phandle = <0x21d>; + + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; + drive-strength = <0x02>; + }; + }; + + cam_sensor_mclk2_suspend { + phandle = <0x21f>; + + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; + drive-strength = <0x02>; + }; + }; + + cam_sensor_rear2_active { + phandle = <0x228>; + + mux { + pins = "gpio28\0gpio79\0gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio28\0gpio79\0gpio92"; + bias-disable; + drive-strength = <0x02>; + }; + }; + + cam_sensor_rear2_suspend { + phandle = <0x22b>; + + mux { + pins = "gpio28\0gpio79\0gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio28\0gpio79\0gpio92"; + bias-pull-down; + drive-strength = <0x02>; + output-low; + }; + }; + + cam_sensor_rear_vana { + + mux { + pins = "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio8"; + bias-disable; + drive-strength = <0x02>; + }; + }; + + cam_res_mgr_active { + + mux { + pins = [00]; + function = "gpio"; + }; + + config { + pins = [00]; + bias-disable; + drive-strength = <0x02>; + }; + }; + + cam_res_mgr_suspend { + + mux { + pins = [00]; + function = "gpio"; + }; + + config { + pins = [00]; + bias-disable; + drive-strength = <0x02>; + output-low; + }; + }; + + trigout_a { + phandle = <0x1df>; + + mux { + pins = "gpio90"; + function = "qdss_cti"; + }; + + config { + pins = "gpio90"; + drive-strength = <0x02>; + bias-disable; + }; + }; + + tsif0_signals_active { + phandle = <0x177>; + + tsif1_clk { + pins = "gpio89"; + function = "tsif1_clk"; + }; + + tsif1_en { + pins = "gpio90"; + function = "tsif1_en"; + }; + + tsif1_data { + pins = "gpio91"; + function = "tsif1_data"; + }; + + signals_cfg { + pins = "gpio89\0gpio90\0gpio91"; + drive_strength = <0x02>; + bias-pull-down; + }; + }; + + tsif0_sync_active { + phandle = <0x178>; + + tsif1_sync { + pins = "gpio12"; + function = "tsif1_sync"; + drive_strength = <0x02>; + bias-pull-down; + }; + }; + + tsif1_signals_active { + phandle = <0x179>; + + tsif2_clk { + pins = "gpio93"; + function = "tsif2_clk"; + }; + + tsif2_en { + pins = "gpio94"; + function = "tsif2_en"; + }; + + tsif2_data { + pins = "gpio95"; + function = "tsif2_data"; + }; + + signals_cfg { + pins = "gpio93\0gpio94\0gpio95"; + drive_strength = <0x02>; + bias-pull-down; + }; + }; + + tsif1_sync_active { + phandle = <0x17a>; + + tsif2_sync { + pins = "gpio96"; + function = "tsif2_sync"; + drive_strength = <0x02>; + bias-pull-down; + }; + }; + + ap2mdm { + + ap2mdm_active { + + mux { + pins = "gpio21\0gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio21\0gpio23"; + drive-strength = <0x10>; + bias-disable; + }; + }; + + ap2mdm_sleep { + + mux { + pins = "gpio21\0gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio21\0gpio23"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + mdm2ap { + + mdm2ap_active { + + mux { + pins = "gpio22\0gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio22\0gpio20"; + drive-strength = <0x08>; + bias-disable; + }; + }; + + mdm2ap_sleep { + + mux { + pins = "gpio22\0gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio22\0gpio20"; + drive-strength = <0x08>; + bias-disable; + }; + }; + }; + + idt { + + idt_int_active { + + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <0x02>; + bias-pull-up; + input-enable; + }; + }; + + idt_int_suspend { + + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <0x02>; + bias-pull-up; + input-enable; + }; + }; + + idt_enable_active { + + mux { + }; + + config { + }; + }; + + idt_enable_suspend { + + mux { + }; + + config { + }; + }; + }; + + lm3644 { + + lm3644_led_active { + phandle = <0x7c>; + + mux { + pins = "gpio93\0gpio96\0gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio93\0gpio96\0gpio135"; + drive-strength = <0x08>; + bias-disable; + }; + }; + + lm3644_led_suspend { + phandle = <0x7f>; + + mux { + pins = "gpio93\0gpio96\0gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio93\0gpio96\0gpio135"; + drive-strength = <0x02>; + bias-disable; + }; + }; + }; + + sbu_mic_oe_ctrl { + + hw-auto-sw-en_idle { + + mux { + pins = "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio43"; + drive-strength = <0x02>; + bias-pull-down; + output-low; + }; + }; + + hw-auto-sw-en_active { + + mux { + pins = "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio43"; + drive-strength = <0x02>; + bias-disable; + output-high; + }; + }; + }; + + sbu_uart_en_ctrl { + + uart_audio_en_idle { + phandle = <0x378>; + + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + drive-strength = <0x02>; + bias-pull-down; + output-low; + }; + }; + + uart_audio_en_active { + phandle = <0x377>; + + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + drive-strength = <0x02>; + bias-disable; + output-high; + }; + }; + }; + + adc2_switch_gpio_ctrl { + + adc2_switch_idle { + + mux { + }; + + config { + }; + }; + + adc2_switch_active { + + mux { + }; + + config { + }; + }; + }; + + cam_sensor_ir_active { + phandle = <0x22f>; + + mux { + pins = "gpio25\0gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio25\0gpio91"; + bias-disable; + drive-strength = <0x02>; + }; + }; + + cam_sensor_ir_oe_active { + phandle = <0x22e>; + + mux { + pins = "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio8"; + bias-pull-down; + drive-strength = <0x02>; + output-low; + }; + }; + + cam_sensor_ir_sel_active { + phandle = <0x22d>; + + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + bias-pull-up; + drive-strength = <0x02>; + output-high; + }; + }; + + cam_sensor_ir_suspend { + phandle = <0x232>; + + mux { + pins = "gpio25\0gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio25\0gpio91"; + bias-pull-down; + drive-strength = <0x02>; + output-low; + }; + }; + + cam_sensor_ir_oesel_suspend { + phandle = <0x231>; + + mux { + pins = "gpio8\0gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio8\0gpio36"; + bias-pull-up; + drive-strength = <0x02>; + output-high; + }; + }; + + cam_sensor_rear2_oesel_active { + phandle = <0x227>; + + mux { + pins = "gpio8\0gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio8\0gpio36"; + bias-pull-down; + drive-strength = <0x02>; + output-low; + }; + }; + + cam_sensor_rear2_oesel_suspend { + phandle = <0x22a>; + + mux { + pins = "gpio8\0gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio8\0gpio36"; + bias-pull-up; + drive-strength = <0x02>; + output-high; + }; + }; + + fp_mux { + + fp_active { + + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <0x08>; + bias-disable; + }; + }; + + fp_suspend { + + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <0x02>; + bias-disable; + }; + }; + }; + + msm_gpio_37 { + phandle = <0x375>; + + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <0x02>; + bias-disable; + output-low; + }; + }; + + msm_gpio_37_output_high { + phandle = <0x376>; + + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <0x02>; + bias-disable; + output-high; + }; + }; + + msm_gpio_121 { + + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <0x02>; + bias-pull-down; + }; + }; + + spk_id_no_pull { + + mux { + pins = "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio44"; + drive-strength = <0x08>; + bias-disable; + input-enable; + }; + }; + + spk_id_pull_up { + + mux { + pins = "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio44"; + drive-strength = <0x08>; + bias-pull-up; + input-enable; + }; + }; + + spk_id_pull_down { + + mux { + pins = "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio44"; + drive-strength = <0x08>; + bias-pull-down; + input-enable; + }; + }; + + atest_usb13_active { + phandle = <0x33d>; + + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + drive-strength = <0x0c>; + output-high; + bias-pull-up; + }; + }; + + atest_usb13_suspend { + phandle = <0x33c>; + + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + drive-strength = <0x02>; + output-low; + bias-pull-down; + }; + }; + }; + + qcom,pcie@0x1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0x00>; + reg = <0x1c00000 0x2000 0x1c06000 0x1000 0x60000000 0xf1d 0x60000f20 0xa8 0x60100000 0x100000 0x60200000 0x100000 0x60300000 0xd00000>; + reg-names = "parf\0phy\0dm_core\0elbi\0conf\0io\0bars"; + #address-cells = <0x03>; + #size-cells = <0x02>; + ranges = <0x1000000 0x00 0x60200000 0x60200000 0x00 0x100000 0x2000000 0x00 0x60300000 0x60300000 0x00 0xd00000>; + interrupt-parent = <0xd2>; + interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25>; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0xffffffff>; + interrupt-map = <0x00 0x00 0x00 0x00 0x01 0x00 0x8d 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x95 0x00 0x00 0x00 0x00 0x02 0x01 0x00 0x96 0x00 0x00 0x00 0x00 0x03 0x01 0x00 0x97 0x00 0x00 0x00 0x00 0x04 0x01 0x00 0x98 0x00 0x00 0x00 0x00 0x05 0x01 0x00 0x8c 0x00 0x00 0x00 0x00 0x06 0x01 0x00 0x2a0 0x00 0x00 0x00 0x00 0x07 0x01 0x00 0x2a1 0x00 0x00 0x00 0x00 0x08 0x01 0x00 0x2a2 0x00 0x00 0x00 0x00 0x09 0x01 0x00 0x2a3 0x00 0x00 0x00 0x00 0x0a 0x01 0x00 0x2a4 0x00 0x00 0x00 0x00 0x0b 0x01 0x00 0x2a5 0x00 0x00 0x00 0x00 0x0c 0x01 0x00 0x2a6 0x00 0x00 0x00 0x00 0x0d 0x01 0x00 0x2a7 0x00 0x00 0x00 0x00 0x0e 0x01 0x00 0x2a8 0x00 0x00 0x00 0x00 0x0f 0x01 0x00 0x2a9 0x00 0x00 0x00 0x00 0x10 0x01 0x00 0x2aa 0x00 0x00 0x00 0x00 0x11 0x01 0x00 0x2ab 0x00 0x00 0x00 0x00 0x12 0x01 0x00 0x2ac 0x00 0x00 0x00 0x00 0x13 0x01 0x00 0x2ad 0x00 0x00 0x00 0x00 0x14 0x01 0x00 0x2ae 0x00 0x00 0x00 0x00 0x15 0x01 0x00 0x2af 0x00 0x00 0x00 0x00 0x16 0x01 0x00 0x2b0 0x00 0x00 0x00 0x00 0x17 0x01 0x00 0x2b1 0x00 0x00 0x00 0x00 0x18 0x01 0x00 0x2b2 0x00 0x00 0x00 0x00 0x19 0x01 0x00 0x2b3 0x00 0x00 0x00 0x00 0x1a 0x01 0x00 0x2b4 0x00 0x00 0x00 0x00 0x1b 0x01 0x00 0x2b5 0x00 0x00 0x00 0x00 0x1c 0x01 0x00 0x2b6 0x00 0x00 0x00 0x00 0x1d 0x01 0x00 0x2b7 0x00 0x00 0x00 0x00 0x1e 0x01 0x00 0x2b8 0x00 0x00 0x00 0x00 0x1f 0x01 0x00 0x2b9 0x00 0x00 0x00 0x00 0x20 0x01 0x00 0x2ba 0x00 0x00 0x00 0x00 0x21 0x01 0x00 0x2bb 0x00 0x00 0x00 0x00 0x22 0x01 0x00 0x2bc 0x00 0x00 0x00 0x00 0x23 0x01 0x00 0x2bd 0x00 0x00 0x00 0x00 0x24 0x01 0x00 0x2be 0x00 0x00 0x00 0x00 0x25 0x01 0x00 0x2bf 0x00>; + interrupt-names = "int_msi\0int_a\0int_b\0int_c\0int_d\0int_global_int\0msi_0\0msi_1\0msi_2\0msi_3\0msi_4\0msi_5\0msi_6\0msi_7\0msi_8\0msi_9\0msi_10\0msi_11\0msi_12\0msi_13\0msi_14\0msi_15\0msi_16\0msi_17\0msi_18\0msi_19\0msi_20\0msi_21\0msi_22\0msi_23\0msi_24\0msi_25\0msi_26\0msi_27\0msi_28\0msi_29\0msi_30\0msi_31"; + qcom,phy-sequence = <0x804 0x01 0x00 0x34 0x14 0x00 0x138 0x30 0x00 0x48 0x07 0x00 0x15c 0x06 0x00 0x90 0x01 0x00 0x88 0x20 0x00 0xf0 0x00 0x00 0xf8 0x01 0x00 0xf4 0xc9 0x00 0x11c 0xff 0x00 0x120 0x3f 0x00 0x164 0x01 0x00 0x154 0x00 0x00 0x148 0x0a 0x00 0x5c 0x19 0x00 0x38 0x90 0x00 0xb0 0x82 0x00 0xc0 0x02 0x00 0xbc 0xea 0x00 0xb8 0xab 0x00 0xa0 0x00 0x00 0x9c 0x0d 0x00 0x98 0x04 0x00 0x13c 0x00 0x00 0x60 0x06 0x00 0x68 0x16 0x00 0x70 0x36 0x00 0x184 0x01 0x00 0x138 0x33 0x00 0x3c 0x02 0x00 0x40 0x06 0x00 0x80 0x04 0x00 0xdc 0x00 0x00 0xd8 0x3f 0x00 0x0c 0x09 0x00 0x10 0x01 0x00 0x1c 0x40 0x00 0x20 0x01 0x00 0x14 0x02 0x00 0x18 0x00 0x00 0x24 0x7e 0x00 0x28 0x15 0x00 0x244 0x02 0x00 0x2a4 0x12 0x00 0x260 0x10 0x00 0x28c 0x06 0x00 0x504 0x03 0x00 0x500 0x10 0x00 0x50c 0x14 0x00 0x4d4 0x0e 0x00 0x4d8 0x04 0x00 0x4dc 0x1a 0x00 0x434 0x4b 0x00 0x414 0x04 0x00 0x40c 0x04 0x00 0x4f8 0x71 0x00 0x564 0x59 0x00 0x568 0x59 0x00 0x4fc 0x80 0x00 0x51c 0x40 0x00 0x444 0x71 0x00 0x43c 0x40 0x00 0x854 0x04 0x00 0x62c 0x52 0x00 0x654 0x10 0x00 0x65c 0x1a 0x00 0x660 0x06 0x00 0x8c8 0x83 0x00 0x8cc 0x09 0x00 0x8d0 0xa2 0x00 0x8d4 0x40 0x00 0x8c4 0x02 0x00 0x9ac 0x00 0x00 0x8a0 0x01 0x00 0x9e0 0x00 0x00 0x9dc 0x20 0x00 0x9a8 0x00 0x00 0x8a4 0x01 0x00 0x8a8 0x73 0x00 0x9d8 0xbb 0x00 0x9b0 0x03 0x00 0xa0c 0x0d 0x00 0x86c 0x00 0x00 0x644 0x00 0x00 0x804 0x03 0x00 0x800 0x00 0x00 0x808 0x03 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x2db 0x2dc 0x2dd>; + perst-gpio = <0x3c 0x23 0x00>; + wake-gpio = <0x3c 0x25 0x00>; + gdsc-vdd-supply = <0x2de>; + vreg-1.8-supply = <0x33>; + vreg-0.9-supply = <0x34>; + vreg-cx-supply = <0x1b>; + qcom,vreg-1.8-voltage-level = <0x124f80 0x124f80 0x5dc0>; + qcom,vreg-0.9-voltage-level = <0xd6d80 0xd6d80 0x5dc0>; + qcom,vreg-cx-voltage-level = <0x10000 0x81 0x00>; + qcom,l1ss-supported; + qcom,aux-clk-sync; + qcom,ep-latency = <0x0a>; + qcom,phy-status-offset = <0x974>; + qcom,boot-option = <0x01>; + linux,pci-domain = <0x00>; + qcom,msi-gicm-addr = <0x17a00040>; + qcom,msi-gicm-base = <0x2c0>; + qcom,pcie-phy-ver = <0x30>; + qcom,use-19p2mhz-aux-clk; + qcom,smmu-sid-base = <0x1c10>; + iommu-map = <0x00 0x29 0x1c10 0x01 0x100 0x29 0x1c11 0x01 0x200 0x29 0x1c12 0x01 0x300 0x29 0x1c13 0x01 0x400 0x29 0x1c14 0x01 0x500 0x29 0x1c15 0x01 0x600 0x29 0x1c16 0x01 0x700 0x29 0x1c17 0x01 0x800 0x29 0x1c18 0x01 0x900 0x29 0x1c19 0x01 0xa00 0x29 0x1c1a 0x01 0xb00 0x29 0x1c1b 0x01 0xc00 0x29 0x1c1c 0x01 0xd00 0x29 0x1c1d 0x01 0xe00 0x29 0x1c1e 0x01 0xf00 0x29 0x1c1f 0x01>; + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x2d 0x200 0x00 0x00 0x2d 0x200 0x1f4 0x320>; + clocks = <0x22 0x36 0x21 0x00 0x22 0x31 0x22 0x33 0x22 0x35 0x22 0x37 0x22 0x34 0x22 0x38 0x22 0x06 0x22 0x42 0x22 0x41>; + clock-names = "pcie_0_pipe_clk\0pcie_0_ref_clk_src\0pcie_0_aux_clk\0pcie_0_cfg_ahb_clk\0pcie_0_mstr_axi_clk\0pcie_0_slv_axi_clk\0pcie_0_ldo\0pcie_0_slv_q2a_axi_clk\0pcie_tbu_clk\0pcie_phy_refgen_clk\0pcie_phy_aux_clk"; + max-clock-frequency-hz = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00>; + resets = <0x22 0x01 0x22 0x18>; + reset-names = "pcie_0_core_reset\0pcie_0_phy_reset"; + status = "disabled"; + phandle = <0xd2>; + }; + + qcom,pcie@0x1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <0x01>; + reg = <0x1c08000 0x2000 0x1c0a000 0x2000 0x40000000 0xf1d 0x40000f20 0xa8 0x40100000 0x100000 0x40200000 0x100000 0x40300000 0x1fd00000>; + reg-names = "parf\0phy\0dm_core\0elbi\0conf\0io\0bars"; + #address-cells = <0x03>; + #size-cells = <0x02>; + ranges = <0x1000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x2000000 0x00 0x40300000 0x40300000 0x00 0x1fd00000>; + interrupt-parent = <0x2df>; + interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25>; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0xffffffff>; + interrupt-map = <0x00 0x00 0x00 0x00 0xa2 0x00 0x133 0x00 0x00 0x00 0x00 0x01 0xa2 0x00 0x1b2 0x00 0x00 0x00 0x00 0x02 0xa2 0x00 0x1b3 0x00 0x00 0x00 0x00 0x03 0xa2 0x00 0x1b6 0x00 0x00 0x00 0x00 0x04 0xa2 0x00 0x1b7 0x00 0x00 0x00 0x00 0x05 0xa2 0x00 0x132 0x00 0x00 0x00 0x00 0x06 0xa2 0x00 0x2c0 0x00 0x00 0x00 0x00 0x07 0xa2 0x00 0x2c1 0x00 0x00 0x00 0x00 0x08 0xa2 0x00 0x2c2 0x00 0x00 0x00 0x00 0x09 0xa2 0x00 0x2c3 0x00 0x00 0x00 0x00 0x0a 0xa2 0x00 0x2c4 0x00 0x00 0x00 0x00 0x0b 0xa2 0x00 0x2c5 0x00 0x00 0x00 0x00 0x0c 0xa2 0x00 0x2c6 0x00 0x00 0x00 0x00 0x0d 0xa2 0x00 0x2c7 0x00 0x00 0x00 0x00 0x0e 0xa2 0x00 0x2c8 0x00 0x00 0x00 0x00 0x0f 0xa2 0x00 0x2c9 0x00 0x00 0x00 0x00 0x10 0xa2 0x00 0x2ca 0x00 0x00 0x00 0x00 0x11 0xa2 0x00 0x2cb 0x00 0x00 0x00 0x00 0x12 0xa2 0x00 0x2cc 0x00 0x00 0x00 0x00 0x13 0xa2 0x00 0x2cd 0x00 0x00 0x00 0x00 0x14 0xa2 0x00 0x2ce 0x00 0x00 0x00 0x00 0x15 0xa2 0x00 0x2cf 0x00 0x00 0x00 0x00 0x16 0xa2 0x00 0x2d0 0x00 0x00 0x00 0x00 0x17 0xa2 0x00 0x2d1 0x00 0x00 0x00 0x00 0x18 0xa2 0x00 0x2d2 0x00 0x00 0x00 0x00 0x19 0xa2 0x00 0x2d3 0x00 0x00 0x00 0x00 0x1a 0xa2 0x00 0x2d4 0x00 0x00 0x00 0x00 0x1b 0xa2 0x00 0x2d5 0x00 0x00 0x00 0x00 0x1c 0xa2 0x00 0x2d6 0x00 0x00 0x00 0x00 0x1d 0xa2 0x00 0x2d7 0x00 0x00 0x00 0x00 0x1e 0xa2 0x00 0x2d8 0x00 0x00 0x00 0x00 0x1f 0xa2 0x00 0x2d9 0x00 0x00 0x00 0x00 0x20 0xa2 0x00 0x2da 0x00 0x00 0x00 0x00 0x21 0xa2 0x00 0x2db 0x00 0x00 0x00 0x00 0x22 0xa2 0x00 0x2dc 0x00 0x00 0x00 0x00 0x23 0xa2 0x00 0x2dd 0x00 0x00 0x00 0x00 0x24 0xa2 0x00 0x2de 0x00 0x00 0x00 0x00 0x25 0xa2 0x00 0x2df 0x00>; + interrupt-names = "int_msi\0int_a\0int_b\0int_c\0int_d\0int_global_int\0msi_0\0msi_1\0msi_2\0msi_3\0msi_4\0msi_5\0msi_6\0msi_7\0msi_8\0msi_9\0msi_10\0msi_11\0msi_12\0msi_13\0msi_14\0msi_15\0msi_16\0msi_17\0msi_18\0msi_19\0msi_20\0msi_21\0msi_22\0msi_23\0msi_24\0msi_25\0msi_26\0msi_27\0msi_28\0msi_29\0msi_30\0msi_31"; + qcom,phy-sequence = <0x1804 0x03 0x00 0xdc 0x27 0x00 0x14 0x01 0x00 0x20 0x31 0x00 0x24 0x01 0x00 0x28 0xde 0x00 0x2c 0x07 0x00 0x34 0x4c 0x00 0x38 0x06 0x00 0x54 0x18 0x00 0x58 0xb0 0x00 0x6c 0x8c 0x00 0x70 0x20 0x00 0x78 0x14 0x00 0x7c 0x34 0x00 0xb4 0x06 0x00 0xb8 0x06 0x00 0xc0 0x16 0x00 0xc4 0x16 0x00 0xcc 0x36 0x00 0xd0 0x36 0x00 0xf0 0x05 0x00 0xf8 0x42 0x00 0x100 0x82 0x00 0x108 0x68 0x00 0x11c 0x55 0x00 0x120 0x55 0x00 0x124 0x03 0x00 0x128 0xab 0x00 0x12c 0xaa 0x00 0x130 0x02 0x00 0x150 0x3f 0x00 0x158 0x3f 0x00 0x178 0x10 0x00 0x1cc 0x04 0x00 0x1d0 0x30 0x00 0x1e0 0x04 0x00 0x1e8 0x73 0x00 0x1f0 0x1c 0x00 0x1fc 0x15 0x00 0x21c 0x04 0x00 0x224 0x01 0x00 0x228 0x22 0x00 0x22c 0x00 0x00 0x98 0x05 0x00 0x80c 0x00 0x00 0x818 0x0d 0x00 0x860 0x01 0x00 0x864 0x3a 0x00 0x87c 0x2f 0x00 0x8c0 0x09 0x00 0x8c4 0x09 0x00 0x8c8 0x1a 0x00 0x8d0 0x01 0x00 0x8d4 0x07 0x00 0x8d8 0x31 0x00 0x8dc 0x31 0x00 0x8e0 0x03 0x00 0x8fc 0x02 0x00 0x900 0x01 0x00 0x908 0x12 0x00 0x914 0x25 0x00 0x918 0x00 0x00 0x91c 0x05 0x00 0x920 0x01 0x00 0x924 0x26 0x00 0x928 0x12 0x00 0x930 0x04 0x00 0x934 0x04 0x00 0x938 0x09 0x00 0x954 0x15 0x00 0x960 0x32 0x00 0x968 0x7f 0x00 0x96c 0x07 0x00 0x978 0x04 0x00 0x980 0x70 0x00 0x984 0x8b 0x00 0x988 0x08 0x00 0x98c 0x09 0x00 0x990 0x03 0x00 0x994 0x04 0x00 0x998 0x02 0x00 0x99c 0x0c 0x00 0x9a4 0x02 0x00 0x9c0 0x5c 0x00 0x9c4 0x3e 0x00 0x9c8 0x3f 0x00 0xa30 0x01 0x00 0xa34 0xa0 0x00 0xa38 0x08 0x00 0xaa4 0x01 0x00 0xaac 0xc3 0x00 0xab0 0x00 0x00 0xab8 0x8c 0x00 0xac0 0x7f 0x00 0xac4 0x2a 0x00 0x810 0x0c 0x00 0x814 0x00 0x00 0xacc 0x04 0x00 0x93c 0x20 0x00 0x100c 0x00 0x00 0x1018 0x0d 0x00 0x1060 0x01 0x00 0x1064 0x3a 0x00 0x107c 0x2f 0x00 0x10c0 0x09 0x00 0x10c4 0x09 0x00 0x10c8 0x1a 0x00 0x10d0 0x01 0x00 0x10d4 0x07 0x00 0x10d8 0x31 0x00 0x10dc 0x31 0x00 0x10e0 0x03 0x00 0x10fc 0x02 0x00 0x1100 0x01 0x00 0x1108 0x12 0x00 0x1114 0x25 0x00 0x1118 0x00 0x00 0x111c 0x05 0x00 0x1120 0x01 0x00 0x1124 0x26 0x00 0x1128 0x12 0x00 0x1130 0x04 0x00 0x1134 0x04 0x00 0x1138 0x09 0x00 0x1154 0x15 0x00 0x1160 0x32 0x00 0x1168 0x7f 0x00 0x116c 0x07 0x00 0x1178 0x04 0x00 0x1180 0x70 0x00 0x1184 0x8b 0x00 0x1188 0x08 0x00 0x118c 0x09 0x00 0x1190 0x03 0x00 0x1194 0x04 0x00 0x1198 0x02 0x00 0x119c 0x0c 0x00 0x11a4 0x02 0x00 0x11c0 0x5c 0x00 0x11c4 0x3e 0x00 0x11c8 0x3f 0x00 0x1230 0x01 0x00 0x1234 0xa0 0x00 0x1238 0x08 0x00 0x12a4 0x01 0x00 0x12ac 0xc3 0x00 0x12b0 0x00 0x00 0x12b8 0x8c 0x00 0x12c0 0x7f 0x00 0x12c4 0x2a 0x00 0x1010 0x0c 0x00 0x1014 0x0f 0x00 0x12cc 0x04 0x00 0x113c 0x20 0x00 0x195c 0x3f 0x00 0x1974 0x50 0x00 0x196c 0x9f 0x00 0x182c 0x19 0x00 0x1840 0x07 0x00 0x1854 0x17 0x00 0x1868 0x09 0x00 0x1800 0x00 0x00 0xaa8 0x01 0x00 0x12a8 0x01 0x00 0x1808 0x01 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x2e0 0x2e1 0x2e2>; + perst-gpio = <0x3c 0x66 0x00>; + wake-gpio = <0x3c 0x68 0x00>; + gdsc-vdd-supply = <0x2e3>; + vreg-1.8-supply = <0x33>; + vreg-0.9-supply = <0x34>; + vreg-cx-supply = <0x1b>; + qcom,vreg-1.8-voltage-level = <0x124f80 0x124f80 0x5dc0>; + qcom,vreg-0.9-voltage-level = <0xd6d80 0xd6d80 0x5dc0>; + qcom,vreg-cx-voltage-level = <0x10000 0x101 0x00>; + qcom,l1ss-supported; + qcom,aux-clk-sync; + qcom,ep-latency = <0x0a>; + qcom,slv-addr-space-size = <0x20000000>; + qcom,phy-status-offset = <0x1aac>; + qcom,boot-option = <0x01>; + linux,pci-domain = <0x01>; + qcom,msi-gicm-addr = <0x17a00040>; + qcom,msi-gicm-base = <0x2e0>; + qcom,max-link-speed = <0x03>; + qcom,use-19p2mhz-aux-clk; + qcom,smmu-sid-base = <0x1c00>; + iommu-map = <0x00 0x29 0x1c00 0x01 0x100 0x29 0x1c01 0x01 0x200 0x29 0x1c02 0x01 0x300 0x29 0x1c03 0x01 0x400 0x29 0x1c04 0x01 0x500 0x29 0x1c05 0x01 0x600 0x29 0x1c06 0x01 0x700 0x29 0x1c07 0x01 0x800 0x29 0x1c08 0x01 0x900 0x29 0x1c09 0x01 0xa00 0x29 0x1c0a 0x01 0xb00 0x29 0x1c0b 0x01 0xc00 0x29 0x1c0c 0x01 0xd00 0x29 0x1c0d 0x01 0xe00 0x29 0x1c0e 0x01 0xf00 0x29 0x1c0f 0x01>; + qcom,msm-bus,name = "pcie1"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x64 0x200 0x00 0x00 0x64 0x200 0x1f4 0x320>; + clocks = <0x22 0x3e 0x21 0x00 0x22 0x39 0x22 0x3b 0x22 0x3d 0x22 0x3f 0x22 0x3c 0x22 0x40 0x22 0x06 0x22 0x42 0x22 0x41>; + clock-names = "pcie_1_pipe_clk\0pcie_1_ref_clk_src\0pcie_1_aux_clk\0pcie_1_cfg_ahb_clk\0pcie_1_mstr_axi_clk\0pcie_1_slv_axi_clk\0pcie_1_ldo\0pcie_1_slv_q2a_axi_clk\0pcie_tbu_clk\0pcie_phy_refgen_clk\0pcie_phy_aux_clk"; + max-clock-frequency-hz = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00>; + resets = <0x22 0x02 0x22 0x19>; + reset-names = "pcie_1_core_reset\0pcie_1_phy_reset"; + status = "disabled"; + phandle = <0x2df>; + }; + + qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0x00>; + phandle = <0x2e4>; + }; + + qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + phandle = <0x2ee>; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + phandle = <0x2ef>; + }; + + qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0x01>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "regular"; + phandle = <0x2e5>; + }; + + qcom,msm-ultra-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0x02>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + phandle = <0x2e6>; + }; + + qcom,msm-pcm-dsp-noirq { + compatible = "qcom,msm-pcm-dsp-noirq"; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + phandle = <0x2f0>; + }; + + qcom,msm-compress-dsp { + compatible = "qcom,msm-compress-dsp"; + phandle = <0x2ea>; + }; + + qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + phandle = <0x2e7>; + }; + + qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + qcom,destroy-cvd; + phandle = <0x2e8>; + }; + + qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + phandle = <0x320>; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + phandle = <0x2ec>; + }; + + qcom,msm-dai-q6-hdmi { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <0x08>; + phandle = <0x2f1>; + }; + + qcom,msm-dai-q6-dp { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <0x6020>; + phandle = <0x2f2>; + }; + + qcom,msm-pcm-loopback { + compatible = "qcom,msm-pcm-loopback"; + phandle = <0x2e9>; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + + qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0x00>; + qcom,msm-mi2s-rx-lines = <0x03>; + qcom,msm-mi2s-tx-lines = <0x00>; + phandle = <0x2f3>; + }; + + qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0x01>; + qcom,msm-mi2s-rx-lines = <0x01>; + qcom,msm-mi2s-tx-lines = <0x00>; + phandle = <0x2f4>; + }; + + qcom,msm-dai-q6-mi2s-tert { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0x02>; + qcom,msm-mi2s-rx-lines = <0x00>; + qcom,msm-mi2s-tx-lines = <0x03>; + phandle = <0x2f5>; + }; + + qcom,msm-dai-q6-mi2s-quat { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0x03>; + qcom,msm-mi2s-rx-lines = <0x01>; + qcom,msm-mi2s-tx-lines = <0x02>; + phandle = <0x2f6>; + }; + + qcom,msm-dai-q6-mi2s-quin { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0x04>; + qcom,msm-mi2s-rx-lines = <0x01>; + qcom,msm-mi2s-tx-lines = <0x02>; + }; + + qcom,msm-dai-q6-mi2s-senary { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0x06>; + qcom,msm-mi2s-rx-lines = <0x00>; + qcom,msm-mi2s-tx-lines = <0x03>; + }; + }; + + qcom,msm-lsm-client { + compatible = "qcom,msm-lsm-client"; + phandle = <0x2ed>; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + + qcom,msm-dai-q6-sb-0-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4000>; + phandle = <0x2fb>; + }; + + qcom,msm-dai-q6-sb-0-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4001>; + phandle = <0x2fc>; + }; + + qcom,msm-dai-q6-sb-1-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4002>; + phandle = <0x2fd>; + }; + + qcom,msm-dai-q6-sb-1-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4003>; + phandle = <0x2fe>; + }; + + qcom,msm-dai-q6-sb-2-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4004>; + phandle = <0x2ff>; + }; + + qcom,msm-dai-q6-sb-2-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4005>; + phandle = <0x300>; + }; + + qcom,msm-dai-q6-sb-3-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4006>; + phandle = <0x301>; + }; + + qcom,msm-dai-q6-sb-3-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4007>; + phandle = <0x302>; + }; + + qcom,msm-dai-q6-sb-4-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4008>; + phandle = <0x303>; + }; + + qcom,msm-dai-q6-sb-4-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4009>; + phandle = <0x304>; + }; + + qcom,msm-dai-q6-sb-5-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x400b>; + phandle = <0x305>; + }; + + qcom,msm-dai-q6-sb-5-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x400a>; + phandle = <0x30e>; + }; + + qcom,msm-dai-q6-sb-6-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x400c>; + phandle = <0x30f>; + }; + + qcom,msm-dai-q6-sb-7-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x400e>; + phandle = <0x310>; + }; + + qcom,msm-dai-q6-sb-7-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x400f>; + phandle = <0x311>; + }; + + qcom,msm-dai-q6-sb-8-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4010>; + }; + + qcom,msm-dai-q6-sb-8-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x4011>; + phandle = <0x312>; + }; + + qcom,msm-dai-q6-bt-sco-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x3000>; + }; + + qcom,msm-dai-q6-bt-sco-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x3001>; + }; + + qcom,msm-dai-q6-int-fm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x3004>; + }; + + qcom,msm-dai-q6-int-fm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x3005>; + }; + + qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0xe0>; + phandle = <0x306>; + }; + + qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0xe1>; + phandle = <0x307>; + }; + + qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0xf1>; + phandle = <0x308>; + }; + + qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0xf0>; + phandle = <0x309>; + }; + + qcom,msm-dai-q6-afe-loopback-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x6001>; + }; + + qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x8003>; + phandle = <0x30a>; + }; + + qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x8004>; + phandle = <0x30b>; + }; + + qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x8005>; + phandle = <0x30c>; + }; + + qcom,msm-dai-q6-incall-music-2-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x8002>; + phandle = <0x30d>; + }; + + qcom,msm-dai-q6-usb-audio-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x7000>; + phandle = <0x313>; + }; + + qcom,msm-dai-q6-usb-audio-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <0x7001>; + phandle = <0x314>; + }; + }; + + qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + phandle = <0x2eb>; + }; + + qcom,msm-audio-apr { + compatible = "qcom,msm-audio-apr"; + qcom,subsys-name = "apr_adsp"; + + sound-tavil { + compatible = "qcom,sdm845-asoc-snd-tavil"; + qcom,model = "sdm845-tavil-snd-card"; + qcom,ext-disp-audio-rx; + qcom,wcn-btfm; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <0x01 0x01 0x01 0x01>; + asoc-platform = <0x2e4 0x2e5 0x2e6 0x2e7 0x2e8 0x2e9 0x2ea 0x2eb 0x2ec 0x2ed 0x2ee 0x2ef 0x2f0>; + asoc-platform-names = "msm-pcm-dsp.0\0msm-pcm-dsp.1\0msm-pcm-dsp.2\0msm-voip-dsp\0msm-pcm-voice\0msm-pcm-loopback\0msm-compress-dsp\0msm-pcm-hostless\0msm-pcm-afe\0msm-lsm-client\0msm-pcm-routing\0msm-compr-dsp\0msm-pcm-dsp-noirq"; + asoc-cpu = <0x2f1 0x2f2 0x2f3 0x2f4 0x2f5 0x2f6 0x2f7 0x2f8 0x2f9 0x2fa 0x2fb 0x2fc 0x2fd 0x2fe 0x2ff 0x300 0x301 0x302 0x303 0x304 0x305 0x306 0x307 0x308 0x309 0x30a 0x30b 0x30c 0x30d 0x30e 0x30f 0x310 0x311 0x312 0x313 0x314 0x315 0x316 0x317 0x318 0x319 0x31a 0x31b 0x31c 0x31d>; + asoc-cpu-names = "msm-dai-q6-hdmi.8\0msm-dai-q6-dp.24608\0msm-dai-q6-mi2s.0\0msm-dai-q6-mi2s.1\0msm-dai-q6-mi2s.2\0msm-dai-q6-mi2s.3\0msm-dai-q6-auxpcm.1\0msm-dai-q6-auxpcm.2\0msm-dai-q6-auxpcm.3\0msm-dai-q6-auxpcm.4\0msm-dai-q6-dev.16384\0msm-dai-q6-dev.16385\0msm-dai-q6-dev.16386\0msm-dai-q6-dev.16387\0msm-dai-q6-dev.16388\0msm-dai-q6-dev.16389\0msm-dai-q6-dev.16390\0msm-dai-q6-dev.16391\0msm-dai-q6-dev.16392\0msm-dai-q6-dev.16393\0msm-dai-q6-dev.16395\0msm-dai-q6-dev.224\0msm-dai-q6-dev.225\0msm-dai-q6-dev.241\0msm-dai-q6-dev.240\0msm-dai-q6-dev.32771\0msm-dai-q6-dev.32772\0msm-dai-q6-dev.32773\0msm-dai-q6-dev.32770\0msm-dai-q6-dev.16394\0msm-dai-q6-dev.16396\0msm-dai-q6-dev.16398\0msm-dai-q6-dev.16399\0msm-dai-q6-dev.16401\0msm-dai-q6-dev.28672\0msm-dai-q6-dev.28673\0msm-dai-q6-tdm.36864\0msm-dai-q6-tdm.36865\0msm-dai-q6-tdm.36880\0msm-dai-q6-tdm.36881\0msm-dai-q6-tdm.36896\0msm-dai-q6-tdm.36897\0msm-dai-q6-tdm.36912\0msm-dai-q6-tdm.36913\0msm-dai-q6-tdm.36914"; + qcom,audio-routing = "AIF4 VI\0MCLK\0RX_BIAS\0MCLK\0MADINPUT\0MCLK\0hifi amp\0LINEOUT1\0hifi amp\0LINEOUT2\0AMIC2\0MIC BIAS2\0MIC BIAS2\0Headset Mic\0AMIC3\0MIC BIAS3\0MIC BIAS3\0ANCRight Headset Mic\0AMIC1\0MIC BIAS1\0MIC BIAS1\0ANCLeft Headset Mic\0AMIC4\0MIC BIAS3\0MIC BIAS3\0ANCRight Headset Mic\0AMIC5\0MIC BIAS4\0MIC BIAS4\0Analog Mic5"; + qcom,msm-mbhc-hphl-swh = <0x01>; + qcom,msm-mbhc-gnd-swh = <0x01>; + qcom,hph-en0-gpio = <0x31e>; + qcom,hph-en1-gpio = <0x31f>; + qcom,tavil-mclk-clk-freq = <0x927c00>; + asoc-codec = <0x320 0x321>; + asoc-codec-names = "msm-stub-codec.1\0msm-ext-disp-audio-codec-rx"; + qcom,usbc-analog-en1-gpio = <0x322>; + pinctrl-names = "aud_active\0aud_sleep\0quat-mi2s-active\0quat-mi2s-sleep\0quat-tdm-active\0quat-tdm-sleep"; + pinctrl-0 = <0x323>; + pinctrl-1 = <0x324>; + qcom,wsa-max-devs = <0x00>; + qcom,wsa-devs = <0x325 0x326 0x327 0x328>; + qcom,wsa-aux-dev-prefix = "SpkrLeft\0SpkrRight\0SpkrLeft\0SpkrRight"; + qcom,uart-audio-sw-gpio = <0x322>; + qcom,msm-mbhc-usbc-audio-supported = <0x00>; + pinctrl-2 = <0x329 0x32a 0x32b>; + pinctrl-3 = <0x32c 0x32d 0x32e>; + pinctrl-4 = <0x32f 0x330>; + pinctrl-5 = <0x331 0x332>; + }; + }; + + qcom,msm-pri-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; + qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; + qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; + qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; + qcom,msm-auxpcm-interface = "primary"; + qcom,msm-cpudai-afe-clk-ver = <0x02>; + phandle = <0x2f7>; + }; + + qcom,msm-sec-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; + qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; + qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; + qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; + qcom,msm-auxpcm-interface = "secondary"; + qcom,msm-cpudai-afe-clk-ver = <0x02>; + phandle = <0x2f8>; + }; + + qcom,msm-tert-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; + qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; + qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; + qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; + qcom,msm-auxpcm-interface = "tertiary"; + qcom,msm-cpudai-afe-clk-ver = <0x02>; + phandle = <0x2f9>; + }; + + qcom,msm-quat-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; + qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; + qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; + qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; + qcom,msm-auxpcm-interface = "quaternary"; + qcom,msm-cpudai-afe-clk-ver = <0x02>; + phandle = <0x2fa>; + }; + + qcom,msm-quin-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; + qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; + qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; + qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; + qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; + qcom,msm-auxpcm-interface = "quinary"; + qcom,msm-cpudai-afe-clk-ver = <0x02>; + }; + + qcom,msm-hdmi-dba-codec-rx { + compatible = "qcom,msm-hdmi-dba-codec-rx"; + qcom,dba-bridge-chip = "adv7533"; + }; + + qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + qcom,smmu-version = <0x02>; + qcom,smmu-enabled; + iommus = <0x29 0x1821 0x00>; + qcom,smmu-sid-mask = <0x00 0x0f>; + }; + + qcom,msm-adsp-loader { + status = "ok"; + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0x00>; + }; + + qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <0x9100>; + qcom,msm-cpudai-tdm-group-num-ports = <0x01>; + qcom,msm-cpudai-tdm-group-port-id = <0x9000>; + qcom,msm-cpudai-tdm-clk-rate = <0x177000>; + qcom,msm-cpudai-tdm-clk-internal = <0x01>; + qcom,msm-cpudai-tdm-sync-mode = <0x01>; + qcom,msm-cpudai-tdm-sync-src = <0x01>; + qcom,msm-cpudai-tdm-data-out = <0x00>; + qcom,msm-cpudai-tdm-invert-sync = <0x01>; + qcom,msm-cpudai-tdm-data-delay = <0x01>; + + qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <0x9000>; + qcom,msm-cpudai-tdm-data-align = <0x00>; + phandle = <0x315>; + }; + }; + + qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <0x9101>; + qcom,msm-cpudai-tdm-group-num-ports = <0x01>; + qcom,msm-cpudai-tdm-group-port-id = <0x9001>; + qcom,msm-cpudai-tdm-clk-rate = <0x177000>; + qcom,msm-cpudai-tdm-clk-internal = <0x01>; + qcom,msm-cpudai-tdm-sync-mode = <0x01>; + qcom,msm-cpudai-tdm-sync-src = <0x01>; + qcom,msm-cpudai-tdm-data-out = <0x00>; + qcom,msm-cpudai-tdm-invert-sync = <0x01>; + qcom,msm-cpudai-tdm-data-delay = <0x01>; + + qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <0x9001>; + qcom,msm-cpudai-tdm-data-align = <0x00>; + phandle = <0x316>; + }; + }; + + qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <0x9110>; + qcom,msm-cpudai-tdm-group-num-ports = <0x01>; + qcom,msm-cpudai-tdm-group-port-id = <0x9010>; + qcom,msm-cpudai-tdm-clk-rate = <0x177000>; + qcom,msm-cpudai-tdm-clk-internal = <0x01>; + qcom,msm-cpudai-tdm-sync-mode = <0x01>; + qcom,msm-cpudai-tdm-sync-src = <0x01>; + qcom,msm-cpudai-tdm-data-out = <0x00>; + qcom,msm-cpudai-tdm-invert-sync = <0x01>; + qcom,msm-cpudai-tdm-data-delay = <0x01>; + + qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <0x9010>; + qcom,msm-cpudai-tdm-data-align = <0x00>; + phandle = <0x317>; + }; + }; + + qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <0x9111>; + qcom,msm-cpudai-tdm-group-num-ports = <0x01>; + qcom,msm-cpudai-tdm-group-port-id = <0x9011>; + qcom,msm-cpudai-tdm-clk-rate = <0x177000>; + qcom,msm-cpudai-tdm-clk-internal = <0x01>; + qcom,msm-cpudai-tdm-sync-mode = <0x01>; + qcom,msm-cpudai-tdm-sync-src = <0x01>; + qcom,msm-cpudai-tdm-data-out = <0x00>; + qcom,msm-cpudai-tdm-invert-sync = <0x01>; + qcom,msm-cpudai-tdm-data-delay = <0x01>; + + qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <0x9011>; + qcom,msm-cpudai-tdm-data-align = <0x00>; + phandle = <0x318>; + }; + }; + + qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <0x9120>; + qcom,msm-cpudai-tdm-group-num-ports = <0x01>; + qcom,msm-cpudai-tdm-group-port-id = <0x9020>; + qcom,msm-cpudai-tdm-clk-rate = <0x177000>; + qcom,msm-cpudai-tdm-clk-internal = <0x01>; + qcom,msm-cpudai-tdm-sync-mode = <0x01>; + qcom,msm-cpudai-tdm-sync-src = <0x01>; + qcom,msm-cpudai-tdm-data-out = <0x00>; + qcom,msm-cpudai-tdm-invert-sync = <0x01>; + qcom,msm-cpudai-tdm-data-delay = <0x01>; + + qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <0x9020>; + qcom,msm-cpudai-tdm-data-align = <0x00>; + phandle = <0x319>; + }; + }; + + qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <0x9121>; + qcom,msm-cpudai-tdm-group-num-ports = <0x01>; + qcom,msm-cpudai-tdm-group-port-id = <0x9021>; + qcom,msm-cpudai-tdm-clk-rate = <0x177000>; + qcom,msm-cpudai-tdm-clk-internal = <0x01>; + qcom,msm-cpudai-tdm-sync-mode = <0x01>; + qcom,msm-cpudai-tdm-sync-src = <0x01>; + qcom,msm-cpudai-tdm-data-out = <0x00>; + qcom,msm-cpudai-tdm-invert-sync = <0x01>; + qcom,msm-cpudai-tdm-data-delay = <0x01>; + + qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <0x9021>; + qcom,msm-cpudai-tdm-data-align = <0x00>; + phandle = <0x31a>; + }; + }; + + qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <0x9130>; + qcom,msm-cpudai-tdm-group-num-ports = <0x02>; + qcom,msm-cpudai-tdm-group-port-id = <0x9030 0x9032>; + qcom,msm-cpudai-tdm-clk-rate = <0x177000>; + qcom,msm-cpudai-tdm-clk-internal = <0x01>; + qcom,msm-cpudai-tdm-sync-mode = <0x01>; + qcom,msm-cpudai-tdm-sync-src = <0x01>; + qcom,msm-cpudai-tdm-data-out = <0x00>; + qcom,msm-cpudai-tdm-invert-sync = <0x01>; + qcom,msm-cpudai-tdm-data-delay = <0x01>; + + qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <0x9030>; + qcom,msm-cpudai-tdm-data-align = <0x00>; + phandle = <0x31b>; + }; + + qcom,msm-dai-q6-tdm-quat-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <0x9032>; + qcom,msm-cpudai-tdm-data-align = <0x00>; + phandle = <0x31d>; + }; + }; + + qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <0x9131>; + qcom,msm-cpudai-tdm-group-num-ports = <0x01>; + qcom,msm-cpudai-tdm-group-port-id = <0x9031>; + qcom,msm-cpudai-tdm-clk-rate = <0x177000>; + qcom,msm-cpudai-tdm-clk-internal = <0x01>; + qcom,msm-cpudai-tdm-sync-mode = <0x01>; + qcom,msm-cpudai-tdm-sync-src = <0x01>; + qcom,msm-cpudai-tdm-data-out = <0x00>; + qcom,msm-cpudai-tdm-invert-sync = <0x01>; + qcom,msm-cpudai-tdm-data-delay = <0x01>; + + qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <0x9031>; + qcom,msm-cpudai-tdm-data-align = <0x00>; + phandle = <0x31c>; + }; + }; + + qcom,msm-dai-tdm-quin-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <0x9140>; + qcom,msm-cpudai-tdm-group-num-ports = <0x01>; + qcom,msm-cpudai-tdm-group-port-id = <0x9040>; + qcom,msm-cpudai-tdm-clk-rate = <0x177000>; + qcom,msm-cpudai-tdm-clk-internal = <0x01>; + qcom,msm-cpudai-tdm-sync-mode = <0x01>; + qcom,msm-cpudai-tdm-sync-src = <0x01>; + qcom,msm-cpudai-tdm-data-out = <0x00>; + qcom,msm-cpudai-tdm-invert-sync = <0x01>; + qcom,msm-cpudai-tdm-data-delay = <0x01>; + + qcom,msm-dai-q6-tdm-quin-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <0x9040>; + qcom,msm-cpudai-tdm-data-align = <0x00>; + }; + }; + + qcom,msm-dai-tdm-quin-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <0x9141>; + qcom,msm-cpudai-tdm-group-num-ports = <0x01>; + qcom,msm-cpudai-tdm-group-port-id = <0x9041>; + qcom,msm-cpudai-tdm-clk-rate = <0x177000>; + qcom,msm-cpudai-tdm-clk-internal = <0x01>; + qcom,msm-cpudai-tdm-sync-mode = <0x01>; + qcom,msm-cpudai-tdm-sync-src = <0x01>; + qcom,msm-cpudai-tdm-data-out = <0x00>; + qcom,msm-cpudai-tdm-invert-sync = <0x01>; + qcom,msm-cpudai-tdm-data-delay = <0x01>; + + qcom,msm-dai-q6-tdm-quin-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <0x9041>; + qcom,msm-cpudai-tdm-data-align = <0x00>; + }; + }; + + qcom,avtimer@170f7000 { + compatible = "qcom,avtimer"; + reg = <0x170f700c 0x04 0x170f7010 0x04>; + reg-names = "avtimer_lsb_addr\0avtimer_msb_addr"; + qcom,clk-div = <0xc0>; + qcom,clk-mult = <0x0a>; + }; + + qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0x0d>; + qcom,firmware-name = "a630_zap"; + memory-region = <0x333>; + }; + + qcom,kgsl-busmon { + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <0x1a 0x200>; + qcom,bw-tbl = <0x00 0x17d 0x23c 0x2fa 0x478 0x623 0x826 0xa25 0xb71 0xf27 0x134f 0x172b 0x1ae1>; + phandle = <0x334>; + }; + + qcom,kgsl-3d0@5000000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0\0qcom,kgsl-3d"; + status = "ok"; + reg = <0x5000000 0x40000 0x5061000 0x800 0x509e000 0x1000>; + reg-names = "kgsl_3d0_reg_memory\0kgsl_3d0_cx_dbgc_memory\0cx_misc"; + interrupts = <0x00 0x12c 0x00>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0x00>; + qcom,chipid = <0x6030001>; + qcom,initial-pwrlevel = <0x06>; + qcom,gpu-quirk-hfi-use-reg; + qcom,gpu-quirk-secvid-set-once; + qcom,idle-timeout = <0x40>; + qcom,highest-bank-bit = <0x0f>; + qcom,min-access-length = <0x20>; + qcom,ubwc-mode = <0x02>; + qcom,snapshot-size = <0x100000>; + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; + qcom,tsens-name = "tsens_tz_sensor12"; + #cooling-cells = <0x02>; + tzone-names = "gpu0-usr\0gpu1-usr"; + qcom,pm-qos-active-latency = <0x1cc>; + clocks = <0x1c 0x03 0xd7 0x0a 0x22 0x1a 0x22 0x29 0xd7 0x04 0xb7 0x10>; + clock-names = "core_clk\0rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk\0l3_vote"; + qcom,isense-clk-on-level = <0x01>; + qcom,gpubw-dev = <0x334>; + qcom,bus-control; + qcom,msm-bus,name = "grp3d"; + qcom,bus-width = <0x20>; + qcom,msm-bus,num-cases = <0x0d>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x00 0x00 0x1a 0x200 0x00 0x61a80 0x1a 0x200 0x00 0x927c0 0x1a 0x200 0x00 0xc3500 0x1a 0x200 0x00 0x124f80 0x1a 0x200 0x00 0x192580 0x1a 0x200 0x00 0x2162e0 0x1a 0x200 0x00 0x2990a0 0x1a 0x200 0x00 0x2ee000 0x1a 0x200 0x00 0x3e12a0 0x1a 0x200 0x00 0x4f1a00 0x1a 0x200 0x00 0x5ee8e0 0x1a 0x200 0x00 0x6e1b80>; + regulator-names = "vddcx\0vdd"; + vddcx-supply = <0x1fd>; + vdd-supply = <0x335>; + cache-slice-names = "gpu\0gpuhtw"; + cache-slices = <0x32 0x0c 0x32 0x0b>; + phandle = <0xce>; + + qcom,gpu-coresights { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "qcom,gpu-coresight"; + status = "disabled"; + + qcom,gpu-coresight@0 { + reg = <0x00>; + coresight-name = "coresight-gfx"; + coresight-atid = <0x32>; + + port { + + endpoint { + remote-endpoint = <0x336>; + phandle = <0x1a1>; + }; + }; + }; + + qcom,gpu-coresight@1 { + reg = <0x01>; + coresight-name = "coresight-gfx-cx"; + coresight-atid = <0x33>; + + port { + + endpoint { + remote-endpoint = <0x337>; + phandle = <0x1a2>; + }; + }; + }; + }; + + qcom,l3-pwrlevels { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "qcom,l3-pwrlevels"; + + qcom,l3-pwrlevel@0 { + reg = <0x00>; + qcom,l3-freq = <0x00>; + }; + + qcom,l3-pwrlevel@1 { + reg = <0x01>; + qcom,l3-freq = <0x3010b000>; + }; + + qcom,l3-pwrlevel@2 { + reg = <0x02>; + qcom,l3-freq = <0x4dd1e000>; + }; + }; + + qcom,gpu-mempools { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "qcom,gpu-mempools"; + + qcom,gpu-mempool@0 { + reg = <0x00>; + qcom,mempool-page-size = <0x1000>; + qcom,mempool-reserved = <0x800>; + qcom,mempool-allocate; + }; + + qcom,gpu-mempool@1 { + reg = <0x01>; + qcom,mempool-page-size = <0x2000>; + qcom,mempool-reserved = <0x400>; + qcom,mempool-allocate; + }; + + qcom,gpu-mempool@2 { + reg = <0x02>; + qcom,mempool-page-size = <0x10000>; + qcom,mempool-reserved = <0x100>; + }; + + qcom,gpu-mempool@3 { + reg = <0x03>; + qcom,mempool-page-size = <0x100000>; + qcom,mempool-reserved = <0x20>; + }; + }; + + qcom,gpu-pwrlevels { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0x00>; + qcom,gpu-freq = <0x2a51bd80>; + qcom,bus-freq = <0x0c>; + qcom,bus-min = <0x0c>; + qcom,bus-max = <0x0c>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <0x01>; + qcom,gpu-freq = <0x283baec0>; + qcom,bus-freq = <0x0c>; + qcom,bus-min = <0x0a>; + qcom,bus-max = <0x0c>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <0x02>; + qcom,gpu-freq = <0x23863d00>; + qcom,bus-freq = <0x0a>; + qcom,bus-min = <0x09>; + qcom,bus-max = <0x0c>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <0x03>; + qcom,gpu-freq = <0x1efe9200>; + qcom,bus-freq = <0x09>; + qcom,bus-min = <0x08>; + qcom,bus-max = <0x0b>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <0x04>; + qcom,gpu-freq = <0x18ad2380>; + qcom,bus-freq = <0x08>; + qcom,bus-min = <0x07>; + qcom,bus-max = <0x09>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <0x05>; + qcom,gpu-freq = <0x14628180>; + qcom,bus-freq = <0x06>; + qcom,bus-min = <0x05>; + qcom,bus-max = <0x07>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <0x06>; + qcom,gpu-freq = <0xf518240>; + qcom,bus-freq = <0x04>; + qcom,bus-min = <0x03>; + qcom,bus-max = <0x05>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <0x07>; + qcom,gpu-freq = <0x00>; + qcom,bus-freq = <0x00>; + qcom,bus-min = <0x00>; + qcom,bus-max = <0x00>; + }; + }; + }; + + qcom,kgsl-iommu { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x5040000 0x10000>; + qcom,protect = <0x40000 0xc000>; + qcom,micro-mmu-control = <0x6000>; + clocks = <0x22 0x26 0x22 0x1a 0x22 0x29>; + clock-names = "iface_clk\0mem_clk\0mem_iface_clk"; + qcom,secure_align_mask = <0xfff>; + qcom,retention; + qcom,hyp_secure_alloc; + + gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <0x205 0x00>; + qcom,gpu-offset = <0x48000>; + }; + + gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <0x205 0x02 0x205 0x01>; + }; + }; + + qcom,gmu { + label = "kgsl-gmu"; + compatible = "qcom,gpu-gmu"; + reg = <0x506a000 0x30000 0xb200000 0x300000>; + reg-names = "kgsl_gmu_reg\0kgsl_gmu_pdc_reg"; + interrupts = <0x00 0x130 0x00 0x00 0x131 0x00>; + interrupt-names = "kgsl_hfi_irq\0kgsl_gmu_irq"; + qcom,msm-bus,name = "cnoc"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x01>; + qcom,msm-bus,vectors-KBps = <0x1a 0x2734 0x00 0x00 0x1a 0x2734 0x00 0x64>; + regulator-names = "vddcx\0vdd"; + vddcx-supply = <0x1fd>; + vdd-supply = <0x335>; + clocks = <0xd7 0x04 0xd7 0x0a 0x22 0x1a 0x22 0x29>; + clock-names = "gmu_clk\0cxo_clk\0axi_clk\0memnoc_clk"; + phandle = <0xcd>; + + qcom,gmu-pwrlevels { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "qcom,gmu-pwrlevels"; + + qcom,gmu-pwrlevel@0 { + reg = <0x00>; + qcom,gmu-freq = <0x00>; + }; + + qcom,gmu-pwrlevel@1 { + reg = <0x01>; + qcom,gmu-freq = <0xbebc200>; + }; + + qcom,gmu-pwrlevel@2 { + reg = <0x02>; + qcom,gmu-freq = <0x1dcd6500>; + }; + }; + + gmu_user { + compatible = "qcom,smmu-gmu-user-cb"; + iommus = <0x205 0x04>; + }; + + gmu_kernel { + compatible = "qcom,smmu-gmu-kernel-cb"; + iommus = <0x205 0x05>; + }; + }; + + ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0xf8c00 0x88ee000 0x400>; + reg-names = "core_base\0ahb2phy_base"; + iommus = <0x29 0x740 0x00>; + qcom,smmu-s1-bypass; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + interrupts = <0x00 0x1e9 0x00 0x00 0x82 0x00 0x00 0x1e6 0x00 0x00 0x1e8 0x00>; + interrupt-names = "dp_hs_phy_irq\0pwr_event_irq\0ss_phy_irq\0dm_hs_phy_irq"; + USB3_GDSC-supply = <0x338>; + qcom,usb-dbm = <0x339>; + qcom,dwc-usb3-msm-tx-fifo-size = <0x5328>; + qcom,num-gsi-evt-buffs = <0x03>; + qcom,use-pdc-interrupts; + qcom,pm-qos-latency = <0x2c>; + extcon = <0x36 0x36 0x33a>; + clocks = <0x22 0x95 0x22 0x12 0x22 0x09 0x22 0x97 0x22 0x99 0x22 0xa9 0x22 0x9f>; + clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk\0cfg_ahb_clk\0xo"; + qcom,core-clk-rate = <0x7f28155>; + qcom,core-clk-rate-hs = <0x3f940ab>; + resets = <0x22 0x0f>; + reset-names = "core_reset"; + qcom,msm-bus,name = "usb0"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x03>; + qcom,msm-bus,vectors-KBps = <0x3d 0x200 0x00 0x00 0x3d 0x2a4 0x00 0x00 0x01 0x247 0x00 0x00 0x3d 0x200 0x3a980 0xaae60 0x3d 0x2a4 0x00 0x960 0x01 0x247 0x00 0x9c40>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xcd00>; + interrupts = <0x00 0x85 0x00>; + usb-phy = <0xa8 0x33b>; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = [10]; + snps,usb3_lpm_capable; + usb-core-id = <0x00>; + maximum-speed = "high-speed"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = <0x00 0x84 0x00>; + qcom,bam-type = <0x00>; + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <0x08>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <0x190>; + qcom,usb-bam-max-mbps-superspeed = <0xe10>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <0x02>; + qcom,dir = <0x01>; + qcom,pipe-num = <0x00>; + qcom,peer-bam = <0x00>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0x00>; + qcom,dst-bam-pipe-index = <0x00>; + qcom,data-fifo-offset = <0x00>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + qusb@88e2000 { + compatible = "qcom,qusb2phy-v2"; + reg = <0x88e2000 0x400 0x7801e8 0x04 0x88e7014 0x04>; + reg-names = "qusb_phy_base\0efuse_addr\0refgen_north_bg_reg_addr"; + qcom,efuse-bit-pos = <0x19>; + qcom,efuse-num-bits = <0x03>; + qcom,tune-efuse-correction = <0x00>; + vdd-supply = <0x34>; + vdda18-supply = <0x17b>; + vdda33-supply = <0xa9>; + qcom,override-bias-ctrl2; + qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; + qcom,qusb-phy-reg-offset = <0x240 0x1a0 0x210 0x230 0xa8 0x254 0x198 0x228 0x22c 0x27c 0x280 0x284 0x288 0x2a0>; + qcom,qusb-phy-init-seq = <0x23 0x210 0x03 0x04 0x7c 0x18c 0x80 0x2c 0x0a 0x184 0x19 0xb4 0x40 0x194 0x18 0x198 0x21 0x214 0x08 0x220 0x58 0x224 0x07 0x240 0x29 0x244 0xca 0x248 0x04 0x24c 0x03 0x250 0x00 0x23c 0x22 0x210>; + phy_type = "utmi"; + clocks = <0x21 0x00 0x22 0xa9>; + clock-names = "ref_clk_src\0cfg_ahb_clk"; + resets = <0x22 0x08>; + reset-names = "phy_reset"; + pinctrl-names = "atest_usb13_suspend\0atest_usb13_active"; + pinctrl-0 = <0x33c>; + pinctrl-1 = <0x33d>; + mi,efuse-pll-bias; + mi,efuse-pll-bias-seq = <0x01 0x1d>; + phandle = <0xa8>; + }; + + ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + vdd-supply = <0x34>; + core-supply = <0x33>; + qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = <0x1048 0x07 0x00 0x1080 0x14 0x00 0x1034 0x08 0x00 0x1138 0x30 0x00 0x103c 0x02 0x00 0x108c 0x08 0x00 0x115c 0x16 0x00 0x1164 0x01 0x00 0x113c 0x80 0x00 0x10b0 0x82 0x00 0x10b8 0xab 0x00 0x10bc 0xea 0x00 0x10c0 0x02 0x00 0x1060 0x06 0x00 0x1068 0x16 0x00 0x1070 0x36 0x00 0x10dc 0x00 0x00 0x10d8 0x3f 0x00 0x10f8 0x01 0x00 0x10f4 0xc9 0x00 0x1148 0x0a 0x00 0x10a0 0x00 0x00 0x109c 0x34 0x00 0x1098 0x15 0x00 0x1090 0x04 0x00 0x1154 0x00 0x00 0x1094 0x00 0x00 0x10f0 0x00 0x00 0x1040 0x0a 0x00 0x1010 0x01 0x00 0x101c 0x31 0x00 0x1020 0x01 0x00 0x1014 0x00 0x00 0x1018 0x00 0x00 0x1024 0x85 0x00 0x1028 0x07 0x00 0x1430 0x0b 0x00 0x14d4 0x0f 0x00 0x14d8 0x4e 0x00 0x14dc 0x18 0x00 0x14f8 0x77 0x00 0x14fc 0x80 0x00 0x1504 0x03 0x00 0x150c 0x16 0x00 0x1564 0x05 0x00 0x14c0 0x03 0x00 0x1830 0x0b 0x00 0x18d4 0x0f 0x00 0x18d8 0x4e 0x00 0x18dc 0x18 0x00 0x18f8 0x77 0x00 0x18fc 0x80 0x00 0x1904 0x03 0x00 0x190c 0x16 0x00 0x1964 0x05 0x00 0x18c0 0x03 0x00 0x1260 0x10 0x00 0x12a4 0x12 0x00 0x128c 0x16 0x00 0x1248 0x09 0x00 0x1244 0x06 0x00 0x1660 0x10 0x00 0x16a4 0x12 0x00 0x168c 0x16 0x00 0x1648 0x09 0x00 0x1644 0x06 0x00 0x1cc8 0x83 0x00 0x1ccc 0x09 0x00 0x1cd0 0xa2 0x00 0x1cd4 0x40 0x00 0x1cc4 0x02 0x00 0x1c80 0xd1 0x00 0x1c84 0x1f 0x00 0x1c88 0x47 0x00 0x1c64 0x1b 0x00 0x1434 0x75 0x00 0x1834 0x75 0x00 0x1dd8 0xba 0x00 0x1c0c 0x9f 0x00 0x1c10 0x9f 0x00 0x1c14 0xb7 0x00 0x1c18 0x4e 0x00 0x1c1c 0x65 0x00 0x1c20 0x6b 0x00 0x1c24 0x15 0x00 0x1c28 0x0d 0x00 0x1c2c 0x15 0x00 0x1c30 0x0d 0x00 0x1c34 0x15 0x00 0x1c38 0x0d 0x00 0x1c3c 0x15 0x00 0x1c40 0x1d 0x00 0x1c44 0x15 0x00 0x1c48 0x0d 0x00 0x1c4c 0x15 0x00 0x1c50 0x0d 0x00 0x1e0c 0x21 0x00 0x1e10 0x60 0x00 0x1c5c 0x02 0x00 0x1ca0 0x04 0x00 0x1c8c 0x44 0x00 0x1c70 0xe7 0x00 0x1c74 0x03 0x00 0x1c78 0x40 0x00 0x1c7c 0x00 0x00 0x1cb8 0x75 0x00 0x1cb0 0x86 0x00 0x1cbc 0x13 0x00 0x1cac 0x04 0x00 0xffffffff 0xffffffff 0x00>; + qcom,qmp-phy-reg-offset = <0x1d74 0x1cd8 0x1cdc 0x1c04 0x1c00 0x1c08 0x2a18 0x08 0x04 0x1c 0x00 0x10 0x0c 0x1a0c>; + clocks = <0x22 0xa0 0x22 0xa3 0x21 0x00 0x22 0x9f 0x22 0xa2 0x22 0xa9>; + clock-names = "aux_clk\0pipe_clk\0ref_clk_src\0ref_clk\0com_aux_clk\0cfg_ahb_clk"; + resets = <0x22 0x13 0x22 0x11>; + reset-names = "global_phy_reset\0phy_reset"; + extcon = <0x36>; + phandle = <0x33b>; + }; + + dbm@a6f8000 { + compatible = "qcom,usb-dbm-1p5"; + reg = <0xa6f8000 0x400>; + qcom,reset-ep-after-lpm-resume; + phandle = <0x339>; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <0x29 0x182c 0x00>; + qcom,usb-audio-stream-id = <0x0c>; + qcom,usb-audio-intr-num = <0x02>; + }; + + usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa800000 0xf8c00 0x88ee000 0x400>; + reg-names = "core_base\0ahb2phy_base"; + iommus = <0x29 0x760 0x00>; + qcom,smmu-s1-bypass; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + interrupts = <0x00 0x1eb 0x00 0x00 0x87 0x00 0x00 0x1e7 0x00 0x00 0x1ea 0x00>; + interrupt-names = "dp_hs_phy_irq\0pwr_event_irq\0ss_phy_irq\0dm_hs_phy_irq"; + USB3_GDSC-supply = <0x33e>; + qcom,dwc-usb3-msm-tx-fifo-size = <0x5328>; + qcom,use-pdc-interrupts; + clocks = <0x22 0x9a 0x22 0x13 0x22 0x0a 0x22 0x9c 0x22 0x9e 0x22 0xa9 0x22 0xa4>; + clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk\0cfg_ahb_clk\0xo"; + qcom,core-clk-rate = <0x7f28155>; + qcom,core-clk-rate-hs = <0x3f940ab>; + resets = <0x22 0x10>; + reset-names = "core_reset"; + status = "disabled"; + qcom,msm-bus,name = "usb1"; + qcom,msm-bus,num-cases = <0x02>; + qcom,msm-bus,num-paths = <0x02>; + qcom,msm-bus,vectors-KBps = <0x65 0x200 0x00 0x00 0x01 0x2ef 0x00 0x00 0x65 0x200 0x3a980 0xaae60 0x01 0x2ef 0x00 0x9c40>; + extcon = <0x33f>; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0xa800000 0xcd00>; + interrupts = <0x00 0x8a 0x00>; + usb-phy = <0x340 0x341>; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = [10]; + snps,usb3_lpm_capable; + usb-core-id = <0x01>; + dr_mode = "host"; + maximum-speed = "high-speed"; + }; + }; + + qusb@88e3000 { + compatible = "qcom,qusb2phy-v2"; + reg = <0x88e3000 0x400 0x88e7014 0x04>; + reg-names = "qusb_phy_base\0refgen_north_bg_reg_addr"; + vdd-supply = <0x34>; + vdda18-supply = <0x17b>; + vdda33-supply = <0xa9>; + qcom,override-bias-ctrl2; + qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; + qcom,qusb-phy-reg-offset = <0x240 0x1a0 0x210 0x230 0xa8 0x254 0x198 0x228 0x22c 0x27c 0x280 0x2a0>; + qcom,qusb-phy-init-seq = <0x23 0x210 0x03 0x04 0x7c 0x18c 0x80 0x2c 0x0a 0x184 0x19 0xb4 0x40 0x194 0x20 0x198 0x21 0x214 0x00 0x220 0x58 0x224 0x20 0x240 0x29 0x244 0xca 0x248 0x04 0x24c 0x03 0x250 0x00 0x23c 0x22 0x210>; + phy_type = "utmi"; + clocks = <0x21 0x00 0x22 0xa9>; + clock-names = "ref_clk_src\0cfg_ahb_clk"; + resets = <0x22 0x09>; + reset-names = "phy_reset"; + status = "okay"; + phandle = <0x340>; + }; + + ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88eb000 0x1000 0x1fcbff0 0x04>; + reg-names = "qmp_phy_base\0vls_clamp_reg"; + vdd-supply = <0x34>; + core-supply = <0x33>; + qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = <0x48 0x07 0x00 0x80 0x14 0x00 0x34 0x04 0x00 0x138 0x30 0x00 0x3c 0x02 0x00 0x8c 0x08 0x00 0x15c 0x06 0x00 0x164 0x01 0x00 0x13c 0x80 0x00 0xb0 0x82 0x00 0xb8 0xab 0x00 0xbc 0xea 0x00 0xc0 0x02 0x00 0x60 0x06 0x00 0x68 0x16 0x00 0x70 0x36 0x00 0xdc 0x00 0x00 0xd8 0x3f 0x00 0xf8 0x01 0x00 0xf4 0xc9 0x00 0x148 0x0a 0x00 0xa0 0x00 0x00 0x9c 0x34 0x00 0x98 0x15 0x00 0x90 0x04 0x00 0x154 0x00 0x00 0x94 0x00 0x00 0xf0 0x00 0x00 0x40 0x0a 0x00 0xd0 0x80 0x00 0x10 0x01 0x00 0x1c 0x31 0x00 0x20 0x01 0x00 0x14 0x00 0x00 0x18 0x00 0x00 0x24 0x85 0x00 0x28 0x07 0x00 0x4c0 0x0c 0x00 0x564 0x50 0x00 0x430 0x0b 0x00 0x4d4 0x0e 0x00 0x4d8 0x4e 0x00 0x4dc 0x18 0x00 0x4f8 0x77 0x00 0x4fc 0x80 0x00 0x504 0x03 0x00 0x50c 0x1c 0x00 0x434 0x75 0x00 0x444 0x80 0x00 0x408 0x0a 0x00 0x40c 0x06 0x00 0x500 0x00 0x00 0x260 0x10 0x00 0x2a4 0x12 0x00 0x28c 0xc6 0x00 0x248 0x06 0x00 0x244 0x06 0x00 0x8c8 0x83 0x00 0x8cc 0x09 0x00 0x8d0 0xa2 0x00 0x8d4 0x40 0x00 0x8c4 0x02 0x00 0x864 0x1b 0x00 0x80c 0x9f 0x00 0x810 0x9f 0x00 0x814 0xb5 0x00 0x818 0x4c 0x00 0x81c 0x64 0x00 0x820 0x6a 0x00 0x824 0x15 0x00 0x828 0x0d 0x00 0x82c 0x15 0x00 0x830 0x0d 0x00 0x834 0x15 0x00 0x838 0x0d 0x00 0x83c 0x15 0x00 0x840 0x0d 0x00 0x844 0x15 0x00 0x848 0x0d 0x00 0x84c 0x15 0x00 0x850 0x0d 0x00 0x85c 0x02 0x00 0x8a0 0x04 0x00 0x88c 0x44 0x00 0x880 0xd1 0x00 0x884 0x1f 0x00 0x888 0x47 0x00 0x870 0xe7 0x00 0x874 0x03 0x00 0x878 0x40 0x00 0x87c 0x00 0x00 0x9d8 0xba 0x00 0x8b8 0x75 0x00 0x8b0 0x86 0x00 0x8bc 0x13 0x00 0xa0c 0x21 0x00 0xa10 0x60 0x00 0xffffffff 0xffffffff 0x00>; + qcom,qmp-phy-reg-offset = <0x974 0x8d8 0x8dc 0x804 0x800 0x808>; + clocks = <0x22 0xa5 0x22 0xa8 0x21 0x00 0x22 0xa4 0x22 0xa9>; + clock-names = "aux_clk\0pipe_clk\0ref_clk_src\0ref_clk\0cfg_ahb_clk"; + resets = <0x22 0x14 0x22 0x15>; + reset-names = "phy_reset\0phy_phy_reset"; + status = "okay"; + phandle = <0x341>; + }; + + qcom,csiphy@ac68000 { + cell-index = <0x03>; + compatible = "qcom,csiphy-v1.0\0qcom,csiphy"; + reg = <0xac68000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x68000>; + interrupts = <0x00 0x1c0 0x00>; + interrupt-names = "csiphy"; + regulator-names = "gdscr\0refgen"; + gdscr-supply = <0x215>; + refgen-supply = <0x17c>; + csi-vdd-voltage = <0x124f80>; + mipi-csi-vdd-supply = <0x34>; + clocks = <0xd6 0x06 0xd6 0x55 0xd6 0x54 0xd6 0x09 0xd6 0x0a 0xd6 0x16 0xd6 0x12 0xd6 0x11>; + clock-names = "camnoc_axi_clk\0soc_ahb_clk\0slow_ahb_src_clk\0cpas_ahb_clk\0cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = <0x00 0x00 0x00 0x00 0x16e36000 0x00 0x100db355 0x00>; + status = "ok"; + phandle = <0xcc>; + }; + + qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + arch-compat = "lrme"; + status = "ok"; + }; + + qcom,lrme@ac6b000 { + cell-index = <0x00>; + compatible = "qcom,lrme"; + reg-names = "lrme"; + reg = <0xac6b000 0xa00>; + reg-cam-base = <0x6b000>; + interrupt-names = "lrme"; + interrupts = <0x00 0x1dc 0x00>; + regulator-names = "camss"; + camss-supply = <0x215>; + clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0camnoc_axi_clk\0lrme_clk_src\0lrme_clk"; + clocks = <0x22 0x0c 0x22 0x0d 0xd6 0x55 0xd6 0x09 0xd6 0x06 0xd6 0x41 0xd6 0x40>; + clock-rates = <0x00 0x00 0x00 0x00 0x00 0xbebc200 0xbebc200 0x00 0x00 0x00 0x00 0x00 0x10089d40 0x10089d40 0x00 0x00 0x00 0x00 0x00 0x1312d000 0x1312d000 0x00 0x00 0x00 0x00 0x00 0x17d78400 0x17d78400>; + clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo"; + src-clock-name = "lrme_clk_src"; + status = "ok"; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x00>; + qcom,client-id = <0x00>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x00>; + qcom,client-id = <0x02>; + label = "modem"; + }; + + qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <0x01>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + syscon@0x5091508 { + compatible = "syscon"; + reg = <0x5091508 0x04>; + phandle = <0x1e>; + }; + + syscon@0x5091008 { + compatible = "syscon"; + reg = <0x5091008 0x04>; + phandle = <0x1f>; + }; + + interrupt-controller@0xb220000 { + compatible = "qcom,pdc-sdm845-v2"; + reg = <0xb220000 0x400>; + #interrupt-cells = <0x03>; + interrupt-parent = <0xa2>; + interrupt-controller; + phandle = <0x01>; + }; + + dsi_panel_pwr_supply { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,panel-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <0x1b7740>; + qcom,supply-max-voltage = <0x1b7740>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + qcom,supply-post-on-sleep = <0x14>; + }; + + qcom,panel-supply-entry@1 { + reg = <0x01>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <0x4630c0>; + qcom,supply-max-voltage = <0x5b8d80>; + qcom,supply-enable-load = <0x186a0>; + qcom,supply-disable-load = <0x64>; + }; + + qcom,panel-supply-entry@2 { + reg = <0x02>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <0x4630c0>; + qcom,supply-max-voltage = <0x5b8d80>; + qcom,supply-enable-load = <0x186a0>; + qcom,supply-disable-load = <0x64>; + qcom,supply-post-on-sleep = <0x14>; + }; + }; + + dsi_panel_pwr_supply_no_labibb { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,panel-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <0x1b7740>; + qcom,supply-max-voltage = <0x1b7740>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + qcom,supply-post-on-sleep = <0x14>; + }; + }; + + dsi_panel_pwr_supply_vdd_no_labibb { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,panel-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <0x1b7740>; + qcom,supply-max-voltage = <0x1b7740>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + qcom,supply-post-on-sleep = <0x14>; + }; + + qcom,panel-supply-entry@1 { + reg = <0x01>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0x2dc6c0>; + qcom,supply-max-voltage = <0x2dc6c0>; + qcom,supply-enable-load = <0xd13a8>; + qcom,supply-disable-load = <0x00>; + qcom,supply-post-on-sleep = <0x00>; + }; + }; + + qcom,dsi-display@0 { + compatible = "qcom,dsi-display"; + label = "dsi_sharp_4k_dsc_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d 0x342>; + qcom,dsi-phy = <0x343 0x344>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x34a>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@1 { + compatible = "qcom,dsi-display"; + label = "dsi_sharp_4k_dsc_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d 0x342>; + qcom,dsi-phy = <0x343 0x344>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x34b>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@2 { + compatible = "qcom,dsi-display"; + label = "dsi_sharp_1080_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x34c>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@3 { + compatible = "qcom,dsi-display"; + label = "dsi_dual_sharp_1080_120hz_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d 0x342>; + qcom,dsi-phy = <0x343 0x344>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x34d>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@4 { + compatible = "qcom,dsi-display"; + label = "dsi_dual_nt35597_truly_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d 0x342>; + qcom,dsi-phy = <0x343 0x344>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x34e>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@5 { + compatible = "qcom,dsi-display"; + label = "dsi_dual_nt35597_truly_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d 0x342>; + qcom,dsi-phy = <0x343 0x344>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x34f>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@6 { + compatible = "qcom,dsi-display"; + label = "dsi_nt35597_truly_dsc_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x342>; + qcom,dsi-phy = <0x344>; + clocks = <0x350 0x18 0x350 0x1b>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x351>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@7 { + compatible = "qcom,dsi-display"; + label = "dsi_nt35597_truly_dsc_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x342>; + qcom,dsi-phy = <0x344>; + clocks = <0x350 0x18 0x350 0x1b>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x352>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@8 { + compatible = "qcom,dsi-display"; + label = "dsi_sim_vid_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,dsi-panel = <0x353>; + }; + + qcom,dsi-display@9 { + compatible = "qcom,dsi-display"; + label = "dsi_dual_sim_vid_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d 0x342>; + qcom,dsi-phy = <0x343 0x344>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,dsi-panel = <0x354>; + }; + + qcom,dsi-display@10 { + compatible = "qcom,dsi-display"; + label = "dsi_sim_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,dsi-panel = <0x355>; + }; + + qcom,dsi-display@11 { + compatible = "qcom,dsi-display"; + label = "dsi_dual_sim_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d 0x342>; + qcom,dsi-phy = <0x343 0x344>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,dsi-panel = <0x356>; + }; + + qcom,dsi-display@12 { + compatible = "qcom,dsi-display"; + label = "dsi_sim_dsc_375_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,dsi-panel = <0x357>; + }; + + qcom,dsi-display@13 { + compatible = "qcom,dsi-display"; + label = "dsi_dual_sim_dsc_375_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d 0x342>; + qcom,dsi-phy = <0x343 0x344>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,dsi-panel = <0x358>; + }; + + qcom,dsi-display@14 { + compatible = "qcom,dsi-display"; + label = "dsi_dual_nt35597_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d 0x342>; + qcom,dsi-phy = <0x343 0x344>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x359>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@15 { + compatible = "qcom,dsi-display"; + label = "dsi_dual_nt35597_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d 0x342>; + qcom,dsi-phy = <0x343 0x344>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x35a>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@16 { + compatible = "qcom,dsi-display"; + label = "dsi_jdi_fhd_r63452_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x35b>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + vddts-supply = <0x35c>; + }; + + qcom,dsi-display@17 { + compatible = "qcom,dsi-display"; + label = "dsi_ss_ea8074_fhd_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x35d>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + oled-vdda-supply = <0x35e>; + vci-supply = <0x35f>; + }; + + qcom,dsi-display@18 { + compatible = "qcom,dsi-display"; + label = "dsi_jdi_fhd_nt35596s_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,panel-mode-gpio = <0x3c 0x34 0x00>; + qcom,dsi-panel = <0x360>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@19 { + compatible = "qcom,dsi-display"; + label = "dsi_gvo_rm69299_fhd_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,dsi-panel = <0x361>; + vddio-supply = <0x89>; + vci-supply = <0x35f>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + }; + }; + }; + }; + + qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0x00>; + label = "wb_display"; + phandle = <0x2c>; + }; + + qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + phandle = <0x37>; + + qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + phandle = <0x321>; + }; + }; + + qcom,mdss_dsi_jdi_fhd_r63452_cmd { + qcom,mdss-dsi-panel-name = "jdi fhd cmd incell dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "JDI FHD R63452 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0x00>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = <0xe3503600 0xa9a33a50 0x3d030400>; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-bl-min-level = <0x01>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-brightness-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x01 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x40>; + qcom,mdss-pan-physical-height-dimension = <0x72>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-panel-on-dimming-delay = <0x78>; + qcom,mdss-night-brightness = <0x07 0x19 0x2b 0x3d>; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + phandle = <0x35b>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x780>; + qcom,mdss-dsi-h-front-porch = <0x78>; + qcom,mdss-dsi-h-back-porch = <0x28>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x04>; + qcom,mdss-dsi-v-front-porch = <0x04>; + qcom,mdss-dsi-v-pulse-width = <0x02>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = <0x29000000 0x2b0 0x290000 0x02 0xd6012900 0x00 0xeec64dc 0xec3b5200 0xb0b1315 0x680bb529 0x00 0x2b003 0x39000000 0x235 0x390000 0x02 0x36003900 0x00 0x23a7739 0x00 0x52a00 0x43739 0x00 0x52b00 0x77f39 0x00 0x34400 0x390000 0x02 0x51ff3900 0x00 0x2532439 0x00 0x25500 0x39000000 0x25e 0x390000 0x02 0x84000501 0x1400 0x2290005 0x1000050 0x21100 0x29000000 0x2b0 0x4390000 0x02 0x84002900 0x00 0x2c81129 0x1000000 0x2b003>; + qcom,mdss-dsi-off-command = [29 00 00 00 00 00 02 b0 00 29 00 00 00 00 00 02 d6 01 29 00 00 00 00 00 0e ec 64 dc ec 3b 52 00 0b 0b 13 15 68 0b 95 29 00 00 00 00 00 02 b0 03 05 01 00 00 02 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-phy-timings = <0x1a0406 0xa0a0506 0x5030400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_ss_fhd_ea8074_cmd { + qcom,mdss-dsi-panel-name = "ss fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "SS FHD EA8074 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0x00>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,mdss-dsi-bl-min-level = <0x01>; + qcom,mdss-dsi-bl-max-level = <0x3ff>; + qcom,mdss-brightness-max-level = <0x3ff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0x01 0x01 0x00 0x01 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x89>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-on-command-tuning; + qcom,dispparam-enabled; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + phandle = <0x35d>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x870>; + qcom,mdss-dsi-h-front-porch = <0x30>; + qcom,mdss-dsi-h-back-porch = <0x30>; + qcom,mdss-dsi-h-pulse-width = <0x10>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x1c>; + qcom,mdss-dsi-v-front-porch = <0x14>; + qcom,mdss-dsi-v-pulse-width = <0x0c>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = [05 01 00 00 0a 00 02 11 00 39 00 00 00 00 00 05 2b 00 00 08 6f 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 b0 04 39 00 00 00 00 00 02 b2 00 39 00 00 00 00 00 02 f7 03 39 00 00 00 00 00 03 f0 a5 a5 39 00 00 00 00 00 02 35 00 39 00 00 00 00 00 03 51 00 00 39 00 00 00 00 00 02 53 25 39 01 00 00 6e 00 02 55 00 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-hbm-command = [39 01 00 00 00 00 03 51 00 01 39 01 00 00 01 00 02 53 22]; + qcom,mdss-dsi-doze-lbm-command = [39 01 00 00 00 00 03 51 00 01 39 01 00 00 01 00 02 53 23]; + qcom,mdss-dsi-nolp-command = [39 01 00 00 00 00 02 53 25]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01]; + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02]; + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03]; + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 25]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 e0]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-phy-timings = <0x200808 0x24230808 0x5030400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_ss_notch_fhd_ea8074_cmd { + qcom,mdss-dsi-panel-name = "ss notch fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "SS NOTCH FHD EA8074 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0x00>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <0x3ff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0x01 0x01 0x00 0x01 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x8e>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <0x78>; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x34>; + phandle = <0x364>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x8c8>; + qcom,mdss-dsi-h-front-porch = <0x38>; + qcom,mdss-dsi-h-back-porch = <0x38>; + qcom,mdss-dsi-h-pulse-width = <0x12>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x18>; + qcom,mdss-dsi-v-front-porch = <0x1a>; + qcom,mdss-dsi-v-pulse-width = <0x0c>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = <0x5010000 0xa000211 0x390000 0x05 0x2b000008 0xc7390000 0x03 0xf05a5a39 0x00 0x8eff0 0x31003331 0x14353900 0x00 0x2b00139 0x00 0x2bb03 0x39000000 0x2b0 0x4f390000 0x02 0xcb003900 0x00 0x2b06b39 0x00 0x2cb00 0x39000000 0x2f7 0x3390000 0x02 0xb0053900 0x00 0x2b11039 0x00 0x2b002 0x39000000 0x5d5 0x2175414 0x39010000 0x3f0 0xa5a53900 0x00 0x2350039 0x00 0x35100 0x390000 0x02 0x53203901 0x6e00 0x2550005 0x1000000 0x22900>; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-hbm-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 ef b0 39 00 00 00 00 00 02 b0 17 39 00 00 00 00 00 04 e3 00 00 00 39 01 00 00 01 00 02 53 22 39 01 00 00 00 00 03 f0 a5 a5]; + qcom,mdss-dsi-doze-lbm-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 ef b0 39 00 00 00 00 00 02 b0 17 39 00 00 00 00 00 04 e3 00 00 00 39 01 00 00 01 00 02 53 23 39 01 00 00 00 00 03 f0 a5 a5]; + qcom,mdss-dsi-nolp-command = [05 01 00 00 00 00 02 28 00 39 00 00 00 00 00 03 51 00 00 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 b0 17 39 00 00 00 00 00 04 e3 86 80 01 39 00 00 00 00 00 02 53 20 39 01 00 00 00 00 03 f0 a5 a5 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01]; + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02]; + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03]; + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 e8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [39 00 00 00 00 00 02 53 20 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 b2 00 40 39 00 00 00 00 00 02 b0 04 39 00 00 00 00 00 02 b2 80 39 00 00 00 00 00 02 f7 03 39 01 00 00 00 00 03 f0 a5 a5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [39 01 00 00 00 00 02 53 20 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 b2 00 10 39 00 00 00 00 00 02 b0 04 39 00 00 00 00 00 02 b2 00 39 00 00 00 00 00 02 f7 03 39 00 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 02 53 e0]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-fod2norm-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 b2 00 40 39 00 00 00 00 00 02 b0 04 39 00 00 00 00 00 02 b2 80 39 00 00 00 00 00 02 f7 03 39 01 00 00 00 00 03 f0 a5 a5]; + qcom,mdss-dsi-dispparam-hbm-fod2norm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-jitter = <0x01 0x01>; + qcom,mdss-dsi-read-panel-id-command = [06 01 00 01 05 00 02 db 00]; + qcom,mdss-dsi-read-panel-id-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-phy-timings = <0x220809 0x25230909 0x6030400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_jdi_fhd_nt35596s_video { + qcom,mdss-dsi-panel-name = "jdi fhd video dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "JDI FHD NT35596S VIDEO PANEL"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0x00>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-min-level = <0x01>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-brightness-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x00 0x0f 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x88>; + qcom,cont-splash-enabled; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-panel-on-dimming-delay = <0x78>; + qcom,esd-err-irq-gpio = <0x3c 0x34 0x2001>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,dsi-supported-dfps-list = <0x3c 0x37>; + qcom,dispccbb-enabled; + qcom,dispblnotify-enabled; + qcom,dispparam-enabled; + qcom,disp-paneloff-disablecabc-enabled; + qcom,mdss-night-brightness = <0x07 0x19 0x2b 0x3d>; + qcom,disp-panel-offon-mode-enabled; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-panel-xy-coordinate = <0x0f 0x18>; + qcom,mdss-dsi-panel-max-luminance = <0x0f 0x20>; + qcom,mdss-dsi-panel-max-luminance-valid = <0x01 0x01>; + qcom,mdss-dsi-panel-bl-info = <0x198 0x1f4 0x17c 0x26c>; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x34>; + phandle = <0x360>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x870>; + qcom,mdss-dsi-h-front-porch = <0x10>; + qcom,mdss-dsi-h-back-porch = <0x28>; + qcom,mdss-dsi-h-pulse-width = <0x1c>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x18>; + qcom,mdss-dsi-v-front-porch = <0x07>; + qcom,mdss-dsi-v-pulse-width = <0x04>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 24 15 00 00 00 00 00 02 9d 34 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 c4 25 15 00 00 00 00 00 02 d1 08 15 00 00 00 00 00 02 d2 84 15 01 00 00 00 00 02 ff 26 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 03 1c 15 00 00 00 00 00 02 3b 08 15 00 00 00 00 00 02 6b 08 15 00 00 00 00 00 02 97 08 15 00 00 00 00 00 02 c5 08 15 00 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ff 23 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 01 84 15 00 00 00 00 00 02 05 2d 15 00 00 00 00 00 02 06 00 15 00 00 00 00 00 02 32 00 15 00 00 00 00 00 02 13 ff 15 00 00 00 00 00 02 14 f8 15 00 00 00 00 00 02 15 ed 15 00 00 00 00 00 02 16 e5 15 00 00 00 00 00 02 09 01 15 00 00 00 00 00 02 0a 01 15 00 00 00 00 00 02 0b 01 15 00 00 00 00 00 02 0c 01 15 00 00 00 00 00 02 0d 01 15 00 00 00 00 00 02 0e 01 15 00 00 00 00 00 02 0f 01 15 00 00 00 00 00 02 10 01 15 00 00 00 00 00 02 11 01 15 00 00 00 00 00 02 12 01 15 00 00 00 00 00 02 17 ff 15 00 00 00 00 00 02 18 ee 15 00 00 00 00 00 02 19 dd 15 00 00 00 00 00 02 1a c7 15 00 00 00 00 00 02 1b af 15 00 00 00 00 00 02 1c 99 15 00 00 00 00 00 02 1d 99 15 00 00 00 00 00 02 1e 88 15 00 00 00 00 00 02 1f 77 15 00 00 00 00 00 02 20 66 15 00 00 00 00 00 02 33 00 15 00 00 00 00 00 02 21 ff 15 00 00 00 00 00 02 22 f8 15 00 00 00 00 00 02 23 ef 15 00 00 00 00 00 02 24 e7 15 00 00 00 00 00 02 25 de 15 00 00 00 00 00 02 26 d7 15 00 00 00 00 00 02 27 cd 15 00 00 00 00 00 02 28 c4 15 00 00 00 00 00 02 29 bc 15 00 00 00 00 00 02 2a b3 15 01 00 00 00 00 02 ff 22 15 00 00 00 00 00 02 00 0a 15 00 00 00 00 00 02 01 43 15 00 00 00 00 00 02 02 5b 15 00 00 00 00 00 02 03 6a 15 00 00 00 00 00 02 04 7a 15 00 00 00 00 00 02 05 82 15 00 00 00 00 00 02 06 85 15 00 00 00 00 00 02 07 80 15 00 00 00 00 00 02 08 7c 15 00 00 00 00 00 02 09 7c 15 00 00 00 00 00 02 0a 74 15 00 00 00 00 00 02 0b 71 15 00 00 00 00 00 02 0c 6e 15 00 00 00 00 00 02 0d 68 15 00 00 00 00 00 02 0e 65 15 01 00 00 00 00 02 0f 5c 15 00 00 00 00 00 02 10 32 15 00 00 00 00 00 02 11 18 15 00 00 00 00 00 02 12 00 15 00 00 00 00 00 02 13 00 15 00 00 00 00 00 02 1a 00 15 00 00 00 00 00 02 1b 00 15 00 00 00 00 00 02 1c 00 15 00 00 00 00 00 02 1d 00 15 00 00 00 00 00 02 1e 00 15 00 00 00 00 00 02 1f 00 15 00 00 00 00 00 02 20 00 15 00 00 00 00 00 02 21 00 15 00 00 00 00 00 02 22 00 15 00 00 00 00 00 02 23 00 15 00 00 00 00 00 02 24 00 15 01 00 00 00 00 02 25 00 15 00 00 00 00 00 02 26 00 15 00 00 00 00 00 02 27 00 15 00 00 00 00 00 02 28 00 15 00 00 00 00 00 02 29 00 15 00 00 00 00 00 02 2a 00 15 00 00 00 00 00 02 2b 00 15 00 00 00 00 00 02 2f 00 15 00 00 00 00 00 02 30 00 15 00 00 00 00 00 02 31 00 15 00 00 00 00 00 02 32 0c 15 00 00 00 00 00 02 33 0c 15 00 00 00 00 00 02 34 0c 15 00 00 00 00 00 02 35 0b 15 00 00 00 00 00 02 36 09 15 00 00 00 00 00 02 37 09 15 01 00 00 00 00 02 38 08 15 00 00 00 00 00 02 39 05 15 00 00 00 00 00 02 3a 03 15 00 00 00 00 00 02 3b 00 15 00 00 00 00 00 02 3f 00 15 00 00 00 00 00 02 40 00 15 00 00 00 00 00 02 41 00 15 00 00 00 00 00 02 42 00 15 00 00 00 00 00 02 43 00 15 00 00 00 00 00 02 44 00 15 00 00 00 00 00 02 45 00 15 00 00 00 00 00 02 46 00 15 00 00 00 00 00 02 47 00 15 00 00 00 00 00 02 48 00 15 00 00 00 00 00 02 49 03 15 00 00 00 00 00 02 4a 06 15 01 00 00 00 00 02 4b 07 15 00 00 00 00 00 02 4c 07 15 00 00 00 00 00 02 4d 00 15 00 00 00 00 00 02 4e 00 15 00 00 00 00 00 02 4f 00 15 00 00 00 00 00 02 50 00 15 00 00 00 00 00 02 51 00 15 00 00 00 00 00 02 52 00 15 00 00 00 00 00 02 53 01 15 00 00 00 00 00 02 54 01 15 00 00 00 00 00 02 55 89 15 00 00 00 00 00 02 56 00 15 00 00 00 00 00 02 58 00 15 00 00 00 00 00 02 68 00 15 00 00 00 00 00 02 84 ff 15 00 00 00 00 00 02 85 ff 15 01 00 00 00 00 02 86 03 15 00 00 00 00 00 02 87 00 15 00 00 00 00 00 02 88 00 15 00 00 00 00 00 02 a2 20 15 00 00 00 00 00 02 a9 01 15 00 00 00 00 00 02 aa 12 15 00 00 00 00 00 02 ab 13 15 00 00 00 00 00 02 ac 0a 15 00 00 00 00 00 02 ad 74 15 00 00 00 00 00 02 af 33 15 00 00 00 00 00 02 b0 03 15 00 00 00 00 00 02 b1 14 15 00 00 00 00 00 02 b2 42 15 00 00 00 00 00 02 b3 40 15 00 00 00 00 00 02 b4 a5 15 01 00 00 00 00 02 b6 44 15 00 00 00 00 00 02 b7 04 15 00 00 00 00 00 02 b8 14 15 00 00 00 00 00 02 b9 42 15 00 00 00 00 00 02 ba 40 15 00 00 00 00 00 02 bb a5 15 00 00 00 00 00 02 bd 44 15 00 00 00 00 00 02 be 04 15 00 00 00 00 00 02 bf 00 15 00 00 00 00 00 02 c0 75 15 00 00 00 00 00 02 c1 6a 15 00 00 00 00 00 02 c2 a5 15 00 00 00 00 00 02 c4 22 15 00 00 00 00 00 02 c5 02 15 00 00 00 00 00 02 c6 00 15 01 00 00 00 00 02 c7 95 15 00 00 00 00 00 02 c8 8a 15 00 00 00 00 00 02 c9 a5 15 00 00 00 00 00 02 cb 22 15 00 00 00 00 00 02 cc 02 15 00 00 00 00 00 02 cd 00 15 00 00 00 00 00 02 ce b5 15 00 00 00 00 00 02 cf aa 15 00 00 00 00 00 02 d0 a5 15 00 00 00 00 00 02 d2 22 15 00 00 00 00 00 02 d3 02 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 26 02 15 00 00 00 00 00 02 35 00 15 00 00 00 00 00 02 51 ff 15 00 00 00 00 00 02 53 24 15 00 00 00 00 00 02 55 00 15 01 00 00 00 00 02 b0 00 05 01 00 00 50 00 02 11 00 05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 46 00 02 10 00]; + qcom,mdss-dsi-displayoff-command = [05 01 00 00 20 00 02 28 00]; + qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x01>; + qcom,mdss-dsi-dispparam-cabcuion-command = [15 01 00 00 00 00 02 55 01]; + qcom,mdss-dsi-dispparam-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcstillon-command = [15 00 00 00 00 00 02 55 02]; + qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcmovieon-command = [15 01 00 00 00 00 02 55 03]; + qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcoff-command = [39 01 00 00 01 00 02 55 00]; + qcom,mdss-dsi-dispparam-skince-cabcuion-command = [15 01 00 00 00 00 02 55 81]; + qcom,mdss-dsi-dispparam-skince-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcstillon-command = [15 00 00 00 00 00 02 55 82]; + qcom,mdss-dsi-dispparam-skince-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcmovieon-command = [15 01 00 00 00 00 02 55 83]; + qcom,mdss-dsi-dispparam-skince-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcoff-command = [15 01 00 00 00 00 02 55 80]; + qcom,mdss-dsi-dispparam-skince-cabcoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-idleon-command = [39 01 00 00 01 00 02 39 00]; + qcom,mdss-dsi-dispparam-idleoff-command = [39 01 00 00 01 00 02 38 00]; + qcom,mdss-dsi-dispparam-papermode2-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 01 15 01 00 00 00 00 02 ff 20 15 00 00 00 00 00 02 75 00 15 00 00 00 00 00 02 76 00 15 00 00 00 00 00 02 77 00 15 00 00 00 00 00 02 78 27 15 00 00 00 00 00 02 79 00 15 00 00 00 00 00 02 7a 67 15 00 00 00 00 00 02 7b 00 15 00 00 00 00 00 02 7c 94 15 00 00 00 00 00 02 7d 00 15 00 00 00 00 00 02 7e b8 15 00 00 00 00 00 02 7f 00 15 00 00 00 00 00 02 80 d4 15 00 00 00 00 00 02 81 00 15 00 00 00 00 00 02 82 ea 15 00 00 00 00 00 02 83 00 15 00 00 00 00 00 02 84 fc 15 00 00 00 00 00 02 85 01 15 00 00 00 00 00 02 86 0f 15 00 00 00 00 00 02 87 01 15 00 00 00 00 00 02 88 46 15 00 00 00 00 00 02 89 01 15 00 00 00 00 00 02 8a 70 15 00 00 00 00 00 02 8b 01 15 00 00 00 00 00 02 8c ad 15 00 00 00 00 00 02 8d 01 15 00 00 00 00 00 02 8e da 15 00 00 00 00 00 02 8f 02 15 00 00 00 00 00 02 90 1d 15 00 00 00 00 00 02 91 02 15 00 00 00 00 00 02 92 50 15 00 00 00 00 00 02 93 02 15 00 00 00 00 00 02 94 52 15 00 00 00 00 00 02 95 02 15 00 00 00 00 00 02 96 83 15 00 00 00 00 00 02 97 02 15 00 00 00 00 00 02 98 ba 15 00 00 00 00 00 02 99 02 15 00 00 00 00 00 02 9a de 15 00 00 00 00 00 02 9b 03 15 00 00 00 00 00 02 9c 12 15 00 00 00 00 00 02 9d 03 15 00 00 00 00 00 02 9e 2e 15 00 00 00 00 00 02 9f 03 15 00 00 00 00 00 02 a0 54 15 00 00 00 00 00 02 a2 03 15 00 00 00 00 00 02 a3 61 15 00 00 00 00 00 02 a4 03 15 00 00 00 00 00 02 a5 6f 15 00 00 00 00 00 02 a6 03 15 00 00 00 00 00 02 a7 7e 15 00 00 00 00 00 02 a9 03 15 00 00 00 00 00 02 aa 90 15 00 00 00 00 00 02 ab 03 15 00 00 00 00 00 02 ac a7 15 00 00 00 00 00 02 ad 03 15 00 00 00 00 00 02 ae c2 15 00 00 00 00 00 02 af 03 15 00 00 00 00 00 02 b0 d5 15 00 00 00 00 00 02 b1 03 15 01 00 00 00 00 02 b2 d8 15 00 00 00 00 00 02 b3 00 15 00 00 00 00 00 02 b4 00 15 00 00 00 00 00 02 b5 00 15 00 00 00 00 00 02 b6 27 15 00 00 00 00 00 02 b7 00 15 00 00 00 00 00 02 b8 67 15 00 00 00 00 00 02 b9 00 15 00 00 00 00 00 02 ba 94 15 00 00 00 00 00 02 bb 00 15 00 00 00 00 00 02 bc b8 15 00 00 00 00 00 02 bd 00 15 00 00 00 00 00 02 be d4 15 00 00 00 00 00 02 bf 00 15 00 00 00 00 00 02 c0 ea 15 00 00 00 00 00 02 c1 00 15 00 00 00 00 00 02 c2 fc 15 00 00 00 00 00 02 c3 01 15 00 00 00 00 00 02 c4 0f 15 00 00 00 00 00 02 c5 01 15 00 00 00 00 00 02 c6 46 15 00 00 00 00 00 02 c7 01 15 00 00 00 00 00 02 c8 70 15 00 00 00 00 00 02 c9 01 15 00 00 00 00 00 02 ca ad 15 00 00 00 00 00 02 cb 01 15 00 00 00 00 00 02 cc da 15 00 00 00 00 00 02 cd 02 15 00 00 00 00 00 02 ce 1d 15 00 00 00 00 00 02 cf 02 15 00 00 00 00 00 02 d0 50 15 00 00 00 00 00 02 d1 02 15 00 00 00 00 00 02 d2 52 15 00 00 00 00 00 02 d3 02 15 00 00 00 00 00 02 d4 83 15 00 00 00 00 00 02 d5 02 15 00 00 00 00 00 02 d6 ba 15 00 00 00 00 00 02 d7 02 15 00 00 00 00 00 02 d8 de 15 00 00 00 00 00 02 d9 03 15 00 00 00 00 00 02 da 12 15 00 00 00 00 00 02 db 03 15 00 00 00 00 00 02 dc 2e 15 00 00 00 00 00 02 dd 03 15 00 00 00 00 00 02 de 54 15 00 00 00 00 00 02 df 03 15 00 00 00 00 00 02 e0 61 15 00 00 00 00 00 02 e1 03 15 00 00 00 00 00 02 e2 6f 15 00 00 00 00 00 02 e3 03 15 00 00 00 00 00 02 e4 7e 15 00 00 00 00 00 02 e5 03 15 00 00 00 00 00 02 e6 90 15 00 00 00 00 00 02 e7 03 15 00 00 00 00 00 02 e8 a7 15 00 00 00 00 00 02 e9 03 15 00 00 00 00 00 02 ea c2 15 00 00 00 00 00 02 eb 03 15 00 00 00 00 00 02 ec d5 15 00 00 00 00 00 02 ed 03 15 00 00 00 00 00 02 ee d8 15 00 00 00 00 00 02 ef 00 15 00 00 00 00 00 02 f0 bc 15 00 00 00 00 00 02 f1 00 15 00 00 00 00 00 02 f2 cb 15 00 00 00 00 00 02 f3 00 15 00 00 00 00 00 02 f4 e4 15 00 00 00 00 00 02 f5 00 15 00 00 00 00 00 02 f6 f9 15 00 00 00 00 00 02 f7 01 15 00 00 00 00 00 02 f8 0b 15 00 00 00 00 00 02 f9 01 15 00 00 00 00 00 02 fa 1b 15 01 00 00 00 00 02 ff 21 15 00 00 00 00 00 02 00 01 15 00 00 00 00 00 02 01 2a 15 00 00 00 00 00 02 02 01 15 00 00 00 00 00 02 03 38 15 00 00 00 00 00 02 04 01 15 00 00 00 00 00 02 05 44 15 00 00 00 00 00 02 06 01 15 00 00 00 00 00 02 07 6e 15 00 00 00 00 00 02 08 01 15 00 00 00 00 00 02 09 8f 15 00 00 00 00 00 02 0a 01 15 00 00 00 00 00 02 0b c2 15 00 00 00 00 00 02 0c 01 15 00 00 00 00 00 02 0d e9 15 00 00 00 00 00 02 0e 02 15 00 00 00 00 00 02 0f 27 15 00 00 00 00 00 02 10 02 15 00 00 00 00 00 02 11 56 15 00 00 00 00 00 02 12 02 15 00 00 00 00 00 02 13 58 15 00 00 00 00 00 02 14 02 15 00 00 00 00 00 02 15 87 15 00 00 00 00 00 02 16 02 15 00 00 00 00 00 02 17 bd 15 00 00 00 00 00 02 18 02 15 00 00 00 00 00 02 19 e2 15 00 00 00 00 00 02 1a 03 15 00 00 00 00 00 02 1b 14 15 00 00 00 00 00 02 1c 03 15 00 00 00 00 00 02 1d 30 15 00 00 00 00 00 02 1e 03 15 00 00 00 00 00 02 1f 58 15 00 00 00 00 00 02 20 03 15 00 00 00 00 00 02 21 64 15 00 00 00 00 00 02 22 03 15 00 00 00 00 00 02 23 72 15 00 00 00 00 00 02 24 03 15 00 00 00 00 00 02 25 81 15 00 00 00 00 00 02 26 03 15 00 00 00 00 00 02 27 95 15 00 00 00 00 00 02 28 03 15 00 00 00 00 00 02 29 ad 15 00 00 00 00 00 02 2a 03 15 00 00 00 00 00 02 2b c6 15 00 00 00 00 00 02 2d 03 15 00 00 00 00 00 02 2f d6 15 00 00 00 00 00 02 30 03 15 01 00 00 00 00 02 31 d8 15 00 00 00 00 00 02 32 00 15 00 00 00 00 00 02 33 bc 15 00 00 00 00 00 02 34 00 15 00 00 00 00 00 02 35 cb 15 00 00 00 00 00 02 36 00 15 00 00 00 00 00 02 37 e4 15 00 00 00 00 00 02 38 00 15 00 00 00 00 00 02 39 f9 15 00 00 00 00 00 02 3a 01 15 00 00 00 00 00 02 3b 0b 15 00 00 00 00 00 02 3d 01 15 00 00 00 00 00 02 3f 1b 15 00 00 00 00 00 02 40 01 15 00 00 00 00 00 02 41 2a 15 00 00 00 00 00 02 42 01 15 00 00 00 00 00 02 43 38 15 00 00 00 00 00 02 44 01 15 00 00 00 00 00 02 45 44 15 00 00 00 00 00 02 46 01 15 00 00 00 00 00 02 47 6e 15 00 00 00 00 00 02 48 01 15 00 00 00 00 00 02 49 8f 15 00 00 00 00 00 02 4a 01 15 00 00 00 00 00 02 4b c2 15 00 00 00 00 00 02 4c 01 15 00 00 00 00 00 02 4d e9 15 00 00 00 00 00 02 4e 02 15 00 00 00 00 00 02 4f 27 15 00 00 00 00 00 02 50 02 15 00 00 00 00 00 02 51 56 15 00 00 00 00 00 02 52 02 15 00 00 00 00 00 02 53 58 15 00 00 00 00 00 02 54 02 15 00 00 00 00 00 02 55 87 15 00 00 00 00 00 02 56 02 15 00 00 00 00 00 02 58 bd 15 00 00 00 00 00 02 59 02 15 00 00 00 00 00 02 5a e2 15 00 00 00 00 00 02 5b 03 15 00 00 00 00 00 02 5c 14 15 00 00 00 00 00 02 5d 03 15 00 00 00 00 00 02 5e 30 15 00 00 00 00 00 02 5f 03 15 00 00 00 00 00 02 60 58 15 00 00 00 00 00 02 61 03 15 00 00 00 00 00 02 62 64 15 00 00 00 00 00 02 63 03 15 00 00 00 00 00 02 64 72 15 00 00 00 00 00 02 65 03 15 00 00 00 00 00 02 66 81 15 00 00 00 00 00 02 67 03 15 00 00 00 00 00 02 68 95 15 00 00 00 00 00 02 69 03 15 01 00 00 00 00 02 6a ad 15 00 00 00 00 00 02 6b 03 15 00 00 00 00 00 02 6c c6 15 00 00 00 00 00 02 6d 03 15 00 00 00 00 00 02 6e d6 15 00 00 00 00 00 02 6f 03 15 00 00 00 00 00 02 70 d8 15 00 00 00 00 00 02 71 01 15 00 00 00 00 00 02 72 7d 15 00 00 00 00 00 02 73 01 15 00 00 00 00 00 02 74 81 15 00 00 00 00 00 02 75 01 15 00 00 00 00 00 02 76 88 15 00 00 00 00 00 02 77 01 15 00 00 00 00 00 02 78 8f 15 00 00 00 00 00 02 79 01 15 00 00 00 00 00 02 7a 96 15 00 00 00 00 00 02 7b 01 15 00 00 00 00 00 02 7c 9d 15 00 00 00 00 00 02 7d 01 15 00 00 00 00 00 02 7e a3 15 00 00 00 00 00 02 7f 01 15 00 00 00 00 00 02 80 a8 15 00 00 00 00 00 02 81 01 15 00 00 00 00 00 02 82 ae 15 00 00 00 00 00 02 83 01 15 00 00 00 00 00 02 84 c3 15 00 00 00 00 00 02 85 01 15 00 00 00 00 00 02 86 d6 15 00 00 00 00 00 02 87 01 15 00 00 00 00 00 02 88 f5 15 00 00 00 00 00 02 89 02 15 00 00 00 00 00 02 8a 12 15 00 00 00 00 00 02 8b 02 15 00 00 00 00 00 02 8c 42 15 00 00 00 00 00 02 8d 02 15 00 00 00 00 00 02 8e 6b 15 00 00 00 00 00 02 8f 02 15 00 00 00 00 00 02 90 6c 15 00 00 00 00 00 02 91 02 15 00 00 00 00 00 02 92 98 15 00 00 00 00 00 02 93 02 15 00 00 00 00 00 02 94 cd 15 00 00 00 00 00 02 95 02 15 00 00 00 00 00 02 96 f2 15 00 00 00 00 00 02 97 03 15 00 00 00 00 00 02 98 20 15 00 00 00 00 00 02 99 03 15 00 00 00 00 00 02 9a 3c 15 00 00 00 00 00 02 9b 03 15 00 00 00 00 00 02 9c 61 15 00 00 00 00 00 02 9d 03 15 00 00 00 00 00 02 9e 6b 15 00 00 00 00 00 02 9f 03 15 00 00 00 00 00 02 a0 77 15 00 00 00 00 00 02 a2 03 15 00 00 00 00 00 02 a3 85 15 00 00 00 00 00 02 a4 03 15 00 00 00 00 00 02 a5 95 15 00 00 00 00 00 02 a6 03 15 00 00 00 00 00 02 a7 9f 15 00 00 00 00 00 02 a9 03 15 00 00 00 00 00 02 aa bf 15 00 00 00 00 00 02 ab 03 15 00 00 00 00 00 02 ac d6 15 00 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae d8 15 00 00 00 00 00 02 af 01 15 00 00 00 00 00 02 b0 7d 15 00 00 00 00 00 02 b1 01 15 00 00 00 00 00 02 b2 81 15 00 00 00 00 00 02 b3 01 15 00 00 00 00 00 02 b4 88 15 00 00 00 00 00 02 b5 01 15 00 00 00 00 00 02 b6 8f 15 00 00 00 00 00 02 b7 01 15 00 00 00 00 00 02 b8 96 15 00 00 00 00 00 02 b9 01 15 00 00 00 00 00 02 ba 9d 15 00 00 00 00 00 02 bb 01 15 00 00 00 00 00 02 bc a3 15 00 00 00 00 00 02 bd 01 15 00 00 00 00 00 02 be a8 15 00 00 00 00 00 02 bf 01 15 00 00 00 00 00 02 c0 ae 15 00 00 00 00 00 02 c1 01 15 00 00 00 00 00 02 c2 c3 15 00 00 00 00 00 02 c3 01 15 00 00 00 00 00 02 c4 d6 15 00 00 00 00 00 02 c5 01 15 00 00 00 00 00 02 c6 f5 15 00 00 00 00 00 02 c7 02 15 00 00 00 00 00 02 c8 12 15 00 00 00 00 00 02 c9 02 15 00 00 00 00 00 02 ca 42 15 00 00 00 00 00 02 cb 02 15 00 00 00 00 00 02 cc 6b 15 00 00 00 00 00 02 cd 02 15 00 00 00 00 00 02 ce 6c 15 00 00 00 00 00 02 cf 02 15 00 00 00 00 00 02 d0 98 15 00 00 00 00 00 02 d1 02 15 00 00 00 00 00 02 d2 cd 15 00 00 00 00 00 02 d3 02 15 00 00 00 00 00 02 d4 f2 15 00 00 00 00 00 02 d5 03 15 00 00 00 00 00 02 d6 20 15 00 00 00 00 00 02 d7 03 15 00 00 00 00 00 02 d8 3c 15 00 00 00 00 00 02 d9 03 15 00 00 00 00 00 02 da 61 15 00 00 00 00 00 02 db 03 15 00 00 00 00 00 02 dc 6b 15 00 00 00 00 00 02 dd 03 15 00 00 00 00 00 02 de 77 15 00 00 00 00 00 02 df 03 15 00 00 00 00 00 02 e0 85 15 00 00 00 00 00 02 e1 03 15 00 00 00 00 00 02 e2 95 15 00 00 00 00 00 02 e3 03 15 00 00 00 00 00 02 e4 9f 15 00 00 00 00 00 02 e5 03 15 00 00 00 00 00 02 e6 bf 15 00 00 00 00 00 02 e7 03 15 00 00 00 00 00 02 e8 d6 15 00 00 00 00 00 02 e9 03 15 00 00 00 00 00 02 ea d8 15 01 00 00 00 00 02 ff 10]; + qcom,mdss-dsi-dispparam-papermode2-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-default-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 02]; + qcom,mdss-dsi-dispparam-default-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-normal1-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 01]; + qcom,mdss-dsi-dispparam-normal1-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-normal2-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 02]; + qcom,mdss-dsi-dispparam-normal2-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-read-brightness-command = [06 01 00 01 05 00 02 52 00]; + qcom,mdss-dsi-read-brightness-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-xy-coordinate-command = [06 01 00 01 05 00 02 a1 00]; + qcom,mdss-dsi-dispparam-xy-coordinate-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-max-luminance-command = [06 01 00 01 05 00 02 a1 00]; + qcom,mdss-dsi-dispparam-max-luminance-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-max-luminance-valid-command = [06 01 00 01 05 00 02 db 00]; + qcom,mdss-dsi-dispparam-max-luminance-valid-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-phy-timings = <0x220808 0x24240808 0x5030400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_gvo_fhd_rm69299_cmd { + qcom,mdss-dsi-panel-name = "gvo fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "GVO FHD RM69299 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0x00>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <0x3ff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0x01 0x01 0x00 0x01 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x89>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-on-command-tuning; + qcom,dispparam-enabled; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x34>; + phandle = <0x361>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x8c8>; + qcom,mdss-dsi-h-front-porch = <0x38>; + qcom,mdss-dsi-h-back-porch = <0x38>; + qcom,mdss-dsi-h-pulse-width = <0x12>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x18>; + qcom,mdss-dsi-v-front-porch = <0x1a>; + qcom,mdss-dsi-v-pulse-width = <0x0c>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = [15 01 00 00 0a 00 02 fe 00 39 00 00 00 00 00 03 51 00 00 39 00 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-hbm-command = [39 01 00 00 00 00 03 51 00 01 39 01 00 00 01 00 02 53 22]; + qcom,mdss-dsi-doze-lbm-command = [39 01 00 00 00 00 03 51 00 01 39 01 00 00 01 00 02 53 23]; + qcom,mdss-dsi-nolp-command = [39 01 00 00 00 00 02 53 20]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01]; + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02]; + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03]; + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 20]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 e0]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-phy-timings = <0x220809 0x25230909 0x6030400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_tianma_fhd_rm69299_cmd { + qcom,mdss-dsi-panel-name = "tianma fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "TIANMA FHD RM69299 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0x00>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <0x3ff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0x01 0x01 0x00 0x01 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x89>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,dispparam-enabled; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x34>; + phandle = <0x369>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x8c8>; + qcom,mdss-dsi-h-front-porch = <0x38>; + qcom,mdss-dsi-h-back-porch = <0x38>; + qcom,mdss-dsi-h-pulse-width = <0x12>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x18>; + qcom,mdss-dsi-v-front-porch = <0x1a>; + qcom,mdss-dsi-v-pulse-width = <0x0c>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = [39 00 00 00 00 00 03 51 00 00 39 00 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-phy-timings = <0x220809 0x25230909 0x6030400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_tianma_fhd_nt36672a_video { + qcom,mdss-dsi-panel-name = "tianma fhd video dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "TIANMA FHD NT36672A VIDEO PANEL"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0x00>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-min-level = <0x01>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-brightness-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x00 0x0a 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x88>; + qcom,cont-splash-enabled; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,esd-err-irq-gpio = <0x3c 0x0a 0x2001>; + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <0x78>; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x33>; + qcom,panel-supply-entries = <0x362>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + phandle = <0x365>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x8c6>; + qcom,mdss-dsi-h-front-porch = <0x28>; + qcom,mdss-dsi-h-back-porch = <0x2c>; + qcom,mdss-dsi-h-pulse-width = <0x14>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x08>; + qcom,mdss-dsi-v-front-porch = <0x0f>; + qcom,mdss-dsi-v-pulse-width = <0x02>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x22150000 0x02 0x401500 0x00 0x201c015 0x00 0x20240 0x15000000 0x203 0x40150000 0x02 0x4401500 0x00 0x2054015 0x00 0x20640 0x15000000 0x207 0x40150000 0x02 0x8401500 0x00 0x2094015 0x00 0x20a40 0x15000000 0x20b 0x40150000 0x02 0xc401500 0x00 0x20d4015 0x00 0x20e40 0x15000000 0x20f 0x40150000 0x02 0x10401500 0x00 0x2115015 0x00 0x21260 0x15000000 0x213 0x70150000 0x02 0x14581500 0x00 0x2156815 0x00 0x21678 0x15010000 0x217 0x77150000 0x02 0x18391500 0x00 0x2192d15 0x00 0x21a2e 0x15000000 0x21b 0x32150000 0x02 0x1c371500 0x00 0x21d3a15 0x00 0x21e40 0x15000000 0x21f 0x40150000 0x02 0x20401500 0x00 0x2214015 0x00 0x22240 0x15000000 0x223 0x40150000 0x02 0x24401500 0x00 0x2254015 0x00 0x22640 0x15000000 0x227 0x40150000 0x02 0x28401500 0x00 0x22d0015 0x00 0x22f40 0x15000000 0x230 0x40150000 0x02 0x31401500 0x00 0x2324015 0x00 0x23340 0x15000000 0x234 0x40150100 0x02 0x35401500 0x00 0x2364015 0x00 0x23740 0x15000000 0x238 0x40150000 0x02 0x39401500 0x00 0x23a4015 0x00 0x23b40 0x15000000 0x23d 0x40150000 0x02 0x3f401500 0x00 0x2404015 0x00 0x24140 0x15000000 0x242 0x40150000 0x02 0x43401500 0x00 0x2444015 0x00 0x24540 0x15000000 0x246 0x40150000 0x02 0x47401500 0x00 0x2484015 0x00 0x24940 0x15000000 0x24a 0x40150000 0x02 0x4b401500 0x00 0x24c4015 0x00 0x24d40 0x15000000 0x24e 0x40150000 0x02 0x4f401501 0x00 0x2504015 0x00 0x25140 0x15000000 0x252 0x40150000 0x02 0x53011500 0x00 0x2540115 0x00 0x255fe 0x15000000 0x256 0x77150000 0x02 0x58cd1500 0x00 0x259d015 0x00 0x25ad0 0x15000000 0x25b 0x50150000 0x02 0x5c501500 0x00 0x25d5015 0x00 0x25e50 0x15000000 0x25f 0x50150000 0x02 0x60501500 0x00 0x2615015 0x00 0x26250 0x15000000 0x263 0x50150000 0x02 0x64501500 0x00 0x2655015 0x00 0x26650 0x15000000 0x267 0x50150000 0x02 0x68501500 0x00 0x2695015 0x1000000 0x26a50 0x15000000 0x26b 0x50150000 0x02 0x6c501500 0x00 0x26d5015 0x00 0x26e50 0x15000000 0x26f 0x50150000 0x02 0x70071500 0x00 0x2710015 0x00 0x27200 0x15000000 0x273 0x150000 0x02 0x74061500 0x00 0x2750c15 0x00 0x27603 0x15000000 0x277 0x9150000 0x02 0x780f1500 0x00 0x2796815 0x00 0x27a88 0x15000000 0x27c 0x80150000 0x02 0x7d801500 0x00 0x27e8015 0x00 0x27f00 0x15000000 0x280 0x150000 0x02 0x81001500 0x00 0x2830115 0x00 0x28400 0x15010000 0x285 0x80150000 0x02 0x86801500 0x00 0x2878015 0x00 0x28840 0x15000000 0x289 0x91150000 0x02 0x8a981500 0x00 0x28b8015 0x00 0x28c80 0x15000000 0x28d 0x80150000 0x02 0x8e801500 0x00 0x28f8015 0x00 0x29080 0x15000000 0x291 0x80150000 0x02 0x92801500 0x00 0x2938015 0x00 0x29480 0x15000000 0x295 0x80150000 0x02 0x96801500 0x00 0x2978015 0x00 0x29880 0x15000000 0x299 0x80150000 0x02 0x9a801500 0x00 0x29b8015 0x00 0x29c80 0x15000000 0x29d 0x80150100 0x02 0x9e801500 0x00 0x29f8015 0x00 0x2a08a 0x15000000 0x2a2 0x80150000 0x02 0xa6801500 0x00 0x2a78015 0x00 0x2a980 0x15000000 0x2aa 0x80150000 0x02 0xab801500 0x00 0x2ac8015 0x00 0x2ad80 0x15000000 0x2ae 0x80150000 0x02 0xaf801500 0x00 0x2b77615 0x00 0x2b876 0x15000000 0x2b9 0x5150000 0x02 0xba0d1500 0x00 0x2bb1415 0x00 0x2bc0f 0x15000000 0x2bd 0x18150000 0x02 0xbe1f1500 0x00 0x2bf0515 0x00 0x2c00d 0x15000000 0x2c1 0x14150000 0x02 0xc2031501 0x00 0x2c30715 0x00 0x2c40a 0x15000000 0x2c5 0xa0150000 0x02 0xc6551500 0x00 0x2c7ff15 0x00 0x2c839 0x15000000 0x2c9 0x44150000 0x02 0xca121500 0x00 0x2cd8015 0x00 0x2db80 0x15000000 0x2dc 0x80150000 0x02 0xdd801500 0x00 0x2e08015 0x00 0x2e180 0x15000000 0x2e2 0x80150000 0x02 0xe3801500 0x00 0x2e48015 0x00 0x2e540 0x15000000 0x2e6 0x40150000 0x02 0xe7401500 0x00 0x2e84015 0x00 0x2e940 0x15000000 0x2ea 0x40150000 0x02 0xeb401500 0x00 0x2ec4015 0x00 0x2ed40 0x15000000 0x2ee 0x40150000 0x02 0xef401500 0x00 0x2f04015 0x00 0x2f140 0x15000000 0x2f2 0x40150000 0x02 0xf3401500 0x00 0x2f44015 0x00 0x2f540 0x15000000 0x2f6 0x40150100 0x02 0xfb011501 0x00 0x2ff2315 0x00 0x2fb01 0x15000000 0x201 0x84150000 0x02 0x52d1500 0x00 0x2060015 0x00 0x21101 0x15000000 0x212 0x7b150000 0x02 0x156f1500 0x00 0x2160b15 0x00 0x2290a 0x15000000 0x230 0xff150000 0x02 0x31ff1500 0x00 0x232ff15 0x00 0x233ff 0x15000000 0x234 0xff150000 0x02 0x35ff1500 0x00 0x236ff15 0x00 0x237ff 0x15000000 0x238 0xfc150100 0x02 0x39f81500 0x00 0x23af415 0x00 0x23bf1 0x15000000 0x23d 0xee150000 0x02 0x3feb1500 0x00 0x240e815 0x00 0x241e5 0x15000000 0x22a 0x13150000 0x02 0x45ff1500 0x00 0x246ff15 0x00 0x247ff 0x15000000 0x248 0xff150000 0x02 0x49ff1500 0x00 0x24aff15 0x00 0x24bff 0x15000000 0x24c 0xff150000 0x02 0x4ded1500 0x00 0x24ed515 0x00 0x24fbf 0x15000000 0x250 0xa6150100 0x02 0x51961500 0x00 0x2528615 0x00 0x25376 0x15000000 0x254 0x66150000 0x02 0x2b0e1500 0x00 0x258ff15 0x00 0x259ff 0x15000000 0x25a 0xff150000 0x02 0x5bff1500 0x00 0x25cff15 0x00 0x25dff 0x15000000 0x25e 0xff150000 0x02 0x5fff1500 0x00 0x260f615 0x00 0x261ea 0x15000000 0x262 0xe1150000 0x02 0x63d81500 0x00 0x264ce15 0x00 0x265c3 0x15000000 0x266 0xba150100 0x02 0x67b31501 0x00 0x2ff2515 0x00 0x2fb01 0x15000000 0x205 0x4150100 0x02 0xff261500 0x00 0x2fb0115 0x00 0x21caf 0x15010000 0x2ff 0x10150000 0x02 0xfb011500 0x00 0x251ff15 0x00 0x25324 0x15000000 0x255 0x50100 0x02 0x29000501 0x4600 0x2110015 0x1000000 0x2ff24 0x15000000 0x2fb 0x1150000 0x02 0xc3011500 0x00 0x2c45415 0x1000000 0x2ff10>; + qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 24 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 c3 00 15 01 00 00 00 00 02 ff 10 05 01 00 00 00 00 02 28 00 05 01 00 00 3c 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x01>; + qcom,mdss-dsi-dispparam-cabcuion-command = [15 01 00 00 00 00 02 55 01]; + qcom,mdss-dsi-dispparam-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcstillon-command = [15 01 00 00 00 00 02 55 02]; + qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcmovieon-command = [15 01 00 00 00 00 02 55 03]; + qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcoff-command = [39 01 00 00 01 00 02 55 00]; + qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcuion-command = [15 01 00 00 00 00 02 55 81]; + qcom,mdss-dsi-dispparam-skince-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcstillon-command = [15 01 00 00 00 00 02 55 82]; + qcom,mdss-dsi-dispparam-skince-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcmovieon-command = [15 01 00 00 00 00 02 55 83]; + qcom,mdss-dsi-dispparam-skince-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcoff-command = [15 01 00 00 00 00 02 55 80]; + qcom,mdss-dsi-dispparam-skince-cabcoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-phy-timings = <0x210808 0x25220908 0x6030400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_ebbg_fhd_ft8716_video { + qcom,mdss-dsi-panel-name = "ebbg fhd video dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "EBBG FHD FT8716 VIDEO PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0x00>; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0x00>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-min-level = <0x01>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-brightness-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <0x01 0x05 0x00 0x02 0x01 0x06>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x88>; + qcom,cont-splash-enabled; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-panel-on-dimming-delay = <0x78>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,dsi-supported-dfps-list = <0x3c 0x37>; + qcom,dispccbb-enabled; + qcom,dispblnotify-enabled; + qcom,dispparam-enabled; + qcom,mdss-night-brightness = <0x07 0x19 0x2b 0x3d>; + qcom,disp-panel-offon-mode-enabled; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-panel-xy-coordinate = <0x04 0x03>; + qcom,mdss-dsi-panel-max-luminance = <0x01 0x01>; + qcom,mdss-dsi-panel-bl-info = <0x134 0x221 0x1a4 0x2bc>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a 0x6010001 0x10b 0x6010001 0x10c 0x6010001 0x10d 0x6010001 0x10f 0x6010001 0x11d 0x6010001 0x1ac>; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c 0x00 0x07 0x00 0xc0 0x02 0x00>; + qcom,mdss-dsi-panel-status-read-length = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; + qcom,mdss-panel-off-keep-reset; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2f>; + phandle = <0x366>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x870>; + qcom,mdss-dsi-h-front-porch = <0x1c>; + qcom,mdss-dsi-h-back-porch = <0x1c>; + qcom,mdss-dsi-h-pulse-width = <0x04>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x10>; + qcom,mdss-dsi-v-front-porch = <0x0e>; + qcom,mdss-dsi-v-pulse-width = <0x02>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-on-command = [15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 04 ff 87 16 01 15 00 00 00 00 00 02 00 80 29 01 00 00 00 00 03 ff 87 16 15 00 00 00 00 00 02 00 81 29 01 00 00 00 00 0d f3 f8 e1 00 f8 e1 00 00 1c 00 00 1c 00 15 00 00 00 00 00 02 00 b3 15 00 00 00 00 00 02 ca 8c 15 00 00 00 00 00 02 00 80 15 00 00 00 00 00 02 a5 bf 15 00 00 00 00 00 02 00 a1 15 00 00 00 00 00 02 c0 0c 15 00 00 00 00 00 02 00 d1 15 00 00 00 00 00 02 c0 0c 15 00 00 00 00 00 02 00 88 29 01 00 00 00 00 05 c2 83 00 12 92 15 00 00 00 00 00 02 00 ca 15 00 00 00 00 00 02 cb 02 15 00 00 00 00 00 02 00 8a 15 00 00 00 00 00 02 cc 04 15 00 00 00 00 00 02 00 9a 15 00 00 00 00 00 02 cc 04 15 00 00 00 00 00 02 00 a9 15 00 00 00 00 00 02 cd 0b 15 00 00 00 00 00 02 00 89 15 01 00 00 00 00 02 cd 0b 15 00 00 00 00 00 02 00 80 29 00 00 00 00 00 0b ca 80 e5 ff 80 ff b2 ff 00 00 00 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 10 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 90 9a 8b 8b c9 9a 99 a9 a9 a9 ba 99 89 88 67 34 22 22 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 11 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 90 8a 9b 99 c8 9a 99 99 a9 99 ba 8a 89 88 67 45 33 22 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 12 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 90 99 9a 8a b9 a9 98 99 a9 99 b9 8a 88 88 78 45 33 33 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 13 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 9a 8a 8a b8 9a 98 99 99 99 a9 9a 88 88 78 56 34 33 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 14 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 8a 9a 89 b8 99 99 98 99 99 b8 8a 88 88 78 56 44 44 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 15 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 99 99 99 a8 99 89 89 99 89 a9 9a 88 88 88 57 44 44 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 16 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 99 99 98 98 8a 89 99 98 89 a9 99 88 88 88 67 55 44 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 17 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 89 99 89 a8 99 88 89 99 98 98 a9 88 88 88 67 55 55 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 18 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 98 99 98 98 89 89 98 98 89 98 99 89 88 88 78 55 55 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 19 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 98 89 89 98 89 89 88 99 88 a8 89 89 88 88 78 66 55 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 1a 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 88 99 88 98 89 89 88 89 98 98 98 89 88 88 78 66 66 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 1b 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 88 89 98 88 89 88 89 98 88 98 89 89 88 88 88 67 66 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 1c 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 88 98 88 98 98 88 88 98 88 98 98 88 88 88 88 77 67 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 1d 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 88 88 98 88 98 88 88 98 88 88 98 88 88 88 88 78 77 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 1e 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 88 88 88 88 89 88 88 88 98 97 88 88 88 88 88 88 78 15 00 00 00 00 00 02 00 00 15 00 00 00 00 00 02 c6 1f 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 13 c7 80 88 88 88 88 88 88 88 88 88 89 88 88 88 88 88 88 88 15 00 00 00 00 00 02 00 00 15 01 00 00 00 00 02 c6 00 15 00 00 00 00 00 02 00 a0 29 00 00 00 00 00 0d d6 0d 0a 07 04 08 10 11 0f 0e 15 13 0f 15 00 00 00 00 00 02 00 b0 29 00 00 00 00 00 0d d6 83 88 79 68 62 65 68 70 7f 8c 8d 92 15 00 00 00 00 00 02 00 c0 29 00 00 00 00 00 0d d6 6d 6b 6a 66 68 70 73 74 75 76 74 72 15 00 00 00 00 00 02 00 d0 29 01 00 00 00 00 0d d6 63 68 80 80 80 80 80 80 80 80 80 80 15 00 00 00 00 00 02 00 00 29 01 00 00 00 00 04 ff 00 00 00 15 00 00 00 00 00 02 00 80 29 01 00 00 00 00 03 ff 00 00 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 05 2a 00 00 04 37 15 00 00 00 00 00 02 00 00 29 01 00 00 00 00 05 2b 00 00 08 6f 15 00 00 00 00 00 02 91 80 15 00 00 00 00 00 02 00 00 29 01 00 00 00 00 04 ff 87 16 01 15 00 00 00 00 00 02 00 80 29 01 00 00 00 00 03 ff 87 16 15 00 00 00 00 00 02 00 81 29 00 00 00 00 00 0d f3 f8 e1 00 f8 e1 00 00 1e 00 00 1e 00 15 00 00 00 00 00 02 51 ff 15 00 00 00 00 00 02 53 24 15 00 00 00 00 00 02 55 00 05 01 00 00 5a 00 02 11 00 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 5a 00 02 10 00 15 01 00 00 00 00 02 00 00 29 01 00 00 05 00 05 f7 5a a5 87 16]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-displayoff-command = [05 01 00 00 16 00 02 28 00]; + qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x01>; + qcom,mdss-dsi-dispparam-cabcuion-command = [15 01 00 00 00 00 02 55 01 15 01 00 00 00 00 02 91 00]; + qcom,mdss-dsi-dispparam-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcstillon-command = [15 01 00 00 00 00 02 55 02 15 01 00 00 00 00 02 91 00]; + qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcmovieon-command = [15 01 00 00 00 00 02 55 03 15 01 00 00 00 00 02 91 00]; + qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcoff-command = [15 01 00 00 00 00 02 55 00 15 01 00 00 00 00 02 91 00]; + qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcuion-command = [15 01 00 00 00 00 02 55 01 15 01 00 00 00 00 02 91 80]; + qcom,mdss-dsi-dispparam-skince-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcstillon-command = [15 00 00 00 00 00 02 55 02 15 01 00 00 00 00 02 91 80]; + qcom,mdss-dsi-dispparam-skince-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcmovieon-command = [15 01 00 00 00 00 02 55 03 15 01 00 00 00 00 02 91 80]; + qcom,mdss-dsi-dispparam-skince-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcoff-command = [15 01 00 00 01 00 02 55 00 15 01 00 00 00 00 02 91 80]; + qcom,mdss-dsi-dispparam-skince-cabcoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-idleon-command = [39 01 00 00 01 00 02 39 00]; + qcom,mdss-dsi-dispparam-idleoff-command = [39 01 00 00 01 00 02 38 00]; + qcom,mdss-dsi-dispparam-xy-coordinate-command = [06 01 00 01 05 00 02 a1 00]; + qcom,mdss-dsi-dispparam-xy-coordinate-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-max-luminance-command = [06 01 00 01 05 00 02 dc 00]; + qcom,mdss-dsi-dispparam-max-luminance-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-phy-timings = <0x1e0808 0x24220808 0x5030400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_ebbg_fhd_ft8719_video { + qcom,mdss-dsi-panel-name = "ebbg fhd video dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "EBBG FHD FT8719 VIDEO PANEL"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0x00>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-min-level = <0x01>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-brightness-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x01 0x04 0x00 0x01 0x01 0x0f>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x8d>; + qcom,cont-splash-enabled; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x401640>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <0x78>; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x41>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a 0x6010001 0x10b 0x6010001 0x10d>; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c 0x00 0x00>; + qcom,mdss-dsi-panel-status-read-length = <0x01 0x01 0x01>; + qcom,panel-supply-entries = <0x363>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + phandle = <0x367>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x8c6>; + qcom,mdss-dsi-h-front-porch = <0x1c>; + qcom,mdss-dsi-h-back-porch = <0x10>; + qcom,mdss-dsi-h-pulse-width = <0x04>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x0c>; + qcom,mdss-dsi-v-front-porch = <0x78>; + qcom,mdss-dsi-v-pulse-width = <0x04>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 00 00 29 00 00 00 00 00 04 ff 87 19 01 15 00 00 00 00 00 02 00 80 29 01 00 00 00 00 03 ff 87 19 15 00 00 00 00 00 02 00 a0 29 00 00 00 00 00 04 ca 0f 0f 0f 15 00 00 00 00 00 02 00 80 29 00 00 00 00 00 0d ca be b5 ad a6 a0 9b 96 91 8d 8a 87 83 15 00 00 00 00 00 02 00 90 29 01 00 00 00 00 0a ca fe ff 66 f6 ff 66 fb ff 32 15 00 00 00 00 00 02 00 a0 29 00 00 00 00 00 0d d6 7a 79 74 8c 8c 92 97 9b 97 8f 80 77 15 00 00 00 00 00 02 00 b0 29 00 00 00 00 00 0d d6 7e 7d 81 7a 7a 7b 7c 81 84 85 80 82 15 00 00 00 00 00 02 00 c0 29 00 00 00 00 00 0d d6 7d 7d 78 8a 89 8f 97 97 8f 8c 80 7a 15 00 00 00 00 00 02 00 d0 29 01 00 00 00 00 0d d6 7e 7d 81 7c 79 7b 7c 80 84 85 80 82 15 00 00 00 00 00 02 00 e0 29 00 00 00 00 00 0d d6 7b 7b 7b 80 80 80 80 80 80 80 80 80 15 00 00 00 00 00 02 00 f0 29 00 00 00 00 00 0d d6 7e 7e 80 80 80 80 80 80 80 80 80 80 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 0d d7 80 80 80 80 80 80 80 80 80 80 80 80 15 00 00 00 00 00 02 00 10 29 01 00 00 00 00 0d d7 80 80 80 80 80 80 80 80 80 80 80 80 15 00 00 00 00 00 02 00 00 29 00 00 00 00 00 04 ff 00 00 00 15 00 00 00 00 00 02 00 80 29 01 00 00 00 00 03 ff 00 00 15 00 00 00 00 00 02 91 00 15 00 00 00 00 00 02 51 ff 15 00 00 00 00 00 02 53 24 15 00 00 00 00 00 02 55 00 05 01 00 00 5a 00 02 11 00 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 5a 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x01>; + qcom,mdss-dsi-dispparam-cabcuion-command = [15 01 00 00 00 00 02 55 01 15 01 00 00 00 00 02 91 00]; + qcom,mdss-dsi-dispparam-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcstillon-command = [15 01 00 00 00 00 02 55 02 15 01 00 00 00 00 02 91 00]; + qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcmovieon-command = [15 01 00 00 00 00 02 55 03 15 01 00 00 00 00 02 91 00]; + qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcoff-command = [15 01 00 00 01 00 02 55 00 15 01 00 00 00 00 02 91 00]; + qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-dimmingon-command = [15 01 00 00 01 00 02 53 2c]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-ceon-command = [15 01 00 00 00 00 02 91 80]; + qcom,mdss-dsi-dispparam-ceon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-ceoff-command = [15 01 00 00 00 00 02 91 00]; + qcom,mdss-dsi-dispparam-ceoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcuion-command = [15 01 00 00 00 00 02 55 01 15 01 00 00 00 00 02 91 80]; + qcom,mdss-dsi-dispparam-skince-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcstillon-command = [15 01 00 00 00 00 02 55 02 15 01 00 00 00 00 02 91 80]; + qcom,mdss-dsi-dispparam-skince-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcmovieon-command = [15 01 00 00 00 00 02 55 03 15 01 00 00 00 00 02 91 80]; + qcom,mdss-dsi-dispparam-skince-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcoff-command = [15 01 00 00 01 00 02 55 00 15 01 00 00 00 00 02 91 80]; + qcom,mdss-dsi-dispparam-skince-cabcoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-phy-timings = <0x210808 0x25220908 0x6030400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_samsung_fhd_ea8076_cmd { + qcom,mdss-dsi-panel-name = "samsung ea8076 fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "SAMSUNG FHD EA8076 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0x00>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <0x7ff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0x00 0x01 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x93>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <0x78>; + qcom,disp-doze-backlight-threshold = <0x08>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + qcom,mdss-dsi-t-clk-post = <0x0f>; + qcom,mdss-dsi-t-clk-pre = <0x37>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <0x01>; + phandle = <0x368>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x924>; + qcom,mdss-dsi-h-front-porch = <0x40>; + qcom,mdss-dsi-h-back-porch = <0x40>; + qcom,mdss-dsi-h-pulse-width = <0x14>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x40>; + qcom,mdss-dsi-v-front-porch = <0x40>; + qcom,mdss-dsi-v-pulse-width = <0x14>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-panel-clockrate = <0x4190ab00>; + qcom,mdss-dsi-panel-jitter = <0x05 0x01>; + qcom,mdss-dsi-on-command = [05 01 00 00 0a 00 02 11 00 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 35 00 39 00 00 00 00 00 03 b7 01 4b 39 01 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 05 2b 00 00 09 23 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 b0 07 39 00 00 00 00 00 03 d9 88 2e 39 01 00 00 00 00 03 f0 a5 a5 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 03 fc 5a 5a 39 00 00 00 00 00 0c e9 11 55 a6 75 a3 b8 bb 2a 00 1a b8 39 00 00 00 00 00 03 f0 a5 a5 39 01 00 00 00 00 03 fc a5 a5 39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 b0 09 39 00 00 00 00 00 02 d8 00 39 01 00 00 00 00 03 f0 a5 a5 39 00 00 00 00 00 02 53 20 39 00 00 00 00 00 03 51 00 00 39 01 00 00 43 00 02 55 00 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-hbm-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 d4 8b 39 00 00 00 00 00 02 b0 a5 39 00 00 00 00 00 02 c7 00 39 00 00 00 00 00 02 b0 69 39 00 00 00 00 00 03 b9 08 8f 39 01 00 00 01 00 02 53 22 39 01 00 00 00 00 03 f0 a5 a5]; + qcom,mdss-dsi-doze-lbm-command = [39 00 00 00 00 00 03 f0 5a 5a 39 00 00 00 00 00 02 d4 8b 39 00 00 00 00 00 02 b0 a5 39 00 00 00 00 00 02 c7 00 39 00 00 00 00 00 02 b0 69 39 00 00 00 00 00 03 b9 08 8f 39 01 00 00 00 00 02 53 23 39 01 00 00 00 00 03 f0 a5 a5]; + qcom,mdss-dsi-nolp-command = [05 01 00 00 22 00 02 28 00 39 01 00 00 00 00 02 53 20 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01]; + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02]; + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03]; + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 e8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-srgb-on-command = [39 01 00 00 00 00 02 81 90 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b1 00 39 01 00 00 00 00 02 b0 01 39 01 00 00 00 00 16 b1 ae 0c 05 3f c6 14 05 07 aa 4a dd c8 c3 14 c0 e8 dc 19 ff f4 d9 39 01 00 00 00 00 02 b0 16 39 01 00 00 00 00 16 b1 bd 02 00 14 d1 00 04 07 aa 0c ec cb c8 0f dd d9 e4 05 ff ff ff 39 01 00 00 00 00 03 f0 a5 a5]; + qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [39 01 00 00 00 00 02 81 91 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b1 00 39 01 00 00 00 00 02 b0 01 39 01 00 00 00 00 16 b1 ae 0c 05 3f c6 14 05 07 aa 4a dd c8 c3 14 c0 e8 dc 19 ff f4 d9 39 01 00 00 00 00 02 b0 16 39 01 00 00 00 00 16 b1 bd 02 00 14 d1 00 04 07 aa 0c ec cb c8 0f dd d9 e4 05 ff ff ff 39 01 00 00 00 00 03 f0 a5 a5]; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-off-command = [39 01 00 00 00 00 02 81 00 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b1 01 39 01 00 00 00 00 03 f0 a5 a5]; + qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0x00>; + qcom,mdss-dsi-panel-phy-timings = <0x240a0a 0x2625090a 0x6020400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_visionox_fhd_r66455_cmd { + qcom,mdss-dsi-panel-name = "visionox r66455 fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "VISIONOX FHD R66455 CMD PANEL"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-min-level = <0x01>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-brightness-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x00 0x02 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x93>; + qcom,mdss-dsi-te-pin-select = <0x01>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <0x01>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x36>; + phandle = <0x36a>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x924>; + qcom,mdss-dsi-h-back-porch = <0x28>; + qcom,mdss-dsi-h-front-porch = <0x60>; + qcom,mdss-dsi-h-pulse-width = <0x04>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x10>; + qcom,mdss-dsi-v-front-porch = <0x19>; + qcom,mdss-dsi-v-pulse-width = <0x03>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 02 b3 00 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 03 51 04 00 39 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 29 00 05 01 00 00 78 00 02 11 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 55 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-phy-timings = <0x230909 0x26240909 0x6020400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + qcom,mdss_dsi_visionox_fhd_r66455_vid { + qcom,mdss-dsi-panel-name = "visionox r66455 fhd video dsi panel"; + qcom,mdss-dsi-panel-id = <0x00>; + qcom,mdss-dsi-panel-model = "VISIONOX FHD R66455 VIDEO PANEL"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0x00>; + qcom,mdss-dsi-stream = <0x00>; + qcom,mdss-dsi-bpp = <0x18>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0x00>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-min-level = <0x01>; + qcom,mdss-dsi-bl-max-level = <0xfff>; + qcom,mdss-brightness-max-level = <0xfff>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0x00 0x02 0x01 0x0a>; + qcom,mdss-pan-physical-width-dimension = <0x44>; + qcom,mdss-pan-physical-height-dimension = <0x93>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; + qcom,mdss-dsi-panel-peak-brightness = <0x419ce0>; + qcom,mdss-dsi-panel-blackness-level = <0xc9e>; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,panel-allow-phy-poweroff; + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x36>; + phandle = <0x36b>; + + qcom,mdss-dsi-display-timings { + + timing@0 { + qcom,mdss-dsi-panel-width = <0x438>; + qcom,mdss-dsi-panel-height = <0x924>; + qcom,mdss-dsi-h-back-porch = <0x28>; + qcom,mdss-dsi-h-front-porch = <0x60>; + qcom,mdss-dsi-h-pulse-width = <0x04>; + qcom,mdss-dsi-h-sync-skew = <0x00>; + qcom,mdss-dsi-v-back-porch = <0x10>; + qcom,mdss-dsi-v-front-porch = <0x19>; + qcom,mdss-dsi-v-pulse-width = <0x03>; + qcom,mdss-dsi-h-left-border = <0x00>; + qcom,mdss-dsi-h-right-border = <0x00>; + qcom,mdss-dsi-v-top-border = <0x00>; + qcom,mdss-dsi-v-bottom-border = <0x00>; + qcom,mdss-dsi-panel-framerate = <0x3c>; + qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 e6 01 39 01 00 00 00 00 03 51 04 00 39 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 29 00 05 01 00 00 78 00 02 11 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 55 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-phy-timings = <0x230909 0x26240909 0x6020400>; + qcom,display-topology = <0x01 0x00 0x01>; + qcom,default-topology-index = <0x00>; + }; + }; + }; + + dsi_amoled_panel_pwr_supply { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,panel-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <0x1b7740>; + qcom,supply-max-voltage = <0x1b7740>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + }; + + qcom,panel-supply-entry@1 { + reg = <0x01>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <0x2dc6c0>; + qcom,supply-max-voltage = <0x2dc6c0>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + qcom,supply-post-on-sleep = <0x0a>; + qcom,supply-pre-off-sleep = <0x0a>; + }; + }; + + dsi_amoled_samsung_ea8076_panel_pwr_supply { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,panel-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <0x1cfde0>; + qcom,supply-max-voltage = <0x1cfde0>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + }; + + qcom,panel-supply-entry@1 { + reg = <0x01>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <0x2dc6c0>; + qcom,supply-max-voltage = <0x2dc6c0>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + qcom,supply-post-on-sleep = <0x0a>; + qcom,supply-pre-off-sleep = <0x0a>; + }; + }; + + dsi_amoled_visionox_r66455_panel_pwr_supply { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,panel-supply-entry@0 { + reg = <0x00>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <0x1b7740>; + qcom,supply-max-voltage = <0x1b7740>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + }; + + qcom,panel-supply-entry@1 { + reg = <0x01>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <0x2ab980>; + qcom,supply-max-voltage = <0x2ab980>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + qcom,supply-post-on-sleep = <0x0a>; + qcom,supply-pre-off-sleep = <0x0a>; + }; + }; + + dsi_nt35596s_panel_pwr_supply { + #address-cells = <0x01>; + #size-cells = <0x00>; + + qcom,panel-supply-entry@0 { + reg = <0x01>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <0x1b7740>; + qcom,supply-max-voltage = <0x1b7740>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + qcom,supply-pre-off-sleep = <0x05>; + }; + + qcom,panel-supply-entry@1 { + reg = <0x02>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <0x4630c0>; + qcom,supply-max-voltage = <0x5b8d80>; + qcom,supply-enable-load = <0x186a0>; + qcom,supply-disable-load = <0x64>; + }; + + qcom,panel-supply-entry@2 { + reg = <0x03>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <0x4630c0>; + qcom,supply-max-voltage = <0x5b8d80>; + qcom,supply-enable-load = <0x186a0>; + qcom,supply-disable-load = <0x64>; + qcom,supply-pre-off-sleep = <0x05>; + }; + }; + + dsi_nt36672a_panel_pwr_supply { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x362>; + + qcom,panel-supply-entry@0 { + reg = <0x01>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <0x1b7740>; + qcom,supply-max-voltage = <0x1b7740>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + qcom,supply-post-on-sleep = <0x01>; + }; + + qcom,panel-supply-entry@1 { + reg = <0x02>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <0x53ec60>; + qcom,supply-max-voltage = <0x53ec60>; + qcom,supply-enable-load = <0x186a0>; + qcom,supply-disable-load = <0x64>; + }; + + qcom,panel-supply-entry@2 { + reg = <0x03>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <0x53ec60>; + qcom,supply-max-voltage = <0x53ec60>; + qcom,supply-enable-load = <0x186a0>; + qcom,supply-disable-load = <0x64>; + }; + }; + + dsi_ft8719_panel_pwr_supply { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x363>; + + qcom,panel-supply-entry@0 { + reg = <0x01>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <0x1b7740>; + qcom,supply-max-voltage = <0x1b7740>; + qcom,supply-enable-load = <0xf230>; + qcom,supply-disable-load = <0x50>; + qcom,supply-post-on-sleep = <0x04>; + qcom,supply-pre-off-sleep = <0x04>; + }; + + qcom,panel-supply-entry@1 { + reg = <0x02>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <0x53ec60>; + qcom,supply-max-voltage = <0x53ec60>; + qcom,supply-enable-load = <0x186a0>; + qcom,supply-disable-load = <0x64>; + qcom,supply-post-on-sleep = <0x03>; + }; + + qcom,panel-supply-entry@2 { + reg = <0x03>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <0x53ec60>; + qcom,supply-max-voltage = <0x3473bc0>; + qcom,supply-enable-load = <0x186a0>; + qcom,supply-disable-load = <0x64>; + qcom,supply-pre-off-sleep = <0x04>; + }; + }; + + qcom,dsi-display@20 { + compatible = "qcom,dsi-display"; + label = "dsi_ss_ea8074_notch_fhd_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,dsi-panel = <0x364>; + vddio-supply = <0x89>; + vci-supply = <0x35f>; + }; + + qcom,dsi-display@21 { + compatible = "qcom,dsi-display"; + label = "dsi_tianma_fhd_nt36672a_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346>; + pinctrl-1 = <0x348>; + qcom,dsi-panel = <0x365>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + qcom,dsi-display-active; + }; + + qcom,dsi-display@22 { + compatible = "qcom,dsi-display"; + label = "dsi_ebbg_fhd_ft8716_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,dsi-panel = <0x366>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@23 { + compatible = "qcom,dsi-display"; + label = "dsi_ebbg_fhd_ft8719_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346>; + pinctrl-1 = <0x348>; + qcom,dsi-panel = <0x367>; + vddio-supply = <0x89>; + lab-supply = <0x8a>; + ibb-supply = <0x8b>; + }; + + qcom,dsi-display@24 { + compatible = "qcom,dsi-display"; + label = "dsi_samsung_fhd_ea8076_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,dsi-panel = <0x368>; + vddio-supply = <0x89>; + vci-supply = <0x35f>; + }; + + qcom,dsi-display@25 { + compatible = "qcom,dsi-display"; + label = "dsi_tianma_rm69299_fhd_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,dsi-panel = <0x369>; + vddio-supply = <0x89>; + vci-supply = <0x35f>; + }; + + qcom,dsi-display@26 { + compatible = "qcom,dsi-display"; + label = "dsi_visionox_fhd_r66455_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,dsi-panel = <0x36a>; + vddio-supply = <0x89>; + vci-supply = <0x35f>; + }; + + qcom,dsi-display@27 { + compatible = "qcom,dsi-display"; + label = "dsi_visionox_fhd_r66455_vid_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl = <0x2d>; + qcom,dsi-phy = <0x343>; + clocks = <0x345 0x06 0x345 0x09>; + clock-names = "mux_byte_clk\0mux_pixel_clk"; + pinctrl-names = "panel_active\0panel_suspend"; + pinctrl-0 = <0x346 0x347>; + pinctrl-1 = <0x348 0x349>; + qcom,platform-te-gpio = <0x3c 0x0a 0x00>; + qcom,platform-reset-gpio = <0x3c 0x06 0x00>; + qcom,dsi-panel = <0x36b>; + vddio-supply = <0x89>; + vci-supply = <0x35f>; + }; + + qcom,camera-flash@0 { + cell-index = <0x00>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <0x36c 0x36d>; + torch-source = <0x36e 0x36f>; + switch-source = <0x370>; + status = "ok"; + phandle = <0x233>; + }; + + qcom,camera-flash@1 { + cell-index = <0x01>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <0x371>; + torch-source = <0x372>; + switch-source = <0x373>; + status = "ok"; + }; + + gpio-regulator@2 { + compatible = "regulator-fixed"; + reg = <0x02 0x00>; + regulator-name = "camera_iovdd_ldo"; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-enable-ramp-delay = <0x87>; + enable-active-high; + gpio = <0x3c 0x32 0x00>; + vin-supply = <0xdf>; + phandle = <0x21b>; + }; + + gpio-regulator@5 { + compatible = "regulator-fixed"; + reg = <0x05 0x00>; + regulator-name = "actuator_rear_regulator"; + regulator-min-microvolt = <0x2ab980>; + regulator-max-microvolt = <0x2ab980>; + regulator-enable-ramp-delay = <0x64>; + enable-active-high; + gpio = <0x3c 0x1a 0x00>; + vin-supply = <0x21c>; + phandle = <0x21a>; + }; + + gpio-regulator@7 { + compatible = "regulator-fixed"; + reg = <0x07 0x00>; + regulator-name = "camera_vdig_ldo"; + regulator-min-microvolt = <0x149970>; + regulator-max-microvolt = <0x149970>; + regulator-enable-ramp-delay = <0x87>; + enable-active-high; + gpio = <0x3c 0x63 0x00>; + phandle = <0x221>; + }; + + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <0x374>; + + vol_up { + label = "volume_up"; + gpios = <0x4c 0x06 0x01>; + linux,input-type = <0x01>; + linux,code = <0x73>; + gpio-key,wakeup; + debounce-interval = <0x0f>; + linux,can-disable; + }; + + hall_key { + label = "hall_key"; + gpios = <0x3c 0x7c 0x01>; + linux,input-type = <0x05>; + linux,code = <0x00>; + gpio-key,wakeup; + debounce-interval = <0x0f>; + }; + }; + + disp_vci_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vci_vreg"; + start-delay-us = <0xfa0>; + enable-active-high; + regulator-boot-on; + gpio = <0x3c 0x23 0x00>; + phandle = <0x35f>; + }; + + disp_vddio_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vddio_vreg"; + startup-delay-us = <0xfa0>; + enable-active-high; + regulator-boot-on; + gpio = <0x3c 0x5a 0x00>; + }; + + fp_vdd_vreg { + compatible = "regulator-fixed"; + regulator-name = "fp_vdd_vreg"; + startup-delay-us = <0xfa0>; + enable-active-high; + gpio = <0x3c 0x5e 0x00>; + regulator-always-on; + }; + + fingerprint_fpc { + status = "ok"; + compatible = "fpc,fpc1020"; + interrupt-parent = <0x3c>; + interrupts = <0x79 0x00>; + fpc,gpio_irq = <0x3c 0x79 0x00>; + pinctrl-names = "fpc1020_reset_reset\0fpc1020_reset_active"; + pinctrl-0 = <0x375>; + pinctrl-1 = <0x376>; + }; + + fingerprint_goodix { + compatible = "goodix,fingerprint"; + gooidx,gpio-reset = <0x3c 0x25 0x00>; + goodix,gpio-irq = <0x3c 0x79 0x00>; + fp-gpio-pwr = <0x3c 0x5e 0x00>; + status = "ok"; + }; + + thermal-message { + thermal,batt-array-size = "26"; + thermal,batt-level-screen-on = "0 3 5 7 9 11 12 12 13 13 14 14 16 0 3 5 7 9 10 11 12 12 13 14 14 16"; + thermal,batt-level-screen-off = "0 2 4 6 8 9 9 9 9 9 9 14 16 0 1 1 2 4 6 7 7 7 8 9 14 16"; + }; + + msm_cdc_pinctrl@49 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x377>; + pinctrl-1 = <0x378>; + qcom,lpi-gpios; + phandle = <0x322>; + }; + + wcd9xxx-irq { + status = "ok"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <0x01>; + interrupt-parent = <0x3c>; + qcom,gpio-connect = <0x3c 0x36 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x379>; + phandle = <0x103>; + }; + + audio_ext_clk_lnbb { + status = "ok"; + compatible = "qcom,audio-ref-clk"; + clock-names = "osr_clk"; + clocks = <0x21 0x02>; + qcom,node_has_rpm_clock; + #clock-cells = <0x01>; + phandle = <0x105>; + }; + + msm_cdc_pinctrl@64 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,cdc-rst-n-gpio = <0x3c 0x40 0x00>; + pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x37a>; + pinctrl-1 = <0x37b>; + phandle = <0x104>; + }; + + qocm,wcd-dsp-glink { + compatible = "qcom,wcd-dsp-glink"; + }; + + qcom,wcd-dsp-mgr { + compatible = "qcom,wcd-dsp-mgr"; + qcom,wdsp-components = <0x37c 0x00 0x37d 0x01 0x37e 0x02>; + qcom,img-filename = "cpe_9340"; + }; + }; + + chosen { + pureason = <0x40181>; + linux,initrd-end = <0x00 0x855fe4b0>; + linux,initrd-start = <0x00 0x85501000>; + kaslr-seed = <0x00 0x00>; + bootargs = "rcupdate.rcu_expedited=1 console=ttyMSM0,115200n8 earlycon=msm_geni_serial,0xA84000 androidboot.hardware=qcom androidboot.console=ttyMSM0 video=vfb:640x400,bpp=32,memsize=3072000 msm_rtb.filter=0x237 ehci-hcd.park=3 lpm_levels.sleep_disabled=1 service_locator.enable=1 swiotlb=2048 androidboot.configfs=true loop.max_part=7 androidboot.usbcontroller=a600000.dwc3 buildvariant=userdebug root=/dev/dm-0 dm=\"system none ro,0 1 android-verity /dev/sde48\" androidboot.verifiedbootstate=orange androidboot.keymaster=1 androidboot.veritymode=enforcing androidboot.bootdevice=1d84000.ufshc androidboot.serialno=dd9c1a51 androidboot.baseband=msm msm_drm.dsi_display0=dsi_tianma_fhd_nt36672a_video_display: androidboot.ramdump=disable androidboot.secureboot=1 androidboot.dp=0x0 androidboot.cpuid=0x01e7c9fa androidboot.hwversion=4.29.0 androidboot.hwc=GLOBAL androidboot.cert=M1805E10A androidboot.hwlevel=MP androidboot.dtb_idx=-1347440721"; + }; + + aliases { + ufshc1 = "/soc/ufshc@1d84000"; + pci-domain0 = "/soc/qcom,pcie@0x1c00000"; + pci-domain1 = "/soc/qcom,pcie@0x1c08000"; + sdhc2 = "/soc/sdhci@8804000"; + serial0 = "/soc/qcom,qup_uart@0xa84000"; + spi0 = "/soc/spi@a80000"; + i2c0 = "/soc/i2c@a88000"; + i2c1 = "/soc/i2c@88c000"; + hsuart0 = "/soc/qcom,qup_uart@0x898000"; + }; + + memory { + ddr_device_type = <0x07>; + device_type = "memory"; + reg = <0x00 0x80000000 0x00 0xc0000000 0x01 0x40000000 0x00 0xbd4a0000>; + }; + + energy-costs { + compatible = "sched-energy"; + + core-cost0 { + busy-cost-data = <0x493e0 0x0c 0x62700 0x11 0x75300 0x15 0x8ca00 0x1b 0x9f600 0x1f 0xb6d00 0x25 0xc9900 0x2a 0xdc500 0x2f 0xef100 0x34 0x101d00 0x39 0x114900 0x3e 0x12c000 0x46 0x143700 0x4e 0x15ae00 0x59 0x172500 0x67 0x189c00 0x7a 0x19c800 0x8d 0x1af400 0xa0>; + idle-cost-data = <0x0a 0x08 0x06 0x04>; + phandle = <0x04>; + }; + + core-cost1 { + busy-cost-data = <0x493e0 0xbd 0x62700 0x20b 0x75300 0x2fb 0x8ca00 0x41c 0x9f600 0x4f9 0xb6d00 0x600 0xc9900 0x6c8 0xdc500 0x786 0xef100 0x83c 0x101d00 0x8ec 0x114900 0x998 0x127500 0xa44 0x13a100 0xaf4 0x14cd00 0xbb0 0x164400 0xcb7 0x177000 0xdab 0x189c00 0xeca 0x19c800 0x1020 0x1af400 0x11b7 0x1c2000 0x139b 0x1d4c00 0x15cf 0x1e7800 0x1852 0x1fef00 0x1bd0 0x211b00 0x1ec4 0x224700 0x21b4 0x237300 0x2480 0x249f00 0x272e 0x25cb00 0x2a36 0x26f700 0x2f0d 0x286e00 0x3d46 0x29e500 0x63f2 0x2a3000 0x7530 0x2a7b00 0x88b8 0x2ac600 0x9c40 0x2b5c00 0xc350 0x2d1e00 0xea60>; + idle-cost-data = <0x64 0x50 0x3c 0x28>; + phandle = <0x0c>; + }; + + cluster-cost0 { + busy-cost-data = <0x493e0 0x03 0x62700 0x04 0x75300 0x04 0x8ca00 0x04 0x9f600 0x05 0xb6d00 0x05 0xc9900 0x06 0xdc500 0x07 0xef100 0x07 0x101d00 0x08 0x114900 0x09 0x12c000 0x09 0x143700 0x0a 0x15ae00 0x0b 0x172500 0x0c 0x189c00 0x0d 0x19c800 0x0f 0x1af400 0x11>; + idle-cost-data = <0x04 0x03 0x02 0x01>; + phandle = <0x05>; + }; + + cluster-cost1 { + busy-cost-data = <0x493e0 0x18 0x62700 0x18 0x75300 0x19 0x8ca00 0x19 0x9f600 0x1a 0xb6d00 0x1b 0xc9900 0x1c 0xdc500 0x1d 0xef100 0x1e 0x101d00 0x20 0x114900 0x22 0x127500 0x25 0x13a100 0x28 0x14cd00 0x2d 0x164400 0x32 0x177000 0x39 0x189c00 0x40 0x19c800 0x4a 0x1af400 0x54 0x1c2000 0x60 0x1d4c00 0x6a 0x1e7800 0x71 0x1fef00 0x78 0x211b00 0x7d 0x224700 0x7f 0x237300 0x82 0x249f00 0x87 0x25cb00 0x8c 0x26f700 0x91 0x286e00 0x96 0x29e500 0x9b 0x2a3000 0xa0 0x2a7b00 0xa5 0x2ac600 0xaa 0x2b5c00 0xb4 0x2d1e00 0xbe>; + idle-cost-data = <0x04 0x03 0x02 0x01>; + phandle = <0x0d>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + vendor { + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0x00 0xffffffff>; + compatible = "simple-bus"; + + ext_5v_boost { + status = "ok"; + compatible = "regulator-fixed"; + regulator-name = "ext_5v_boost"; + gpio = <0x37f 0x0a 0x00>; + enable-active-high; + regulator-enable-ramp-delay = <0x640>; + pinctrl-names = "default"; + pinctrl-0 = <0x380>; + }; + + bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <0x381>; + qca,bt-vdd-xtal-supply = <0xd4>; + qca,bt-vdd-core-supply = <0x142>; + qca,bt-vdd-pa-supply = <0x143>; + qca,bt-vdd-ldo-supply = <0x144>; + qca,bt-vdd-io-voltage-level = <0x14a140 0x14a140>; + qca,bt-vdd-xtal-voltage-level = <0x1f20c0 0x1f20c0>; + qca,bt-vdd-core-voltage-level = <0x1b7740 0x1b7740>; + qca,bt-vdd-pa-voltage-level = <0x13e5c0 0x13e5c0>; + qca,bt-vdd-ldo-voltage-level = <0x328980 0x328980>; + qca,bt-vdd-io-current-level = <0x01>; + qca,bt-vdd-xtal-current-level = <0x01>; + qca,bt-vdd-core-current-level = <0x01>; + qca,bt-vdd-pa-current-level = <0x01>; + qca,bt-vdd-ldo-current-level = <0x01>; + }; + + qcom,battery-data { + qcom,batt-id-range-pct = <0x0f>; + phandle = <0xac>; + + qcom,e10_atl_4000mah { + qcom, = <0x18>; + qcom,max-voltage-uv = <0x432380>; + qcom,fastchg-current-ma = <0xaf0>; + qcom,nom-batt-capacity-mah = <0xfa0>; + qcom,fg-cc-cv-threshold-mv = <0x1126>; + qcom,batt-id-kohm = <0x44>; + qcom,battery-beta = <0xd34>; + qcom,battery-type = "e10_atl_4000mAh"; + qcom,jeita-fcc-ranges = <0x00 0x32 0x5f370 0x33 0x64 0x11da50 0x65 0x96 0x11da50 0x97 0x1c2 0x2ab980 0x1c3 0x258 0x1dc130>; + qcom,jeita-fv-ranges = <0x00 0x32 0x432380 0x33 0x64 0x432380 0x65 0x96 0x432380 0x97 0x1c2 0x432380 0x1c3 0x258 0x3e8fa0>; + qcom,checksum = <0xa0e7>; + qcom,gui-version = "PMI8998GUI - 2.0.0.58"; + qcom,fg-profile-data = <0xa11e8bfd 0x10034407 0xd61c1802 0x6d0d050b 0xf117ce23 0x4f44745a 0x67000000 0x10000000 0x27b2 0x74cdecba 0x1c000800 0xf4e27fed 0x410615fa 0x640d310a 0xe2ec5732 0x24060920 0x27001400 0x941fd205 0x420a8b06 0xae1c4f03 0xab158c12 0x73180e2a 0x954df35b 0x65000000 0xd000000 0xecd5 0x6cca478b 0x15000000 0x8aeb7fed 0xfffdcfeb 0xefecc002 0xc7f4001b 0xa133ccff 0x7100000 0x940f6646 0x15004000 0x91010afa 0xff000000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + }; + + qcom,e10_cos_4000mah { + qcom, = <0x18>; + qcom,max-voltage-uv = <0x432380>; + qcom,fastchg-current-ma = <0xaf0>; + qcom,nom-batt-capacity-mah = <0xfa0>; + qcom,fg-cc-cv-threshold-mv = <0x1126>; + qcom,batt-id-kohm = <0x64>; + qcom,battery-beta = <0xd34>; + qcom,battery-type = "e10_cos_4000mAh"; + qcom,jeita-fcc-ranges = <0x00 0x32 0x5f370 0x33 0x64 0x11da50 0x65 0x96 0x11da50 0x97 0x1c2 0x2ab980 0x1c3 0x258 0x1dc130>; + qcom,jeita-fv-ranges = <0x00 0x32 0x432380 0x33 0x64 0x432380 0x65 0x96 0x432380 0x97 0x1c2 0x432380 0x1c3 0x258 0x3e8fa0>; + qcom,checksum = <0x920>; + qcom,gui-version = "PMI8998GUI - 2.0.0.58"; + qcom,fg-profile-data = <0x3f1ffc05 0x290aa506 0xe81ce401 0xd00d8d0a 0x98170e2a 0x44a95a 0x73000000 0x10000000 0xacc5 0x64c496c2 0x20000800 0xcdb6ee5 0x6805d201 0xe214f605 0x11ece723 0x31060920 0x27001400 0xe01f6305 0xa40a2406 0xc11c1103 0xe0155312 0x8218f823 0xc04d8b5b 0x69000000 0xd000000 0x40cc 0x10ca78bc 0x17000000 0x9fe36ee5 0x6d060401 0xd7068ffb 0xeef2bc1b 0xba33ccff 0x7100000 0x9c0f6646 0x17004000 0x6e010afa 0xff000000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + }; + }; + + extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + vbus-gpio = <0x37f 0x08 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x382>; + phandle = <0x33f>; + }; + }; + + firmware { + + android { + compatible = "android,firmware"; + + fstab { + compatible = "android,fstab"; + + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait"; + status = "ok"; + }; + + system { + mnt_point = "/system_root"; + compatible = "android,system"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait"; + status = "ok"; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + hyp_region@85700000 { + no-map; + reg = <0x00 0x85700000 0x00 0x600000>; + }; + + xbl_region@85e00000 { + no-map; + reg = <0x00 0x85d00000 0x00 0x200000>; + }; + + removed_region@85fc0000 { + no-map; + reg = <0x00 0x85fc0000 0x00 0x4940000>; + }; + + qseecom_region@0x8ab00000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x00 0x8ab00000 0x00 0x1400000>; + phandle = <0x206>; + }; + + camera_region@0x8bf00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x8bf00000 0x00 0x500000>; + phandle = <0x239>; + }; + + ips_fw_region@0x8c400000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x8c400000 0x00 0x10000>; + phandle = <0x13f>; + }; + + ipa_gsi_region@0x8c410000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x8c410000 0x00 0x5000>; + }; + + gpu_region@0x8c415000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x8c415000 0x00 0x2000>; + phandle = <0x333>; + }; + + adsp_region@0x8c500000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x8c500000 0x00 0x1e00000>; + phandle = <0xfb>; + }; + + wlan_fw_region@0x8e300000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x8e300000 0x00 0x100000>; + }; + + modem_region@0x8e400000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x8e400000 0x00 0x7800000>; + phandle = <0xf7>; + }; + + video_region@0x95c00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x95c00000 0x00 0x500000>; + phandle = <0x118>; + }; + + cdsp_region@0x96100000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x96100000 0x00 0x800000>; + phandle = <0x113>; + }; + + mba_region@0x96900000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x96900000 0x00 0x200000>; + phandle = <0xfa>; + }; + + slpi_region@0x96b00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x96b00000 0x00 0x1400000>; + phandle = <0x100>; + }; + + pil_spss_region@0x97f00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0x97f00000 0x00 0x100000>; + phandle = <0x112>; + }; + + adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00 0x00 0x00 0xffffffff>; + reusable; + alignment = <0x00 0x400000>; + size = <0x00 0x1000000>; + phandle = <0x116>; + }; + + qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00 0x00 0x00 0xffffffff>; + reusable; + alignment = <0x00 0x400000>; + size = <0x00 0x1000000>; + phandle = <0x207>; + }; + + secure_sp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00 0x00 0x00 0xffffffff>; + reusable; + alignment = <0x00 0x400000>; + size = <0x00 0x800000>; + phandle = <0x208>; + }; + + cont_splash_region@9d400000 { + reg = <0x00 0x9d400000 0x00 0x2400000>; + label = "cont_splash_region"; + }; + + secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00 0x00 0x00 0xffffffff>; + reusable; + alignment = <0x00 0x400000>; + size = <0x00 0x5c00000>; + phandle = <0x209>; + }; + + mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x2400000>; + phandle = <0x176>; + }; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00 0x00 0x00 0xffffffff>; + reusable; + alignment = <0x00 0x400000>; + size = <0x00 0x2000000>; + linux,cma-default; + }; + + ramoops@b0000000 { + compatible = "ramoops"; + reg = <0x00 0xb0000000 0x00 0x400000>; + record-size = <0x40000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size = <0x200000>; + ecc-size = <0x00>; + }; + + ramdump_fb_region@af000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x00 0xaf000000 0x00 0x1000000>; + }; + }; + + regulator-pm8998-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8998_s4"; + qcom,hpm-min-load = <0x186a0>; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + phandle = <0xdf>; + }; +}; diff --git a/sdm845Pkg/Binary/beryllium/ASN1X509Dxe/ASN1X509Dxe.efi b/sdm845Pkg/Binary/beryllium/ASN1X509Dxe/ASN1X509Dxe.efi new file mode 100755 index 0000000..e13fda1 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/ASN1X509Dxe/ASN1X509Dxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/AdcDxe/AdcDxe.depex b/sdm845Pkg/Binary/beryllium/AdcDxe/AdcDxe.depex new file mode 100755 index 0000000..743af29 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/AdcDxe/AdcDxe.depex @@ -0,0 +1 @@ +B¹7®E‘L¡–ÙfŸÓG£k0_ú}ôÄJ¤}ˆ/‚ì0 \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/AdcDxe/AdcDxe.efi b/sdm845Pkg/Binary/beryllium/AdcDxe/AdcDxe.efi new file mode 100755 index 0000000..66744bb Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/AdcDxe/AdcDxe.efi differ diff --git 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b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/MMCHS.c new file mode 100755 index 0000000..528dabc --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/MMCHS.c @@ -0,0 +1,375 @@ +#include "MMCHS.h" + +STATIC struct mmc_device * +PlatformCallbackInitSlot(struct mmc_config_data *config) +{ + EFI_STATUS Status; + BIO_INSTANCE *Instance; + + // Initialize MMC device + struct mmc_device *dev = mmc_init(config); + if (dev == NULL) { + return NULL; + } + + // Allocate instance + Status = BioInstanceContructor(&Instance); + if (EFI_ERROR(Status)) { + return dev; + } + + // Set data + Instance->MmcDev = dev; + Instance->BlockMedia.BlockSize = dev->card.block_size; + Instance->BlockMedia.LastBlock = + dev->card.capacity / Instance->BlockMedia.BlockSize - 1; + + // Give every device a slighty different GUID + Instance->DevicePath.Mmc.Guid.Data4[7] = config->slot; + + // Register for ExitBS event + Status = gBS->CreateEventEx( + EVT_NOTIFY_SIGNAL, TPL_NOTIFY, MMCHSExitBsUninit, (VOID *)Instance, + &gEfiEventExitBootServicesGuid, &Instance->ExitBsEvent); + ASSERT_EFI_ERROR(Status); + + // Publish BlockIO + Status = gBS->InstallMultipleProtocolInterfaces( + &Instance->Handle, &gEfiBlockIoProtocolGuid, &Instance->BlockIo, + &gEfiDevicePathProtocolGuid, &Instance->DevicePath, NULL); + ASSERT_EFI_ERROR(Status); + + return dev; +} + +STATIC BIO_INSTANCE mBioTemplate = { + BIO_INSTANCE_SIGNATURE, + NULL, // Handle + { + // BlockIo + EFI_BLOCK_IO_INTERFACE_REVISION, // Revision + NULL, // *Media + MMCHSReset, // Reset + MMCHSReadBlocks, // ReadBlocks + MMCHSWriteBlocks, // WriteBlocks + MMCHSFlushBlocks // FlushBlocks + }, + { + // BlockMedia + BIO_INSTANCE_SIGNATURE, // MediaId + FALSE, // RemovableMedia + TRUE, // MediaPresent + FALSE, // LogicalPartition + FALSE, // ReadOnly + FALSE, // WriteCaching + 0, // BlockSize + 4, // IoAlign + 0, // Pad + 0 // LastBlock + }, + { + // DevicePath + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + {(UINT8)(sizeof(VENDOR_DEVICE_PATH)), + (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8)}, + }, + // Hardware Device Path for Bio + EFI_CALLER_ID_GUID // Use the driver's GUID + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + {sizeof(EFI_DEVICE_PATH_PROTOCOL), 0}, + }, + }, + NULL, // MMCDev + NULL, // ExitBS Event +}; + +/* + * Function: mmc_write + * Arg : Data address on card, data length, i/p buffer + * Return : 0 on Success, non zero on failure + * Flow : Write the data from in to the card + */ +STATIC UINT32 +mmc_write(BIO_INSTANCE *Instance, UINT64 data_addr, UINT32 data_len, VOID *in) +{ + UINT32 val = 0; + UINT32 block_size = 0; + UINT32 write_size = SDHCI_ADMA_MAX_TRANS_SZ; + UINT8 *sptr = (UINT8 *)in; + + block_size = Instance->BlockMedia.BlockSize; + + ASSERT(!(data_addr % block_size)); + + if (data_len % block_size) + data_len = ROUNDUP(data_len, block_size); + + /* + * Flush the cache before handing over the data to + * storage driver + */ + arch_clean_invalidate_cache_range((addr_t)in, data_len); + + /* TODO: This function is aware of max data that can be + * tranferred using sdhci adma mode, need to have a cleaner + * implementation to keep this function independent of sdhci + * limitations + */ + while (data_len > write_size) { + val = mmc_sdhci_write( + Instance->MmcDev, (VOID *)sptr, (data_addr / block_size), + (write_size / block_size)); + if (val) { + DEBUG( + (EFI_D_ERROR, "Failed Writing block @ %x\n", + (UINTN)(data_addr / block_size))); + return val; + } + sptr += write_size; + data_addr += write_size; + data_len -= write_size; + } + + if (data_len) + val = mmc_sdhci_write( + Instance->MmcDev, (VOID *)sptr, (data_addr / block_size), + (data_len / block_size)); + + if (val) + DEBUG( + (EFI_D_ERROR, "Failed Writing block @ %x\n", + (UINTN)(data_addr / block_size))); + + return val; +} + +/* + * Function: mmc_read + * Arg : Data address on card, o/p buffer & data length + * Return : 0 on Success, non zero on failure + * Flow : Read data from the card to out + */ +STATIC UINT32 +mmc_read(BIO_INSTANCE *Instance, UINT64 data_addr, UINT32 *out, UINT32 data_len) +{ + UINT32 ret = 0; + UINT32 block_size; + UINT32 read_size = SDHCI_ADMA_MAX_TRANS_SZ; + UINT8 *sptr = (UINT8 *)out; + + block_size = Instance->BlockMedia.BlockSize; + + ASSERT(!(data_addr % block_size)); + ASSERT(!(data_len % block_size)); + + /* + * dma onto write back memory is unsafe/nonportable, + * but callers to this routine normally provide + * write back buffers. Invalidate cache + * before read data from mmc. + */ + arch_clean_invalidate_cache_range((addr_t)(out), data_len); + + /* TODO: This function is aware of max data that can be + * tranferred using sdhci adma mode, need to have a cleaner + * implementation to keep this function independent of sdhci + * limitations + */ + while (data_len > read_size) { + ret = mmc_sdhci_read( + Instance->MmcDev, (VOID *)sptr, (data_addr / block_size), + (read_size / block_size)); + if (ret) { + DEBUG( + (EFI_D_ERROR, "Failed Reading block @ %x\n", + (UINTN)(data_addr / block_size))); + return ret; + } + sptr += read_size; + data_addr += read_size; + data_len -= read_size; + } + + if (data_len) + ret = mmc_sdhci_read( + Instance->MmcDev, (VOID *)sptr, (data_addr / block_size), + (data_len / block_size)); + + if (ret) + DEBUG( + (EFI_D_ERROR, "Failed Reading block @ %x\n", + (UINTN)(data_addr / block_size))); + + return ret; +} + +EFI_STATUS +EFIAPI +MMCHSReset(IN EFI_BLOCK_IO_PROTOCOL *This, IN BOOLEAN ExtendedVerification) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MMCHSReadBlocks( + IN EFI_BLOCK_IO_PROTOCOL *This, IN UINT32 MediaId, IN EFI_LBA Lba, + IN UINTN BufferSize, OUT VOID *Buffer) +{ + BIO_INSTANCE * Instance; + EFI_BLOCK_IO_MEDIA *Media; + EFI_TPL OldTpl; + UINTN BlockSize; + UINTN RC; + + Instance = BIO_INSTANCE_FROM_BLOCKIO_THIS(This); + Media = &Instance->BlockMedia; + BlockSize = Media->BlockSize; + + if (MediaId != Media->MediaId) { + return EFI_MEDIA_CHANGED; + } + + if (Lba > Media->LastBlock) { + return EFI_INVALID_PARAMETER; + } + + if ((Lba + (BufferSize / BlockSize) - 1) > Media->LastBlock) { + return EFI_INVALID_PARAMETER; + } + + if (BufferSize % BlockSize != 0) { + return EFI_BAD_BUFFER_SIZE; + } + + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (BufferSize == 0) { + return EFI_SUCCESS; + } + + OldTpl = gBS->RaiseTPL(TPL_NOTIFY); + RC = mmc_read(Instance, (UINT64)Lba * BlockSize, Buffer, BufferSize); + gBS->RestoreTPL(OldTpl); + + if (RC == 0) + return EFI_SUCCESS; + else + return EFI_DEVICE_ERROR; +} + +EFI_STATUS +EFIAPI +MMCHSWriteBlocks( + IN EFI_BLOCK_IO_PROTOCOL *This, IN UINT32 MediaId, IN EFI_LBA Lba, + IN UINTN BufferSize, IN VOID *Buffer) +{ + BIO_INSTANCE * Instance; + EFI_BLOCK_IO_MEDIA *Media; + UINTN BlockSize; + UINTN RC; + EFI_TPL OldTpl; + + Instance = BIO_INSTANCE_FROM_BLOCKIO_THIS(This); + Media = &Instance->BlockMedia; + BlockSize = Media->BlockSize; + + if (MediaId != Media->MediaId) { + return EFI_MEDIA_CHANGED; + } + + if (Lba > Media->LastBlock) { + return EFI_INVALID_PARAMETER; + } + + if ((Lba + (BufferSize / BlockSize) - 1) > Media->LastBlock) { + return EFI_INVALID_PARAMETER; + } + + if (BufferSize % BlockSize != 0) { + return EFI_BAD_BUFFER_SIZE; + } + + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (BufferSize == 0) { + return EFI_SUCCESS; + } + + // Here goes a fail-safe design (see issue #5) + // Assume the partition layout before partition 36 is identical on our target + // devices + // Only slot 1 (eMMC) is protected + if (Instance->MmcDev->config.slot <= 1 && (0 <= Lba && Lba <= 253951)) { + return EFI_UNSUPPORTED; + } + + OldTpl = gBS->RaiseTPL(TPL_NOTIFY); + RC = mmc_write(Instance, (UINT64)Lba * BlockSize, BufferSize, Buffer); + gBS->RestoreTPL(OldTpl); + + if (RC == 0) + return EFI_SUCCESS; + else + return EFI_DEVICE_ERROR; +} + +EFI_STATUS +EFIAPI +MMCHSFlushBlocks(IN EFI_BLOCK_IO_PROTOCOL *This) +{ + // Nothing required + return EFI_SUCCESS; +} + +VOID EFIAPI MMCHSExitBsUninit(IN EFI_EVENT Event, IN VOID *Context) +{ + EFI_TPL OldTpl; + + BIO_INSTANCE *Instance = (BIO_INSTANCE *)Context; + ASSERT(Instance != NULL); + + OldTpl = gBS->RaiseTPL(TPL_NOTIFY); + + // Put card into sleep + mmc_put_card_to_sleep(Instance->MmcDev); + + gBS->RestoreTPL(OldTpl); +} + +EFI_STATUS +BioInstanceContructor(OUT BIO_INSTANCE **NewInstance) +{ + BIO_INSTANCE *Instance; + + Instance = AllocateCopyPool(sizeof(BIO_INSTANCE), &mBioTemplate); + if (Instance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Instance->BlockIo.Media = &Instance->BlockMedia; + + *NewInstance = Instance; + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MMCHSInitialize(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable) +{ + // let the target register MMC devices + LibQcomTargetMmcSdhciInit(PlatformCallbackInitSlot); + + return EFI_SUCCESS; +} diff --git a/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/MMCHS.h b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/MMCHS.h new file mode 100755 index 0000000..1f85d16 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/MMCHS.h @@ -0,0 +1,127 @@ +#ifndef _MMCHS_H_ +#define _MMCHS_H_ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +//#include "mmc_p.h" + +// +// Device structures +// +typedef struct { + VENDOR_DEVICE_PATH Mmc; + EFI_DEVICE_PATH End; +} MMCHS_DEVICE_PATH; + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + EFI_BLOCK_IO_PROTOCOL BlockIo; + EFI_BLOCK_IO_MEDIA BlockMedia; + MMCHS_DEVICE_PATH DevicePath; + struct mmc_device * MmcDev; + EFI_EVENT ExitBsEvent; +} BIO_INSTANCE; + +#define BIO_INSTANCE_SIGNATURE SIGNATURE_32('e', 'm', 'm', 'c') + +#define BIO_INSTANCE_FROM_BLOCKIO_THIS(a) \ + CR(a, BIO_INSTANCE, BlockIo, BIO_INSTANCE_SIGNATURE) + +#ifdef DEBUG_SDHCI +#define DBG(...) dprintf(ALWAYS, __VA_ARGS__) +#else +#define DBG(...) +#endif + +// +// Function Prototypes +// + +EFI_STATUS +EFIAPI +MMCHSReset(IN EFI_BLOCK_IO_PROTOCOL *This, IN BOOLEAN ExtendedVerification); + +EFI_STATUS +EFIAPI +MMCHSReadBlocks( + IN EFI_BLOCK_IO_PROTOCOL *This, IN UINT32 MediaId, IN EFI_LBA Lba, + IN UINTN BufferSize, OUT VOID *Buffer); + +EFI_STATUS +EFIAPI +MMCHSWriteBlocks( + IN EFI_BLOCK_IO_PROTOCOL *This, IN UINT32 MediaId, IN EFI_LBA Lba, + IN UINTN BufferSize, IN VOID *Buffer); + +EFI_STATUS +EFIAPI +MMCHSFlushBlocks(IN EFI_BLOCK_IO_PROTOCOL *This); + +EFI_STATUS +BioInstanceContructor(OUT BIO_INSTANCE **NewInstance); + +VOID EFIAPI MMCHSExitBsUninit(IN EFI_EVENT Event, IN VOID *Context); + +/* API: to initialize the controller */ +void sdhci_init(struct sdhci_host *); +/* API: Send the command & transfer data using adma */ +uint32_t sdhci_send_command(struct sdhci_host *, struct mmc_command *); +/* API: Set the bus width for the contoller */ +uint8_t sdhci_set_bus_width(struct sdhci_host *, uint16_t); +/* API: Clock supply for the controller */ +uint32_t sdhci_clk_supply(struct sdhci_host *, uint32_t); +/* API: To enable SDR/DDR mode */ +void sdhci_set_uhs_mode(struct sdhci_host *, uint32_t); +/* API: Soft reset for the controller */ +void sdhci_reset(struct sdhci_host *host, uint8_t mask); + +/* + * APIS exposed to block level driver + */ +/* API: Initialize the mmc card */ +struct mmc_device *mmc_init(struct mmc_config_data *); +/* API: Read required number of blocks from card into destination */ +uint32_t mmc_sdhci_read( + struct mmc_device *dev, void *dest, uint64_t blk_addr, uint32_t num_blocks); +/* API: Write requried number of blocks from source to card */ +uint32_t mmc_sdhci_write( + struct mmc_device *dev, void *src, uint64_t blk_addr, uint32_t num_blocks); +/* API: Erase len bytes (after converting to number of erase groups), from + * specified address */ +uint32_t +mmc_sdhci_erase(struct mmc_device *dev, uint32_t blk_addr, uint64_t len); +/* API: Write protect or release len bytes (after converting to number of write + * protect groups) from specified start address*/ +uint32_t mmc_set_clr_power_on_wp_user( + struct mmc_device *dev, uint32_t addr, uint64_t len, uint8_t set_clr); +/* API: Get the WP status of write protect groups starting at addr */ +uint32_t +mmc_get_wp_status(struct mmc_device *dev, uint32_t addr, uint8_t *wp_status); +/* API: Put the mmc card in sleep mode */ +void mmc_put_card_to_sleep(struct mmc_device *dev); +/* API: Change the driver type of the card */ +bool mmc_set_drv_type( + struct sdhci_host *host, struct mmc_card *card, uint8_t drv_type); +/* API: Send the read & write command sequence to rpmb */ +uint32_t mmc_sdhci_rpmb_send(struct mmc_device *dev, struct mmc_command *cmd); +/* API: De-init the card */ +void mmc_put_card_to_sleep_disable_hc(struct mmc_device *dev); + +#endif diff --git a/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/SdhciMMCHS.inf b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/SdhciMMCHS.inf new file mode 100755 index 0000000..d8663ce --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/SdhciMMCHS.inf @@ -0,0 +1,58 @@ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MMCHS + FILE_GUID = 891F2B63-4ED3-4305-A660-016D02810541 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = MMCHSInitialize + + +[Sources.common] + MMCHS.c + mmc_sdhci.c + sdhci.c + sdhci_msm.c + +#[Packages] +# MdePkg/MdePkg.dec +# ArmPkg/ArmPkg.dec +# EmbeddedPkg/EmbeddedPkg.dec +# Lumia950XLPkg/Lumia950XLPkg.dec + +[LibraryClasses] + UefiLib + UefiDriverEntryPoint + ArmLib + IoLib + TimerLib + #LcmLib + #MallocLib + CacheMaintenanceLib + #InterruptsLib + #QcomPlatformMmcLib + #QcomTargetMmcSdhciLib + +[BuildOptions.AARCH64] + GCC:*_*_*_CC_FLAGS = -Wno-pointer-to-int-cast + +[Protocols] + gEfiBlockIoProtocolGuid + gEfiDevicePathProtocolGuid + +[Guids] + gEfiEventVirtualAddressChangeGuid + gEfiEventExitBootServicesGuid + +[FeaturePcd] + gQcomTokenSpaceGuid.PcdMmcHs200Caps + +[Pcd.common] + gQcomTokenSpaceGuid.PcdSdccMciHcMode + gQcomTokenSpaceGuid.PcdSdccHcPwrctlStatusReg + gQcomTokenSpaceGuid.PcdSdccHcPwrctlMaskReg + gQcomTokenSpaceGuid.PcdSdccHcPwrctlClearReg + gQcomTokenSpaceGuid.PcdSdccHcPwrctlCtlReg + gQcomTokenSpaceGuid.PcdMmcSdhciDdrCfgVal + +[Depex] + TRUE diff --git a/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/Source.txt b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/Source.txt new file mode 100755 index 0000000..3e2963c --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/Source.txt @@ -0,0 +1,2 @@ +URL: https://source.codeaurora.org/quic/la/kernel/lk +BRANCH: LA.BF64.1.2.3-01510-8x94.0 diff --git a/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/mmc_sdhci.c b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/mmc_sdhci.c new file mode 100755 index 0000000..373fddd --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/mmc_sdhci.c @@ -0,0 +1,2439 @@ +/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include + +#include +// Must come in order +#include + +#include "sdhci_msm.h" +// Must come in order +#include "MMCHS.h" + +/* data access time unit in ns */ +static const uint32_t taac_unit[] = {1, 10, 100, 1000, + 10000, 100000, 1000000, 10000000}; + +/* data access time value x 10 */ +static const uint32_t taac_value[] = {0, 10, 12, 13, 15, 20, 25, 30, + 35, 40, 45, 50, 55, 60, 70, 80}; + +/* data transfer rate in kbit/s */ +static const uint32_t xfer_rate_unit[] = {100, 1000, 10000, 100000, 0, 0, 0, 0}; + +/* data transfer rate value x 10*/ +static const uint32_t xfer_rate_value[] = {0, 10, 12, 13, 15, 20, 26, 30, + 35, 40, 45, 52, 55, 60, 70, 80}; + +/* + * Function: mmc decode and save csd + * Arg : Card structure & raw csd + * Return : 0 on Success, 1 on Failure + * Flow : Decodes CSD response received from the card. + * Note that we have defined only few of the CSD elements + * in csd structure. We'll only decode those values. + */ +static uint32_t mmc_decode_and_save_csd(struct mmc_card *card) +{ + uint32_t mmc_sizeof = 0; + uint32_t mmc_unit = 0; + uint32_t mmc_value = 0; + uint32_t mmc_temp = 0; + uint32_t *raw_csd = card->raw_csd; + + struct mmc_csd mmc_csd; + + mmc_sizeof = sizeof(uint32_t) * 8; + + mmc_csd.cmmc_structure = UNPACK_BITS(raw_csd, 126, 2, mmc_sizeof); + + if (MMC_CARD_SD(card)) { + /* Parse CSD according to SD card spec. */ + + /* CSD register is little bit differnet for CSD version 2.0 High + * Capacity and CSD version 1.0/2.0 Standard memory cards. + * In Version 2.0 some of the fields have fixed values and it's + * not necessary for host to refer these fields in CSD sent by + * card + */ + + if (mmc_csd.cmmc_structure == 1) { + /* CSD Version 2.0 */ + mmc_csd.card_cmd_class = UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof); + /* Fixed value is 9 = 2^9 = 512 */ + mmc_csd.write_blk_len = 512; + /* Fixed value is 9 = 512 */ + mmc_csd.read_blk_len = 512; + /* Fixed value: 010b */ + mmc_csd.r2w_factor = 0x2; + /* Not there in version 2.0 */ + mmc_csd.c_size_mult = 0; + mmc_csd.c_size = UNPACK_BITS(raw_csd, 48, 22, mmc_sizeof); + mmc_csd.nsac_clk_cycle = UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100; + + mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof); + mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof); + mmc_csd.taac_ns = (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10; + + mmc_csd.erase_blk_len = 1; + mmc_csd.read_blk_misalign = 0; + mmc_csd.write_blk_misalign = 0; + mmc_csd.read_blk_partial = 0; + mmc_csd.write_blk_partial = 0; + + mmc_unit = UNPACK_BITS(raw_csd, 96, 3, mmc_sizeof); + mmc_value = UNPACK_BITS(raw_csd, 99, 4, mmc_sizeof); + mmc_csd.tran_speed = + (xfer_rate_value[mmc_value] * xfer_rate_unit[mmc_unit]) / 10; + + mmc_csd.wp_grp_size = 0x0; + mmc_csd.wp_grp_enable = 0x0; + mmc_csd.perm_wp = UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof); + mmc_csd.temp_wp = UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof); + + /* Calculate the card capcity */ + card->capacity = (unsigned long long)(1 + mmc_csd.c_size) * 512 * 1024; + } + else { + /* CSD Version 1.0 */ + mmc_csd.card_cmd_class = UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof); + + mmc_temp = UNPACK_BITS(raw_csd, 22, 4, mmc_sizeof); + mmc_csd.write_blk_len = + (mmc_temp > 8 && mmc_temp < 12) ? (1 << mmc_temp) : 512; + + mmc_temp = UNPACK_BITS(raw_csd, 80, 4, mmc_sizeof); + mmc_csd.read_blk_len = + (mmc_temp > 8 && mmc_temp < 12) ? (1 << mmc_temp) : 512; + + mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof); + mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof); + mmc_csd.taac_ns = (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10; + + mmc_unit = UNPACK_BITS(raw_csd, 96, 3, mmc_sizeof); + mmc_value = UNPACK_BITS(raw_csd, 99, 4, mmc_sizeof); + mmc_csd.tran_speed = + (xfer_rate_value[mmc_value] * xfer_rate_unit[mmc_unit]) / 10; + + mmc_csd.nsac_clk_cycle = UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100; + + mmc_csd.r2w_factor = UNPACK_BITS(raw_csd, 26, 3, mmc_sizeof); + mmc_csd.sector_size = UNPACK_BITS(raw_csd, 39, 7, mmc_sizeof) + 1; + + mmc_csd.erase_blk_len = UNPACK_BITS(raw_csd, 46, 1, mmc_sizeof); + mmc_csd.read_blk_misalign = UNPACK_BITS(raw_csd, 77, 1, mmc_sizeof); + mmc_csd.write_blk_misalign = UNPACK_BITS(raw_csd, 78, 1, mmc_sizeof); + mmc_csd.read_blk_partial = UNPACK_BITS(raw_csd, 79, 1, mmc_sizeof); + mmc_csd.write_blk_partial = UNPACK_BITS(raw_csd, 21, 1, mmc_sizeof); + + mmc_csd.c_size_mult = UNPACK_BITS(raw_csd, 47, 3, mmc_sizeof); + mmc_csd.c_size = UNPACK_BITS(raw_csd, 62, 12, mmc_sizeof); + mmc_csd.wp_grp_size = UNPACK_BITS(raw_csd, 32, 7, mmc_sizeof); + mmc_csd.wp_grp_enable = UNPACK_BITS(raw_csd, 31, 1, mmc_sizeof); + mmc_csd.perm_wp = UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof); + mmc_csd.temp_wp = UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof); + + /* Calculate the card capacity */ + mmc_temp = (1 << (mmc_csd.c_size_mult + 2)) * (mmc_csd.c_size + 1); + card->capacity = (unsigned long long)mmc_temp * mmc_csd.read_blk_len; + } + } + else { + /* Parse CSD according to MMC card spec. */ + mmc_csd.spec_vers = UNPACK_BITS(raw_csd, 122, 4, mmc_sizeof); + mmc_csd.card_cmd_class = UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof); + mmc_csd.write_blk_len = 1 << UNPACK_BITS(raw_csd, 22, 4, mmc_sizeof); + mmc_csd.read_blk_len = 1 << UNPACK_BITS(raw_csd, 80, 4, mmc_sizeof); + mmc_csd.r2w_factor = UNPACK_BITS(raw_csd, 26, 3, mmc_sizeof); + mmc_csd.c_size_mult = UNPACK_BITS(raw_csd, 47, 3, mmc_sizeof); + mmc_csd.c_size = UNPACK_BITS(raw_csd, 62, 12, mmc_sizeof); + mmc_csd.nsac_clk_cycle = UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100; + + mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof); + mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof); + mmc_csd.taac_ns = (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10; + + mmc_csd.read_blk_misalign = UNPACK_BITS(raw_csd, 77, 1, mmc_sizeof); + mmc_csd.write_blk_misalign = UNPACK_BITS(raw_csd, 78, 1, mmc_sizeof); + mmc_csd.read_blk_partial = UNPACK_BITS(raw_csd, 79, 1, mmc_sizeof); + mmc_csd.write_blk_partial = UNPACK_BITS(raw_csd, 21, 1, mmc_sizeof); + + /* Ignore -- no use of this value. */ + mmc_csd.tran_speed = 0x00; + + mmc_csd.erase_grp_size = UNPACK_BITS(raw_csd, 42, 5, mmc_sizeof); + mmc_csd.erase_grp_mult = UNPACK_BITS(raw_csd, 37, 5, mmc_sizeof); + mmc_csd.wp_grp_size = UNPACK_BITS(raw_csd, 32, 5, mmc_sizeof); + mmc_csd.wp_grp_enable = UNPACK_BITS(raw_csd, 31, 1, mmc_sizeof); + mmc_csd.perm_wp = UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof); + mmc_csd.temp_wp = UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof); + + /* Calculate the card capcity */ + if (mmc_csd.c_size != 0xFFF) { + /* For cards less than or equal to 2GB */ + mmc_temp = (1 << (mmc_csd.c_size_mult + 2)) * (mmc_csd.c_size + 1); + card->capacity = (unsigned long long)mmc_temp * mmc_csd.read_blk_len; + } + else { + /* For cards greater than 2GB, Ext CSD register's SEC_COUNT + * is used to calculate the size. + */ + uint64_t sec_count; + + sec_count = (card->ext_csd[MMC_SEC_COUNT4] << MMC_SEC_COUNT4_SHIFT) | + (card->ext_csd[MMC_SEC_COUNT3] << MMC_SEC_COUNT3_SHIFT) | + (card->ext_csd[MMC_SEC_COUNT2] << MMC_SEC_COUNT2_SHIFT) | + card->ext_csd[MMC_SEC_COUNT1]; + card->capacity = sec_count * MMC_BLK_SZ; + } + } + + /* save the information in card structure */ + memcpy( + (struct mmc_csd *)&card->csd, (struct mmc_csd *)&mmc_csd, + sizeof(struct mmc_csd)); + + /* Calculate the wp grp size */ + if (MMC_CARD_MMC(card)) { + if (card->ext_csd[MMC_ERASE_GRP_DEF]) + card->wp_grp_size = + MMC_HC_ERASE_MULT * card->ext_csd[MMC_HC_ERASE_GRP_SIZE] / MMC_BLK_SZ; + else + card->wp_grp_size = (card->csd.wp_grp_size + 1) * + (card->csd.erase_grp_size + 1) * + (card->csd.erase_grp_mult + 1); + + card->rpmb_size = RPMB_PART_MIN_SIZE * card->ext_csd[RPMB_SIZE_MULT]; + card->rel_wr_count = card->ext_csd[REL_WR_SEC_C]; + } + + dprintf(SPEW, "Decoded CSD fields:\n"); + dprintf(SPEW, "cmmc_structure: %u\n", mmc_csd.cmmc_structure); + dprintf(SPEW, "card_cmd_class: %x\n", mmc_csd.card_cmd_class); + dprintf(SPEW, "write_blk_len: %u\n", mmc_csd.write_blk_len); + dprintf(SPEW, "read_blk_len: %u\n", mmc_csd.read_blk_len); + dprintf(SPEW, "r2w_factor: %u\n", mmc_csd.r2w_factor); + dprintf(SPEW, "sector_size: %u\n", mmc_csd.sector_size); + dprintf(SPEW, "c_size_mult:%u\n", mmc_csd.c_size_mult); + dprintf(SPEW, "c_size: %u\n", mmc_csd.c_size); + dprintf(SPEW, "nsac_clk_cycle: %u\n", mmc_csd.nsac_clk_cycle); + dprintf(SPEW, "taac_ns: %u\n", mmc_csd.taac_ns); + dprintf(SPEW, "tran_speed: %u kbps\n", mmc_csd.tran_speed); + dprintf(SPEW, "erase_blk_len: %u\n", mmc_csd.erase_blk_len); + dprintf(SPEW, "read_blk_misalign: %u\n", mmc_csd.read_blk_misalign); + dprintf(SPEW, "write_blk_misalign: %u\n", mmc_csd.write_blk_misalign); + dprintf(SPEW, "read_blk_partial: %u\n", mmc_csd.read_blk_partial); + dprintf(SPEW, "write_blk_partial: %u\n", mmc_csd.write_blk_partial); + dprintf(SPEW, "wp_grp_size: %u\n", card->wp_grp_size); + dprintf(SPEW, "Card Capacity: %llu Bytes\n", card->capacity); + + return 0; +} + +/* + * Function: mmc decode & save cid + * Arg : card structure & raw cid + * Return : 0 on Success, 1 on Failure + * Flow : Decode CID sent by the card. + */ +static uint32_t +mmc_decode_and_save_cid(struct mmc_card *card, uint32_t *raw_cid) +{ + struct mmc_cid mmc_cid; + uint32_t mmc_sizeof = 0; + int i = 0; + + if (!raw_cid) { + return 1; + } + + mmc_sizeof = sizeof(uint32_t) * 8; + + if (MMC_CARD_SD(card)) { + mmc_cid.mid = UNPACK_BITS(raw_cid, 120, 8, mmc_sizeof); + mmc_cid.oid = UNPACK_BITS(raw_cid, 104, 16, mmc_sizeof); + + for (i = 0; i < 5; i++) { + mmc_cid.pnm[i] = + (uint8_t)UNPACK_BITS(raw_cid, (104 - 8 * (i + 1)), 8, mmc_sizeof); + } + mmc_cid.pnm[5] = 0; + mmc_cid.pnm[6] = 0; + + mmc_cid.prv = UNPACK_BITS(raw_cid, 56, 8, mmc_sizeof); + mmc_cid.psn = UNPACK_BITS(raw_cid, 24, 32, mmc_sizeof); + mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof); + mmc_cid.year = UNPACK_BITS(raw_cid, 12, 8, mmc_sizeof); + mmc_cid.year += 2000; + } + else { + mmc_cid.mid = UNPACK_BITS(raw_cid, 120, 8, mmc_sizeof); + mmc_cid.oid = UNPACK_BITS(raw_cid, 104, 16, mmc_sizeof); + + for (i = 0; i < 6; i++) { + mmc_cid.pnm[i] = + (uint8_t)UNPACK_BITS(raw_cid, (104 - 8 * (i + 1)), 8, mmc_sizeof); + } + mmc_cid.pnm[6] = 0; + + mmc_cid.prv = UNPACK_BITS(raw_cid, 48, 8, mmc_sizeof); + mmc_cid.psn = UNPACK_BITS(raw_cid, 16, 32, mmc_sizeof); + mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof); + mmc_cid.year = UNPACK_BITS(raw_cid, 12, 4, mmc_sizeof); + mmc_cid.year += 1997; + } + + /* save it in card database */ + memcpy( + (struct mmc_cid *)&card->cid, (struct mmc_cid *)&mmc_cid, + sizeof(struct mmc_cid)); + + dprintf(SPEW, "Decoded CID fields:\n"); + dprintf(SPEW, "Manufacturer ID: %x\n", mmc_cid.mid); + dprintf(SPEW, "OEM ID: 0x%x\n", mmc_cid.oid); + dprintf(SPEW, "Product Name: %s\n", mmc_cid.pnm); + dprintf( + SPEW, "Product revision: %d.%d\n", (mmc_cid.prv >> 4), + (mmc_cid.prv & 0xF)); + dprintf(SPEW, "Product serial number: %X\n", mmc_cid.psn); + dprintf(SPEW, "Manufacturing date: %d %d\n", mmc_cid.month, mmc_cid.year); + + return 0; +} + +/* + * Function: mmc reset cards + * Arg : host structure + * Return : 0 on Success, 1 on Failure + * Flow : Reset all the cards to idle condition (CMD 0) + */ +static uint8_t mmc_reset_card(struct sdhci_host *host) +{ + struct mmc_command cmd; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + cmd.cmd_index = CMD0_GO_IDLE_STATE; + cmd.argument = 0; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_NONE; + + /* send command */ + return sdhci_send_command(host, &cmd); +} + +/* + * Function: mmc operations command + * Arg : host & card structure + * Return : 0 on Success, 1 on Failure + * Flow : Send CMD1 to know whether the card supports host VDD profile or + * not. + */ +static uint32_t mmc_send_op_cond(struct sdhci_host *host, struct mmc_card *card) +{ + struct mmc_command cmd; + uint32_t mmc_resp = 0; + uint32_t mmc_ret = 0; + uint32_t mmc_retry = 0; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* CMD1 format: + * [31] Busy bit + * [30:29] Access mode + * [28:24] reserved + * [23:15] 2.7-3.6 + * [14:8] 2.0-2.6 + * [7] 1.7-1.95 + * [6:0] reserved + */ + + cmd.cmd_index = CMD1_SEND_OP_COND; + cmd.argument = card->ocr; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R3; + + do { + mmc_ret = sdhci_send_command(host, &cmd); + if (mmc_ret) + return mmc_ret; + + /* Command returned success, now it's time to examine response */ + mmc_resp = cmd.resp[0]; + + /* Check the response for busy status */ + if (!(mmc_resp & MMC_OCR_BUSY)) { + mmc_retry++; + gBS->Stall(1000); + continue; + } + else + break; + } while (mmc_retry < MMC_MAX_COMMAND_RETRY); + + /* If we reached here after max retries, we failed to get OCR */ + if (mmc_retry == MMC_MAX_COMMAND_RETRY && !(mmc_resp & MMC_OCR_BUSY)) { + dprintf(CRITICAL, "Card has busy status set. Init did not complete\n"); + return 1; + } + + /* Response contains card's ocr. Update card's information */ + card->ocr = mmc_resp; + + if (mmc_resp & MMC_OCR_SEC_MODE) + card->type = MMC_TYPE_MMCHC; + else + card->type = MMC_TYPE_STD_MMC; + + return 0; +} + +/* + * Function: mmc send cid + * Arg : host & card structure + * Return : 0 on Success, 1 on Failure + * Flow : Request any card to send its uniquie card identification + * (CID) number (CMD2). + */ +static uint32_t mmc_all_send_cid(struct sdhci_host *host, struct mmc_card *card) +{ + struct mmc_command cmd; + uint32_t mmc_ret = 0; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* CMD2 Format: + * [31:0] stuff bits + */ + cmd.cmd_index = CMD2_ALL_SEND_CID; + cmd.argument = 0; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R2; + + /* send command */ + mmc_ret = sdhci_send_command(host, &cmd); + if (mmc_ret) { + return mmc_ret; + } + + /* Response contains card's 128 bits CID register */ + mmc_ret = mmc_decode_and_save_cid(card, cmd.resp); + if (mmc_ret) { + return mmc_ret; + } + + return 0; +} + +/* + * Function: mmc send relative address + * Arg : host & card structure + * Return : 0 on Success, 1 on Failure + * Flow : Ask card to send it's relative card address (RCA). + * This RCA number is shorter than CID and is used by + * the host to address the card in future (CMD3) + */ +static uint32_t +mmc_send_relative_address(struct sdhci_host *host, struct mmc_card *card) +{ + struct mmc_command cmd; + uint32_t mmc_ret = 0; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* CMD3 Format: + * [31:0] stuff bits + */ + if (MMC_CARD_SD(card)) { + cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR; + cmd.argument = 0; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R6; + + /* send command */ + mmc_ret = sdhci_send_command(host, &cmd); + if (mmc_ret) + return mmc_ret; + + /* For sD, card will send RCA. Store it */ + card->rca = (cmd.resp[0] >> 16); + } + else { + cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR; + cmd.argument = (MMC_RCA << 16); + card->rca = (cmd.argument >> 16); + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R6; + + /* send command */ + mmc_ret = sdhci_send_command(host, &cmd); + if (mmc_ret) + return mmc_ret; + } + + return 0; +} + +/* + * Function: mmc send csd + * Arg : host, card structure & o/p arg to store csd + * Return : 0 on Success, 1 on Failure + * Flow : Requests card to send it's CSD register's contents. (CMD9) + */ +static uint32_t mmc_send_csd(struct sdhci_host *host, struct mmc_card *card) +{ + struct mmc_command cmd; + uint32_t mmc_arg = 0; + uint32_t mmc_ret = 0; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* CMD9 Format: + * [31:16] RCA + * [15:0] stuff bits + */ + mmc_arg |= card->rca << 16; + + cmd.cmd_index = CMD9_SEND_CSD; + cmd.argument = mmc_arg; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R2; + + /* send command */ + mmc_ret = sdhci_send_command(host, &cmd); + if (mmc_ret) + return mmc_ret; + + /* response contains the card csd */ + memcpy(card->raw_csd, cmd.resp, sizeof(cmd.resp)); + + return 0; +} + +/* + * Function: mmc select card + * Arg : host, card structure + * Return : 0 on Success, 1 on Failure + * Flow : Selects a card by sending CMD7 to the card with its RCA. + * If RCA field is set as 0 ( or any other address ), + * the card will be de-selected. (CMD7) + */ +static uint32_t mmc_select_card(struct sdhci_host *host, struct mmc_card *card) +{ + struct mmc_command cmd; + uint32_t mmc_arg = 0; + uint32_t mmc_ret = 0; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* CMD7 Format: + * [31:16] RCA + * [15:0] stuff bits + */ + mmc_arg |= card->rca << 16; + + cmd.cmd_index = CMD7_SELECT_DESELECT_CARD; + cmd.argument = mmc_arg; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + + /* If we are deselecting card, we do not get response */ + if (card->rca) { + if (MMC_CARD_SD(card)) + cmd.resp_type = SDHCI_CMD_RESP_R1B; + else + cmd.resp_type = SDHCI_CMD_RESP_R1; + } + else + cmd.resp_type = SDHCI_CMD_RESP_NONE; + + /* send command */ + mmc_ret = sdhci_send_command(host, &cmd); + if (mmc_ret) + return mmc_ret; + + return 0; +} + +/* + * Function: mmc get card status + * Arg : host, card structure & o/p argument card status + * Return : 0 on Success, 1 on Failure + * Flow : Get the current status of the card + */ +static uint32_t mmc_get_card_status( + struct sdhci_host *host, struct mmc_card *card, uint32_t *status) +{ + struct mmc_command cmd; + uint32_t mmc_ret = 0; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* CMD13 Format: + * [31:16] RCA + * [15:0] stuff bits + */ + cmd.cmd_index = CMD13_SEND_STATUS; + cmd.argument = card->rca << 16; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + + /* send command */ + mmc_ret = sdhci_send_command(host, &cmd); + if (mmc_ret) + return mmc_ret; + + /* Checking ADDR_OUT_OF_RANGE error in CMD13 response */ + if ((cmd.resp[0] >> 31) & 0x01) + return 1; + + *status = cmd.resp[0]; + return 0; +} + +/* + * Function: mmc get ext csd + * Arg : host, card structure & array to hold ext attributes + * Return : 0 on Success, 1 on Failure + * Flow : Send ext csd command & get the card attributes + */ +static uint32_t mmc_get_ext_csd(struct sdhci_host *host, struct mmc_card *card) +{ + struct mmc_command cmd; + uint32_t mmc_ret = 0; + + card->ext_csd = memalign(CACHE_LINE, ROUNDUP(512, CACHE_LINE)); + + ASSERT(card->ext_csd); + + memset(card->ext_csd, 0, sizeof(card->ext_csd)); + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* CMD8 */ + cmd.cmd_index = CMD8_SEND_EXT_CSD; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + cmd.data.data_ptr = card->ext_csd; + cmd.data.num_blocks = 1; + cmd.data_present = 0x1; + cmd.trans_mode = SDHCI_MMC_READ; + + /* send command */ + mmc_ret = sdhci_send_command(host, &cmd); + if (mmc_ret) + return mmc_ret; + + return mmc_ret; +} + +/* + * Function: mmc switch command + * Arg : Host, card structure, access mode, index & value to be set + * Return : 0 on Success, 1 on Failure + * Flow : Send switch command to the card to set the ext attribute @ index + */ +static uint32_t mmc_switch_cmd( + struct sdhci_host *host, struct mmc_card *card, uint32_t access, + uint32_t index, uint32_t value) +{ + + struct mmc_command cmd; + uint32_t mmc_ret = 0; + uint32_t mmc_status; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* CMD6 Format: + * [31:26] set to 0 + * [25:24] access + * [23:16] index + * [15:8] value + * [7:3] set to 0 + * [2:0] cmd set + */ + cmd.cmd_index = CMD6_SWITCH_FUNC; + cmd.argument |= (access << 24); + cmd.argument |= (index << 16); + cmd.argument |= (value << 8); + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1B; + + mmc_ret = sdhci_send_command(host, &cmd); + if (mmc_ret) { + dprintf(CRITICAL, "CMD6 send failed\n"); + return mmc_ret; + } + + /* Check if the card completed the switch command processing */ + mmc_ret = mmc_get_card_status(host, card, &mmc_status); + if (mmc_ret) { + dprintf(CRITICAL, "Get card status failed\n"); + return mmc_ret; + } + + if (MMC_CARD_STATUS(mmc_status) != MMC_TRAN_STATE) { + dprintf( + CRITICAL, "Switch cmd failed. Card not in tran state %x\n", mmc_status); + mmc_ret = 1; + } + + if (mmc_status & MMC_SWITCH_FUNC_ERR_FLAG) { + dprintf(CRITICAL, "Switch cmd failed. Switch Error.\n"); + mmc_ret = 1; + } + + return mmc_ret; +} + +bool mmc_set_drv_type( + struct sdhci_host *host, struct mmc_card *card, uint8_t drv_type) +{ + uint32_t ret = 0; + bool drv_type_changed = false; + + uint32_t value = ((drv_type << 4) | MMC_HS200_TIMING); + + if (card->ext_csd[MMC_EXT_MMC_DRV_STRENGTH] & (1 << drv_type)) + ret = mmc_switch_cmd( + host, card, MMC_ACCESS_WRITE, MMC_EXT_MMC_HS_TIMING, value); + if (!ret) + drv_type_changed = true; + + return drv_type_changed; +} +/* + * Function: mmc set bus width + * Arg : Host, card structure & width + * Return : 0 on Success, 1 on Failure + * Flow : Send switch command to set bus width + */ +static uint32_t mmc_set_bus_width( + struct sdhci_host *host, struct mmc_card *card, uint32_t width) +{ + uint32_t mmc_ret = 0; + + mmc_ret = mmc_switch_cmd( + host, card, MMC_ACCESS_WRITE, MMC_EXT_MMC_BUS_WIDTH, width); + + if (mmc_ret) { + dprintf(CRITICAL, "Switch cmd failed\n"); + return mmc_ret; + } + + return 0; +} + +/* + * Function: mmc card supports hs400 mode + * Arg : None + * Return : 1 if hs400 mode is supported, 0 otherwise + * Flow : Check the ext csd attributes of the card + */ +static uint8_t mmc_card_supports_hs400_mode(struct mmc_card *card) +{ + if (card->ext_csd[MMC_DEVICE_TYPE] & MMC_HS_HS400_MODE) + return 1; + else + return 0; +} + +/* + * Function: mmc card supports hs200 mode + * Arg : None + * Return : 1 if HS200 mode is supported, 0 otherwise + * Flow : Check the ext csd attributes of the card + */ +static uint8_t mmc_card_supports_hs200_mode(struct mmc_card *card) +{ + if (card->ext_csd[MMC_DEVICE_TYPE] & MMC_HS_HS200_MODE) + return 1; + else + return 0; +} + +/* + * Function: mmc card supports ddr mode + * Arg : None + * Return : 1 if DDR mode is supported, 0 otherwise + * Flow : Check the ext csd attributes of the card + */ +static uint8_t mmc_card_supports_ddr_mode(struct mmc_card *card) +{ + if (card->ext_csd[MMC_DEVICE_TYPE] & MMC_HS_DDR_MODE) + return 1; + else + return 0; +} + +/* + * Function : Enable HS200 mode + * Arg : Host, card structure and bus width + * Return : 0 on Success, 1 on Failure + * Flow : + * - Set the bus width to 4/8 bit SDR as supported by the target & + * host + * - Set the HS_TIMING on ext_csd 185 for the card + */ +static uint32_t mmc_set_hs200_mode( + struct sdhci_host *host, struct mmc_card *card, uint32_t width) +{ + uint32_t mmc_ret = 0; + + DBG("\n Enabling HS200 Mode Start\n"); + + /* Set 4/8 bit SDR bus width */ + mmc_ret = mmc_set_bus_width(host, card, width); + if (mmc_ret) { + dprintf(CRITICAL, "Failure to set wide bus for Card(RCA:%x)\n", card->rca); + return mmc_ret; + } + + /* Setting HS200 in HS_TIMING using EXT_CSD (CMD6) */ + mmc_ret = mmc_switch_cmd( + host, card, MMC_ACCESS_WRITE, MMC_EXT_MMC_HS_TIMING, MMC_HS200_TIMING); + + if (mmc_ret) { + dprintf(CRITICAL, "Switch cmd returned failure %d\n", __LINE__); + return mmc_ret; + } + + /* Enable SDR104 mode in controller */ + sdhci_set_uhs_mode(host, SDHCI_SDR104_MODE); + + /* Run the clock @ 400 Mhz */ + if (host->caps.hs400_support && mmc_card_supports_hs400_mode(card)) { + /* Save the timing value, before changing the clock */ + MMC_SAVE_TIMING(host, MMC_HS400_TIMING); + /* + * Set the MCI_CLK divider before changing the sdcc core + * core clk to ensure card receives no more than 200 MHZ + * clock frequency + */ + sdhci_msm_set_mci_clk(host); + LibQcomPlatformMmcClockConfig(host->msm_host->slot, SDHCI_CLK_400MHZ); + } + + /* Execute Tuning for hs200 mode */ + if ((mmc_ret = sdhci_msm_execute_tuning(host, card, width))) + dprintf(CRITICAL, "Tuning for hs200 failed\n"); + + /* Once the tuning is executed revert back the clock to 200MHZ + * and disable the MCI_CLK divider so that we can use SDHC clock + * divider to supply clock to the card + */ + if (host->timing == MMC_HS400_TIMING) { + MMC_SAVE_TIMING(host, MMC_HS200_TIMING); + sdhci_msm_set_mci_clk(host); + LibQcomPlatformMmcClockConfig(host->msm_host->slot, MMC_CLK_192MHZ); + } + else { + /* Save the timing value, before changing the clock */ + MMC_SAVE_TIMING(host, MMC_HS200_TIMING); + } + + DBG("\n Enabling HS200 Mode Done\n"); + + return mmc_ret; +} + +/* + * Function: mmc set ddr mode + * Arg : Host & card structure + * Return : 0 on Success, 1 on Failure + * Flow : Set bus width for ddr mode & set controller in DDR mode + */ +static uint8_t mmc_set_ddr_mode(struct sdhci_host *host, struct mmc_card *card) +{ + uint8_t mmc_ret = 0; + + DBG("\n Enabling DDR Mode Start\n"); + + /* Set width for 8 bit DDR mode by default */ + mmc_ret = mmc_set_bus_width(host, card, DATA_DDR_BUS_WIDTH_8BIT); + + if (mmc_ret) { + dprintf(CRITICAL, "Failure to set DDR mode for Card(RCA:%x)\n", card->rca); + return mmc_ret; + } + + /* Save the timing value, before changing the clock */ + MMC_SAVE_TIMING(host, SDHCI_DDR50_MODE); + + /* Set the DDR mode in controller */ + sdhci_set_uhs_mode(host, SDHCI_DDR50_MODE); + + DBG("\n Enabling DDR Mode Done\n"); + + return 0; +} + +/* + * Function: mmc set high speed interface + * Arg : Host & card structure + * Return : None + * Flow : Sets the sdcc clock & clock divider in the host controller + * Adjust the interface speed to optimal speed + */ +static uint32_t +mmc_set_hs_interface(struct sdhci_host *host, struct mmc_card *card) +{ + uint32_t mmc_ret = 0; + + /* Setting HS_TIMING in EXT_CSD (CMD6) */ + mmc_ret = mmc_switch_cmd( + host, card, MMC_ACCESS_WRITE, MMC_EXT_MMC_HS_TIMING, MMC_HS_TIMING); + + if (mmc_ret) { + dprintf(CRITICAL, "Switch cmd returned failure %d\n", __LINE__); + return mmc_ret; + } + + /* Save the timing value, before changing the clock */ + MMC_SAVE_TIMING(host, SDHCI_SDR25_MODE); + + /* Set the SDR25 mode in controller */ + sdhci_set_uhs_mode(host, SDHCI_SDR25_MODE); + + return 0; +} + +/* + * Function : Enable HS400 mode + * Arg : Host, card structure and bus width + * Return : 0 on Success, 1 on Failure + * Flow : + * - Set the bus width to 8 bit DDR + * - Set the HS_TIMING on ext_csd 185 for the card + */ +uint32_t mmc_set_hs400_mode( + struct sdhci_host *host, struct mmc_card *card, uint32_t width) +{ + uint32_t mmc_ret = 0; + + /* + * Emmc 5.0 spec does not allow changing to hs400 mode directly + * Need to follow the sequence to change to hs400 mode + * 1. Enable HS200 mode, perform tuning + * 2. Change to high speed mode + * 3. Enable DDR mode + * 4. Enable HS400 mode & execute tuning + */ + + DBG("\n Enabling HS400 Mode Start\n"); + /* HS400 mode is supported only in DDR 8-bit */ + if (width != DATA_BUS_WIDTH_8BIT) { + dprintf( + CRITICAL, "Bus width is not 8-bit, cannot switch to hs400: %u\n", + width); + return 1; + } + + /* 1.Enable HS200 mode */ + mmc_ret = mmc_set_hs200_mode(host, card, width); + + if (mmc_ret) { + dprintf( + CRITICAL, "Failure Setting HS200 mode %s\t%d\n", __func__, __LINE__); + return mmc_ret; + } + + /* 2. Enable High speed mode */ + /* This is needed to set the clock to a low value & + * so that we can switch to hs_timing --> 0x1 */ + /* Save the timing value, before changing the clock */ + MMC_SAVE_TIMING(host, SDHCI_SDR12_MODE); + sdhci_set_uhs_mode(host, SDHCI_SDR12_MODE); + + /* 3. Set HS_TIMING to 0x1 */ + mmc_ret = mmc_set_hs_interface(host, card); + if (mmc_ret) { + dprintf( + CRITICAL, "Error adjusting interface speed!:%s\t%d\n", __func__, + __LINE__); + return mmc_ret; + } + + /*4. Enable DDR mode */ + mmc_ret = mmc_set_ddr_mode(host, card); + if (mmc_ret) { + dprintf(CRITICAL, "Failure setting DDR mode:%s\t%d\n", __func__, __LINE__); + return mmc_ret; + } + + /*5. Set hs400 timing */ + mmc_ret = mmc_switch_cmd( + host, card, MMC_ACCESS_WRITE, MMC_EXT_MMC_HS_TIMING, MMC_HS400_TIMING); + + if (mmc_ret) { + dprintf( + CRITICAL, "Switch cmd returned failure %s\t%d\n", __func__, __LINE__); + return mmc_ret; + } + + /* 6. Enable SDR104 mode in controller */ + /* Save the timing value, before changing the clock */ + MMC_SAVE_TIMING(host, MMC_HS400_TIMING); + sdhci_set_uhs_mode(host, SDHCI_SDR104_MODE); + /* + * Enable HS400 mode + */ + sdhci_msm_set_mci_clk(host); + /* Set the clock back to 400 MHZ */ + LibQcomPlatformMmcClockConfig(host->msm_host->slot, SDHCI_CLK_400MHZ); + + /* 7. Execute Tuning for hs400 mode */ + if ((mmc_ret = sdhci_msm_execute_tuning(host, card, width))) + dprintf(CRITICAL, "Tuning for hs400 failed\n"); + + DBG("\n Enabling HS400 Mode Done\n"); + + return mmc_ret; +} + +/* + * Function: mmc_host_init + * Arg : mmc device structure + * Return : 0 on success, 1 on Failure + * Flow : Initialize the host contoller + * Set the clock rate to 400 KHZ for init + */ +static uint8_t mmc_host_init(struct mmc_device *dev) +{ + uint8_t mmc_ret = 0; + EFI_STATUS Status; + + struct sdhci_host * host; + struct mmc_config_data *cfg; + struct sdhci_msm_data * data; + + EFI_EVENT sdhc_event = (EFI_EVENT)NULL; + + host = &dev->host; + cfg = &dev->config; + + Status = gBS->CreateEvent(0, 0, NULL, NULL, &sdhc_event); + ASSERT_EFI_ERROR(Status); + + host->base = cfg->sdhc_base; + host->sdhc_event = sdhc_event; + host->caps.hs200_support = cfg->hs200_support; + host->caps.hs400_support = cfg->hs400_support; + + data = (struct sdhci_msm_data *)malloc(sizeof(struct sdhci_msm_data)); + ASSERT(data); + + data->sdhc_event = sdhc_event; + data->pwrctl_base = cfg->pwrctl_base; + data->pwr_irq = cfg->pwr_irq; + data->slot = cfg->slot; + data->use_io_switch = cfg->use_io_switch; + + host->msm_host = data; + + /* Initialize any clocks needed for SDC controller */ + LibQcomPlatformMmcClockInit(cfg->slot); + + LibQcomPlatformMmcClockConfig(cfg->slot, cfg->max_clk_rate); + + /* Configure the CDC clocks needed for emmc storage + * we use slot '1' for emmc + */ + if (cfg->slot == 1) + LibQcomPlatformMmcClockConfigCdc(cfg->slot); + + /* + * MSM specific sdhc init + */ + sdhci_msm_init(host, data); + + /* + * Initialize the controller, read the host capabilities + * set power on mode + */ + sdhci_init(host); + + /* Setup initial freq to 400KHz */ + mmc_ret = sdhci_clk_supply(host, SDHCI_CLK_400KHZ); + + return mmc_ret; +} + +/* + * Function: mmc identify card + * Arg : host & card structure + * Return : 0 on Success, 1 on Failure + * Flow : Performs card identification process: + * 1. Get card's unique identification number (CID) + * 2. Get(for sd)/set (for mmc) relative card address (RCA) + * 3. Select the card to put it in TRAN state + */ +static uint32_t +mmc_identify_card(struct sdhci_host *host, struct mmc_card *card) +{ + uint32_t mmc_return = 0; + + /* Ask card to send its unique card identification (CID) number (CMD2) */ + mmc_return = mmc_all_send_cid(host, card); + if (mmc_return) { + dprintf(CRITICAL, "Failure getting card's CID number!\n"); + return mmc_return; + } + + /* Ask card to send a relative card address (RCA) (CMD3) */ + mmc_return = mmc_send_relative_address(host, card); + if (mmc_return) { + dprintf(CRITICAL, "Failure getting card's RCA!\n"); + return mmc_return; + } + + /* Get card's CSD register (CMD9) */ + mmc_return = mmc_send_csd(host, card); + if (mmc_return) { + dprintf(CRITICAL, "Failure getting card's CSD information!\n"); + return mmc_return; + } + + /* Select the card (CMD7) */ + mmc_return = mmc_select_card(host, card); + if (mmc_return) { + dprintf(CRITICAL, "Failure selecting the Card with RCA: %x\n", card->rca); + return mmc_return; + } + + /* Set the card status as active */ + card->status = MMC_STATUS_ACTIVE; + + return 0; +} + +/* + * Function: mmc_reset_card_and_send_op + * Arg : Host & Card structure + * Return : 0 on Success, 1 on Failure + * Flow : Routine to initialize MMC card. It resets a card to idle state, + * verify operating voltage and set the card in ready state. + */ +static uint32_t +mmc_reset_card_and_send_op(struct sdhci_host *host, struct mmc_card *card) +{ + uint32_t mmc_return = 0; + + /* 1. Card Reset - CMD0 */ + mmc_return = mmc_reset_card(host); + if (mmc_return) { + dprintf(CRITICAL, "Failure resetting MMC cards!\n"); + return mmc_return; + } + + /* 2. Card Initialization process */ + + /* + * Send CMD1 to identify and reject cards that do not match host's VDD range + * profile. Cards sends its OCR register in response. + */ + + mmc_return = mmc_send_op_cond(host, card); + + /* OCR is not received, init could not complete */ + if (mmc_return) { + dprintf(CRITICAL, "Failure getting OCR response from MMC Card\n"); + return mmc_return; + } + + return 0; +} + +static uint32_t mmc_send_app_cmd(struct sdhci_host *host, struct mmc_card *card) +{ + struct mmc_command cmd = {0}; + + cmd.cmd_index = CMD55_APP_CMD; + cmd.argument = (card->rca << 16); + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + + if (sdhci_send_command(host, &cmd)) { + dprintf(CRITICAL, "Failed Sending CMD55\n"); + return 1; + } + return 0; +} + +uint32_t mmc_sd_card_init(struct sdhci_host *host, struct mmc_card *card) +{ + uint8_t i; + struct mmc_command cmd; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* Use the SD card RCA 0x0 during init */ + card->rca = SD_CARD_RCA; + + /* Send CMD8 for voltage check*/ + for (i = 0; i < SD_CMD8_MAX_RETRY; i++) { + cmd.cmd_index = CMD8_SEND_IF_COND; + cmd.argument = MMC_SD_HC_VOLT_SUPPLIED; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R7; + + if (sdhci_send_command(host, &cmd)) { + dprintf( + CRITICAL, + "The response for CMD8 does not match the supplied value\n"); + return 1; + } + else { + /* If the command response echos the voltage back */ + if (cmd.resp[0] == MMC_SD_HC_VOLT_SUPPLIED) + break; + } + /* As per SDCC the spec try for max three times with + * 1 ms delay + */ + gBS->Stall(1000); + } + + if (i == SD_CMD8_MAX_RETRY && (cmd.resp[0] != MMC_SD_HC_VOLT_SUPPLIED)) { + dprintf(CRITICAL, "Error: CMD8 response timed out\n"); + return 1; + } + + /* Send ACMD41 for OCR */ + for (i = 0; i < SD_ACMD41_MAX_RETRY; i++) { + /* Send APP_CMD before ACMD41*/ + if (mmc_send_app_cmd(host, card)) { + dprintf(CRITICAL, "Failed sending App command\n"); + return 1; + } + + /* APP_CMD is successful, send ACMD41 now */ + cmd.cmd_index = ACMD41_SEND_OP_COND; + cmd.argument = MMC_SD_OCR | MMC_SD_HC_HCS; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R3; + + if (sdhci_send_command(host, &cmd)) { + dprintf(CRITICAL, "Failure sending ACMD41\n"); + return 1; + } + else { + if (cmd.resp[0] & MMC_SD_DEV_READY) { + if (cmd.resp[0] & (1 << 30)) + card->type = MMC_CARD_TYPE_SDHC; + else + card->type = MMC_CARD_TYPE_STD_SD; + + break; + } + } + /* + * As per SDCC spec try for max 1 second + */ + gBS->Stall(50 * 1000); + } + + if (i == SD_ACMD41_MAX_RETRY && !(cmd.resp[0] & MMC_SD_DEV_READY)) { + dprintf(CRITICAL, "Error: ACMD41 response timed out\n"); + return 1; + } + + return 0; +} + +/* + * Function to read SD card information from SD status + */ +static uint32_t +mmc_sd_get_card_ssr(struct sdhci_host *host, struct mmc_card *card) +{ + void * raw_sd_status; + struct mmc_command cmd = {0}; + uint32_t sd_status[16]; + uint32_t * status = sd_status; + uint32_t au_size; + int i; + int j; + + if (mmc_send_app_cmd(host, card)) { + dprintf(CRITICAL, "Failed sending App command\n"); + return 1; + } + + raw_sd_status = memalign(CACHE_LINE, ROUNDUP(64, CACHE_LINE)); + + cmd.cmd_index = ACMD13_SEND_SD_STATUS; + cmd.argument = 0x0; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + cmd.trans_mode = SDHCI_MMC_READ; + cmd.data_present = 0x1; + cmd.data.data_ptr = raw_sd_status; + cmd.data.num_blocks = 0x1; + cmd.data.blk_sz = 0x40; + + /* send command */ + if (sdhci_send_command(host, &cmd)) { + free(raw_sd_status); + return 1; + } + + memcpy(sd_status, raw_sd_status, sizeof(sd_status)); + + for (i = 15, j = 0; i >= 0; i--, j++) + sd_status[i] = swap_endian32(sd_status[j]); + + au_size = UNPACK_BITS(status, MMC_SD_AU_SIZE_BIT, MMC_SD_AU_SIZE_LEN, 32); + /* Card AU size in sectors */ + card->ssr.au_size = 1 << (au_size + 4); + card->ssr.num_aus = + UNPACK_BITS(status, MMC_SD_ERASE_SIZE_BIT, MMC_SD_ERASE_SIZE_LEN, 32); + + free(raw_sd_status); + + return 0; +} + +/* + * Function to read the SD CARD configuration register + */ +static uint32_t +mmc_sd_get_card_scr(struct sdhci_host *host, struct mmc_card *card) +{ + void * scr_resp; + struct mmc_command cmd = {0}; + uint32_t raw_scr[2]; + + /* Now read the SCR register */ + /* Send APP_CMD before ACMD51*/ + if (mmc_send_app_cmd(host, card)) { + dprintf(CRITICAL, "Failed sending App command\n"); + return 1; + } + + scr_resp = memalign(CACHE_LINE, ROUNDUP(8, CACHE_LINE)); + + cmd.cmd_index = ACMD51_READ_CARD_SCR; + cmd.argument = 0x0; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + cmd.trans_mode = SDHCI_MMC_READ; + cmd.data_present = 0x1; + cmd.data.data_ptr = scr_resp; + cmd.data.num_blocks = 0x1; + cmd.data.blk_sz = 0x8; + + /* send command */ + if (sdhci_send_command(host, &cmd)) { + free(scr_resp); + return 1; + } + + memcpy(raw_scr, scr_resp, sizeof(raw_scr)); + + card->raw_scr[0] = swap_endian32(raw_scr[0]); + card->raw_scr[1] = swap_endian32(raw_scr[1]); + + /* + * Parse & Populate the SCR data as per sdcc spec + */ + card->scr.bus_widths = + (card->raw_scr[0] & SD_SCR_BUS_WIDTH_MASK) >> SD_SCR_BUS_WIDTH; + card->scr.cmd23_support = (card->raw_scr[0] & SD_SCR_CMD23_SUPPORT); + card->scr.sd_spec = + (card->raw_scr[0] & SD_SCR_SD_SPEC_MASK) >> SD_SCR_SD_SPEC; + card->scr.sd3_spec = + (card->raw_scr[0] & SD_SCR_SD_SPEC3_MASK) >> SD_SCR_SD_SPEC3; + + free(scr_resp); + + return 0; +} + +/* + * Function: mmc_set_sd_bus_width + * Arg : host, device structure & width + * Return : 0 on Success, 1 on Failure + * Flow : Set the bus width for the card + */ +uint32_t mmc_sd_set_bus_width( + struct sdhci_host *host, struct mmc_card *card, uint8_t width) +{ + struct mmc_command cmd = {0}; + + /* Send APP_CMD before ACMD6*/ + if (mmc_send_app_cmd(host, card)) { + dprintf(CRITICAL, "Failed sending App command\n"); + return 1; + } + + cmd.cmd_index = ACMD6_SET_BUS_WIDTH; + cmd.argument = (width == DATA_BUS_WIDTH_4BIT) ? (1 << 1) : 0; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + + /* send command */ + if (sdhci_send_command(host, &cmd)) + return 1; + + return 0; +} + +uint32_t mmc_sd_set_hs(struct sdhci_host *host, struct mmc_card *card) +{ + struct mmc_command cmd = {0}; + void * switch_resp; + + switch_resp = memalign(CACHE_LINE, ROUNDUP(64, CACHE_LINE)); + + cmd.cmd_index = CMD6_SWITCH_FUNC; + cmd.argument = MMC_SD_SWITCH_HS; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + cmd.trans_mode = SDHCI_MMC_READ; + cmd.data_present = 0x1; + cmd.data.data_ptr = switch_resp; + cmd.data.num_blocks = 0x1; + cmd.data.blk_sz = 0x40; + + /* send command */ + if (sdhci_send_command(host, &cmd)) { + free(switch_resp); + return 1; + } + + /* Set the SDR25 mode in controller*/ + sdhci_set_uhs_mode(host, SDHCI_SDR25_MODE); + + free(switch_resp); + + return 0; +} + +/* + * Function: mmc_init_card + * Arg : mmc device structure + * Return : 0 on Success, 1 on Failure + * Flow : Performs initialization and identification of eMMC cards connected + * to the host. + */ + +static uint32_t mmc_card_init(struct mmc_device *dev) +{ + uint32_t mmc_return = 0; + uint8_t bus_width = 0; + + struct sdhci_host * host; + struct mmc_card * card; + struct mmc_config_data *cfg; + + host = &dev->host; + card = &dev->card; + cfg = &dev->config; + + /* Initialize MMC card structure */ + card->status = MMC_STATUS_INACTIVE; + + /* TODO: Get the OCR params from target */ + card->ocr = MMC_OCR_27_36 | MMC_OCR_SEC_MODE; + + /* Initialize the internal MMC */ + mmc_return = mmc_reset_card_and_send_op(host, card); + if (mmc_return) { + dprintf(CRITICAL, "MMC card failed to respond, try for SD card\n"); + /* Reset the card & get the OCR */ + mmc_return = mmc_sd_card_init(host, card); + if (mmc_return) { + dprintf(CRITICAL, "Failed to initialize SD card\n"); + return mmc_return; + } + } + + /* Identify (CMD2, CMD3 & CMD9) and select the card (CMD7) */ + mmc_return = mmc_identify_card(host, card); + if (mmc_return) + return mmc_return; + + /* set interface speed */ + if (MMC_CARD_SD(card)) { + mmc_return = mmc_sd_set_hs(host, card); + if (mmc_return) { + dprintf(CRITICAL, "Failed to set HS for SD card\n"); + return mmc_return; + } + } + else { + mmc_return = mmc_set_hs_interface(host, card); + if (mmc_return) { + dprintf(CRITICAL, "Error adjusting interface speed!\n"); + return mmc_return; + } + } + + /* Now get the extended CSD for the card */ + if (MMC_CARD_MMC(card)) { + /* For MMC cards, also get the extended csd */ + mmc_return = mmc_get_ext_csd(host, card); + + if (mmc_return) { + dprintf(CRITICAL, "Failure getting card's ExtCSD information!\n"); + return mmc_return; + } + } + else { + /*Read SCR for sd card */ + if (mmc_sd_get_card_scr(host, card)) { + dprintf(CRITICAL, "Failure getting card's SCR register\n"); + return 1; + } + /* Read SSR for the SD card */ + if (mmc_sd_get_card_ssr(host, card)) { + dprintf(CRITICAL, "Failed to get SSR from the card\n"); + return 1; + } + } + + /* Decode and save the CSD register */ + mmc_return = mmc_decode_and_save_csd(card); + if (mmc_return) { + dprintf(CRITICAL, "Failure decoding card's CSD information!\n"); + return mmc_return; + } + + if (MMC_CARD_MMC(card)) { + /* Set the bus width based on host, target capbilities */ + if (cfg->bus_width == DATA_BUS_WIDTH_8BIT && host->caps.bus_width_8bit) + bus_width = DATA_BUS_WIDTH_8BIT; + /* + * Host contoller by default supports 4 bit & 1 bit mode. + * No need to check for host support here + */ + else if (cfg->bus_width == DATA_BUS_WIDTH_4BIT) + bus_width = DATA_BUS_WIDTH_4BIT; + else + bus_width = DATA_BUS_WIDTH_1BIT; + + /* Set 4/8 bit SDR bus width in controller */ + mmc_return = sdhci_set_bus_width(host, bus_width); + + if (mmc_return) { + dprintf(CRITICAL, "Failed to set bus width for host controller\n"); + return 1; + } + + /* Enable high speed mode in the follwing order: + * 1. HS400 mode if supported by host & card + * 1. HS200 mode if supported by host & card + * 2. DDR mode host, if supported by host & card + * 3. Use normal speed mode with supported bus width + */ + if (host->caps.hs400_support && mmc_card_supports_hs400_mode(card)) { + dprintf(INFO, "SDHC Running in HS400 mode\n"); + mmc_return = mmc_set_hs400_mode(host, card, bus_width); + if (mmc_return) { + dprintf( + CRITICAL, "Failure to set HS400 mode for Card(RCA:%x)\n", + card->rca); + return mmc_return; + } + } + else if ( + (FeaturePcdGet(PcdMmcHs200Caps) && + (host->caps.hs200_support && host->caps.sdr104_support && + mmc_card_supports_hs200_mode(card))) || + (!FeaturePcdGet(PcdMmcHs200Caps) && + (host->caps.sdr104_support && mmc_card_supports_hs200_mode(card)))) { + dprintf(INFO, "SDHC Running in HS200 mode\n"); + mmc_return = mmc_set_hs200_mode(host, card, bus_width); + + if (mmc_return) { + dprintf( + CRITICAL, "Failure to set HS200 mode for Card(RCA:%x)\n", + card->rca); + return mmc_return; + } + } + else if (host->caps.ddr_support && mmc_card_supports_ddr_mode(card)) { + dprintf(INFO, "SDHC Running in DDR mode\n"); + mmc_return = mmc_set_ddr_mode(host, card); + + if (mmc_return) { + dprintf( + CRITICAL, "Failure to set DDR mode for Card(RCA:%x)\n", card->rca); + return mmc_return; + } + } + else { + dprintf(INFO, "SDHC Running in High Speed mode\n"); + /* Set HS_TIMING mode */ + mmc_return = mmc_set_hs_interface(host, card); + if (mmc_return) { + dprintf( + CRITICAL, "Failure to enalbe HS mode for Card(RCA:%x)\n", + card->rca); + return mmc_return; + } + /* Set wide bus mode */ + mmc_return = mmc_set_bus_width(host, card, bus_width); + if (mmc_return) { + dprintf( + CRITICAL, "Failure to set wide bus for Card(RCA:%x)\n", card->rca); + return mmc_return; + } + } + } + else { + /* Check the supported bus width for the card from SCR register */ + if (card->scr.bus_widths & SD_SCR_WIDTH_4BIT) + bus_width = DATA_BUS_WIDTH_4BIT; + else + bus_width = DATA_BUS_WIDTH_1BIT; + + mmc_return = mmc_sd_set_bus_width(host, card, bus_width); + if (mmc_return) { + dprintf(CRITICAL, "Failed to set bus width for the card\n"); + return mmc_return; + } + + /* Set bit SDR bus width in controller */ + mmc_return = sdhci_set_bus_width(host, bus_width); + if (mmc_return) { + dprintf(CRITICAL, "Failed to set bus width for host controller\n"); + return mmc_return; + } + } + + card->block_size = MMC_BLK_SZ; + + /* Enable RST_n_FUNCTION */ + if (MMC_CARD_MMC(card) && !card->ext_csd[MMC_EXT_CSD_RST_N_FUNC]) { + mmc_return = mmc_switch_cmd( + host, card, MMC_SET_BIT, MMC_EXT_CSD_RST_N_FUNC, RST_N_FUNC_ENABLE); + + if (mmc_return) { + dprintf(CRITICAL, "Failed to enable RST_n_FUNCTION\n"); + return mmc_return; + } + } + + return mmc_return; +} + +/* + * Function: mmc display csd + * Arg : None + * Return : None + * Flow : Displays the csd information + */ +static void mmc_display_csd(struct mmc_card *card) +{ + dprintf(SPEW, "erase_grpsize: %d\n", card->csd.erase_grp_size); + dprintf(SPEW, "erase_grpmult: %d\n", card->csd.erase_grp_mult); + dprintf(SPEW, "wp_grpsize: %d\n", card->csd.wp_grp_size); + dprintf(SPEW, "wp_grpen: %d\n", card->csd.wp_grp_enable); + dprintf(SPEW, "perm_wp: %d\n", card->csd.perm_wp); + dprintf(SPEW, "temp_wp: %d\n", card->csd.temp_wp); +} + +/* + * Function: mmc_init + * Arg : MMC configuration data + * Return : Pointer to mmc device + * Flow : Entry point to MMC boot process + * Initialize the sd host controller + * Initialize the mmc card + * Set the clock & high speed mode + */ +struct mmc_device *mmc_init(struct mmc_config_data *data) +{ + uint8_t mmc_ret = 0; + struct mmc_device *dev; + + dev = (struct mmc_device *)malloc(sizeof(struct mmc_device)); + + if (!dev) { + dprintf(CRITICAL, "Error allocating mmc device\n"); + return NULL; + } + + ASSERT(data); + + memcpy((void *)&dev->config, (void *)data, sizeof(struct mmc_config_data)); + + memset((struct mmc_card *)&dev->card, 0, sizeof(struct mmc_card)); + dev->card.slot = data->slot; + + /* Initialize the host & clock */ + dprintf(SPEW, " Initializing MMC host data structure and clock!\n"); + + mmc_ret = mmc_host_init(dev); + if (mmc_ret) { + dprintf(CRITICAL, "Error Initializing MMC host : %u\n", mmc_ret); + return NULL; + } + + /* Initialize and identify cards connected to host */ + mmc_ret = mmc_card_init(dev); + if (mmc_ret) { + dprintf(CRITICAL, "Failed detecting MMC/SDC @ slot%d\n", dev->config.slot); + return NULL; + } + + dprintf(INFO, "Done initialization of the card\n"); + + mmc_display_csd(&dev->card); + + return dev; +} + +static uint32_t mmc_parse_response(uint32_t resp) +{ + /* Trying to write beyond card capacity */ + if (resp & MMC_R1_ADDR_OUT_OF_RANGE) { + dprintf( + CRITICAL, "Attempting to read or write beyond the Device capacity\n"); + return 1; + } + + /* Misaligned address not matching block length */ + if (resp & MMC_R1_ADDR_ERR) { + dprintf( + CRITICAL, + "The misaligned address did not match the block length used\n"); + return 1; + } + + /* Invalid block length */ + if (resp & MMC_R1_BLOCK_LEN_ERR) { + dprintf( + CRITICAL, "The transferred bytes does not match the block length\n"); + return 1; + } + + /* Tried to program write protected block */ + if (resp & MMC_R1_WP_VIOLATION) { + dprintf(CRITICAL, "Attempt to program a write protected block\n"); + return 1; + } + + /* card controller error */ + if (resp & MMC_R1_CC_ERROR) { + dprintf( + CRITICAL, + "Device error occurred, which is not related to the host command\n"); + return 1; + } + + /* Generic error */ + if (resp & MMC_R1_GENERIC_ERR) { + dprintf(CRITICAL, "A generic Device error\n"); + return 1; + } + + /* Finally check for card in TRAN state */ + if (MMC_CARD_STATUS(resp) != MMC_TRAN_STATE) { + dprintf(CRITICAL, "MMC card is not in TRAN state\n"); + return 1; + } + + return 0; +} + +static uint32_t mmc_stop_command(struct mmc_device *dev) +{ + struct mmc_command cmd; + uint32_t mmc_ret = 0; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + cmd.cmd_index = CMD12_STOP_TRANSMISSION; + cmd.argument = (dev->card.rca << 16); + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + + mmc_ret = sdhci_send_command(&dev->host, &cmd); + if (mmc_ret) { + dprintf(CRITICAL, "Failed to send stop command\n"); + return mmc_ret; + } + + /* Response contains 32 bit Card status. + * Parse the errors & provide relevant information */ + + return mmc_parse_response(cmd.resp[0]); +} + +/* + * Function: mmc sdhci read + * Arg : mmc device structure, block address, number of blocks & destination + * Return : 0 on Success, non zero on success + * Flow : Fill in the command structure & send the command + */ +uint32_t mmc_sdhci_read( + struct mmc_device *dev, void *dest, uint64_t blk_addr, uint32_t num_blocks) +{ + uint32_t mmc_ret = 0; + struct mmc_command cmd; + struct mmc_card * card = &dev->card; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* CMD17/18 Format: + * [31:0] Data Address + */ + if (num_blocks == 1) + cmd.cmd_index = CMD17_READ_SINGLE_BLOCK; + else + cmd.cmd_index = CMD18_READ_MULTIPLE_BLOCK; + + /* + * Standard emmc cards use byte mode addressing + * convert the block address to byte address before + * sending the command + */ + if (card->type == MMC_TYPE_STD_MMC) + cmd.argument = blk_addr * card->block_size; + else + cmd.argument = blk_addr; + + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + cmd.trans_mode = SDHCI_MMC_READ; + cmd.data_present = 0x1; + + /* Use CMD23 If card supports CMD23: + * For SD card use the value read from SCR register + * For emmc by default use CMD23. + * Also as per SDCC spec always use CMD23 to stop + * multiblock read/write if UHS (Ultra High Speed) is + * enabled + */ + if (MMC_CARD_SD(card)) + cmd.cmd23_support = dev->card.scr.cmd23_support; + else + cmd.cmd23_support = 0x1; + + cmd.data.data_ptr = dest; + cmd.data.num_blocks = num_blocks; + + /* send command */ + mmc_ret = sdhci_send_command(&dev->host, &cmd); + + /* For multi block read failures send stop command */ + if (mmc_ret && num_blocks > 1) { + return mmc_stop_command(dev); + } + + /* + * Response contains 32 bit Card status. + * Parse the errors & provide relevant information + */ + return mmc_parse_response(cmd.resp[0]); +} + +/* + * Function: mmc sdhci write + * Arg : mmc device structure, block address, number of blocks & source + * Return : 0 on Success, non zero on success + * Flow : Fill in the command structure & send the command + */ +uint32_t mmc_sdhci_write( + struct mmc_device *dev, void *src, uint64_t blk_addr, uint32_t num_blocks) +{ + uint32_t mmc_ret = 0; + struct mmc_command cmd; + struct mmc_card * card = &dev->card; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* CMD24/25 Format: + * [31:0] Data Address + */ + + if (num_blocks == 1) + cmd.cmd_index = CMD24_WRITE_SINGLE_BLOCK; + else + cmd.cmd_index = CMD25_WRITE_MULTIPLE_BLOCK; + + /* + * Standard emmc cards use byte mode addressing + * convert the block address to byte address before + * sending the command + */ + if (card->type == MMC_TYPE_STD_MMC) + cmd.argument = blk_addr * card->block_size; + else + cmd.argument = blk_addr; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + cmd.trans_mode = SDHCI_MMC_WRITE; + + /* Use CMD23 If card supports CMD23: + * For SD card use the value read from SCR register + * For emmc by default use CMD23. + * Also as per SDCC spec always use CMD23 to stop + * multiblock read/write if UHS (Ultra High Speed) is + * enabled + */ + if (MMC_CARD_SD(card)) + cmd.cmd23_support = dev->card.scr.cmd23_support; + else + cmd.cmd23_support = 0x1; + + cmd.data_present = 0x1; + cmd.data.data_ptr = src; + cmd.data.num_blocks = num_blocks; + + /* send command */ + mmc_ret = sdhci_send_command(&dev->host, &cmd); + + /* For multi block write failures send stop command */ + if (mmc_ret && num_blocks > 1) { + return mmc_stop_command(dev); + } + + /* + * Response contains 32 bit Card status. + * Parse the errors & provide relevant information + */ + return mmc_parse_response(cmd.resp[0]); +} + +/* + * Send the erase group start address using CMD35 + */ +static uint32_t +mmc_send_erase_grp_start(struct mmc_device *dev, uint32_t erase_start) +{ + struct mmc_command cmd; + struct mmc_card * card = &dev->card; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + if (MMC_CARD_MMC(card)) + cmd.cmd_index = CMD35_ERASE_GROUP_START; + else + cmd.cmd_index = CMD32_ERASE_WR_BLK_START; + + /* + * Standard emmc cards use byte mode addressing + * convert the block address to byte address before + * sending the command + */ + if (card->type == MMC_TYPE_STD_MMC) + cmd.argument = erase_start * card->block_size; + else + cmd.argument = erase_start; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + + /* send command */ + if (sdhci_send_command(&dev->host, &cmd)) + return 1; + + /* + * CMD35 on failure returns address out of range error + */ + if (MMC_ADDR_OUT_OF_RANGE(cmd.resp[0])) { + dprintf(CRITICAL, "Address for CMD35 is out of range\n"); + return 1; + } + + return 0; +} + +/* + * Send the erase group end address using CMD36 + */ +static uint32_t +mmc_send_erase_grp_end(struct mmc_device *dev, uint32_t erase_end) +{ + struct mmc_command cmd; + struct mmc_card * card = &dev->card; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + if (MMC_CARD_MMC(card)) + cmd.cmd_index = CMD36_ERASE_GROUP_END; + else + cmd.cmd_index = CMD33_ERASE_WR_BLK_END; + + /* + * Standard emmc cards use byte mode addressing + * convert the block address to byte address before + * sending the command + */ + if (card->type == MMC_TYPE_STD_MMC) + cmd.argument = erase_end * card->block_size; + else + cmd.argument = erase_end; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + + /* send command */ + if (sdhci_send_command(&dev->host, &cmd)) + return 1; + + /* + * CMD3 on failure returns address out of range error + */ + if (MMC_ADDR_OUT_OF_RANGE(cmd.resp[0])) { + dprintf(CRITICAL, "Address for CMD36 is out of range\n"); + return 1; + } + + return 0; +} + +/* + * Send the erase CMD38, to erase the selected erase groups + */ +static uint32_t mmc_send_erase(struct mmc_device *dev, uint64_t erase_timeout) +{ + struct mmc_command cmd; + uint32_t status; + uint32_t retry = 0; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + cmd.cmd_index = CMD38_ERASE; + cmd.argument = 0x00000000; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1B; + cmd.cmd_timeout = erase_timeout; + + /* send command */ + if (sdhci_send_command(&dev->host, &cmd)) + return 1; + + do { + if (mmc_get_card_status(&dev->host, &dev->card, &status)) { + dprintf(CRITICAL, "Failed to get card status after erase\n"); + return 1; + } + /* Check if the response of erase command has eras skip status set */ + if (status & MMC_R1_WP_ERASE_SKIP) + dprintf( + CRITICAL, + "Write Protect set for the region, only partial space was erased\n"); + + retry++; + gBS->Stall(1000); + if (retry == MMC_MAX_CARD_STAT_RETRY) { + dprintf( + CRITICAL, + "Card status check timed out after sending erase command\n"); + return 1; + } + } while (!(status & MMC_READY_FOR_DATA) || + (MMC_CARD_STATUS(status) == MMC_PROG_STATE)); + + return 0; +} + +/* + * Function: mmc sdhci erase + * Arg : mmc device structure, block address and length + * Return : 0 on Success, non zero on failure + * Flow : Fill in the command structure & send the command + */ +uint32_t +mmc_sdhci_erase(struct mmc_device *dev, uint32_t blk_addr, uint64_t len) +{ + uint32_t erase_unit_sz = 0; + uint32_t erase_start; + uint32_t erase_end; + uint32_t blk_end; + uint32_t num_erase_grps; + uint64_t erase_timeout = 0; + struct mmc_card *card; + + card = &dev->card; + + /* + * Calculate the erase unit size, + * 1. Based on emmc 4.5 spec for emmc card + * 2. Use SD Card Status info for SD cards + */ + if (MMC_CARD_MMC(card)) { + /* + * Calculate the erase unit size as per the emmc specification v4.5 + */ + if (dev->card.ext_csd[MMC_ERASE_GRP_DEF]) + erase_unit_sz = + (MMC_HC_ERASE_MULT * dev->card.ext_csd[MMC_HC_ERASE_GRP_SIZE]) / + MMC_BLK_SZ; + else + erase_unit_sz = (dev->card.csd.erase_grp_size + 1) * + (dev->card.csd.erase_grp_mult + 1); + } + else + erase_unit_sz = dev->card.ssr.au_size * dev->card.ssr.num_aus; + + /* Convert length in blocks */ + len = len / MMC_BLK_SZ; + + if (len < erase_unit_sz) { + dprintf(CRITICAL, "Requested length is less than min erase group size\n"); + return 1; + } + + /* Calculate erase groups based on the length in blocks */ + num_erase_grps = len / erase_unit_sz; + + /* Start address of the erase range */ + erase_start = blk_addr; + + /* Last address of the erase range */ + erase_end = blk_addr + ((num_erase_grps - 1) * erase_unit_sz); + + /* Boundary check for overlap */ + blk_end = blk_addr + len; + + if (erase_end > blk_end) { + dprintf(CRITICAL, "The erase group overlaps the max requested for erase\n"); + erase_end -= erase_unit_sz; + } + + /* Send CMD35 for erase group start */ + if (mmc_send_erase_grp_start(dev, erase_start)) { + dprintf(CRITICAL, "Failed to send erase grp start address\n"); + return 1; + } + + /* Send CMD36 for erase group end */ + if (mmc_send_erase_grp_end(dev, erase_end)) { + dprintf(CRITICAL, "Failed to send erase grp end address\n"); + return 1; + } + + /* + * As per emmc 4.5 spec section 7.4.27, calculate the erase timeout + * erase_timeout = 300ms * ERASE_TIMEOUT_MULT * num_erase_grps + */ + erase_timeout = + (300 * 1000 * card->ext_csd[MMC_ERASE_TIMEOUT_MULT] * num_erase_grps); + + /* Send CMD38 to perform erase */ + if (mmc_send_erase(dev, erase_timeout)) { + dprintf(CRITICAL, "Failed to erase the specified partition\n"); + return 1; + } + + return 0; +} + +/* + * Function: mmc get wp status + * Arg : mmc device structure, block address and buffer for getting wp + * status Return : 0 on Success, 1 on Failure Flow : Get the WP group status + * by sending CMD31 + */ +uint32_t +mmc_get_wp_status(struct mmc_device *dev, uint32_t addr, uint8_t *wp_status) +{ + struct mmc_command cmd; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + cmd.cmd_index = CMD31_SEND_WRITE_PROT_TYPE; + cmd.argument = addr; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + cmd.trans_mode = SDHCI_MMC_READ; + cmd.data_present = 0x1; + cmd.data.data_ptr = wp_status; + cmd.data.num_blocks = 0x1; + cmd.data.blk_sz = 0x8; + + if (sdhci_send_command(&dev->host, &cmd)) { + dprintf(CRITICAL, "Failed to get status of write protect bits\n"); + return 1; + } + + return 0; +} + +/* + * Function: mmc set/clear WP on user area + * Arg : mmc device structure, block address,len, & flag to set or clear + * Return : 0 on success, 1 on failure + * Flow : Function to set/clear power on write protect on user area + */ + +uint32_t mmc_set_clr_power_on_wp_user( + struct mmc_device *dev, uint32_t addr, uint64_t len, uint8_t set_clr) +{ + struct mmc_command cmd; + struct mmc_card * card = &dev->card; + uint32_t wp_grp_size; + uint32_t status; + uint32_t num_wp_grps; + uint32_t ret; + uint32_t retry = 0; + uint32_t i; + + memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command)); + + /* Convert len into blocks */ + len = len / MMC_BLK_SZ; + wp_grp_size = dev->card.wp_grp_size; + + /* Disable PERM WP */ + ret = mmc_switch_cmd( + &dev->host, &dev->card, MMC_SET_BIT, MMC_USR_WP, MMC_US_PERM_WP_DIS); + + if (ret) { + dprintf(CRITICAL, "Failed to Disable PERM WP\n"); + return ret; + } + + /* Read the default values for user WP */ + ret = mmc_get_ext_csd(&dev->host, &dev->card); + + if (ret) { + dprintf(CRITICAL, "Failed to read ext csd for the card\n"); + return ret; + } + + /* Check if user power on WP is disabled or perm WP is enabled */ + if ((dev->card.ext_csd[MMC_USR_WP] & MMC_US_PWR_WP_DIS) || + (dev->card.ext_csd[MMC_USR_WP] & MMC_US_PERM_WP_EN)) { + dprintf(CRITICAL, "Power on protection is disabled, cannot be set\n"); + return 1; + } + + if (len < wp_grp_size) { + dprintf(CRITICAL, "Length is less than min WP size, WP was not set\n"); + return 1; + } + + /* Set power on USER WP */ + ret = mmc_switch_cmd( + &dev->host, &dev->card, MMC_SET_BIT, MMC_USR_WP, MMC_US_PWR_WP_EN); + + if (ret) { + dprintf(CRITICAL, "Failed to set power on WP for user\n"); + return ret; + } + + num_wp_grps = ROUNDUP(len, wp_grp_size) / wp_grp_size; + + if (set_clr) + cmd.cmd_index = CMD28_SET_WRITE_PROTECT; + else + cmd.cmd_index = CMD29_CLEAR_WRITE_PROTECT; + + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1B; + + for (i = 0; i < num_wp_grps; i++) { + /* + * Standard emmc cards use byte mode addressing + * convert the block address to byte address before + * sending the command + */ + if (card->type == MMC_TYPE_STD_MMC) + cmd.argument = (addr + (i * wp_grp_size)) * card->block_size; + else + cmd.argument = addr + (i * wp_grp_size); + + if (sdhci_send_command(&dev->host, &cmd)) + return 1; + + /* CMD28/CMD29 On failure returns address out of range error */ + if (MMC_ADDR_OUT_OF_RANGE(cmd.resp[0])) { + dprintf(CRITICAL, "Address for CMD28/29 is out of range\n"); + return 1; + } + + /* Check the card status */ + do { + if (mmc_get_card_status(&dev->host, &dev->card, &status)) { + dprintf( + CRITICAL, + "Failed to get card status afterapplying write protect\n"); + return 1; + } + + /* Time out for WP command */ + retry++; + gBS->Stall(1000); + if (retry == MMC_MAX_CARD_STAT_RETRY) { + dprintf( + CRITICAL, + "Card status timed out after sending write protect command\n"); + return 1; + } + } while (!(status & MMC_READY_FOR_DATA) || + (MMC_CARD_STATUS(status) == MMC_PROG_STATE)); + } + + return 0; +} + +/* Function to put the mmc card to sleep and disable HC */ +void mmc_put_card_to_sleep_disable_hc(struct mmc_device *dev) +{ + mmc_put_card_to_sleep(dev); + sdhci_mode_disable(&dev->host); +} + +/* Function to put the mmc card to sleep */ +void mmc_put_card_to_sleep(struct mmc_device *dev) +{ + struct mmc_command cmd = {0}; + struct mmc_card * card = &dev->card; + + cmd.cmd_index = CMD7_SELECT_DESELECT_CARD; + cmd.argument = 0x00000000; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_NONE; + + /* send command */ + if (sdhci_send_command(&dev->host, &cmd)) { + dprintf(CRITICAL, "card deselect error: %s\n", __func__); + return; + } + + cmd.cmd_index = CMD5_SLEEP_AWAKE; + cmd.argument = (card->rca << MMC_CARD_RCA_BIT) | MMC_CARD_SLEEP; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1B; + + /* send command */ + if (sdhci_send_command(&dev->host, &cmd)) + dprintf(CRITICAL, "card sleep error: %s\n", __func__); +} + +/* + * Switch the partition access type to rpmb or default + */ +static uint32_t mmc_sdhci_switch_part(struct mmc_device *dev, uint32_t type) +{ + uint32_t part_access; + uint32_t ret; + + /* Clear the partition access */ + part_access = + dev->card.ext_csd[MMC_PARTITION_CONFIG] & ~PARTITION_ACCESS_MASK; + part_access |= type; + + ret = mmc_switch_cmd( + &dev->host, &dev->card, MMC_ACCESS_WRITE, MMC_PARTITION_CONFIG, + part_access); + + if (ret) { + dprintf(CRITICAL, "Failed to switch partition to type: %u\n", type); + return 1; + } + + dev->card.ext_csd[MMC_PARTITION_CONFIG] = part_access; + return 0; +} + +static uint32_t mmc_sdhci_set_blk_cnt( + struct mmc_device *dev, uint32_t blk_cnt, uint32_t rel_write) +{ + struct mmc_command cmd = {0}; + + cmd.cmd_index = CMD23_SET_BLOCK_COUNT; + cmd.argument = blk_cnt & 0x0000ffff; + cmd.argument |= rel_write; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + + if (sdhci_send_command(&dev->host, &cmd)) { + dprintf(CRITICAL, "Set block count failed: %s\n", __func__); + return 1; + } + + return 0; +} + +uint32_t mmc_sdhci_rpmb_send(struct mmc_device *dev, struct mmc_command *cmd) +{ + int i; + uint32_t retry = 5; + uint32_t status; + uint32_t rel_write = 0; + uint32_t ret = 1; + + ASSERT(cmd); + + /* 1. Set the partition type to rpmb */ + if (mmc_sdhci_switch_part(dev, PART_ACCESS_RPMB)) + return 1; + + for (i = 0; i < MAX_RPMB_CMDS; i++) { + if (!cmd[i].cmd_index) + break; + + if (cmd[i].write_flag == true) + rel_write = BIT(31); + else + rel_write = 0; + + /* 2. Set the block count using cmd23 */ + if (mmc_sdhci_set_blk_cnt(dev, cmd[i].data.num_blocks, rel_write)) + goto err; + + /* 3. Send the command */ + if (sdhci_send_command(&dev->host, &cmd[i])) + goto err; + do { + /* 4. Poll for card status to ensure rpmb operation completeness */ + if (mmc_get_card_status(&dev->host, &dev->card, &status)) { + dprintf(CRITICAL, "Failed to get card status after rpmb operations\n"); + goto err; + } + + retry--; + gBS->Stall(500); + if (!retry) { + dprintf( + CRITICAL, "Card status check timed out after rpmb operations\n"); + goto err; + } + } while (!(status & MMC_READY_FOR_DATA) || + (MMC_CARD_STATUS(status) == MMC_PROG_STATE)); + } + + /* If we reach here, that means success */ + ret = 0; + +err: + /* 5. Switch the partition back to default type */ + if (mmc_sdhci_switch_part(dev, PART_ACCESS_DEFAULT)) + ret = 1; + + return ret; +} diff --git a/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/sdhci.c b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/sdhci.c new file mode 100755 index 0000000..c761676 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/sdhci.c @@ -0,0 +1,969 @@ +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include + +#include + +#include "sdhci_msm.h" +// Must come in order +#include "MMCHS.h" + +static void sdhci_dumpregs(struct sdhci_host *host) +{ + DBG("****************** SDHC REG DUMP START ********************\n"); + + DBG("Version: 0x%08x\n", REG_READ32(host, SDHCI_ARG2_REG)); + DBG("Arg2: 0x%08x\t Blk Cnt: 0x%08x\n", + REG_READ32(host, SDHCI_ARG2_REG), REG_READ16(host, SDHCI_BLK_CNT_REG)); + DBG("Arg1: 0x%08x\t Blk Sz : 0x%08x\n", + REG_READ32(host, SDHCI_ARGUMENT_REG), REG_READ16(host, SDHCI_BLKSZ_REG)); + DBG("Command: 0x%08x\t Trans mode: 0x%08x\n", + REG_READ16(host, SDHCI_CMD_REG), REG_READ16(host, SDHCI_TRANS_MODE_REG)); + DBG("Resp0: 0x%08x\t Resp1: 0x%08x\n", + REG_READ32(host, SDHCI_RESP_REG), REG_READ32(host, SDHCI_RESP_REG + 0x4)); + DBG("Resp2: 0x%08x\t Resp3: 0x%08x\n", + REG_READ32(host, SDHCI_RESP_REG + 0x8), + REG_READ32(host, SDHCI_RESP_REG + 0xC)); + DBG("Prsnt State: 0x%08x\t Host Ctrl1: 0x%08x\n", + REG_READ32(host, SDHCI_PRESENT_STATE_REG), + REG_READ8(host, SDHCI_HOST_CTRL1_REG)); + DBG("Timeout ctrl: 0x%08x\t Power Ctrl: 0x%08x\n", + REG_READ8(host, SDHCI_TIMEOUT_REG), REG_READ8(host, SDHCI_PWR_CTRL_REG)); + DBG("Error stat: 0x%08x\t Int Status: 0x%08x\n", + REG_READ16(host, SDHCI_ERR_INT_STS_REG), + REG_READ16(host, SDHCI_NRML_INT_STS_REG)); + DBG("Host Ctrl2: 0x%08x\t Clock ctrl: 0x%08x\n", + REG_READ16(host, SDHCI_HOST_CTRL2_REG), + REG_READ16(host, SDHCI_CLK_CTRL_REG)); + DBG("Caps1: 0x%08x\t Caps2: 0x%08x\n", + REG_READ32(host, SDHCI_CAPS_REG1), REG_READ32(host, SDHCI_CAPS_REG1)); + DBG("Adma Err: 0x%08x\t Auto Cmd err: 0x%08x\n", + REG_READ8(host, SDHCI_ADM_ERR_REG), REG_READ16(host, SDHCI_AUTO_CMD_ERR)); + DBG("Adma addr1: 0x%08x\t Adma addr2: 0x%08x\n", + REG_READ32(host, SDHCI_ADM_ADDR_REG), + REG_READ32(host, SDHCI_ADM_ADDR_REG + 0x4)); + + DBG("****************** SDHC REG DUMP END ********************\n"); + + DBG("************* SDHC VENDOR REG DUMPS START ***************\n"); + DBG("SDCC_DLL_CONFIG_REG: 0x%08x\n", + REG_READ32(host, SDCC_DLL_CONFIG_REG)); + DBG("SDCC_VENDOR_SPECIFIC_FUNC: 0x%08x\n", + REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC)); + DBG("SDCC_REG_DLL_STATUS: 0x%08x\n", + REG_READ32(host, SDCC_REG_DLL_STATUS)); + DBG("************* SDHC VENDOR REG DUMPS END ***************\n"); +} + +/* + * Function: sdhci reset + * Arg : Host structure & mask to write to reset register + * Return : None + * Flow: : Reset the host controller + */ +void sdhci_reset(struct sdhci_host *host, uint8_t mask) +{ + uint32_t reg; + uint32_t timeout = SDHCI_RESET_MAX_TIMEOUT; + + REG_WRITE8(host, mask, SDHCI_RESET_REG); + + /* Wait for the reset to complete */ + do { + reg = REG_READ8(host, SDHCI_RESET_REG); + reg &= mask; + + if (!reg) + break; + if (!timeout) { + dprintf(CRITICAL, "Error: sdhci reset failed for: %x\n", mask); + break; + } + + timeout--; + gBS->Stall(1000); + + } while (1); +} + +/* + * Function: sdhci error status enable + * Arg : Host structure + * Return : None + * Flow: : Enable command error status + */ +static void sdhci_error_status_enable(struct sdhci_host *host) +{ + /* Enable all interrupt status */ + REG_WRITE16(host, SDHCI_NRML_INT_STS_EN, SDHCI_NRML_INT_STS_EN_REG); + REG_WRITE16(host, SDHCI_ERR_INT_STS_EN, SDHCI_ERR_INT_STS_EN_REG); + /* Enable all interrupt signal */ + REG_WRITE16(host, SDHCI_NRML_INT_SIG_EN, SDHCI_NRML_INT_SIG_EN_REG); + REG_WRITE16(host, SDHCI_ERR_INT_SIG_EN, SDHCI_ERR_INT_SIG_EN_REG); +} + +/* + * Function: sdhci clock supply + * Arg : Host structure + * Return : 0 on Success, 1 on Failure + * Flow: : 1. Calculate the clock divider + * 2. Set the clock divider + * 3. Check if clock stable + * 4. Enable Clock + */ +uint32_t sdhci_clk_supply(struct sdhci_host *host, uint32_t clk) +{ + uint32_t div = 0; + uint32_t freq = 0; + uint16_t clk_val = 0; + + if (clk >= host->caps.base_clk_rate) + goto clk_ctrl; + + /* As per the sd spec div should be a multiplier of 2 */ + for (div = 2; div < SDHCI_CLK_MAX_DIV; div += 2) { + freq = host->caps.base_clk_rate / div; + if (freq <= clk) + break; + } + + div >>= 1; + +clk_ctrl: + /* As per the sdhci spec 3.0, bits 6-7 of the clock + * control registers will be mapped to bit 8-9, to + * support a 10 bit divider value. + * This is needed when the divider value overflows + * the 8 bit range. + */ + clk_val = ((div & SDHCI_SDCLK_FREQ_MASK) << SDHCI_SDCLK_FREQ_SEL); + clk_val |= ((div & SDHC_SDCLK_UP_BIT_MASK) >> SDHCI_SDCLK_FREQ_SEL) + << SDHCI_SDCLK_UP_BIT_SEL; + + clk_val |= SDHCI_INT_CLK_EN; + REG_WRITE16(host, clk_val, SDHCI_CLK_CTRL_REG); + + /* Check for clock stable */ + while (!(REG_READ16(host, SDHCI_CLK_CTRL_REG) & SDHCI_CLK_STABLE)) + ; + + /* Now clock is stable, enable it */ + clk_val = REG_READ16(host, SDHCI_CLK_CTRL_REG); + clk_val |= SDHCI_CLK_EN; + REG_WRITE16(host, clk_val, SDHCI_CLK_CTRL_REG); + + host->cur_clk_rate = clk; + + DBG("\n %s: clock_rate: %d clock_div:0x%08x\n", __func__, clk, div); + + return 0; +} + +/* + * Function: sdhci set bus power + * Arg : Host structure + * Return : None + * Flow: : 1. Set the voltage + * 2. Set the sd power control register + */ +static void sdhci_set_bus_power_on(struct sdhci_host *host) +{ + uint8_t voltage; + + voltage = host->caps.voltage; + + voltage <<= SDHCI_BUS_VOL_SEL; + REG_WRITE8(host, voltage, SDHCI_PWR_CTRL_REG); + + voltage |= SDHCI_BUS_PWR_EN; + + DBG("\n %s: voltage: 0x%02x\n", __func__, voltage); + + REG_WRITE8(host, voltage, SDHCI_PWR_CTRL_REG); +} + +/* + * Function: sdhci set SDR mode + * Arg : Host structure, UHS mode + * Return : None + * Flow: : 1. Disable the clock + * 2. Enable UHS mode + * 3. Enable the clock + * Details : SDR50/SDR104 mode is nothing but HS200 + * mode SDCC spec refers to it as SDR mode + * & emmc spec refers as HS200 mode. + */ +void sdhci_set_uhs_mode(struct sdhci_host *host, uint32_t mode) +{ + uint16_t clk; + uint16_t ctrl = 0; + uint32_t clk_val = 0; + + /* Disable the clock */ + clk = REG_READ16(host, SDHCI_CLK_CTRL_REG); + clk &= ~SDHCI_CLK_EN; + REG_WRITE16(host, clk, SDHCI_CLK_CTRL_REG); + + ctrl = REG_READ16(host, SDHCI_HOST_CTRL2_REG); + + ctrl &= ~SDHCI_UHS_MODE_MASK; + + /* Enable SDR50/SDR104/DDR50 mode */ + switch (mode) { + case SDHCI_SDR104_MODE: + ctrl |= SDHCI_SDR104_MODE_EN; + clk_val = SDHCI_CLK_200MHZ; + break; + case SDHCI_SDR50_MODE: + ctrl |= SDHCI_SDR50_MODE_EN; + clk_val = SDHCI_CLK_100MHZ; + break; + case SDHCI_DDR50_MODE: + ctrl |= SDHCI_DDR50_MODE_EN; + clk_val = SDHCI_CLK_50MHZ; + break; + case SDHCI_SDR25_MODE: + ctrl |= SDHCI_SDR25_MODE_EN; + clk_val = SDHCI_CLK_50MHZ; + break; + case SDHCI_SDR12_MODE_EN: + ctrl |= SDHCI_SDR12_MODE_EN; + clk_val = SDHCI_CLK_25MHZ; + break; + default: + dprintf(CRITICAL, "Error: Invalid UHS mode: %x\n", mode); + ASSERT(0); + }; + + REG_WRITE16(host, ctrl, SDHCI_HOST_CTRL2_REG); + + /* Run the clock back */ + sdhci_clk_supply(host, clk_val); +} + +/* + * Function: sdhci set adma mode + * Arg : Host structure + * Return : None + * Flow: : Set adma mode + */ +static void sdhci_set_adma_mode(struct sdhci_host *host) +{ + /* Select 32 Bit ADMA2 type */ + REG_WRITE8(host, SDHCI_ADMA_32BIT, SDHCI_HOST_CTRL1_REG); +} + +/* + * Function: sdhci set bus width + * Arg : Host & width + * Return : 0 on Sucess, 1 on Failure + * Flow: : Set the bus width for controller + */ +uint8_t sdhci_set_bus_width(struct sdhci_host *host, uint16_t width) +{ + uint16_t reg = 0; + + reg = REG_READ8(host, SDHCI_HOST_CTRL1_REG); + + switch (width) { + case DATA_BUS_WIDTH_8BIT: + width = SDHCI_BUS_WITDH_8BIT; + break; + case DATA_BUS_WIDTH_4BIT: + width = SDHCI_BUS_WITDH_4BIT; + break; + case DATA_BUS_WIDTH_1BIT: + width = SDHCI_BUS_WITDH_1BIT; + break; + default: + dprintf(CRITICAL, "Bus width is invalid: %u\n", width); + return 1; + } + + DBG("\n %s: bus width:0x%04x\n", __func__, width); + + REG_WRITE8(host, (reg | width), SDHCI_HOST_CTRL1_REG); + + return 0; +} + +/* + * Function: sdhci command err status + * Arg : Host structure + * Return : 0 on Sucess, 1 on Failure + * Flow: : Look for error status + */ +static uint8_t sdhci_cmd_err_status(struct sdhci_host *host) +{ + uint32_t err; + + err = REG_READ16(host, SDHCI_ERR_INT_STS_REG); + + if (err & SDHCI_CMD_TIMEOUT_MASK) { + dprintf(CRITICAL, "Error: Command timeout error\n"); + return 1; + } + else if (err & SDHCI_CMD_CRC_MASK) { + dprintf(CRITICAL, "Error: Command CRC error\n"); + return 1; + } + else if (err & SDHCI_CMD_END_BIT_MASK) { + dprintf(CRITICAL, "Error: CMD end bit error\n"); + return 1; + } + else if (err & SDHCI_CMD_IDX_MASK) { + dprintf(CRITICAL, "Error: Command Index error\n"); + return 1; + } + else if (err & SDHCI_DAT_TIMEOUT_MASK) { + dprintf(CRITICAL, "Error: DATA time out error\n"); + return 1; + } + else if (err & SDHCI_DAT_CRC_MASK) { + dprintf(CRITICAL, "Error: DATA CRC error\n"); + return 1; + } + else if (err & SDHCI_DAT_END_BIT_MASK) { + dprintf(CRITICAL, "Error: DATA end bit error\n"); + return 1; + } + else if (err & SDHCI_CUR_LIM_MASK) { + dprintf(CRITICAL, "Error: Current limit error\n"); + return 1; + } + else if (err & SDHCI_AUTO_CMD12_MASK) { + dprintf(CRITICAL, "Error: Auto CMD12 error\n"); + return 1; + } + else if (err & SDHCI_ADMA_MASK) { + dprintf(CRITICAL, "Error: ADMA error\n"); + return 1; + } + + return 0; +} + +/* + * Function: sdhci command complete + * Arg : Host & command structure + * Return : 0 on Sucess, 1 on Failure + * Flow: : 1. Check for command complete + * 2. Check for transfer complete + * 3. Get the command response + * 4. Check for errors + */ +static uint8_t +sdhci_cmd_complete(struct sdhci_host *host, struct mmc_command *cmd) +{ + uint8_t i; + uint8_t ret = 0; + uint8_t need_reset = 0; + uint64_t retry = 0; + uint32_t int_status; + uint32_t trans_complete = 0; + uint32_t err_status; + uint64_t max_trans_retry = + (cmd->cmd_timeout ? cmd->cmd_timeout : SDHCI_MAX_TRANS_RETRY); + + do { + int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG); + + if (int_status & SDHCI_INT_STS_CMD_COMPLETE) + break; + else if (int_status & SDHCI_ERR_INT_STAT_MASK && !host->tuning_in_progress) + goto err; + + /* + * If Tuning is in progress ignore cmd crc, cmd timeout & cmd end bit errors + */ + if (host->tuning_in_progress) { + err_status = REG_READ16(host, SDHCI_ERR_INT_STS_REG); + if ((err_status & SDHCI_CMD_CRC_MASK) || + (err_status & SDHCI_CMD_END_BIT_MASK) || + err_status & SDHCI_CMD_TIMEOUT_MASK) { + sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA)); + return 0; + } + } + + retry++; + gBS->Stall(1); + if (retry == SDHCI_MAX_CMD_RETRY) { + dprintf(CRITICAL, "Error: Command never completed\n"); + ret = 1; + goto err; + } + } while (1); + + /* Command is complete, clear the interrupt bit */ + REG_WRITE16(host, SDHCI_INT_STS_CMD_COMPLETE, SDHCI_NRML_INT_STS_REG); + + /* Copy the command response, + * The valid bits for R2 response are 0-119, & but the actual response + * is stored in bits 8-128. We need to move 8 bits of MSB of each + * response to register 8 bits of LSB of next response register. + * As: + * MSB 8 bits of RESP0 --> LSB 8 bits of RESP1 + * MSB 8 bits of RESP1 --> LSB 8 bits of RESP2 + * MSB 8 bits of RESP2 --> LSB 8 bits of RESP3 + */ + if (cmd->resp_type == SDHCI_CMD_RESP_R2) { + for (i = 0; i < 4; i++) { + cmd->resp[i] = REG_READ32(host, SDHCI_RESP_REG + (i * 4)); + cmd->resp[i] <<= SDHCI_RESP_LSHIFT; + + if (i != 0) + cmd->resp[i] |= + (REG_READ32(host, SDHCI_RESP_REG + ((i - 1) * 4)) >> + SDHCI_RESP_RSHIFT); + } + } + else + cmd->resp[0] = REG_READ32(host, SDHCI_RESP_REG); + + retry = 0; + + /* + * Clear the transfer complete interrupt + */ + if (cmd->data_present || cmd->resp_type == SDHCI_CMD_RESP_R1B) { + do { + int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG); + + if (int_status & SDHCI_INT_STS_TRANS_COMPLETE) { + trans_complete = 1; + break; + } + /* + * Some controllers set the data timout first on issuing an erase & take + * time to set data complete interrupt. We need to wait hoping the + * controller would set data complete + */ + else if ( + int_status & SDHCI_ERR_INT_STAT_MASK && !host->tuning_in_progress && + !((REG_READ16(host, SDHCI_ERR_INT_STS_REG) & SDHCI_DAT_TIMEOUT_MASK))) + goto err; + + /* + * If we are in tuning then we need to wait until Data timeout , Data end + * or Data CRC error + */ + if (host->tuning_in_progress) { + err_status = REG_READ16(host, SDHCI_ERR_INT_STS_REG); + if ((err_status & SDHCI_DAT_TIMEOUT_MASK) || + (err_status & SDHCI_DAT_CRC_MASK)) { + sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA)); + return 0; + } + } + + retry++; + gBS->Stall(1); + if (retry == max_trans_retry) { + dprintf(CRITICAL, "Error: Transfer never completed\n"); + ret = 1; + goto err; + } + } while (1); + + /* Transfer is complete, clear the interrupt bit */ + REG_WRITE16(host, SDHCI_INT_STS_TRANS_COMPLETE, SDHCI_NRML_INT_STS_REG); + } + +err: + /* Look for errors */ + int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG); + + if (int_status & SDHCI_ERR_INT_STAT_MASK) { + /* + * As per SDHC spec transfer complete has higher priority than data timeout + * If both transfer complete & data timeout are set then we should ignore + * data timeout error. + * --------------------------------------------------------------------------- + * | Transfer complete | Data timeout error | Meaning of the Status | + * |--------------------------------------------------------------------------| + * | 0 | 0 | Interrupted by another factor + * | + * |--------------------------------------------------------------------------| + * | 0 | 1 | Time out occured during + * transfer| + * |--------------------------------------------------------------------------| + * | 1 | Don't Care | Command execution complete | + * -------------------------------------------------------------------------- + */ + if ((REG_READ16(host, SDHCI_ERR_INT_STS_REG) & SDHCI_DAT_TIMEOUT_MASK) && + trans_complete) { + ret = 0; + } + else if (sdhci_cmd_err_status(host)) { + ret = 1; + /* Dump sdhc registers on error */ + sdhci_dumpregs(host); + } + /* Reset Command & Dat lines on error */ + need_reset = 1; + } + + /* Reset data & command line */ + if (need_reset) + sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA)); + + return ret; +} + +/* + * Function: sdhci prep desc table + * Arg : Pointer data & length + * Return : Pointer to desc table + * Flow: : Prepare the adma table as per the sd spec v 3.0 + */ +static struct desc_entry *sdhci_prep_desc_table(void *data, uint32_t len) +{ + struct desc_entry *sg_list; + uint32_t sg_len = 0; + uint32_t remain = 0; + uint32_t i; + uint32_t table_len = 0; + + if (len <= SDHCI_ADMA_DESC_LINE_SZ) { + /* Allocate only one descriptor */ + sg_list = (struct desc_entry *)memalign( + lcm(4, CACHE_LINE), ROUNDUP(sizeof(struct desc_entry), CACHE_LINE)); + + if (!sg_list) { + dprintf(CRITICAL, "Error allocating memory\n"); + ASSERT(0); + } + + sg_list[0].addr = (uint32_t)data; + sg_list[0].len = (len < SDHCI_ADMA_DESC_LINE_SZ) + ? len + : (SDHCI_ADMA_DESC_LINE_SZ & 0xffff); + sg_list[0].tran_att = + SDHCI_ADMA_TRANS_VALID | SDHCI_ADMA_TRANS_DATA | SDHCI_ADMA_TRANS_END; + + sg_len = 1; + table_len = sizeof(struct desc_entry); + } + else { + /* Calculate the number of entries in desc table */ + sg_len = len / SDHCI_ADMA_DESC_LINE_SZ; + remain = len - (sg_len * SDHCI_ADMA_DESC_LINE_SZ); + + /* Allocate sg_len + 1 entries if there are remaining bytes at the end */ + if (remain) + sg_len++; + + table_len = (sg_len * sizeof(struct desc_entry)); + + sg_list = (struct desc_entry *)memalign( + lcm(4, CACHE_LINE), ROUNDUP(table_len, CACHE_LINE)); + + if (!sg_list) { + dprintf(CRITICAL, "Error allocating memory\n"); + ASSERT(0); + } + + memset((void *)sg_list, 0, table_len); + + /* + * Prepare sglist in the format: + * ___________________________________________________ + * |Transfer Len | Transfer ATTR | Data Address | + * | (16 bit) | (16 bit) | (32 bit) | + * |_____________|_______________|_____________________| + */ + for (i = 0; i < (sg_len - 1); i++) { + sg_list[i].addr = (uint32_t)data; + /* + * Length attribute is 16 bit value & max transfer size for one + * descriptor line is 65536 bytes, As per SD Spec3.0 'len = 0' + * implies 65536 bytes. Truncate the length to limit to 16 bit + * range. + */ + sg_list[i].len = (SDHCI_ADMA_DESC_LINE_SZ & 0xffff); + sg_list[i].tran_att = SDHCI_ADMA_TRANS_VALID | SDHCI_ADMA_TRANS_DATA; + data += SDHCI_ADMA_DESC_LINE_SZ; + len -= SDHCI_ADMA_DESC_LINE_SZ; + } + + /* Fill the last entry of the table with Valid & End + * attributes + */ + sg_list[sg_len - 1].addr = (uint32_t)data; + sg_list[sg_len - 1].len = (len < SDHCI_ADMA_DESC_LINE_SZ) + ? len + : (SDHCI_ADMA_DESC_LINE_SZ & 0xffff); + sg_list[sg_len - 1].tran_att = + SDHCI_ADMA_TRANS_VALID | SDHCI_ADMA_TRANS_DATA | SDHCI_ADMA_TRANS_END; + } + + arch_clean_invalidate_cache_range((addr_t)sg_list, table_len); + + for (i = 0; i < sg_len; i++) { + DBG("\n %s: sg_list: addr: 0x%08x len: 0x%04x attr: 0x%04x\n", __func__, + sg_list[i].addr, + (sg_list[i].len ? sg_list[i].len : SDHCI_ADMA_DESC_LINE_SZ), + sg_list[i].tran_att); + } + + return sg_list; +} + +/* + * Function: sdhci adma transfer + * Arg : Host structure & command stucture + * Return : Pointer to desc table + * Flow : 1. Prepare descriptor table + * 2. Write adma register + * 3. Write block size & block count register + */ +static struct desc_entry * +sdhci_adma_transfer(struct sdhci_host *host, struct mmc_command *cmd) +{ + uint32_t num_blks = 0; + uint32_t sz; + void * data; + struct desc_entry *adma_addr; + + num_blks = cmd->data.num_blocks; + data = cmd->data.data_ptr; + + /* + * Some commands send data on DAT lines which is less + * than SDHCI_MMC_BLK_SZ, in that case trying to read + * more than the data sent by the card results in data + * CRC errors. To avoid such errors allow data to pass + * the required block size, if the block size is not + * passed use the default value + */ + if (cmd->data.blk_sz) + sz = num_blks * cmd->data.blk_sz; + else + sz = num_blks * SDHCI_MMC_BLK_SZ; + + /* Prepare adma descriptor table */ + adma_addr = sdhci_prep_desc_table(data, sz); + + /* Write adma address to adma register */ + REG_WRITE32(host, (uint32_t)adma_addr, SDHCI_ADM_ADDR_REG); + + /* Write the block size */ + if (cmd->data.blk_sz) + REG_WRITE16(host, cmd->data.blk_sz, SDHCI_BLKSZ_REG); + else + REG_WRITE16(host, SDHCI_MMC_BLK_SZ, SDHCI_BLKSZ_REG); + + /* + * Set block count in block count register + */ + REG_WRITE16(host, num_blks, SDHCI_BLK_CNT_REG); + + return adma_addr; +} + +/* + * Function: sdhci send command + * Arg : Host structure & command stucture + * Return : 0 on Success, 1 on Failure + * Flow: : 1. Prepare the command register + * 2. If data is present, prepare adma table + * 3. Run the command + * 4. Check for command results & take action + */ +uint32_t sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) +{ + uint32_t ret = 0; + uint8_t retry = 0; + uint32_t resp_type = 0; + uint16_t trans_mode = 0; + uint16_t present_state; + uint32_t flags; + struct desc_entry *sg_list = NULL; + + DBG("\n %s: START: cmd:%04d, arg:0x%08x, resp_type:0x%04x, data_present:%d\n", + __func__, cmd->cmd_index, cmd->argument, cmd->resp_type, + cmd->data_present); + + if (cmd->data_present) + ASSERT(cmd->data.data_ptr); + + /* + * Assert if the data buffer is not aligned to cache + * line size for read operations. + * For write operations this function assumes that + * the cache is already flushed by the caller. As + * the data buffer we receive for write operation + * may not be aligned to cache boundary due to + * certain image formats like sparse image. + */ + if (cmd->trans_mode == SDHCI_READ_MODE) + ASSERT(IS_CACHE_LINE_ALIGNED(cmd->data.data_ptr)); + + do { + present_state = REG_READ32(host, SDHCI_PRESENT_STATE_REG); + /* check if CMD & DAT lines are free */ + present_state &= SDHCI_STATE_CMD_DAT_MASK; + + if (!present_state) + break; + gBS->Stall(1000); + retry++; + if (retry == 10) { + dprintf(CRITICAL, "Error: CMD or DAT lines were never freed\n"); + return 1; + } + } while (1); + + switch (cmd->resp_type) { + case SDHCI_CMD_RESP_R1: + case SDHCI_CMD_RESP_R3: + case SDHCI_CMD_RESP_R6: + case SDHCI_CMD_RESP_R7: + /* Response of length 48 have 32 bits + * of response data stored in RESP0[0:31] + */ + resp_type = SDHCI_CMD_RESP_48; + break; + + case SDHCI_CMD_RESP_R2: + /* Response of length 136 have 120 bits + * of response data stored in RESP0[0:119] + */ + resp_type = SDHCI_CMD_RESP_136; + break; + + case SDHCI_CMD_RESP_R1B: + /* Response of length 48 have 32 bits + * of response data stored in RESP0[0:31] + * & set CARD_BUSY status if card is busy + */ + resp_type = SDHCI_CMD_RESP_48_BUSY; + break; + + case SDHCI_CMD_RESP_NONE: + resp_type = SDHCI_CMD_RESP_NONE; + break; + + default: + dprintf(CRITICAL, "Invalid response type for the command\n"); + return 1; + }; + + flags = (resp_type << SDHCI_CMD_RESP_TYPE_SEL_BIT); + flags |= (cmd->data_present << SDHCI_CMD_DATA_PRESENT_BIT); + flags |= (cmd->cmd_type << SDHCI_CMD_CMD_TYPE_BIT); + + /* Enable Command CRC & Index check for commands with response + * R1, R6, R7 & R1B. Also only CRC check for R2 response + */ + switch (cmd->resp_type) { + case SDHCI_CMD_RESP_R1: + case SDHCI_CMD_RESP_R6: + case SDHCI_CMD_RESP_R7: + case SDHCI_CMD_RESP_R1B: + flags |= (1 << SDHCI_CMD_CRC_CHECK_BIT) | (1 << SDHCI_CMD_IDX_CHECK_BIT); + break; + case SDHCI_CMD_RESP_R2: + flags |= (1 << SDHCI_CMD_CRC_CHECK_BIT); + break; + default: + break; + }; + + /* Set the timeout value */ + REG_WRITE8(host, SDHCI_CMD_TIMEOUT, SDHCI_TIMEOUT_REG); + + /* Check if data needs to be processed */ + if (cmd->data_present) + sg_list = sdhci_adma_transfer(host, cmd); + + /* Write the argument 1 */ + REG_WRITE32(host, cmd->argument, SDHCI_ARGUMENT_REG); + + /* Set the Transfer mode */ + if (cmd->data_present) { + /* Enable DMA */ + trans_mode |= SDHCI_DMA_EN; + + if (cmd->trans_mode == SDHCI_MMC_READ) { + trans_mode |= SDHCI_READ_MODE; + if (cmd->cmd_index == CMD21_SEND_TUNING_BLOCK) + sdhci_msm_toggle_cdr(host, false); + else + sdhci_msm_toggle_cdr(host, true); + } + else { + sdhci_msm_toggle_cdr(host, false); + } + + /* Enable auto cmd23 or cmd12 for multi block transfer + * based on what command card supports + */ + if (cmd->data.num_blocks > 1) { + if (cmd->cmd23_support) { + trans_mode |= + SDHCI_TRANS_MULTI | SDHCI_AUTO_CMD23_EN | SDHCI_BLK_CNT_EN; + REG_WRITE32(host, cmd->data.num_blocks, SDHCI_ARG2_REG); + } + else + trans_mode |= + SDHCI_TRANS_MULTI | SDHCI_AUTO_CMD12_EN | SDHCI_BLK_CNT_EN; + } + } + + /* Write to transfer mode register */ + REG_WRITE16(host, trans_mode, SDHCI_TRANS_MODE_REG); + + /* Write the command register */ + REG_WRITE16(host, SDHCI_PREP_CMD(cmd->cmd_index, flags), SDHCI_CMD_REG); + + /* Command complete sequence */ + if (sdhci_cmd_complete(host, cmd)) { + ret = 1; + goto err; + } + + /* Invalidate the cache only for read operations */ + if (cmd->trans_mode == SDHCI_MMC_READ) { + /* Read can be performed on block size < SDHCI_MMC_BLK_SZ, make sure to + * flush the data only for the read size instead + */ + arch_invalidate_cache_range( + (addr_t)cmd->data.data_ptr, + (cmd->data.blk_sz) ? (cmd->data.num_blocks * cmd->data.blk_sz) + : (cmd->data.num_blocks * SDHCI_MMC_BLK_SZ)); + } + + DBG("\n %s: END: cmd:%04d, arg:0x%08x, resp:0x%08x 0x%08x 0x%08x 0x%08x\n", + __func__, cmd->cmd_index, cmd->argument, cmd->resp[0], cmd->resp[1], + cmd->resp[2], cmd->resp[3]); +err: + /* Free the scatter/gather list */ + if (sg_list) + free(sg_list); + + return ret; +} + +/* + * Function: sdhci init + * Arg : Host structure + * Return : None + * Flow: : 1. Reset the controller + * 2. Read the capabilities register & populate the host + * controller capabilities for use by other functions + * 3. Enable the power control + * 4. Set initial bus width + * 5. Set Adma mode + * 6. Enable the error status + */ +void sdhci_init(struct sdhci_host *host) +{ + uint32_t caps[2]; + uint32_t version; + UINTN Index; + EFI_STATUS Status; + + /* Read the capabilities register & store the info */ + caps[0] = REG_READ32(host, SDHCI_CAPS_REG1); + caps[1] = REG_READ32(host, SDHCI_CAPS_REG2); + + DBG("\n %s: Host capability: cap1:0x%08x, cap2: 0x%08x\n", __func__, caps[0], + caps[1]); + + host->caps.base_clk_rate = + (caps[0] & SDHCI_CLK_RATE_MASK) >> SDHCI_CLK_RATE_BIT; + host->caps.base_clk_rate *= 1000000; + + /* Get the max block length for mmc */ + host->caps.max_blk_len = (caps[0] & SDHCI_BLK_LEN_MASK) >> SDHCI_BLK_LEN_BIT; + + /* 8 bit Bus width */ + if (caps[0] & SDHCI_8BIT_WIDTH_MASK) + host->caps.bus_width_8bit = 1; + + /* Adma support */ + if (caps[0] & SDHCI_BLK_ADMA_MASK) + host->caps.adma_support = 1; + + /* Supported voltage */ + if (caps[0] & SDHCI_3_3_VOL_MASK) + host->caps.voltage = SDHCI_VOL_3_3; + else if (caps[0] & SDHCI_3_0_VOL_MASK) + host->caps.voltage = SDHCI_VOL_3_0; + else if (caps[0] & SDHCI_1_8_VOL_MASK) + host->caps.voltage = SDHCI_VOL_1_8; + + /* DDR mode support */ + host->caps.ddr_support = (caps[1] & SDHCI_DDR50_MODE_MASK) ? 1 : 0; + + /* SDR50 mode support */ + host->caps.sdr50_support = (caps[1] & SDHCI_SDR50_MODE_MASK) ? 1 : 0; + + /* SDR104 mode support */ + host->caps.sdr104_support = (caps[1] & SDHCI_SDR104_MODE_MASK) ? 1 : 0; + + version = readl(host->msm_host->pwrctl_base + MCI_VERSION); + + host->major = (version & CORE_VERSION_MAJOR_MASK) >> CORE_VERSION_MAJOR_SHIFT; + host->minor = (version & CORE_VERSION_MINOR_MASK); + + if (host->major == 0x1 && host->minor < 0x34) + host->use_cdclp533 = true; + else + host->use_cdclp533 = false; + + /* Set bus power on */ + sdhci_set_bus_power_on(host); + + /* Wait for power interrupt to be handled */ + Status = gBS->WaitForEvent(1, &host->sdhc_event, &Index); + ASSERT_EFI_ERROR(Status); + + /* Complete */ + gBS->CloseEvent(&host->sdhc_event); + host->sdhc_event = NULL; + host->msm_host->sdhc_event = NULL; + + /* Set bus width */ + sdhci_set_bus_width(host, SDHCI_BUS_WITDH_1BIT); + + /* Set Adma mode */ + sdhci_set_adma_mode(host); + + /* + * Enable error status + */ + sdhci_error_status_enable(host); +} diff --git a/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/sdhci_msm.c b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/sdhci_msm.c new file mode 100755 index 0000000..a4e7e82 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/sdhci_msm.c @@ -0,0 +1,936 @@ +/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include + +#include +// Must come in order +#include + +#include "sdhci_msm.h" +// Must come in order +#include "MMCHS.h" + +/* SDHCI */ +#define SDCC_MCI_HC_MODE ((UINTN)PcdGet64(PcdSdccMciHcMode)) +#define SDCC_HC_PWRCTL_STATUS_REG ((UINTN)PcdGet64(PcdSdccHcPwrctlStatusReg)) +#define SDCC_HC_PWRCTL_MASK_REG ((UINTN)PcdGet64(PcdSdccHcPwrctlMaskReg)) +#define SDCC_HC_PWRCTL_CLEAR_REG ((UINTN)PcdGet64(PcdSdccHcPwrctlClearReg)) +#define SDCC_HC_PWRCTL_CTL_REG ((UINTN)PcdGet64(PcdSdccHcPwrctlCtlReg)) + +#define MX_DRV_SUPPORTED_HS200 3 +static bool attempt_cdr_unlock; + +/* Known data stored in the card & read during tuning + * process. 64 bytes for 4bit bus width & 128 bytes + * of data for 8 bit bus width. + * These values are derived from HPG + */ +static const uint32_t tuning_block_64[] = { + 0x00FF0FFF, 0xCCC3CCFF, 0xFFCC3CC3, 0xEFFEFFFE, 0xDDFFDFFF, 0xFBFFFBFF, + 0xFF7FFFBF, 0xEFBDF777, 0xF0FFF0FF, 0x3CCCFC0F, 0xCFCC33CC, 0xEEFFEFFF, + 0xFDFFFDFF, 0xFFBFFFDF, 0xFFF7FFBB, 0xDE7B7FF7}; + +static const uint32_t tuning_block_128[] = { + 0xFF00FFFF, 0x0000FFFF, 0xCCCCFFFF, 0xCCCC33CC, 0xCC3333CC, 0xFFFFCCCC, + 0xFFFFEEFF, 0xFFEEEEFF, 0xFFDDFFFF, 0xDDDDFFFF, 0xBBFFFFFF, 0xBBFFFFFF, + 0xFFFFFFBB, 0xFFFFFF77, 0x77FF7777, 0xFFEEDDBB, 0x00FFFFFF, 0x00FFFFFF, + 0xCCFFFF00, 0xCC33CCCC, 0x3333CCCC, 0xFFCCCCCC, 0xFFEEFFFF, 0xEEEEFFFF, + 0xDDFFFFFF, 0xDDFFFFFF, 0xFFFFFFDD, 0xFFFFFFBB, 0xFFFFBBBB, 0xFFFF77FF, + 0xFF7777FF, 0xEEDDBB77}; + +/* + * Function: sdhci int handler + * Arg : MSM specific data for sdhci + * Return : 0 + * Flow: : 1. Read the power control mask register + * 2. Check if bus is ON + * 3. Write success to ack regiser + * Details : This is power control interrupt handler. + * Once we receive the interrupt, we will ack the power control + * register that we have successfully completed pmic transactions + */ +static enum handler_return sdhci_int_handler(struct sdhci_msm_data *data) +{ + uint32_t ack; + uint32_t status; + + /* + * Read the mask register to check if BUS & IO level + * interrupts are enabled + */ + status = readl(data->pwrctl_base + SDCC_HC_PWRCTL_MASK_REG); + + if (status & (SDCC_HC_BUS_ON | SDCC_HC_BUS_OFF)) + ack = SDCC_HC_BUS_ON_OFF_SUCC; + if (status & (SDCC_HC_IO_SIG_LOW | SDCC_HC_IO_SIG_HIGH)) + ack |= SDCC_HC_IO_SIG_SUCC; + + /* Write success to power control register */ + writel(ack, (data->pwrctl_base + SDCC_HC_PWRCTL_CTL_REG)); + + if (data->sdhc_event != NULL) { + gBS->SignalEvent(data->sdhc_event); + } + + return 0; +} + +/* + * Function: sdhci clear pending interrupts + * Arg : MSM specific data for sdhci + * Return : None + * Flow: : Clear pending interrupts + */ +static void sdhci_clear_power_ctrl_irq(struct sdhci_msm_data *data) +{ + uint32_t irq_ctl; + uint32_t irq_stat; + + /* + * Read the power control status register to know + * the status of BUS & IO_HIGH_V + */ + irq_stat = readl(data->pwrctl_base + SDCC_HC_PWRCTL_STATUS_REG); + + /* Clear the power control status */ + writel(irq_stat, (data->pwrctl_base + SDCC_HC_PWRCTL_CLEAR_REG)); + + /* + * Handle the pending irq by ack'ing the bus & IO switch + */ + irq_ctl = readl(data->pwrctl_base + SDCC_HC_PWRCTL_CTL_REG); + + if (irq_stat & (SDCC_HC_BUS_ON | SDCC_HC_BUS_OFF)) + irq_ctl |= SDCC_HC_BUS_ON_OFF_SUCC; + if (irq_stat & (SDCC_HC_IO_SIG_LOW | SDCC_HC_IO_SIG_HIGH)) + irq_ctl |= SDCC_HC_IO_SIG_SUCC; + + writel(irq_ctl, (data->pwrctl_base + SDCC_HC_PWRCTL_CTL_REG)); +} + +/* + * Function: sdhci msm init + * Arg : MSM specific config data for sdhci + * Return : None + * Flow: : Enable sdhci mode & do msm specific init + */ +void sdhci_msm_init(struct sdhci_host *host, struct sdhci_msm_data *config) +{ + uint32_t io_switch; + uint32_t caps = 0; + uint32_t version; + + REG_WRITE32(host, 0xA1C, SDCC_VENDOR_SPECIFIC_FUNC); + + /* Enable sdhc mode */ + RMWREG32( + (config->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, + SDHCI_HC_WIDTH, SDHCI_HC_MODE_EN); + + /* Set the FF_CLK_SW_RST_DIS to 1 */ + RMWREG32( + (config->pwrctl_base + SDCC_MCI_HC_MODE), FF_CLK_SW_RST_DIS_START, + FF_CLK_SW_RST_DIS_WIDTH, 1); + + /* + * Reset the controller + */ + sdhci_reset(host, SDHCI_SOFT_RESET); + + /* + * Some platforms have same SDC instance shared between emmc & sd card. + * For such platforms the emmc IO voltage has to be switched from 3.3 to + * 1.8 for the contoller to work with emmc. + */ + + if (config->use_io_switch) { + io_switch = REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC); + io_switch |= HC_IO_PAD_PWR_SWITCH | HC_IO_PAD_PWR_SWITCH_EN; + REG_WRITE32(host, io_switch, SDCC_VENDOR_SPECIFIC_FUNC); + } + + /* + * CORE_SW_RST may trigger power irq if previous status of PWRCTL + * was either BUS_ON or IO_HIGH. So before we enable the power irq + * interrupt in GIC (by registering the interrupt handler), we need to + * ensure that any pending power irq interrupt status is acknowledged + * otherwise power irq interrupt handler would be fired prematurely. + */ + sdhci_clear_power_ctrl_irq(config); + + /* + * Register the interrupt handler for pwr irq + */ + register_int_handler( + config->pwr_irq, (int_handler)sdhci_int_handler, (void *)config); + + unmask_interrupt(config->pwr_irq); + + /* Enable pwr control interrupt */ + writel(SDCC_HC_PWR_CTRL_INT, (config->pwrctl_base + SDCC_HC_PWRCTL_MASK_REG)); + + version = readl(host->msm_host->pwrctl_base + MCI_VERSION); + + host->major = (version & CORE_VERSION_MAJOR_MASK) >> CORE_VERSION_MAJOR_SHIFT; + host->minor = (version & CORE_VERSION_MINOR_MASK); + + /* + * For SDCC5 the capabilities registers does not have voltage advertised + * Override the values using SDCC_HC_VENDOR_SPECIFIC_CAPABILITIES0 + */ + if (host->major >= 1 && host->minor != 0x11 && host->minor != 0x12) { + caps = REG_READ32(host, SDHCI_CAPS_REG1); + + if (config->slot == 0x1) + REG_WRITE32( + host, (caps | SDHCI_1_8_VOL_MASK), + SDCC_HC_VENDOR_SPECIFIC_CAPABILITIES0); + else + REG_WRITE32( + host, (caps | SDHCI_3_0_VOL_MASK), + SDCC_HC_VENDOR_SPECIFIC_CAPABILITIES0); + } + + config->tuning_done = false; + config->calibration_done = false; + host->tuning_in_progress = false; +} + +/* + * Function: sdhci msm set mci clk + * Arg : Host structure + * Return : None + * Flow: : Set HC_SELECT & HC_SELECT_EN for hs400 + */ +void sdhci_msm_set_mci_clk(struct sdhci_host *host) +{ + struct sdhci_msm_data *msm_host; + + msm_host = host->msm_host; + + if (host->timing == MMC_HS400_TIMING) { + /* + * If the current tuning mode is HS400 then we should set the MCLK to run + * the clock @ MCLK/2. Also set HS400 mode in SELECT_IN of vendor specific + * register + */ + REG_RMW32( + host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_HS400_START, + SDCC_HC_MCLK_HS400_WIDTH, SDCC_HC_MCLK_SEL_HS400); + + /* Enable HS400 mode from HC_SELECT_IN bit of VENDOR_SPEC register + * As the SDCC spec does not have matching mode for HS400 + */ + if (msm_host->tuning_done && !msm_host->calibration_done) { + REG_RMW32( + host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_START, + SDCC_HC_MCLK_SEL_IN_WIDTH, SDCC_HC_MCLK_SEL_IN_HS400); + REG_RMW32( + host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_EN_START, + SDCC_HC_MCLK_SEL_IN_EN_WIDTH, SDCC_HC_MCLK_SEL_IN_EN); + } + } + else { + /* + * Set 0x0 mode in SELECT_IN of vendor specific register so that the + * host control2 register settings from sdhc spec are used for + * speed mode + */ + REG_RMW32( + host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_START, + SDCC_HC_MCLK_SEL_IN_WIDTH, 0x0); + REG_RMW32( + host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_EN_START, + SDCC_HC_MCLK_SEL_IN_EN_WIDTH, 0x0); + } +} + +/* + * Set the value based on sdcc clock frequency + */ +static void msm_set_dll_freq(struct sdhci_host *host) +{ + uint32_t reg_val = 0; + + /* Set clock freq value based on clock range */ + if (host->cur_clk_rate <= 112000000) + reg_val = 0x0; + else if (host->cur_clk_rate <= 125000000) + reg_val = 0x1; + else if (host->cur_clk_rate <= 137000000) + reg_val = 0x2; + else if (host->cur_clk_rate <= 150000000) + reg_val = 0x3; + else if (host->cur_clk_rate <= 162000000) + reg_val = 0x4; + else if (host->cur_clk_rate <= 175000000) + reg_val = 0x5; + else if (host->cur_clk_rate <= 187000000) + reg_val = 0x6; + else if (host->cur_clk_rate <= 200000000) + reg_val = 0x7; + + DBG("\n %s: DLL freq: 0x%08x\n", __func__, reg_val); + + REG_RMW32( + host, SDCC_DLL_CONFIG_REG, SDCC_DLL_CONFIG_MCLK_START, + SDCC_DLL_CONFIG_MCLK_WIDTH, reg_val); +} + +static void sdhci_dll_clk_enable(struct sdhci_host *host, int enable) +{ + if (enable) { + REG_WRITE32( + host, + (REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) & ~SDCC_DLL_CLOCK_DISABLE), + SDCC_HC_REG_DLL_CONFIG_2); + } + else { + REG_WRITE32( + host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_CLK_OUT_EN), + SDCC_DLL_CONFIG_REG); + REG_WRITE32( + host, + (REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) | SDCC_DLL_CLOCK_DISABLE), + SDCC_HC_REG_DLL_CONFIG_2); + } +} + +/* Initialize DLL (Programmable Delay Line) */ +static uint32_t sdhci_msm_init_dll(struct sdhci_host *host) +{ + uint32_t pwr_save = 0; + uint32_t timeout = SDHCI_DLL_TIMEOUT; + uint32_t dll_cfg2; + uint32_t mclk_clk_freq = 0; + + pwr_save = REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) & SDCC_DLL_PWR_SAVE_EN; + + /* Dll sequence needs additional steps for sdcc core version 42 */ + if (host->major == 1 && host->minor >= 0x42) { + /* Disable DLL clock before configuring */ + sdhci_dll_clk_enable(host, 0); + } + + /* PWR SAVE to 0 */ + if (pwr_save) + REG_WRITE32( + host, + (REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) & ~SDCC_DLL_PWR_SAVE_EN), + SDCC_VENDOR_SPECIFIC_FUNC); + /* Set DLL_RST to 1 */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_RESET_EN), + SDCC_DLL_CONFIG_REG); + /* Set DLL_PDN to 1 */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_PDN_EN), + SDCC_DLL_CONFIG_REG); + + /* Set frequency field in DLL_CONFIG */ + msm_set_dll_freq(host); + + /* Configure the mclk freq based on the current clock rate + * and fll cycle count + */ + if (host->major == 1 && host->minor >= 0x42) { + dll_cfg2 = REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2); + if (dll_cfg2 & SDCC_FLL_CYCLE_CNT) + mclk_clk_freq = (host->cur_clk_rate / TCXO_FREQ) * 8; + else + mclk_clk_freq = (host->cur_clk_rate / TCXO_FREQ) * 4; + + REG_WRITE32( + host, + ((REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) & ~(0xFF << 10)) | + (mclk_clk_freq << 10)), + SDCC_HC_REG_DLL_CONFIG_2); + + gBS->Stall(5); + } + + /* Write 0 to DLL_RST */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_RESET_EN), + SDCC_DLL_CONFIG_REG); + /* Write 0 to DLL_PDN */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_PDN_EN), + SDCC_DLL_CONFIG_REG); + + /* Set the mclk clock and enable the dll clock */ + if (host->major == 1 && host->minor >= 0x42) { + msm_set_dll_freq(host); + sdhci_dll_clk_enable(host, 1); + } + /* Write 1 to DLL_EN */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_EN), + SDCC_DLL_CONFIG_REG); + /* Write 1 to CLK_OUT_EN */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_CLK_OUT_EN), + SDCC_DLL_CONFIG_REG); + /* Wait for DLL_LOCK in DLL_STATUS register, wait time 50us */ + while (!((REG_READ32(host, SDCC_REG_DLL_STATUS)) & SDCC_DLL_LOCK_STAT)) { + gBS->Stall(1); + timeout--; + if (!timeout) { + dprintf( + CRITICAL, "%s: Failed to get DLL lock: 0x%08x\n", __func__, + REG_READ32(host, SDCC_REG_DLL_STATUS)); + return 1; + } + } + + /* Set the powersave back on */ + if (pwr_save) + REG_WRITE32( + host, + (REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) | SDCC_DLL_PWR_SAVE_EN), + SDCC_VENDOR_SPECIFIC_FUNC); + + return 0; +} + +void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable) +{ + uint32_t core_cfg; + + core_cfg = REG_READ32(host, SDCC_DLL_CONFIG_REG); + + if (enable) { + core_cfg |= SDCC_DLL_CDR_EN; + core_cfg &= ~SDCC_DLL_CDR_EXT_EN; + } + else { + core_cfg &= ~SDCC_DLL_CDR_EN; + core_cfg |= SDCC_DLL_CDR_EXT_EN; + } + + REG_WRITE32(host, core_cfg, SDCC_DLL_CONFIG_REG); +} + +/* Configure DLL with delay value based on 'phase' */ +static uint32_t sdhci_msm_config_dll(struct sdhci_host *host, uint32_t phase) +{ + uint32_t core_cfg = 0; + uint32_t timeout = SDHCI_DLL_TIMEOUT; + + /* Gray code values from SWI */ + uint32_t gray_code[] = {0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, + 0xC, 0xD, 0xF, 0xE, 0xA, 0xB, 0x9, 0x8}; + + /* set CDR_EN & CLK_OUT_EN to 0 and + * CDR_EXT_EN & DLL_EN to 1*/ + core_cfg = REG_READ32(host, SDCC_DLL_CONFIG_REG); + core_cfg &= ~(SDCC_DLL_CDR_EN | SDCC_DLL_CLK_OUT_EN); + core_cfg |= (SDCC_DLL_CDR_EXT_EN | SDCC_DLL_EN); + REG_WRITE32(host, core_cfg, SDCC_DLL_CONFIG_REG); + + /* Wait until CLK_OUT_EN is 0 */ + while (REG_READ32(host, SDCC_DLL_CONFIG_REG) & SDCC_DLL_CLK_OUT_EN) + ; + + REG_RMW32( + host, SDCC_DLL_CONFIG_REG, SDCC_DLL_GRAY_CODE_START, + SDCC_DLL_GRAY_CODE_WIDTH, gray_code[phase]); + + REG_WRITE32( + host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_CLK_OUT_EN), + SDCC_DLL_CONFIG_REG); + + /* Wait until CLK_OUT_EN is 1, wait time 50us */ + while (!(REG_READ32(host, SDCC_DLL_CONFIG_REG) & SDCC_DLL_CLK_OUT_EN)) { + timeout--; + gBS->Stall(1); + if (!timeout) { + dprintf( + CRITICAL, "%s: clk_out_en timed out: %08x\n", __func__, + REG_READ32(host, SDCC_DLL_CONFIG_REG)); + return 1; + } + } + + core_cfg = REG_READ32(host, SDCC_DLL_CONFIG_REG); + + core_cfg |= SDCC_DLL_CDR_EN; + core_cfg &= ~SDCC_DLL_CDR_EXT_EN; + + REG_WRITE32(host, core_cfg, SDCC_DLL_CONFIG_REG); + + return 0; +} + +/* + * Find the right tuning delay, this function finds the largest + * consecutive sequence of phases & then selects the 3/4 th of + * the range which has max entries + * For eg: If we get the following sequence in phase_table[] + * (A) phase_table[] = 0x1, 0x2, 0x3, 0x4 , 0x5 + * (B) phase_table[] = 0xA, 0xB, 0xC + * In the above case the (A) has maximum consecutive entries with '5' entries + * So delay would be phase_table[(0x5 * 3) / 4] = 0x3 + */ +static int sdhci_msm_find_appropriate_phase( + struct sdhci_host *host, uint32_t *phase_table, uint32_t total_phases) +{ + int sub_phases[MAX_PHASES][MAX_PHASES] = {{0}}; + uint32_t phases_per_row[MAX_PHASES] = {0}; + uint32_t i, j; + int selected_phase = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + uint32_t phase_15_row_idx = 0; + uint32_t phases_0_row_idx = 0; + uint32_t max_phases_3_4_idx = 0; + uint32_t max_phases = 0; + uint32_t max_phases_row = 0; + bool found_loop = false; + + if (!phase_table[0] && phase_table[total_phases - 1] == (MAX_PHASES - 1)) + found_loop = true; + + for (i = 0; i < total_phases; i++) { + /* Break the phase table entries into different sub arrays based + * on the consecutive entries. Each row will have one sub array + * of consecutive entries. + * for eg: phase_table [] = { 0x0, 0x1, 0x2, 0xA, 0xB} + * sub_phases [0][] = { 0x0, 0x1, 0x2} + * sub_phases [1][] = { 0xA, 0xB} + */ + sub_phases[row_index][col_index] = phase_table[i]; + phases_per_row[row_index]++; + col_index++; + + /* If we are at the last phase no need to check further */ + if ((i + 1) == total_phases) + break; + + /* If phase_table does not have consecutive entries, move to next entry */ + if (phase_table[i] + 1 != phase_table[i + 1]) { + row_index++; + col_index = 0; + } + } + + if (found_loop && total_phases < MAX_PHASES) { + /* For consecutive entries we need to consider loops. + * If the phase_table contains 0x0 & 0xF then we have + * a loop, the number after 0xF in the sequence would be + * 0x0. + * for eg: + * phase_table = { 0x0, 0x1, 0x2, 0xD, 0xE, 0xF } + * then + * sub_phase [0][] = { 0x0, 0x1, 0x2 } + * sub_phase [1][] = { 0xD, 0xE, 0xF } + * Since we have a loop here, we need to merge the sub arrays as: + * sub_phase [1][] = { 0xD, 0xE, 0xF, 0x0, 0x1, 0x2 } + */ + + /* The entry 0xF will always be in the last row + * and entry 0x0 will always be in the first row + */ + phase_15_row_idx = row_index; + j = 0; + for (i = phases_per_row[phase_15_row_idx]; i < MAX_PHASES; i++) { + sub_phases[phase_15_row_idx][i] = sub_phases[phases_0_row_idx][j]; + if (++j >= phases_per_row[phases_0_row_idx]) + break; + } + + /* Update the number of entries for the sub_phase after the merger */ + phases_per_row[phase_15_row_idx] = + phases_per_row[phase_15_row_idx] + phases_per_row[phases_0_row_idx]; + phases_per_row[phases_0_row_idx] = 0; + } + + for (i = 0; i <= row_index; i++) { + if (phases_per_row[i] > max_phases) { + max_phases = phases_per_row[i]; + max_phases_row = i; + } + } + + max_phases_3_4_idx = (max_phases * 3) / 4; + if (max_phases_3_4_idx) + max_phases_3_4_idx--; + + selected_phase = sub_phases[max_phases_row][max_phases_3_4_idx]; + + return selected_phase; +} + +static uint32_t sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) +{ + uint32_t timeout = 0; + + DBG("\n CM_DLL_SDC4 Calibration Start\n"); + + /*1.Write the DDR config value to SDCC_HC_REG_DDR_CONFIG register*/ + REG_WRITE32( + host, (UINTN)PcdGet64(PcdMmcSdhciDdrCfgVal), SDCC_HC_REG_DDR_CONFIG); + + /*2. Write DDR_CAL_EN to '1' */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) | DDR_CAL_EN), + SDCC_HC_REG_DLL_CONFIG_2); + + /*3. Wait for DLL_LOCK for hs400 to be set */ + timeout = DDR_CAL_TIMEOUT_MAX; + while (!(REG_READ32(host, SDCC_REG_DLL_STATUS) & DDR_DLL_LOCK_JDR)) { + timeout--; + gBS->Stall(1000); + if (!timeout) { + dprintf(CRITICAL, "Error: DLL lock for hs400 operation is not set\n"); + return 1; + } + } + + /*4. Set powersave dll */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_HC_VENDOR_SPECIFIC_FUNC3) | PWRSAVE_DLL), + SDCC_HC_VENDOR_SPECIFIC_FUNC3); + + DBG("\n CM_DLL_SDC4 Calibration Done\n"); + + return 0; +} + +static uint32_t sdhci_msm_cdclp533_calibration(struct sdhci_host *host) +{ + uint32_t timeout; + uint32_t cdc_err; + + DBG("\n CDCLP533 Calibration Start\n"); + + /* Write 0 to CDC_T4_DLY_SEL field in VENDOR_SPEC_DDR200_CFG */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) & ~CDC_T4_DLY_SEL), + SDCC_CDC_DDR200_CFG); + + /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) & ~START_CDC_TRAFFIC), + SDCC_CDC_DDR200_CFG); + + /* Write 0 to CDC_SWITCH_BYPASS_OFF field in CSR_CDC_GEN_CFG */ + REG_WRITE32( + host, + (REG_READ32(host, SDCC_VENDOR_SPEC_CSR_CDC_CFG) & ~CDC_SWITCH_BYPASS_OFF), + SDCC_VENDOR_SPEC_CSR_CDC_CFG); + + /* Write 1 to CDC_SWITCH_RC_EN field in CSR_CDC_GEN_CFG */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_VENDOR_SPEC_CSR_CDC_CFG) | CDC_SWITCH_RC_EN), + SDCC_VENDOR_SPEC_CSR_CDC_CFG); + + /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) & ~START_CDC_TRAFFIC), + SDCC_CDC_DDR200_CFG); + + /* Perform CDCLP533 initialization sequence + * SDCC_CSR_CDC_CTRL_CFG0 --> 0x11800EC + * SDCC_CSR_CDC_CTRL_CFG1 --> 0x3011111 + * SDCC_CSR_CDC_CAL_TIMER_CFG0 --> 0x1201000 + * SDCC_CSR_CDC_CAL_TIMER_CFG1 --> 0x4 + * SDCC_CSR_CDC_REFCOUNT_CFG --> 0xCB732020 + * SDCC_CSR_CDC_COARSE_CAL_CFG --> 0xB19 + * SDCC_CSR_CDC_DELAY_CFG --> 0x4E2 + * SDCC_CDC_OFFSET_CFG --> 0x0 + * SDCC_CDC_SLAVE_DDA_CFG --> 0x16334 + */ + + REG_WRITE32(host, 0x11800EC, SDCC_CSR_CDC_CTRL_CFG0); + REG_WRITE32(host, 0x3011111, SDCC_CSR_CDC_CTRL_CFG1); + REG_WRITE32(host, 0x1201000, SDCC_CSR_CDC_CAL_TIMER_CFG0); + REG_WRITE32(host, 0x4, SDCC_CSR_CDC_CAL_TIMER_CFG1); + REG_WRITE32(host, 0xCB732020, SDCC_CSR_CDC_REFCOUNT_CFG); + REG_WRITE32(host, 0xB19, SDCC_CSR_CDC_COARSE_CAL_CFG); + REG_WRITE32(host, 0x4E2, SDCC_CSR_CDC_DELAY_CFG); + REG_WRITE32(host, 0x0, SDCC_CDC_OFFSET_CFG); + REG_WRITE32(host, 0x16334, SDCC_CDC_SLAVE_DDA_CFG); + + /* Write 1 to SW_TRIGGER_FULL_CALIB */ + REG_WRITE32( + host, + (REG_READ32(host, SDCC_CSR_CDC_CTRL_CFG0) | CDC_SW_TRIGGER_FULL_CALIB), + SDCC_CSR_CDC_CTRL_CFG0); + + /* Write 0 to SW_TRIGGER_FULL_CALIB */ + REG_WRITE32( + host, + (REG_READ32(host, SDCC_CSR_CDC_CTRL_CFG0) & ~CDC_SW_TRIGGER_FULL_CALIB), + SDCC_CSR_CDC_CTRL_CFG0); + + /* Write 1 to HW_AUTO_CAL_EN */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_CSR_CDC_CTRL_CFG0) | CDC_HW_AUTO_CAL_EN), + SDCC_CSR_CDC_CTRL_CFG0); + + /* Write 1 to TIMER_ENA */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_CSR_CDC_CAL_TIMER_CFG0) | CDC_TIMER_EN), + SDCC_CSR_CDC_CAL_TIMER_CFG0); + + /* Wait for CALIBRATION_DONE in CDC_STATUS */ + timeout = CDC_STATUS_TIMEOUT; + while (!(REG_READ32(host, SDCC_CSR_CDC_STATUS0) & BIT(0))) { + timeout--; + gBS->Stall(1000); + if (!timeout) { + dprintf(CRITICAL, "Error: Calibration done in CDC status not set\n"); + return 1; + } + } + + cdc_err = REG_READ32(host, SDCC_CSR_CDC_STATUS0) & CSR_CDC_ERROR_MASK; + if (cdc_err) { + dprintf(CRITICAL, "CDC error set during calibration: %x\n", cdc_err); + return 1; + } + /* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) | START_CDC_TRAFFIC), + SDCC_CDC_DDR200_CFG); + + DBG("\n CDCLP533 Calibration Done\n"); + + return 0; +} + +static uint32_t sdhci_msm_hs400_calibration(struct sdhci_host *host) +{ + DBG("\n HS400 Calibration Start\n"); + + /* Reset & Initialize the DLL block */ + if (sdhci_msm_init_dll(host)) + return 1; + + /* Write the save phase */ + if (sdhci_msm_config_dll(host, host->msm_host->saved_phase)) + return 1; + + /* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */ + REG_WRITE32( + host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | CMD_DAT_TRACK_SEL), + SDCC_DLL_CONFIG_REG); + + if (host->use_cdclp533) + return sdhci_msm_cdclp533_calibration(host); + else + return sdhci_msm_cm_dll_sdc4_calibration(host); + + DBG("\n HS400 Calibration Done\n"); + + return 0; +} + +/* + * Function: sdhci msm execute tuning + * Arg : Host structure & bus width + * Return : 0 on Success, 1 on Failure + * Flow: : Execute Tuning sequence for HS200 and calibration for hs400 + */ +uint32_t sdhci_msm_execute_tuning( + struct sdhci_host *host, struct mmc_card *card, uint32_t bus_width) +{ + uint32_t * tuning_block; + uint32_t * tuning_data; + uint32_t tuned_phases[MAX_PHASES] = {0}; + uint32_t size; + uint32_t phase = 0; + uint32_t tuned_phase_cnt = 0; + uint8_t drv_type = 0; + bool drv_type_changed = false; + int ret = 0; + uint32_t i; + struct sdhci_msm_data *msm_host; + + msm_host = host->msm_host; + + /* In Tuning mode */ + host->tuning_in_progress = true; + + if (bus_width == DATA_BUS_WIDTH_8BIT) { + tuning_block = (uint32_t *)tuning_block_128; + size = sizeof(tuning_block_128); + } + else { + tuning_block = (uint32_t *)tuning_block_64; + size = sizeof(tuning_block_64); + } + + tuning_data = (uint32_t *)memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE)); + + ASSERT(tuning_data); + + /* Calibration for CDCLP533 needed for HS400 mode */ + if (msm_host->tuning_done && !msm_host->calibration_done && + host->timing == MMC_HS400_TIMING) { + ret = sdhci_msm_hs400_calibration(host); + if (!ret) + msm_host->calibration_done = true; + goto out; + } + + /* Reset & Initialize the DLL block */ + if (sdhci_msm_init_dll(host)) { + ret = 1; + goto out; + } + +retry_tuning: + tuned_phase_cnt = 0; + phase = 0; + struct mmc_command cmd = {0}; + + while (phase < MAX_PHASES) { + /* configure dll to set phase delay */ + if (sdhci_msm_config_dll(host, phase)) { + ret = 1; + goto out; + } + + cmd.cmd_index = CMD21_SEND_TUNING_BLOCK; + cmd.argument = 0x0; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + cmd.trans_mode = SDHCI_MMC_READ; + cmd.data_present = 0x1; + cmd.data.data_ptr = tuning_data; + cmd.data.blk_sz = size; + cmd.data.num_blocks = 0x1; + + /* send command */ + if (!sdhci_send_command(host, &cmd) && + !memcmp(tuning_data, tuning_block, size)) + tuned_phases[tuned_phase_cnt++] = phase; + + phase++; + } + + /* + * Check if all the tuning phases passed */ + if (tuned_phase_cnt == MAX_PHASES) { + /* Change the driver type & rerun tuning */ + while (++drv_type <= MX_DRV_SUPPORTED_HS200) { + drv_type_changed = mmc_set_drv_type(host, card, drv_type); + if (drv_type_changed) { + goto retry_tuning; + } + } + } + + /* Restore the driver strength to default value */ + if (drv_type_changed) + mmc_set_drv_type(host, card, 0); + + if (tuned_phase_cnt == MAX_PHASES) { + attempt_cdr_unlock = true; + dprintf( + CRITICAL, + "WARNING: All phase passed.The selected phase may not be optimal\n"); + } + + /* Find the appropriate tuned phase */ + if (tuned_phase_cnt) { + DBG("\n Tuned phase\n"); + for (i = 0; i < tuned_phase_cnt; i++) { + DBG("%d\t", tuned_phases[i]); + } + + ret = sdhci_msm_find_appropriate_phase(host, tuned_phases, tuned_phase_cnt); + + if (ret < 0) { + dprintf(CRITICAL, "Failed in selecting the tuning phase\n"); + ret = 1; + goto out; + } + + phase = (uint32_t)ret; + ret = 0; + + DBG("\n: %s: Tuned Phase: 0x%08x\n", __func__, phase); + + if (sdhci_msm_config_dll(host, phase)) + goto out; + + /* Save the tuned phase */ + host->msm_host->saved_phase = phase; + } + else { + dprintf(CRITICAL, "Failed to get tuned phase\n"); + ret = 1; + } + +out: + /* If all the tuning phases passed, send CMD21 after enabling + * CDR to make sure right tuning phase is selected by CDR + */ + if (attempt_cdr_unlock) { + cmd.cmd_index = CMD21_SEND_TUNING_BLOCK; + cmd.argument = 0x0; + cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL; + cmd.resp_type = SDHCI_CMD_RESP_R1; + cmd.trans_mode = SDHCI_MMC_READ; + cmd.data_present = 0x1; + cmd.data.data_ptr = tuning_data; + cmd.data.blk_sz = size; + cmd.data.num_blocks = 0x1; + + /* send command */ + if (!sdhci_send_command(host, &cmd)) { + DBG("\n: %s: Sending CMD21 after CDR enable with default phases fail\n", + __func__); + } + } + + free(tuning_data); + /* Tuning done */ + host->tuning_in_progress = false; + host->msm_host->tuning_done = true; + return ret; +} + +/* + * API to disable HC mode + */ +void sdhci_mode_disable(struct sdhci_host *host) +{ + /* Disable HC mode */ + RMWREG32( + (host->msm_host->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, + SDHCI_HC_WIDTH, 0); +} diff --git a/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/sdhci_msm.h b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/sdhci_msm.h new file mode 100755 index 0000000..87205e4 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/SdhciMMCHSDxe/sdhci_msm.h @@ -0,0 +1,148 @@ +/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SDHCI_MSM_H__ +#define __SDHCI_MSM_H__ + +#include + +#define SDHCI_HC_START_BIT 0x0 +#define SDHCI_HC_WIDTH 0x1 + +#define SDCC_MCI_POWER 0x0 +#define CORE_SW_RST_START 0x7 +#define CORE_SW_RST_WIDTH 0x1 + +/* DLL & CDC registers + * DLL: Delay Line + * CDC: Calibrated Delay Circuit + */ +#define SDCC_DLL_CONFIG_REG 0x100 +#define SDCC_VENDOR_SPECIFIC_FUNC 0x10C +#define SDCC_REG_DLL_STATUS 0x108 +#define SDCC_CDC_DDR200_CFG 0x184 +#define SDCC_VENDOR_SPEC_CSR_CDC_CFG 0x178 +#define SDCC_CSR_CDC_CTRL_CFG0 0x130 +#define SDCC_CSR_CDC_CTRL_CFG1 0x134 +#define SDCC_CSR_CDC_CAL_TIMER_CFG0 0x138 +#define SDCC_CSR_CDC_CAL_TIMER_CFG1 0x13C +#define SDCC_CSR_CDC_REFCOUNT_CFG 0x140 +#define SDCC_CSR_CDC_COARSE_CAL_CFG 0x144 +#define SDCC_CSR_CDC_DELAY_CFG 0x150 +#define SDCC_CDC_OFFSET_CFG 0x14C +#define SDCC_CDC_SLAVE_DDA_CFG 0x160 +#define SDCC_CSR_CDC_STATUS0 0x164 + +/* Macros for CM_DLL_SDC4 related macros */ +#define SDCC_HC_VENDOR_SPECIFIC_FUNC3 0x1B0 +#define SDCC_HC_REG_DLL_CONFIG_2 0x1B4 +#define SDCC_HC_REG_DDR_CONFIG 0x1B8 + +#define DDR_CAL_EN BIT(0) +#define DDR_CAL_TIMEOUT_MAX 50 +#define DDR_DLL_LOCK_JDR BIT(11) +#define PWRSAVE_DLL BIT(3) +#define DDR_CONFIG_VAL 0x80040853 + +/* DLL & CDC helper macros */ +#define SDCC_DLL_PWR_SAVE_EN BIT(1) +#define SDCC_DLL_LOCK_STAT BIT(7) +#define SDCC_DLL_EN BIT(16) +#define SDCC_DLL_CDR_EN BIT(17) +#define SDCC_DLL_CLK_OUT_EN BIT(18) +#define SDCC_FLL_CYCLE_CNT BIT(18) +#define SDCC_DLL_CDR_EXT_EN BIT(19) +#define SDCC_DLL_CLOCK_DISABLE BIT(21) +#define SDCC_DLL_PDN_EN BIT(29) +#define SDCC_DLL_RESET_EN BIT(30) +#define SDCC_DLL_CONFIG_MCLK_START 0x18 +#define SDCC_DLL_CONFIG_MCLK_WIDTH 0x3 +#define SDCC_DLL_GRAY_CODE_START 0x14 +#define SDCC_DLL_GRAY_CODE_WIDTH 0x4 +#define CMD_DAT_TRACK_SEL BIT(0) +#define CDC_T4_DLY_SEL BIT(0) +#define CDC_SWITCH_BYPASS_OFF BIT(0) +#define CDC_SWITCH_RC_EN BIT(1) +#define START_CDC_TRAFFIC BIT(6) +#define FF_CLK_SW_RST_DIS_START 0xD +#define FF_CLK_SW_RST_DIS_WIDTH 0x1 +#define CDC_SW_TRIGGER_FULL_CALIB BIT(16) +#define CDC_HW_AUTO_CAL_EN BIT(17) +#define CDC_TIMER_EN BIT(16) +#define CSR_CDC_ERROR_MASK 0x7000000 + +/* SDCC macros for HS400 */ +#define SDCC_HC_MCLK_SEL_HS400 0x3 +#define SDCC_HC_MCLK_HS400_START 0x8 +#define SDCC_HC_MCLK_HS400_WIDTH 0x2 +#define SDCC_HC_MCLK_SEL_IN_HS400 0x6 +#define SDCC_HC_MCLK_SEL_IN_DFLT 0x2 +#define SDCC_HC_MCLK_SEL_IN_UHS 0x4 +#define SDCC_HC_MCLK_SEL_IN_START 0x13 +#define SDCC_HC_MCLK_SEL_IN_WIDTH 0x3 +#define SDCC_HC_MCLK_SEL_IN_EN 0x1 +#define SDCC_HC_MCLK_SEL_IN_EN_START 0x12 +#define SDCC_HC_MCLK_SEL_IN_EN_WIDTH 0x1 + +#define MAX_PHASES 16 + +/* SDCC version macros */ +#define MCI_VERSION 0x50 +#define CORE_VERSION_MAJOR_MASK 0xF0000000 +#define CORE_VERSION_MAJOR_SHIFT 0x1C +#define CORE_VERSION_MINOR_MASK 0x000000FF + +#define SDHCI_DLL_TIMEOUT 50 +#define CDC_STATUS_TIMEOUT 50 + +#define HC_IO_PAD_PWR_SWITCH_EN BIT(15) +#define HC_IO_PAD_PWR_SWITCH BIT(16) + +#define SDCC_HC_VENDOR_SPECIFIC_CAPABILITIES0 0x11C + +#define TCXO_FREQ 19200000 + +struct sdhci_msm_data { + uint32_t pwrctl_base; + uint32_t pwr_irq; + uint8_t tuning_done; + uint8_t calibration_done; + uint8_t saved_phase; + uint8_t slot; + uint8_t use_io_switch; + EFI_EVENT sdhc_event; +}; + +void sdhci_msm_init(struct sdhci_host *host, struct sdhci_msm_data *data); +uint32_t sdhci_msm_execute_tuning( + struct sdhci_host *host, struct mmc_card *card, uint32_t bus_width); +void sdhci_mode_disable(struct sdhci_host *host); +/* API: Toggle the bit for clock-data recovery */ +void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable); +void sdhci_msm_set_mci_clk(struct sdhci_host *host); +#endif diff --git a/sdm845Pkg/Binary/beryllium/SecRSADxe/SecRSADxe.efi b/sdm845Pkg/Binary/beryllium/SecRSADxe/SecRSADxe.efi new file mode 100755 index 0000000..9ddb875 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/SecRSADxe/SecRSADxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/SecurityDxe/SecurityDxe.efi b/sdm845Pkg/Binary/beryllium/SecurityDxe/SecurityDxe.efi new file mode 100755 index 0000000..0941f0f Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/SecurityDxe/SecurityDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/SimpleTextInOutSerial/SimpleTextInOutSerial.depex b/sdm845Pkg/Binary/beryllium/SimpleTextInOutSerial/SimpleTextInOutSerial.depex new file mode 100755 index 0000000..2a47cc2 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/SimpleTextInOutSerial/SimpleTextInOutSerial.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/SimpleTextInOutSerial/SimpleTextInOutSerial.efi b/sdm845Pkg/Binary/beryllium/SimpleTextInOutSerial/SimpleTextInOutSerial.efi new file mode 100755 index 0000000..1fa51fc Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/SimpleTextInOutSerial/SimpleTextInOutSerial.efi differ diff --git a/sdm845Pkg/Binary/beryllium/SmemDxe/SmemDxe.depex b/sdm845Pkg/Binary/beryllium/SmemDxe/SmemDxe.depex new file mode 100755 index 0000000..2a47cc2 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/SmemDxe/SmemDxe.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/SmemDxe/SmemDxe.efi b/sdm845Pkg/Binary/beryllium/SmemDxe/SmemDxe.efi new file mode 100755 index 0000000..0d1b425 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/SmemDxe/SmemDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/SpiDxe(from pixel3, doesn't work)/SpiDxe.efi b/sdm845Pkg/Binary/beryllium/SpiDxe(from pixel3, doesn't work)/SpiDxe.efi new file mode 100755 index 0000000..56ab247 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/SpiDxe(from pixel3, doesn't work)/SpiDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/StatusCodeHandlerRuntimeDxe/StatusCodeHandlerRuntimeDxe.depex b/sdm845Pkg/Binary/beryllium/StatusCodeHandlerRuntimeDxe/StatusCodeHandlerRuntimeDxe.depex new file mode 100755 index 0000000..0ae5438 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/StatusCodeHandlerRuntimeDxe/StatusCodeHandlerRuntimeDxe.depex @@ -0,0 +1 @@ +6)!†vÈA :*òü9â \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/StatusCodeHandlerRuntimeDxe/StatusCodeHandlerRuntimeDxe.efi b/sdm845Pkg/Binary/beryllium/StatusCodeHandlerRuntimeDxe/StatusCodeHandlerRuntimeDxe.efi new file mode 100755 index 0000000..8d8d353 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/StatusCodeHandlerRuntimeDxe/StatusCodeHandlerRuntimeDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/TsensDxe/TsensDxe.depex b/sdm845Pkg/Binary/beryllium/TsensDxe/TsensDxe.depex new file mode 100755 index 0000000..d24065d --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/TsensDxe/TsensDxe.depex @@ -0,0 +1 @@ +B¹7®E‘L¡–ÙfŸÓG£ \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/TsensDxe/TsensDxe.efi b/sdm845Pkg/Binary/beryllium/TsensDxe/TsensDxe.efi new file mode 100755 index 0000000..ba0cfe2 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/TsensDxe/TsensDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/TzDxe/TzDxe.depex b/sdm845Pkg/Binary/beryllium/TzDxe/TzDxe.depex new file mode 100755 index 0000000..430b438 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/TzDxe/TzDxe.depex differ diff --git a/sdm845Pkg/Binary/beryllium/TzDxe/TzDxe.efi b/sdm845Pkg/Binary/beryllium/TzDxe/TzDxe.efi new file mode 100755 index 0000000..9f0772c Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/TzDxe/TzDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/UFSDxe/UFSDxe.depex b/sdm845Pkg/Binary/beryllium/UFSDxe/UFSDxe.depex new file mode 100755 index 0000000..098cfdc --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/UFSDxe/UFSDxe.depex @@ -0,0 +1 @@ +ÐÇåô9ÒËGªÍfïv28 \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/UFSDxe/UFSDxe.efi b/sdm845Pkg/Binary/beryllium/UFSDxe/UFSDxe.efi new file mode 100755 index 0000000..cf0939a Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/UFSDxe/UFSDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/ULogDxe/ULogDxe.depex b/sdm845Pkg/Binary/beryllium/ULogDxe/ULogDxe.depex new file mode 100755 index 0000000..2a47cc2 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/ULogDxe/ULogDxe.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/ULogDxe/ULogDxe.efi b/sdm845Pkg/Binary/beryllium/ULogDxe/ULogDxe.efi new file mode 100755 index 0000000..fe26a57 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/ULogDxe/ULogDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/UsbConfigDxe/UsbConfigDxe.depex b/sdm845Pkg/Binary/beryllium/UsbConfigDxe/UsbConfigDxe.depex new file mode 100755 index 0000000..8f72e31 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/UsbConfigDxe/UsbConfigDxe.depex @@ -0,0 +1 @@ +iv° —zH¤µ(Û{EÎñÐÇåô9ÒËGªÍfïv28E\z²!ÅCº|‚/î_噎—ëßÏÆI¾KÙ¥²† \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/UsbConfigDxe/UsbConfigDxe.efi b/sdm845Pkg/Binary/beryllium/UsbConfigDxe/UsbConfigDxe.efi new file mode 100755 index 0000000..3ca43fe Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/UsbConfigDxe/UsbConfigDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/UsbDeviceDxe/UsbDeviceDxe.depex b/sdm845Pkg/Binary/beryllium/UsbDeviceDxe/UsbDeviceDxe.depex new file mode 100755 index 0000000..2a47cc2 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/UsbDeviceDxe/UsbDeviceDxe.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/UsbDeviceDxe/UsbDeviceDxe.efi b/sdm845Pkg/Binary/beryllium/UsbDeviceDxe/UsbDeviceDxe.efi new file mode 100755 index 0000000..842a493 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/UsbDeviceDxe/UsbDeviceDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/UsbMsdDxe/UsbMsdDxe.depex b/sdm845Pkg/Binary/beryllium/UsbMsdDxe/UsbMsdDxe.depex new file mode 100755 index 0000000..2a47cc2 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/UsbMsdDxe/UsbMsdDxe.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/UsbMsdDxe/UsbMsdDxe.efi b/sdm845Pkg/Binary/beryllium/UsbMsdDxe/UsbMsdDxe.efi new file mode 100755 index 0000000..b2e4880 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/UsbMsdDxe/UsbMsdDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex b/sdm845Pkg/Binary/beryllium/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex new file mode 100755 index 0000000..2a47cc2 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi b/sdm845Pkg/Binary/beryllium/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi new file mode 100755 index 0000000..b54846d Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/UsbfnDwc3Dxe/UsbfnDwc3Dxe.depex b/sdm845Pkg/Binary/beryllium/UsbfnDwc3Dxe/UsbfnDwc3Dxe.depex new file mode 100755 index 0000000..43d06b2 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/UsbfnDwc3Dxe/UsbfnDwc3Dxe.depex differ diff --git a/sdm845Pkg/Binary/beryllium/UsbfnDwc3Dxe/UsbfnDwc3Dxe.efi b/sdm845Pkg/Binary/beryllium/UsbfnDwc3Dxe/UsbfnDwc3Dxe.efi new file mode 100755 index 0000000..1887390 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/UsbfnDwc3Dxe/UsbfnDwc3Dxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/VerifiedBootDxe/VerifiedBootDxe.depex b/sdm845Pkg/Binary/beryllium/VerifiedBootDxe/VerifiedBootDxe.depex new file mode 100755 index 0000000..2a47cc2 --- /dev/null +++ b/sdm845Pkg/Binary/beryllium/VerifiedBootDxe/VerifiedBootDxe.depex @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/sdm845Pkg/Binary/beryllium/VerifiedBootDxe/VerifiedBootDxe.efi b/sdm845Pkg/Binary/beryllium/VerifiedBootDxe/VerifiedBootDxe.efi new file mode 100755 index 0000000..ce76ea6 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/VerifiedBootDxe/VerifiedBootDxe.efi differ diff --git a/sdm845Pkg/Binary/beryllium/WatchdogTimer/WatchdogTimer.depex b/sdm845Pkg/Binary/beryllium/WatchdogTimer/WatchdogTimer.depex new file mode 100755 index 0000000..03d5718 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/WatchdogTimer/WatchdogTimer.depex differ diff --git a/sdm845Pkg/Binary/beryllium/WatchdogTimer/WatchdogTimer.efi b/sdm845Pkg/Binary/beryllium/WatchdogTimer/WatchdogTimer.efi new file mode 100755 index 0000000..ac7e0a7 Binary files /dev/null and b/sdm845Pkg/Binary/beryllium/WatchdogTimer/WatchdogTimer.efi differ diff --git a/sdm845Pkg/beryllium.dsc b/sdm845Pkg/beryllium.dsc new file mode 100755 index 0000000..55659c7 --- /dev/null +++ b/sdm845Pkg/beryllium.dsc @@ -0,0 +1,26 @@ +[Defines] + PLATFORM_NAME = sdm845Pkg + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = sdm845Pkg/beryllium.fdf + +!include sdm845Pkg/sdm845Pkg.dsc + +[PcdsFixedAtBuild.common] + # System Memory (5GB) + gArmTokenSpaceGuid.PcdSystemMemorySize|0x140000000 + + gsdm845PkgTokenSpaceGuid.PcdMipiFrameBufferAddress|0x9D469780 + gsdm845PkgTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gsdm845PkgTokenSpaceGuid.PcdMipiFrameBufferHeight|2140 + + #uncomment section underneath and comment out the above section to use full display, including the notch + #gsdm845PkgTokenSpaceGuid.PcdMipiFrameBufferPixelBpp|32|UINT32|0x0000a403 + #gsdm845PkgTokenSpaceGuid.PcdMipiFrameBufferVisibleWidth|1080|UINT32|0x0000a404 + #gsdm845PkgTokenSpaceGuid.PcdMipiFrameBufferVisibleHeight|2234|UINT32|0x0000a405 + diff --git a/sdm845Pkg/beryllium.fdf b/sdm845Pkg/beryllium.fdf new file mode 100644 index 0000000..2403cd5 --- /dev/null +++ b/sdm845Pkg/beryllium.fdf @@ -0,0 +1,347 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.sdm845Pkg_UEFI] +BaseAddress = 0xd0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x200 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +# from ArmVirtPkg/ArmVirtQemuKernel.fdf +# +# Implement the Linux kernel header layout so that the loader will identify +# it as something bootable, and execute it with a FDT pointer in x0 or r2. +# +0x00000000|0x00008000 +DATA = { + 0x01, 0x00, 0x00, 0x10, # code0: adr x1, . + 0xff, 0x1f, 0x00, 0x14, # code1: b 0x8000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, # text_offset: 512 KB + 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, # image_size: 2 MB + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # flags + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res2 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res3 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res4 + 0x41, 0x52, 0x4d, 0x64, # magic: "ARM\x64" + 0x00, 0x00, 0x00, 0x00 # res5 +} + +0x00008000|0x001f8000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + } + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + FILE DRIVER = af9763a2-033b-4109-8e17-56a98d380c92 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/HWIODxeDriver/HWIODxeDriver.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/HWIODxeDriver/HWIODxeDriver.efi + SECTION UI = "HWIODxeDriver" + } + + FILE DRIVER = 5776232e-082d-4b75-9a0e-fe1d13f7a5d9 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/PmicDxe/PmicDxe.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/PmicDxe/PmicDxe.efi + SECTION UI = "PmicDxe" + } + + FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/ButtonsDxe/ButtonsDxe.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/ButtonsDxe/ButtonsDxe.efi + SECTION UI = "ButtonsDxe" + } + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + FILE DRIVER = 3299a266-15f0-4346-8318-716336736d3e { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/UsbDeviceDxe/UsbDeviceDxe.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/UsbDeviceDxe/UsbDeviceDxe.efi + SECTION UI = "UsbDeviceDxe" + } + + FILE DRIVER = 11faed4c-b21f-4d88-8e48-c4c28a1e50df { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi + SECTION UI = "UsbPwrCtrlDxe" + } + + FILE DRIVER = 5af77f10-90df-4e7e-8325-a17ec09d5443 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/UsbMsdDxe/UsbMsdDxe.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/UsbMsdDxe/UsbMsdDxe.efi + SECTION UI = "UsbMsdDxe" + } + + FILE DRIVER = 94f8a6a7-dc34-4101-88c1-99179cceae83 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/UsbfnDwc3Dxe/UsbfnDwc3Dxe.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/UsbfnDwc3Dxe/UsbfnDwc3Dxe.efi + SECTION UI = "UsbfnDwc3Dxe" + } + + FILE DRIVER = cd823a4d-7dec-4531-ae5d-4134fa4127b8 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/UsbConfigDxe/UsbConfigDxe.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/UsbConfigDxe/UsbConfigDxe.efi + SECTION UI = "UsbDeviceDxe" + } + + # + # GPIO + # + + # + # Virtual Keyboard + # + INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf + + INF sdm845Pkg/sdm845Dxe/sdm845Dxe.inf + INF sdm845Pkg/SimpleFbDxe/SimpleFbDxe.inf + + FILE DRIVER = 0d35cd8e-97ea-4f9a-96af-0f0d89f76567 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/UFSDxe/UFSDxe.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/UFSDxe/UFSDxe.efi + SECTION UI = "UFSDxe" + } + FILE DRIVER = 2a7b4bef-80cd-49e1-b473-374ba4d673fc { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/SPMI/SPMI.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/SPMI/SPMI.efi + SECTION UI = "SPMI" + } + + FILE DRIVER = f541d663-4a48-40aa-aabf-ff158ccae34c { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/SmemDxe/SmemDxe.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/SmemDxe/SmemDxe.efi + SECTION UI = "SmemDxe" + } + + FILE DRIVER = 10e193df-9966-44e7-b17c-59dd831e20fc { + SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/ChipInfo/ChipInfo.depex + SECTION PE32 = sdm845Pkg/Binary/beryllium/ChipInfo/ChipInfo.efi + SECTION UI = "ChipInfo" + } + + #FILE DRIVER = 7a32bd23-f735-4f57-aa1a-447d2fe3be0d { + # SECTION DXE_DEPEX = sdm845Pkg/Binary/beryllium/SPI/SPI.depex + # SECTION PE32 = sdm845Pkg/Binary/beryllium/SPI/SPI.efi + # SECTION UI = "SPI" + #} + + + # + # USB Host Support + # + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + + # + # USB Mass Storage Support + # + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # USB Peripheral Support + # + INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf + + # + # Fastboot + # + INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + # INF RuleOverride = ACPITABLE sdm845Pkg/AcpiTables/AcpiTables.inf + + FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + # SECTION RAW = sdm845Pkg/AcpiTables/minimal/DBG2.aml + # SECTION RAW = sdm845Pkg/AcpiTables/minimal/DSDT.aml + # SECTION RAW = sdm845Pkg/AcpiTables/minimal/FACP.aml + # SECTION RAW = sdm845Pkg/AcpiTables/minimal/GTDT.aml + # SECTION RAW = sdm845Pkg/AcpiTables/minimal/APIC.aml + SECTION RAW = sdm845Pkg/AcpiTables/testing/DBG2.aml + SECTION RAW = sdm845Pkg/AcpiTables/testing/DSDT.aml + SECTION RAW = sdm845Pkg/AcpiTables/testing/CSRT.aml + SECTION RAW = sdm845Pkg/AcpiTables/testing/FADT.aml + SECTION RAW = sdm845Pkg/AcpiTables/testing/FACS.aml + SECTION RAW = sdm845Pkg/AcpiTables/testing/GTDT.aml + SECTION RAW = sdm845Pkg/AcpiTables/testing/IORT.aml + SECTION RAW = sdm845Pkg/AcpiTables/testing/MCFG.aml + SECTION RAW = sdm845Pkg/AcpiTables/testing/MADT.aml + SECTION RAW = sdm845Pkg/AcpiTables/testing/PPTT.aml + SECTION RAW = sdm845Pkg/AcpiTables/testing/TPM2.aml + SECTION UI = "AcpiTables" + } + + # + # SMBIOS Support + # + INF sdm845Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # UEFI applications + # + INF ShellPkg/Application/Shell/Shell.inf +!ifdef $(INCLUDE_TFTP_COMMAND) + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + # + # Bds + # + INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF sdm845Pkg/Drivers/LogoDxe/LogoDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePi/PeiUniCore.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + +!include sdm845Pkg/CommonFdf.fdf.inc + + + +