From: strongtz Date: 星期五, 30 Oct 2020 09:52:12 +0000 (+0800) Subject: Nothing. For future research only X-Git-Tag: v0.2~35 X-Git-Url: https://git.renegade-project.org/?a=commitdiff_plain;h=b698655553828b1413dd7c5362fdb6e92b068c13;p=edk2-sdm845.git Nothing. For future research only --- diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/ConnectionSecurity.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/ConnectionSecurity.asl new file mode 100644 index 0000000..08860e6 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/ConnectionSecurity.asl @@ -0,0 +1,15 @@ +// +// Copyright (c) 2018, Mmoclauq Technologies Inc. All rights reserved. +// +// This file contains the Connection Security device definitions. +// + + // + // Mmoclauq Connection Security driver + // + Device (CSEC) + { + Name (_HID, "HID_CSEC") + Name (_UID, 0) + } + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/Csrt.aslc b/sdm845Pkg/AcpiTables/src/sc8180x/common/Csrt.aslc new file mode 100644 index 0000000..9357fed --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/Csrt.aslc @@ -0,0 +1,118 @@ +/*++ + +Copyright (c) 2011-2014 Mmoclauq Technologies Inc. All rights reserved. + + +Module Name: + + Csrt.aslc + +Abstract: + + Core System Resource Table + +Author: + +Environment: + + Firmware. + +Revision History: + +--*/ + +#include "Platform.h" +#include "Socdata.h" +#include +#include + +#pragma pack(push, 1) + +#define ACPI_CSRT_RG_DEVICE_ID_TIMER 0x100A +#define ACPI_CSRT_RG_DEVICE_ID_DMA 0x1002 +#define ACPI_CSRT_RG_DEVICE_ID_INTERRUPT 0x1003 +#define ACPI_CSRT_RG_DEVICE_ID_WDOG_TIMER 0x100B + +typedef enum _RD_TIMER_TYPE { + UnknownTimer = 0, + QWdogTimer = 2 +} RD_TIMER_TYPE, *PRD_TIMER_TYPE; + +typedef struct { + CSRT_RESOURCE_DESCRIPTOR_HEADER Header; + RD_TIMER_TYPE Type; + UINT64 BaseAddress; + UINT32 Frequency; + UINT32 Gsi; +} RD_TIMER, *PRD_TIMER; + +typedef struct { + CSRT_RESOURCE_GROUP_HEADER Header; + RD_TIMER Timer1; +} RG_TIMER; + +// number of ADM channels mapped into Scorpion domain +// CSRT structure for this platform +//------------------------------------------------------------------------ + +typedef struct { + ACPI_HEADER Header; + RG_TIMER TimerResourceGroup; +} CSRT; + +#define RG_HEADER(_TYPE, _DEVID, _SHARED_SIZE) \ + sizeof(_TYPE), /* Resource Group Length */\ + SIGNATURE4('Q','C','O','M'), /* VendorId */\ + 0, /* SubvendorId */\ + _DEVID, /* DeviceId */\ + 0, /* SubdeviceId */\ + 0, /* Revision */\ + 0, /* Reserved */\ + _SHARED_SIZE /* Size of shared area */\ + +//------------------------------------------------------------------------ +// CSRT structure for this platform +//------------------------------------------------------------------------ +typedef struct { + ACPI_HEADER CsrtHeader; + RG_TIMER Timer1; + SOCDTABLE_SOCD SocData; +} ACPI_CSRT_TABLE; + +ACPI_CSRT_TABLE Csrt = { + //------------------------------------------------------------------------ + // CSRT Header + //------------------------------------------------------------------------ + ACPI_CSRT_SIGNATURE, // Signature + sizeof(ACPI_CSRT_TABLE), // Length + ACPI_CSRT_REVISION, // Revision + 0x00, // Checksum calculated at runtime. + ACPI_OEM_ID, // OEMID is a 6 bytes long field. + ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long). + ACPI_OEM_REVISION, // OEM revision number. + ACPI_CREATOR_ID, // ASL compiler vendor ID. + ACPI_CREATOR_REVISION, // ASL compiler revision number. + + //------------------------------------------------------------------------ + // Timer Resource Group - Shared (memory-mapped) QTimer + //------------------------------------------------------------------------ + + RG_HEADER(RG_TIMER, ACPI_CSRT_RG_DEVICE_ID_WDOG_TIMER, 0), + + + // Timer1 Resource Descriptor + + + sizeof(RD_TIMER), + CSRT_RD_TYPE_TIMER, + CSRT_RD_SUBTYPE_TIMER, + 1, + QWdogTimer, + 0x17C10000 , // Timer base address + 32765, // frequency + 32, // GSIV + .SocData=SOCDTABLE_SOCD_VAR, +}; + +#pragma pack(pop) + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/Facp.aslc b/sdm845Pkg/AcpiTables/src/sc8180x/common/Facp.aslc new file mode 100644 index 0000000..8bada55 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/Facp.aslc @@ -0,0 +1,148 @@ +// +// Copyright (c) 2011, Mmoclauq Technologies Inc. All rights reserved. +// + +#include "Platform.h" + +ACPI_FACP FACP = { + { + ACPI_FACP_SIGNATURE, + sizeof (ACPI_FACP), + ACPI_FACP_REVISION, + 0, + ACPI_OEM_ID, + ACPI_OEM_TABLE_ID, + ACPI_OEM_REVISION, + ACPI_CREATOR_ID, + ACPI_CREATOR_REVISION + }, + + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_PM_PROFILE_SLATE, // Preferred_PM_Profile + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + + ACPI_HARDWARE_REDUCED|LOW_POWER_S0_CAPABLE, + + { + ACPI_GAS_ID_EMBEDDED_CONTROLLER, + 0, + 0, + ACPI_GAS_ACCESS_DWORD, + HWIO_SCSS_RESET_ADDR + }, + + SCSS_SYS_POR, // RESET_VALUE; + // Bit 0 is for PSCI support + // Bit 1 is to tell the OS to use HVC instead of SMC. + // 0x0 to disable PSCI + 0x1, // ARM_BOOT_ARCH; + ACPI_RESERVED, // FADT Minor Version; + ACPI_RESERVED, // X_FIRMWARE_CTRL; + ACPI_RESERVED, // X_DSDT; + { // X_PM1a_EVT_BLK; + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + }, + { // X_PM1b_EVT_BLK; + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + }, + { // X_PM1a_CNT_BLK; + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + }, + { // X_PM1b_CNT_BLK; + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + }, + { // X_PM2_CNT_BLK; + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + }, + { // X_PM_TMR_BLK; + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + }, + { // X_GPE0_BLK; + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + }, + { // X_GPE1_BLK; + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + }, + { // SLEEP_CONTROL_REG; + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + }, + { // SLEEP_STATUS_REG; + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + }, + HYP_VENDOR_ID, // Hypervisor Vendor Identity +}; + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/Facs.aslc b/sdm845Pkg/AcpiTables/src/sc8180x/common/Facs.aslc new file mode 100644 index 0000000..d546172 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/Facs.aslc @@ -0,0 +1,48 @@ +// +// Copyright (c) 2011, Mmoclauq Technologies Inc. All rights reserved. +// + +#include "Platform.h" + +ACPI_FACS FACS = { + ACPI_FACS_SIGNATURE, + sizeof (ACPI_FACS), + 0x00000000, + 0x00, + 0x00, + 0x00, + 0x00000000, + 0x02, + { + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + }, + 0x00, + { + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED, + ACPI_RESERVED + } +}; diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/Gtdt.aslc b/sdm845Pkg/AcpiTables/src/sc8180x/common/Gtdt.aslc new file mode 100644 index 0000000..8e24f93 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/Gtdt.aslc @@ -0,0 +1,96 @@ +/*++ + +Copyright (c) 2016, Mmoclauq Technologies Inc. All rights reserved. + + +Module Name: + + Gdtd.aslc + +Abstract: + + Generic Timer Description Table + +Author: + + Harb Abdulhamid harba 1-Jan-2012 + +Environment: + + Firmware. + +Revision History: + +--*/ + +#include "Platform.h" +#include + +#pragma pack(push, 1) + +#define UNSUPPORTED_ADDR 0xFFFFFFFFFFFFFFFF +#define QTIMER_PHYS_AC_ADDR 0x17C20000 +#define QTIMER_CNTBASE_PHYS_ADDR 0x17C21000 +#define QTIMER_CNTEL0BASE_PHYS_ADDR 0x17C22000 + +ACPI_GTDT Gtdt = { + //------------------------------------------------------------------------ + // GTDT Header + //------------------------------------------------------------------------ + ACPI_GTDT_SIGNATURE, // Signature (4 bytes) + sizeof(ACPI_GTDT), // Length (4 bytes) + ACPI_GTDT_REVISION, // Revision (1 byte) + 0x00, // Checksum calculated at runtime (1 byte) + ACPI_OEM_ID, // OEMID is a 6 bytes long field (6 bytes) + ACPI_OEM_TABLE_ID, // OEM table identification (8 bytes) + ACPI_OEM_REVISION, // OEM revision number (4 bytes) + ACPI_CREATOR_ID, // ASL compiler vendor ID (4 bytes) + ACPI_CREATOR_REVISION, // ASL compiler revision number (4 bytes) + + //------------------------------------------------------------------------ + // Content + //------------------------------------------------------------------------ + + UNSUPPORTED_ADDR, // CntControlBase Physical Address (8 bytes) + 0x0, // GlobalFlags - memory mapped, level (4 bytes) + 17, // SecurePL1GSIV (4 bytes) + 0x0, // SecurePL1Flags - level, active high (4 bytes) + 18, // NonSecurePL1GSIV (4 bytes) + 0x0, // NonSecurePL1Flags - level, active high (4 bytes) + 19, // VirtualGSIV (4 bytes) + 0, // VirtualFlags - level, active high (4 bytes) + 16, // NonSecurePL2GSIV - not really supported (4 bytes) + 0, // NonSecurePL2Flags - level, active high (4 bytes) + + // ------------------------------------------------------------------------ + // Platform timer definitions + // ------------------------------------------------------------------------ + + UNSUPPORTED_ADDR, // CntReadBase Phys Addr (8 bytes) + 1, // Platform Timer Count (4 bytes) + 96, // Platform timer offset (4 bytes) + { + { + 0, // GT block type (1 byte) + 60, // Length, 20 + n * 40 (2 bytes) + 0, // Reserved (1 byte) + QTIMER_PHYS_AC_ADDR, // Physical address for CntControlBase (8 bytes) + 1, // Number of timers (4 bytes) + 20, // Offset to the platform timer from start of this struct (4 bytes) + + {{ + 0, // Frame number (1 byte) + 0,0,0, // Reserved (3 bytes) + QTIMER_CNTBASE_PHYS_ADDR, // CntBase phys addr (8 bytes) + QTIMER_CNTEL0BASE_PHYS_ADDR, // CntEl0Base phys addr (8 bytes) + 40, // GSIV for physical timer (4 bytes) + 0, // Trigger for physical timer - Level High (4 bytes) + 38, // GSIV for virtual timer, 0 if not implemented (4 bytes) + 0, // Flags for virtual timer - Level High (4 bytes) + 2, // Common flags; 0x2 = always-on (4 bytes) + }} + } + } +}; + +#pragma pack(pop) diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/HoyaSmmu.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/HoyaSmmu.asl new file mode 100644 index 0000000..9549a9b --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/HoyaSmmu.asl @@ -0,0 +1,221 @@ + + + // + // SMMU Driver + // + // SMT vector diagram: \\brewmp4\public\Istari\ + // + // Need to change Device Name in resorce file + // Currently Marking CP-P, CP-NP as CP_Pixel only need to add these VM + // to SMMU driver and need to update + + Device (MMU0) + { + // ATCU + + Name (_HID, "HID_MMU0") + Name (_UID, 0) + Alias(\_SB.PSUB, _SUB) + Alias(\_SB.SVMJ, _HRV) + Name (_DEP, Package (0x1) + { + \_SB_.MMU1 + }) + + + Method (_CRS, 0x0, NotSerialized) + { + Return (ResourceTemplate () + { + // a-TCU register address space + Memory32Fixed (ReadWrite, 0x15000000, 0x100000) + + // a-TCU: there is one interrupt for each CB handled by HLOS clients (only non-secure CBs) + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {129} // CB 0 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {130} // CB 1 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {131} // CB 2 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {132} // CB 3 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {133} // CB 4 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {134} // CB 5 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {135} // CB 6 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {136} // CB 7 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {137} // CB 8 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {138} // CB 9 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {139} // CB 10 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {140} // CB 11 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {141} // CB 12 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {142} // CB 13 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {143} // CB 14 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {144} // CB 15 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {145} // CB 16 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {146} // CB 17 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {147} // CB 18 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {148} // CB 19 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {149} // CB 20 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {150} // CB 21 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {213} // CB 22 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {214} // CB 23 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {215} // CB 24 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {216} // CB 25 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {217} // CB 26 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {218} // CB 27 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {219} // CB 28 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {220} // CB 29 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {221} // CB 30 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {222} // CB 31 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {223} // CB 32 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {224} // CB 33 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {347} // CB 34 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {348} // CB 35 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {349} // CB 36 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {350} // CB 37 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {351} // CB 38 + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {352} // CB 39 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {353} // CB 40 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {354} // CB 41 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {355} // CB 42 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {356} // CB 43 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {357} // CB 44 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {358} // CB 45 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {359} // CB 46 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {360} // CB 47 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {361} // CB 48 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {362} // CB 49 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {363} // CB 50 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {364} // CB 51 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {365} // CB 52 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {366} // CB 53 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {367} // CB 54 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {368} // CB 55 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {369} // CB 56 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {370} // CB 57 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {371} // CB 58 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {372} // CB 59 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {373} // CB 60 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {374} // CB 61 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {375} // CB 62 + + + // Not used for mapping + //Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {376} // CB 63 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {377} // CB 64 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {427} // CB 65 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {428} // CB 66 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {429} // CB 67 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {430} // CB 68 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {431} // CB 69 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {432} // CB 70 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {433} // CB 71 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {434} // CB 72 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {435} // CB 73 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {436} // CB 74 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {437} // CB 75 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {438} // CB 76 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {439} // CB 77 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {440} // CB 78 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {441} // CB 79 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {442} // CB 80 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {443} // CB 81 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {444} // CB 82 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {445} // CB 83 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {672} // CB 97 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {673} // CB 96 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {674} // CB 95 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {675} // CB 94 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {738} // CB 84 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {739} // CB 85 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {740} // CB 86 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {741} // CB 87 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {742} // CB 88 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {743} // CB 89 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {744} // CB 90 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {745} // CB 91 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {746} // CB 92 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {747} // CB 93 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {800} // CB 98 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {801} // CB 99 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {802} // CB 100 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {803} // CB 101 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {804} // CB 102 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {805} // CB 103 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {806} // CB 104 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {807} // CB 105 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {808} // CB 106 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {809} // CB 107 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {810} // CB 108 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {811} // CB 109 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {812} // CB 110 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {813} // CB 111 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {814} // CB 112 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {815} // CB 113 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {816} // CB 114 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {817} // CB 115 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {818} // CB 116 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {819} // CB 117 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {820} // CB 118 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {821} // CB 119 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {822} // CB 120 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {823} // CB 121 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {824} // CB 122 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {825} // CB 123 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {826} // CB 124 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {827} // CB 125 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {828} // CB 126 + // Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {829} // CB 127 + + }) + } + } + + Device (MMU1) + { + // This is the SMMU for Oxili/GFX + + Name (_HID, "HID_MMU0") + Name (_UID, 1) + Alias(\_SB.PSUB, _SUB) + Alias(\_SB.SVMJ, _HRV) + Name (_DEP, Package() + { + \_SB_.PEP0 + }) + + // When testing on 8960, delete the _CRS method. This will cause + // the driver to use a chunk of RAM. + + Method (_CRS, 0x0, NotSerialized) + { + Return (ResourceTemplate () + { + //g-TCU register address space + Memory32Fixed (ReadWrite, 0x02CA0000, 0x10000) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {712} // CB 0 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {713} // CB 1 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {714} // CB 2 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {715} // CB 3 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {716} // CB 4 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {717} // CB 5 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {718} // CB 6 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {719} // CB 7 + }) + } + } + Device (IMM0) + { + // ATCU + + Name (_HID, "HID_IMMU") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + } + + Device (IMM1) + { + // This is the SMMU for Oxili/GFX + + Name (_HID, "HID_IMMU") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + } diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/IORT.aslc b/sdm845Pkg/AcpiTables/src/sc8180x/common/IORT.aslc new file mode 100644 index 0000000..5002c2b --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/IORT.aslc @@ -0,0 +1,2776 @@ +//######################################################################### +//######################################################################### +//# THIS IS AN AUTOGENERATED FILE, DO NOT EDIT MANUALLY # +//######################################################################### +//######################################################################### + + + +#include "Platform.h" +#define offsetof(s,m) (UINT64)&(((s *)0)->m) + +#pragma pack(1) +typedef struct _INTERRUPT { + UINT32 GSIV; + UINT32 InterruptFlags; +}INTERRUPT; + + + +typedef struct _SMMUV2NODE_SMMU_APPSTCU{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT64 BaseAddress; + UINT64 Span; + UINT32 Model; + UINT32 Flags; + UINT32 GlobalIntOffset; + UINT32 NumContextInterrupts; + UINT32 ContextIntOffset; + UINT32 NumPMUInterrupts; + UINT32 PMUIntOffset; + UINT32 NSGIRPT_GSIV; + UINT32 NSGIRPT_FLAGS; + UINT32 NSGCFGIRPT_GSIV; + UINT32 NSGCFGIRPT_FLAGS; + INTERRUPT ContextInterrupts[128]; + INTERRUPT PMUInterrupts[9]; +}SMMUV2NODE_SMMU_APPSTCU; + +#define SMMUV2NODE_SMMU_APPSTCU_VAR { \ + .Type = 3, \ + .Length = sizeof(SMMUV2NODE_SMMU_APPSTCU), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 0, \ + .MappingsOffset = 0, \ + .BaseAddress = 0x15000000, \ + .Span = 0x100000, \ + .Model = 3, \ + .Flags = 0, \ + .GlobalIntOffset = offsetof(SMMUV2NODE_SMMU_APPSTCU,NSGIRPT_GSIV), \ + .NumContextInterrupts = 128, \ + .ContextIntOffset = offsetof(SMMUV2NODE_SMMU_APPSTCU,ContextInterrupts), \ + .NumPMUInterrupts = 9, \ + .PMUIntOffset = offsetof(SMMUV2NODE_SMMU_APPSTCU,PMUInterrupts), \ + .NSGIRPT_GSIV = 97, \ + .NSGIRPT_FLAGS = 0, \ + .NSGCFGIRPT_GSIV = 0, \ + .NSGCFGIRPT_FLAGS = 0, \ + .ContextInterrupts ={ \ + { \ + .InterruptFlags = 1, \ + .GSIV = 129, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 130, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 131, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 132, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 133, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 134, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 135, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 136, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 137, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 138, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 139, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 140, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 141, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 142, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 143, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 144, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 145, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 146, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 147, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 148, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 149, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 150, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 213, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 214, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 215, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 216, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 217, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 218, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 219, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 220, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 221, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 222, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 223, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 224, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 347, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 348, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 349, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 350, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 351, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 352, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 353, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 354, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 355, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 356, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 357, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 358, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 359, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 360, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 361, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 362, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 363, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 364, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 365, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 366, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 367, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 368, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 369, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 370, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 371, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 372, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 373, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 374, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 375, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 376, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 377, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 427, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 428, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 429, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 430, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 431, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 432, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 433, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 434, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 435, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 436, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 437, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 438, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 439, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 440, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 441, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 442, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 443, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 444, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 445, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 672, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 673, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 674, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 675, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 738, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 739, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 740, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 741, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 742, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 743, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 744, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 745, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 746, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 747, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 800, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 801, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 802, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 803, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 804, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 805, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 806, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 807, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 808, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 809, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 810, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 811, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 812, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 813, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 814, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 815, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 816, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 817, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 818, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 819, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 820, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 821, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 822, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 823, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 824, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 825, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 826, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 827, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 828, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 829, \ + }, \ + }, \ + .PMUInterrupts ={ \ + { \ + .InterruptFlags = 1, \ + .GSIV = 100, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 101, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 102, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 103, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 104, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 105, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 126, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 127, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 128, \ + }, \ + }, \ +} + +typedef struct _SMMUV2NODE_SMMU_GFXTCU{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT64 BaseAddress; + UINT64 Span; + UINT32 Model; + UINT32 Flags; + UINT32 GlobalIntOffset; + UINT32 NumContextInterrupts; + UINT32 ContextIntOffset; + UINT32 NumPMUInterrupts; + UINT32 PMUIntOffset; + UINT32 NSGIRPT_GSIV; + UINT32 NSGIRPT_FLAGS; + UINT32 NSGCFGIRPT_GSIV; + UINT32 NSGCFGIRPT_FLAGS; + INTERRUPT ContextInterrupts[8]; + INTERRUPT PMUInterrupts[4]; +}SMMUV2NODE_SMMU_GFXTCU; + +#define SMMUV2NODE_SMMU_GFXTCU_VAR { \ + .Type = 3, \ + .Length = sizeof(SMMUV2NODE_SMMU_GFXTCU), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 0, \ + .MappingsOffset = 0, \ + .BaseAddress = 0x2CA0000, \ + .Span = 0x10000, \ + .Model = 3, \ + .Flags = 0, \ + .GlobalIntOffset = offsetof(SMMUV2NODE_SMMU_GFXTCU,NSGIRPT_GSIV), \ + .NumContextInterrupts = 8, \ + .ContextIntOffset = offsetof(SMMUV2NODE_SMMU_GFXTCU,ContextInterrupts), \ + .NumPMUInterrupts = 4, \ + .PMUIntOffset = offsetof(SMMUV2NODE_SMMU_GFXTCU,PMUInterrupts), \ + .NSGIRPT_GSIV = 705, \ + .NSGIRPT_FLAGS = 0, \ + .NSGCFGIRPT_GSIV = 0, \ + .NSGCFGIRPT_FLAGS = 0, \ + .ContextInterrupts ={ \ + { \ + .InterruptFlags = 1, \ + .GSIV = 712, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 713, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 714, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 715, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 716, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 717, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 718, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 719, \ + }, \ + }, \ + .PMUInterrupts ={ \ + { \ + .InterruptFlags = 1, \ + .GSIV = 708, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 709, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 710, \ + }, \ + { \ + .InterruptFlags = 1, \ + .GSIV = 711, \ + }, \ + }, \ +} + +typedef struct _SIDMAPPING { + UINT32 InputBase; + UINT32 NumIDs; + UINT32 OutputBase; + UINT32 OutputReference; + UINT32 Flags; +}SIDMAPPING; + + + +typedef struct _PCIROOTCOMPLEX_PCI{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT64 MemAccessProps; + UINT32 ATSAttribute; + UINT32 PCISegmentNumber; + SIDMAPPING SIDMappings[4]; +}PCIROOTCOMPLEX_PCI; + +#define PCIROOTCOMPLEX_PCI_VAR { \ + .Type = 2, \ + .Length = sizeof(PCIROOTCOMPLEX_PCI), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 4, \ + .MappingsOffset = offsetof(PCIROOTCOMPLEX_PCI,SIDMappings), \ + .MemAccessProps = 0x0100000000000001, \ + .ATSAttribute = 1, \ + .PCISegmentNumber = 0, \ + .SIDMappings ={ \ + { \ + .InputBase = 0x87030000, \ + .NumIDs = 0x7F, \ + .OutputBase = 0x1C80, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x87030080, \ + .NumIDs = 0x7F, \ + .OutputBase = 0x1D00, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x87030100, \ + .NumIDs = 0x7F, \ + .OutputBase = 0x1D80, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x87030180, \ + .NumIDs = 0x7F, \ + .OutputBase = 0x1E00, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_GPU0{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[51]; +}NAMEDNODE_GPU0; + +#define NAMEDNODE_GPU0_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_GPU0), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 51, \ + .MappingsOffset = offsetof(NAMEDNODE_GPU0,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 40, \ + .DevObjectName = "\\_SB.GPU0", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x030A0000, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0002, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x030A0001, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0402, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x030A0002, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0802, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x030A0003, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0C02, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030000, \ + .NumIDs = 0x1, \ + .OutputBase = 0x0000, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030002, \ + .NumIDs = 0x1, \ + .OutputBase = 0x400, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030004, \ + .NumIDs = 0x1, \ + .OutputBase = 0x800, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030006, \ + .NumIDs = 0x1, \ + .OutputBase = 0xC00, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0303000C, \ + .NumIDs = 0x0, \ + .OutputBase = 0x04, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0303000D, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0404, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0303000E, \ + .NumIDs = 0x0, \ + .OutputBase = 0x804, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0303000F, \ + .NumIDs = 0x0, \ + .OutputBase = 0xC04, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030008, \ + .NumIDs = 0x0, \ + .OutputBase = 0x5, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030009, \ + .NumIDs = 0x0, \ + .OutputBase = 0x405, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0303000A, \ + .NumIDs = 0x0, \ + .OutputBase = 0x805, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0303000B, \ + .NumIDs = 0x0, \ + .OutputBase = 0xC05, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x00030000, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0800, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x000A0000, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0801, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x00030001, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0820, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x000A0001, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0821, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x00030002, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0C00, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x000A0002, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0C01, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x00030003, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0C20, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x000A0003, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0C21, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x06030000, \ + .NumIDs = 0x0, \ + .OutputBase = 0x2040, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x060A0000, \ + .NumIDs = 0x0, \ + .OutputBase = 0x2041, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030010, \ + .NumIDs = 0x0, \ + .OutputBase = 0x7, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030011, \ + .NumIDs = 0x0, \ + .OutputBase = 0x9, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030012, \ + .NumIDs = 0x0, \ + .OutputBase = 0x407, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030013, \ + .NumIDs = 0x0, \ + .OutputBase = 0x409, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030014, \ + .NumIDs = 0x0, \ + .OutputBase = 0x807, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030015, \ + .NumIDs = 0x0, \ + .OutputBase = 0x809, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030016, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0C07, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x03030017, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0C09, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_gfxtcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0C030000, \ + .NumIDs = 3, \ + .OutputBase = 0x504, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0C030004, \ + .NumIDs = 0x0, \ + .OutputBase = 0x512, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0C030005, \ + .NumIDs = 0, \ + .OutputBase = 0x51F, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0C030006, \ + .NumIDs = 5, \ + .OutputBase = 0x514, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0C090000, \ + .NumIDs = 0, \ + .OutputBase = 0x513, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0C090001, \ + .NumIDs = 0, \ + .OutputBase = 0x51E, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0C090002, \ + .NumIDs = 1, \ + .OutputBase = 0x51C, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x04030000, \ + .NumIDs = 0, \ + .OutputBase = 0x2300, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x04030001, \ + .NumIDs = 0, \ + .OutputBase = 0x2320, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x04030002, \ + .NumIDs = 0, \ + .OutputBase = 0x2340, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x04090000, \ + .NumIDs = 0, \ + .OutputBase = 0x2301, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x04090001, \ + .NumIDs = 0, \ + .OutputBase = 0x2305, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x040A0000, \ + .NumIDs = 0, \ + .OutputBase = 0x2303, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x040A0001, \ + .NumIDs = 0, \ + .OutputBase = 0x2323, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x040B0000, \ + .NumIDs = 0, \ + .OutputBase = 0x2304, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x040B0001, \ + .NumIDs = 0, \ + .OutputBase = 0x2324, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x040B0002, \ + .NumIDs = 0, \ + .OutputBase = 0x2344, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_JPGE{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[2]; +}NAMEDNODE_JPGE; + +#define NAMEDNODE_JPGE_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_JPGE), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 2, \ + .MappingsOffset = offsetof(NAMEDNODE_JPGE,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.JPGE", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x02030000, \ + .NumIDs = 0, \ + .OutputBase = 0x2100, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x02030001, \ + .NumIDs = 0, \ + .OutputBase = 0x2120, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_ARPC{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[57]; +}NAMEDNODE_ARPC; + +#define NAMEDNODE_ARPC_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_ARPC), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 57, \ + .MappingsOffset = offsetof(NAMEDNODE_ARPC,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.ARPC", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x17030010, \ + .NumIDs = 0, \ + .OutputBase = 0x1B23, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030011, \ + .NumIDs = 0, \ + .OutputBase = 0x1B24, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030012, \ + .NumIDs = 0, \ + .OutputBase = 0x1B25, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030000, \ + .NumIDs = 0, \ + .OutputBase = 0x1401, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030001, \ + .NumIDs = 0, \ + .OutputBase = 0x1421, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030002, \ + .NumIDs = 0, \ + .OutputBase = 0x1441, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030003, \ + .NumIDs = 0, \ + .OutputBase = 0x1001, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030004, \ + .NumIDs = 0, \ + .OutputBase = 0x1021, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030005, \ + .NumIDs = 0, \ + .OutputBase = 0x1041, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030006, \ + .NumIDs = 0, \ + .OutputBase = 0x1402, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030007, \ + .NumIDs = 0, \ + .OutputBase = 0x1422, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030008, \ + .NumIDs = 0, \ + .OutputBase = 0x1442, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030009, \ + .NumIDs = 0, \ + .OutputBase = 0x1002, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703000A, \ + .NumIDs = 0, \ + .OutputBase = 0x1022, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703000B, \ + .NumIDs = 0, \ + .OutputBase = 0x1042, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030013, \ + .NumIDs = 0, \ + .OutputBase = 0x1403, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030014, \ + .NumIDs = 0, \ + .OutputBase = 0x1423, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030015, \ + .NumIDs = 0, \ + .OutputBase = 0x1443, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030016, \ + .NumIDs = 0, \ + .OutputBase = 0x1003, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030017, \ + .NumIDs = 0, \ + .OutputBase = 0x1023, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030018, \ + .NumIDs = 0, \ + .OutputBase = 0x1043, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030019, \ + .NumIDs = 0, \ + .OutputBase = 0x1404, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703001A, \ + .NumIDs = 0, \ + .OutputBase = 0x1424, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703001B, \ + .NumIDs = 0, \ + .OutputBase = 0x1444, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703001C, \ + .NumIDs = 0, \ + .OutputBase = 0x1004, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703001D, \ + .NumIDs = 0, \ + .OutputBase = 0x1024, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703001E, \ + .NumIDs = 0, \ + .OutputBase = 0x1044, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703001F, \ + .NumIDs = 0, \ + .OutputBase = 0x1405, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030020, \ + .NumIDs = 0, \ + .OutputBase = 0x1425, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030021, \ + .NumIDs = 0, \ + .OutputBase = 0x1445, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030022, \ + .NumIDs = 0, \ + .OutputBase = 0x1005, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030023, \ + .NumIDs = 0, \ + .OutputBase = 0x1025, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030024, \ + .NumIDs = 0, \ + .OutputBase = 0x1045, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030025, \ + .NumIDs = 0, \ + .OutputBase = 0x1426, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030026, \ + .NumIDs = 0, \ + .OutputBase = 0x1006, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030027, \ + .NumIDs = 0, \ + .OutputBase = 0x1446, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030028, \ + .NumIDs = 0, \ + .OutputBase = 0x1026, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030029, \ + .NumIDs = 0, \ + .OutputBase = 0x1406, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703002A, \ + .NumIDs = 0, \ + .OutputBase = 0x1046, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703002B, \ + .NumIDs = 0, \ + .OutputBase = 0x1407, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703002C, \ + .NumIDs = 0, \ + .OutputBase = 0x1427, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703002D, \ + .NumIDs = 0, \ + .OutputBase = 0x1447, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703002E, \ + .NumIDs = 0, \ + .OutputBase = 0x1007, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x1703002F, \ + .NumIDs = 0, \ + .OutputBase = 0x1027, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030030, \ + .NumIDs = 0, \ + .OutputBase = 0x1047, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030031, \ + .NumIDs = 0, \ + .OutputBase = 0x1408, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030032, \ + .NumIDs = 0, \ + .OutputBase = 0x1428, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030033, \ + .NumIDs = 0, \ + .OutputBase = 0x1448, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030034, \ + .NumIDs = 0, \ + .OutputBase = 0x1008, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030035, \ + .NumIDs = 0, \ + .OutputBase = 0x1028, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x17030036, \ + .NumIDs = 0, \ + .OutputBase = 0x1048, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x170A0000, \ + .NumIDs = 0, \ + .OutputBase = 0x1409, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x170A0001, \ + .NumIDs = 0, \ + .OutputBase = 0x1429, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x170A0002, \ + .NumIDs = 0, \ + .OutputBase = 0x1449, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x170A0003, \ + .NumIDs = 0, \ + .OutputBase = 0x1009, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x170A0004, \ + .NumIDs = 0, \ + .OutputBase = 0x1029, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x170A0005, \ + .NumIDs = 0, \ + .OutputBase = 0x1049, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_IPA{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_IPA; + +#define NAMEDNODE_IPA_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_IPA), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_IPA,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.IPA", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x0B030000, \ + .NumIDs = 2, \ + .OutputBase = 0x520, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_USBA{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_USBA; + +#define NAMEDNODE_USBA_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_USBA), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_USBA,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.USBA", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x0703000A, \ + .NumIDs = 0x0, \ + .OutputBase = 0x1B2F, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_NPU0{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[4]; +}NAMEDNODE_NPU0; + +#define NAMEDNODE_NPU0_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_NPU0), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 4, \ + .MappingsOffset = offsetof(NAMEDNODE_NPU0,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.NPU0", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x18030000, \ + .NumIDs = 0, \ + .OutputBase = 0x1081, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x18030001, \ + .NumIDs = 0, \ + .OutputBase = 0x1481, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x180A0000, \ + .NumIDs = 0, \ + .OutputBase = 0x1084, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x180A0001, \ + .NumIDs = 0, \ + .OutputBase = 0x1484, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_QDSS{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[2]; +}NAMEDNODE_QDSS; + +#define NAMEDNODE_QDSS_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_QDSS), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 2, \ + .MappingsOffset = offsetof(NAMEDNODE_QDSS,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.QDSS", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x89030000, \ + .NumIDs = 0, \ + .OutputBase = 0x4A0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x89030001, \ + .NumIDs = 0, \ + .OutputBase = 0x5E0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_ADCM{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[6]; +}NAMEDNODE_ADCM; + +#define NAMEDNODE_ADCM_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_ADCM), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 6, \ + .MappingsOffset = offsetof(NAMEDNODE_ADCM,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.ADSP.SLM1.ADCM", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x07030000, \ + .NumIDs = 0, \ + .OutputBase = 0x1B21, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x07030001, \ + .NumIDs = 0x0, \ + .OutputBase = 0x1B46, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x07030002, \ + .NumIDs = 4, \ + .OutputBase = 0x1B4D, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0703000B, \ + .NumIDs = 0x0, \ + .OutputBase = 0x1B53, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0703000C, \ + .NumIDs = 0x0, \ + .OutputBase = 0x1B58, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0703000D, \ + .NumIDs = 0x2, \ + .OutputBase = 0x1B5C, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_QSPI0{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_QSPI0; + +#define NAMEDNODE_QSPI0_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_QSPI0), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_QSPI0,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.QSPI0", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x14030000, \ + .NumIDs = 0, \ + .OutputBase = 0x760, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_QSPI1{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_QSPI1; + +#define NAMEDNODE_QSPI1_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_QSPI1), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_QSPI1,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.QSPI1", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x14030001, \ + .NumIDs = 0, \ + .OutputBase = 0x7E0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_QUP{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[6]; +}NAMEDNODE_QUP; + +#define NAMEDNODE_QUP_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_QUP), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 6, \ + .MappingsOffset = offsetof(NAMEDNODE_QUP,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.QUP", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x13030000, \ + .NumIDs = 0, \ + .OutputBase = 0x4D6, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x13030001, \ + .NumIDs = 0, \ + .OutputBase = 0x4C3, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x10030000, \ + .NumIDs = 0, \ + .OutputBase = 0x603, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x10030001, \ + .NumIDs = 0, \ + .OutputBase = 0x616, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x12030000, \ + .NumIDs = 0, \ + .OutputBase = 0x7A3, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x12030001, \ + .NumIDs = 0, \ + .OutputBase = 0x7B6, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_SDC2{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[2]; +}NAMEDNODE_SDC2; + +#define NAMEDNODE_SDC2_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_SDC2), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 2, \ + .MappingsOffset = offsetof(NAMEDNODE_SDC2,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.SDC2", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x86030000, \ + .NumIDs = 0x0, \ + .OutputBase = 0x6A0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x86030001, \ + .NumIDs = 0x0, \ + .OutputBase = 0x6C0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_SEN1{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[2]; +}NAMEDNODE_SEN1; + +#define NAMEDNODE_SEN1_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_SEN1), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 2, \ + .MappingsOffset = offsetof(NAMEDNODE_SEN1,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.SEN1", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x85030000, \ + .NumIDs = 0, \ + .OutputBase = 0x4E3, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x85030001, \ + .NumIDs = 2, \ + .OutputBase = 0x5A1, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_TSC5{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_TSC5; + +#define NAMEDNODE_TSC5_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_TSC5), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_TSC5,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.TSC5", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x88030000, \ + .NumIDs = 0xF, \ + .OutputBase = 0x620, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_UFS0{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[3]; +}NAMEDNODE_UFS0; + +#define NAMEDNODE_UFS0_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_UFS0), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 3, \ + .MappingsOffset = offsetof(NAMEDNODE_UFS0,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0x0100000000000001, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.UFS0", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x81030000, \ + .NumIDs = 0, \ + .OutputBase = 0x000, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x81030001, \ + .NumIDs = 0, \ + .OutputBase = 0x2E0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x81030002, \ + .NumIDs = 0, \ + .OutputBase = 0x300, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_URS0{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_URS0; + +#define NAMEDNODE_URS0_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_URS0), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_URS0,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.URS0", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x80030000, \ + .NumIDs = 0, \ + .OutputBase = 0x140, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_USB0{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_USB0; + +#define NAMEDNODE_USB0_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_USB0), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_USB0,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.USB0", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x80030000, \ + .NumIDs = 0, \ + .OutputBase = 0x0140, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_URS1{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_URS1; + +#define NAMEDNODE_URS1_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_URS1), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_URS1,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.URS1", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x80030001, \ + .NumIDs = 0, \ + .OutputBase = 0x160, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_USB1{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_USB1; + +#define NAMEDNODE_USB1_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_USB1), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_USB1,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.USB1", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x80030001, \ + .NumIDs = 0, \ + .OutputBase = 0x160, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_URS2{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_URS2; + +#define NAMEDNODE_URS2_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_URS2), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_URS2,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.URS2", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x80030002, \ + .NumIDs = 0, \ + .OutputBase = 0x060, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_USB2{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_USB2; + +#define NAMEDNODE_USB2_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_USB2), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_USB2,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.USB2", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x80030002, \ + .NumIDs = 0, \ + .OutputBase = 0x060, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_VFE0{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[31]; +}NAMEDNODE_VFE0; + +#define NAMEDNODE_VFE0_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_VFE0), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 31, \ + .MappingsOffset = offsetof(NAMEDNODE_VFE0,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.GPU0.AVS0", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x01030000, \ + .NumIDs = 0, \ + .OutputBase = 0x20C0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030001, \ + .NumIDs = 0, \ + .OutputBase = 0x23C0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030002, \ + .NumIDs = 0, \ + .OutputBase = 0x2000, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030003, \ + .NumIDs = 0, \ + .OutputBase = 0x2140, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030004, \ + .NumIDs = 0, \ + .OutputBase = 0x2160, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030005, \ + .NumIDs = 0, \ + .OutputBase = 0x2042, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030006, \ + .NumIDs = 0, \ + .OutputBase = 0x0A00, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030007, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0A20, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030008, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0A40, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030009, \ + .NumIDs = 0, \ + .OutputBase = 0x0A60, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0103000A, \ + .NumIDs = 0, \ + .OutputBase = 0x0A80, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0103000B, \ + .NumIDs = 0, \ + .OutputBase = 0x0AA0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0103000C, \ + .NumIDs = 0, \ + .OutputBase = 0x0AC0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0103000D, \ + .NumIDs = 0, \ + .OutputBase = 0x0AE0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0103000E, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0E00, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0103000F, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0E20, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030010, \ + .NumIDs = 0, \ + .OutputBase = 0x0E40, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030011, \ + .NumIDs = 0, \ + .OutputBase = 0x0E60, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030012, \ + .NumIDs = 0, \ + .OutputBase = 0x0E80, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030013, \ + .NumIDs = 0, \ + .OutputBase = 0x0EA0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030014, \ + .NumIDs = 0, \ + .OutputBase = 0x0EC0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030015, \ + .NumIDs = 0x0, \ + .OutputBase = 0x0EE0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030016, \ + .NumIDs = 0x0, \ + .OutputBase = 0x2080, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030017, \ + .NumIDs = 0, \ + .OutputBase = 0x20A0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030018, \ + .NumIDs = 0, \ + .OutputBase = 0x2380, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x01030019, \ + .NumIDs = 0, \ + .OutputBase = 0x23A0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0103001A, \ + .NumIDs = 0x0, \ + .OutputBase = 0x20E0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x0103001B, \ + .NumIDs = 0x0, \ + .OutputBase = 0x23E0, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x010D0000, \ + .NumIDs = 0, \ + .OutputBase = 0x1029, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x010D0001, \ + .NumIDs = 0, \ + .OutputBase = 0x1031, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + { \ + .InputBase = 0x010D0002, \ + .NumIDs = 0, \ + .OutputBase = 0x1039, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _NAMEDNODE_WLAN{ + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumberofMappings; + UINT32 MappingsOffset; + UINT32 NodeFlags; + UINT64 MemAccessProps; + UINT8 DeviceMemAddressSize; + UINT8 DevObjectName[32]; + SIDMAPPING SIDMappings[1]; +}NAMEDNODE_WLAN; + +#define NAMEDNODE_WLAN_VAR { \ + .Type = 1, \ + .Length = sizeof(NAMEDNODE_WLAN), \ + .Revision = 0, \ + .Reserved = 0, \ + .NumberofMappings = 1, \ + .MappingsOffset = offsetof(NAMEDNODE_WLAN,SIDMappings), \ + .NodeFlags = 0, \ + .MemAccessProps = 0, \ + .DeviceMemAddressSize = 36, \ + .DevObjectName = "\\_SB.AMSS.QWLN", \ + .SIDMappings ={ \ + { \ + .InputBase = 0x11030000, \ + .NumIDs = 1, \ + .OutputBase = 0x640, \ + .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \ + .Flags = 0, \ + }, \ + }, \ +} + +typedef struct _IORT{ + UINT32 Signature; + UINT32 Length; + UINT8 Revision; + UINT8 Checksum; + UINT8 OEMID[6]; + UINT64 OEMTableID; + UINT32 OEMRevision; + UINT32 CreatorID; + UINT32 CreatorRevision; + UINT32 NumberofIORTNodes; + UINT32 IORTNodesOffset; + UINT32 Reserved; + SMMUV2NODE_SMMU_APPSTCU SMMUV2Nodes_smmu_appstcu; + SMMUV2NODE_SMMU_GFXTCU SMMUV2Nodes_smmu_gfxtcu; + PCIROOTCOMPLEX_PCI PCIRootComplexes_pci; + NAMEDNODE_GPU0 NamedNodes_gpu0; + NAMEDNODE_JPGE NamedNodes_jpge; + NAMEDNODE_ARPC NamedNodes_arpc; + NAMEDNODE_IPA NamedNodes_ipa; + NAMEDNODE_USBA NamedNodes_usba; + NAMEDNODE_NPU0 NamedNodes_npu0; + NAMEDNODE_QDSS NamedNodes_qdss; + NAMEDNODE_ADCM NamedNodes_adcm; + NAMEDNODE_QSPI0 NamedNodes_qspi0; + NAMEDNODE_QSPI1 NamedNodes_qspi1; + NAMEDNODE_QUP NamedNodes_qup; + NAMEDNODE_SDC2 NamedNodes_sdc2; + NAMEDNODE_SEN1 NamedNodes_sen1; + NAMEDNODE_TSC5 NamedNodes_tsc5; + NAMEDNODE_UFS0 NamedNodes_ufs0; + NAMEDNODE_URS0 NamedNodes_urs0; + NAMEDNODE_USB0 NamedNodes_usb0; + NAMEDNODE_URS1 NamedNodes_urs1; + NAMEDNODE_USB1 NamedNodes_usb1; + NAMEDNODE_URS2 NamedNodes_urs2; + NAMEDNODE_USB2 NamedNodes_usb2; + NAMEDNODE_VFE0 NamedNodes_vfe0; + NAMEDNODE_WLAN NamedNodes_wlan; +}IORT; + +IORT IORT_TABLE = { + .Signature = 'TROI', + .Length = sizeof(IORT), + .Revision = 0, + .Checksum = 0, + .OEMID = ACPI_OEM_ID, + .OEMTableID = ACPI_OEM_TABLE_ID, + .OEMRevision = ACPI_OEM_REVISION, + .CreatorID = ACPI_CREATOR_ID, + .CreatorRevision = ACPI_CREATOR_REVISION, + .NumberofIORTNodes = 26, + .IORTNodesOffset = offsetof(IORT,Reserved)+4, + .Reserved = 0, + .SMMUV2Nodes_smmu_appstcu = SMMUV2NODE_SMMU_APPSTCU_VAR , + .SMMUV2Nodes_smmu_gfxtcu = SMMUV2NODE_SMMU_GFXTCU_VAR , + .PCIRootComplexes_pci = PCIROOTCOMPLEX_PCI_VAR , + .NamedNodes_gpu0 = NAMEDNODE_GPU0_VAR , + .NamedNodes_jpge = NAMEDNODE_JPGE_VAR , + .NamedNodes_arpc = NAMEDNODE_ARPC_VAR , + .NamedNodes_ipa = NAMEDNODE_IPA_VAR , + .NamedNodes_usba = NAMEDNODE_USBA_VAR , + .NamedNodes_npu0 = NAMEDNODE_NPU0_VAR , + .NamedNodes_qdss = NAMEDNODE_QDSS_VAR , + .NamedNodes_adcm = NAMEDNODE_ADCM_VAR , + .NamedNodes_qspi0 = NAMEDNODE_QSPI0_VAR , + .NamedNodes_qspi1 = NAMEDNODE_QSPI1_VAR , + .NamedNodes_qup = NAMEDNODE_QUP_VAR , + .NamedNodes_sdc2 = NAMEDNODE_SDC2_VAR , + .NamedNodes_sen1 = NAMEDNODE_SEN1_VAR , + .NamedNodes_tsc5 = NAMEDNODE_TSC5_VAR , + .NamedNodes_ufs0 = NAMEDNODE_UFS0_VAR , + .NamedNodes_urs0 = NAMEDNODE_URS0_VAR , + .NamedNodes_usb0 = NAMEDNODE_USB0_VAR , + .NamedNodes_urs1 = NAMEDNODE_URS1_VAR , + .NamedNodes_usb1 = NAMEDNODE_USB1_VAR , + .NamedNodes_urs2 = NAMEDNODE_URS2_VAR , + .NamedNodes_usb2 = NAMEDNODE_USB2_VAR , + .NamedNodes_vfe0 = NAMEDNODE_VFE0_VAR , + .NamedNodes_wlan = NAMEDNODE_WLAN_VAR , +}; + +#pragma pack() diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/Madt.aslc b/sdm845Pkg/AcpiTables/src/sc8180x/common/Madt.aslc new file mode 100644 index 0000000..0a4799d --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/Madt.aslc @@ -0,0 +1,366 @@ +/** @file + MADT Table + + This file contains a structure definition for the ACPI 6.x Multiple APIC + Description Table (MADT). + + Copyright (c) 2016 Mmoclauq Technologies Inc. All rights reserved.
+ +**/ + +#include "Platform.h" +#include "Acpi.h" + + +#define ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x00000005 + + +// +// Local APIC GIC address +// These are physical addresses on SDM845 +// +#define DISTRIBUTOR_PHYSICAL_ADDRESS 0x17A00000 +#define APCS_QGICDR_QGICDR_GICA 0x17A10000 +#define APCS_QGICDR_QGICDR_GICR 0x17A60000 + +//These addresses are defined by the MP shared region defined in the UEFI memory map. +#define MP_MAILBOX_ADDRESS_GIC0 0x0 +#define MP_MAILBOX_ADDRESS_GIC1 0x0 +#define MP_MAILBOX_ADDRESS_GIC2 0x0 +#define MP_MAILBOX_ADDRESS_GIC3 0x0 +#define MP_MAILBOX_ADDRESS_GIC4 0x0 +#define MP_MAILBOX_ADDRESS_GIC5 0x0 +#define MP_MAILBOX_ADDRESS_GIC6 0x0 +#define MP_MAILBOX_ADDRESS_GIC7 0x0 + +#define ACPI_PROCESSOR_LOCAL_GIC 11 +#define ACPI_GIC_DISTRIBUTOR 12 +#define ACPI_GIC_MSI_FRAME 13 +#define ACPI_GIC_REDISTRIBUTOR 14 + +#define PLGF_ENABLED_BIT 0 +#define PLGF_ENABLED (1 << PLGF_ENABLED_BIT) + +#pragma pack (1) + +typedef struct _ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 Identifier; + UINT32 AcpiProcessorId; + UINT32 Flags; + UINT32 ParkingProtocolVersion; + UINT32 PerformanceInterruptGsi; + UINT64 MailboxPhysicalAddress; + UINT64 ControllerPhysicalAddress; + UINT64 GICVirtual; // GIC virtual CPU interface registers. + UINT64 GICH; // GIC virtual interface control block registers. + UINT32 VGICMaintenanceInterrupt; // GVIS for Virtual GIC maintenance interrupt. + UINT64 GICRedistributorBaseAddress; // 64-bit address of the GIC Redistributor. + UINT64 MPIDR; + UINT8 ProcessorPowerEfficiencyClass; // added towards ACPI 6 + UINT8 Reserved2[3]; +} ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE; + +typedef struct _ACPI_GIC_DISTRIBUTOR_STRUCTURE { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 Identifier; + UINT64 ControllerPhysicalAddress; + UINT32 GsivBase; + UINT8 GicVersion; + UINT32 Reserved; +} ACPI_GIC_DISTRIBUTOR_STRUCTURE; + +typedef struct _ACPI_GIC_REDISTRIBUTOR_STRUCTURE { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 GICRedistributorPhysicalBaseAddress; + UINT32 GICRDiscoveryRangeLength; +} ACPI_GIC_REDISTRIBUTOR_STRUCTURE; + +typedef struct _ACPI_GIC_MSI_FRAME_STRUCTURE { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 Identifier; + UINT64 ControllerPhysicalAddress; + UINT32 Flags; + UINT16 SPI_Count; + UINT16 SPI_Base; +} ACPI_GIC_MSI_FRAME_STRUCTURE; + +typedef struct { + ACPI_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} APIC_DESCRIPTION_TABLE_HEADER; + + +// +// ACPI 5.0 MADT structure +// +typedef struct { + + APIC_DESCRIPTION_TABLE_HEADER Header; + ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic0; + ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic1; + ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic2; + ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic3; + ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic4; + ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic5; + ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic6; + ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic7; + ACPI_GIC_DISTRIBUTOR_STRUCTURE Distributor; + ACPI_GIC_REDISTRIBUTOR_STRUCTURE ReDistributor; + ACPI_GIC_MSI_FRAME_STRUCTURE MSIFrame0; +} ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// + +#pragma pack(1) +// +// Multiple APIC Description Table +// +ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = +{ + //Header + { + { + ACPI_APIC_SIGNATURE, //Signature + sizeof (ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE), //Length + ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, //Revision + 0, //Checksum + ACPI_OEM_ID, //OEMID + ACPI_OEM_TABLE_ID, //OEMTableID + ACPI_OEM_REVISION, //OEMRevision + ACPI_CREATOR_ID, //CreatorID + ACPI_CREATOR_REVISION //CreatorRevision + }, + 0x00000000, //LocalApicAddress + 0 //Flags + }, + + //LocalGic0 + { + ACPI_PROCESSOR_LOCAL_GIC, //Type + sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length + 0x00, //Reserved + 0x00, //Identifier + 0x00, //AcpiProcessorId + PLGF_ENABLED, //Flags + 0x00, //ParkingProtocolVersion + (16 + 5), //PerformanceInterruptGsi + MP_MAILBOX_ADDRESS_GIC0, //MailboxPhysicalAddress + 0x0000000000000000, //ControllerPhysicalAddress + 0x0000000000000000, // GIC virtual CPU interface registers. + 0x0000000000000000, // GIC virtual interface control block registers. + 0x18, // GVIS for Virtual GIC maintenance interrupt. + 0x0000000000000000, // 64-bit address of the GIC Redistributor. + 0x0000000000000000, //MPIDR + 0x00, //ProcessorPowerEfficiencyClass + {0x00, 0x00, 0x00} //Reserved + }, + + //LocalGic1 + { + ACPI_PROCESSOR_LOCAL_GIC, //Type + sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length + 0x00, //Reserved + 0x01, //Identifier + 0x01, //AcpiProcessorId + PLGF_ENABLED, //Flags + 0x00, //ParkingProtocolVersion + (16 + 5), //PerformanceInterruptGsi + MP_MAILBOX_ADDRESS_GIC1, //MailboxPhysicalAddress + 0x0000000000000000, //ControllerPhysicalAddress + 0x0000000000000000, // GIC virtual CPU interface registers. + 0x0000000000000000, // GIC virtual interface control block registers. + 0x18, // GVIS for Virtual GIC maintenance interrupt. + 0x0000000000000000, // 64-bit address of the GIC Redistributor. + 0x0000000000000100, //MPIDR + 0x00, //ProcessorPowerEfficiencyClass + {0x00, 0x00, 0x00} //Reserved + }, + + //LocalGic2 + { + ACPI_PROCESSOR_LOCAL_GIC, //Type + sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length + 0x00, //Reserved + 0x02, //Identifier + 0x02, //AcpiProcessorId + PLGF_ENABLED, //Flags + 0x00, //ParkingProtocolVersion + (16 + 5), //PerformanceInterruptGsi + MP_MAILBOX_ADDRESS_GIC2, //MailboxPhysicalAddress + 0x0000000000000000, //ControllerPhysicalAddress + 0x0000000000000000, // GIC virtual CPU interface registers. + 0x0000000000000000, // GIC virtual interface control block registers. + 0x18, // GVIS for Virtual GIC maintenance interrupt. + 0x0000000000000000, // 64-bit address of the GIC Redistributor. + 0x0000000000000200, //MPIDR + 0x00, //ProcessorPowerEfficiencyClass + {0x00, 0x00, 0x00} //Reserved + }, + + //LocalGic3 + { + ACPI_PROCESSOR_LOCAL_GIC, //Type + sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length + 0x00, //Reserved + 0x03, //Identifier + 0x03, //AcpiProcessorId + PLGF_ENABLED, //Flags + 0x0000, //ParkingProtocolVersion + (16 + 5), //PerformanceInterruptGsi + MP_MAILBOX_ADDRESS_GIC3, //MailboxPhysicalAddress + 0x0000000000000000, //ControllerPhysicalAddress + 0x0000000000000000, // GIC virtual CPU interface registers. + 0x0000000000000000, // GIC virtual interface control block registers. + 0x18, // GVIS for Virtual GIC maintenance interrupt. + 0x0000000000000000, // 64-bit address of the GIC Redistributor. + 0x0000000000000300, //MPIDR + 0x00, //ProcessorPowerEfficiencyClass + {0x00, 0x00, 0x00} //Reserved + }, + + //LocalGic4 + { + ACPI_PROCESSOR_LOCAL_GIC, //Type + sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length + 0x00, //Reserved + 0x04, //Identifier + 0x04, //AcpiProcessorId + PLGF_ENABLED, //Flags + 0x00, //ParkingProtocolVersion + (16 + 5), //PerformanceInterruptGsi + MP_MAILBOX_ADDRESS_GIC4, //MailboxPhysicalAddress + 0x0000000000000000, //ControllerPhysicalAddress + 0x0000000000000000, // GIC virtual CPU interface registers. + 0x0000000000000000, // GIC virtual interface control block registers. + 0x18, // GVIS for Virtual GIC maintenance interrupt. + 0x0000000000000000, // 64-bit address of the GIC Redistributor. + 0x0000000000000400, //MPIDR + 0x01, //ProcessorPowerEfficiencyClass + {0x00, 0x00, 0x00} //Reserved + }, + + //LocalGic5 + { + ACPI_PROCESSOR_LOCAL_GIC, //Type + sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length + 0x00, //Reserved + 0x05, //Identifier + 0x05, //AcpiProcessorId + PLGF_ENABLED, //Flags + 0x00, //ParkingProtocolVersion + (16 + 5), //PerformanceInterruptGsi + MP_MAILBOX_ADDRESS_GIC5, //MailboxPhysicalAddress + 0x0000000000000000, //ControllerPhysicalAddress + 0x0000000000000000, // GIC virtual CPU interface registers. + 0x0000000000000000, // GIC virtual interface control block registers. + 0x18, // GVIS for Virtual GIC maintenance interrupt. + 0x0000000000000000, // 64-bit address of the GIC Redistributor. + 0x0000000000000500, //MPIDR + 0x01, //ProcessorPowerEfficiencyClass + {0x00, 0x00, 0x00} //Reserved + }, + + //LocalGic6 + { + ACPI_PROCESSOR_LOCAL_GIC, //Type + sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length + 0x00, //Reserved + 0x06, //Identifier + 0x06, //AcpiProcessorId + PLGF_ENABLED, //Flags + 0x00, //ParkingProtocolVersion + (16 + 5), //PerformanceInterruptGsi + MP_MAILBOX_ADDRESS_GIC6, //MailboxPhysicalAddress + 0x0000000000000000, //ControllerPhysicalAddress + 0x0000000000000000, // GIC virtual CPU interface registers. + 0x0000000000000000, // GIC virtual interface control block registers. + 0x18, // GVIS for Virtual GIC maintenance interrupt. + 0x0000000000000000, // 64-bit address of the GIC Redistributor. + 0x0000000000000600, //MPIDR + 0x01, //ProcessorPowerEfficiencyClass + {0x00, 0x00, 0x00} //Reserved + }, + + //LocalGic7 + { + ACPI_PROCESSOR_LOCAL_GIC, //Type + sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length + 0x00, //Reserved + 0x07, //Identifier + 0x07, //AcpiProcessorId + PLGF_ENABLED, //Flags + 0x00, //ParkingProtocolVersion + (16 + 5), //PerformanceInterruptGsi + MP_MAILBOX_ADDRESS_GIC7, //MailboxPhysicalAddress + 0x0000000000000000, //ControllerPhysicalAddress + 0x0000000000000000, // GIC virtual CPU interface registers. + 0x0000000000000000, // GIC virtual interface control block registers. + 0x18, // GVIS for Virtual GIC maintenance interrupt. + 0x0000000000000000, // 64-bit address of the GIC Redistributor. + 0x0000000000000700, //MPIDR + 0x01, //ProcessorPowerEfficiencyClass + {0x00, 0x00, 0x00} //Reserved + }, + + //Distributor + { + ACPI_GIC_DISTRIBUTOR, //Type + sizeof (ACPI_GIC_DISTRIBUTOR_STRUCTURE), //Length + 0, //Reserved1 + 0, //Identfier + DISTRIBUTOR_PHYSICAL_ADDRESS, //ControllerPhysicalAddress + 0, //GsivBase + 3, //GicVersion + 0 //Reserved + }, + + //ReDistributor + { + ACPI_GIC_REDISTRIBUTOR, //Type + sizeof (ACPI_GIC_REDISTRIBUTOR_STRUCTURE), //Length + 0, //Reserved + APCS_QGICDR_QGICDR_GICR, //RedistributorPhysicalAddress + 0x100000 //Length + }, + + //MSI Frame0// + { + ACPI_GIC_MSI_FRAME, //Type + sizeof (ACPI_GIC_MSI_FRAME_STRUCTURE), //Length + 0x0, //Reserved1 + 0x0, //Identfier + APCS_QGICDR_QGICDR_GICA, //ControllerPhysicalAddress + 0x1, //Flags + 0x80, //SPI_Count + 0x340 //SPI_Base + } +}; +#pragma pack() + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from removing the + // data structure from the exeutable + // + return (VOID*)&Madt; +} + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/Mcfg.aslc b/sdm845Pkg/AcpiTables/src/sc8180x/common/Mcfg.aslc new file mode 100644 index 0000000..1919d8f --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/Mcfg.aslc @@ -0,0 +1,73 @@ +// +// Copyright (c) 2011-2014, Mmoclauq Technologies Inc. All rights reserved. +// + +#include "Platform.h" +#include + +#pragma pack(push, 1) + +typedef struct +{ + UINT64 BASE_ADDRESS ; + UINT16 PCI_SEGMENT_GROUP_NUMBER; + UINT8 START_BUS_NUMBER; + UINT8 END_BUS_NUMBER; + UINT32 RESERVED; +} MEMORY_MAPPED_CONFIG_BASE_ADDRESS; + +typedef struct +{ + ACPI_HEADER Header ; + UINT64 Reserved ; + MEMORY_MAPPED_CONFIG_BASE_ADDRESS Buses[4]; +}ENHANCED_CONFIGURATION_SPACE_ACCESS; + + +ENHANCED_CONFIGURATION_SPACE_ACCESS MCFG ={ + { + ACPI_MCFG_SIGNATURE, + sizeof (ENHANCED_CONFIGURATION_SPACE_ACCESS), + 1, + 0, // to make sum of entire table == 0, + ACPI_OEM_ID, + ACPI_OEM_TABLE_ID, + ACPI_OEM_REVISION, + ACPI_CREATOR_ID, + ACPI_CREATOR_REVISION + }, + 0x0, // reserved + { + { + 0x0000000060000000, //PCIE_GEN3X2_DBI + 0, //PCI Segment Group Number + 0, //Start Bus Number + 1, // End Bus Number + 0x0, //Reserved + }, + { + 0x0000000068000000, //PCIE_GEN3X2_DBI + 1, //PCI Segment Group Number + 0, //Start Bus Number + 1, // End Bus Number + 0x0, //Reserved + }, + { + 0x0000000070000000, //PCIE_GEN3X2_DBI + 2, //PCI Segment Group Number + 0, //Start Bus Number + 1, // End Bus Number + 0x0, //Reserved + }, + { + 0x0000000040000000, //PCIE_GEN3X4_EDMA_DBI + 3, //PCI Segment Group Number + 0, //Start Bus Number + 1, // End Bus Number + 0x0, //Reserved + } + } +}; +#pragma pack(pop) + + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/Pep_lpi.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/Pep_lpi.asl new file mode 100644 index 0000000..15fd046 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/Pep_lpi.asl @@ -0,0 +1,649 @@ + +Device (SYSM) { + Name (_HID, "ACPI0010") + Name (_UID, 0x100000) + Name (_LPI, Package() + { + 0, // Version + 0x1000000, // Level ID + 1, // Count + + // DRIPS State - Xo Shutdown + Cx retention + AOSS Sleep + LLC deactivate + Package () { + 9500, // Min residency (us) + 6000, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0x20, // Arch context last flags + 0x20 For Debugger Transistion by PEP. + 0, // Residency counter frequency + 0, // Enabled parent state + 0xA300, // Integer entry method PSCI E3 + F3 + LLC + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "platform.DRIPS" // Name + } + }) // End of _LPI + + + Device (CLUS) + { + Name (_HID, "ACPI0010") + Name (_UID, 0x10) + Name (_LPI, Package() + { + 0, // Version + 0x1000000, // Level ID + 2, // Count + + // State 0: D2 + Package () + { + 5900, // Min residency (us) + 3000, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + 0x20, // Integer entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "L3Cluster.D2" // Name + }, + // State 1: D4 + Package () + { + 6000, // Min residency (us) + 3300, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Till F1) + 0x40, // Integer entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "L3Cluster.D4" // Name + } + }) // End of _LPI + + + Device (CPU0) // Kyro Silver CPU0 < SYSM.APSS.CPU0 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x0) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C2" // Name + }, + // C3 + Package () + { + 3850, // Min residency (us) + 860, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C3" // Name + }, + // C4 + Package () + { + 3950, // Min residency (us) + 910, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C4" // Name + } + + }) // End of _LPI + } // End of CPU0 + + Device (CPU1) // Kyro Silver CPU1 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x1) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C2" // Name + }, + // C3 + Package () + { + 3850, // Min residency (us) + 860, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C3" // Name + }, + // C4 + Package () + { + 3950, // Min residency (us) + 910, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C4" // Name + } + + }) // End of _LPI + } // End of CPU1 + + Device (CPU2) // Kyro Silver CPU2 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x2) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C2" // Name + }, + // C3 + Package () + { + 3850, // Min residency (us) + 860, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C3" // Name + }, + // C4 + Package () + { + 3950, // Min residency (us) + 910, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C4" // Name + } + + }) // End of _LPI + } // End of CPU2 + + Device (CPU3) // Kyro Silver CPU3 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x3) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C2" // Name + }, + // C3 + Package () + { + 3850, // Min residency (us) + 860, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C3" // Name + }, + // C4 + Package () + { + 3950, // Min residency (us) + 910, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C4" // Name + } + + }) // End of _LPI + } // End of CPU3 + + Device (CPU4) // Kyro Gold CPU0 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x4) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C2" // Name + }, + // C3 + Package () + { + 3990, // Min residency (us) + 1000, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C3" // Name + }, + // C4 + Package () + { + 4490, // Min residency (us) + 1500, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C4" // Name + } + + }) // End of _LPI + } // End of CPU4 + + Device (CPU5) // Kyro Gold CPU1 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x5) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C2" // Name + }, + // C3 + Package () + { + 3990, // Min residency (us) + 1000, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C3" // Name + }, + // C4 + Package () + { + 4490, // Min residency (us) + 1500, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C4" // Name + } + + }) // End of _LPI + } // End of CPU5 + + Device (CPU6) // Kyro Gold CPU2 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x6) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C2" // Name + }, + // C3 + Package () + { + 3990, // Min residency (us) + 1000, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C3" // Name + }, + // C4 + Package () + { + 4490, // Min residency (us) + 1500, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000004 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C4" // Name + } + + }) // End of _LPI + } // End of CPU6 + + Device (CPU7) // Kyro Gold CPU3 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x7) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold3.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold3.C2" // Name + }, + // C3 + Package () + { + 3990, // Min residency (us) + 1000, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold3.C3" // Name + }, + // C4 + Package () + { + 4490, // Min residency (us) + 1500, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000004 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold3.C4" // Name + } + + }) // End of _LPI + } // End of CPU7 + + } // End of CLUS +} // End of SYSM \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/Pptt.aslc b/sdm845Pkg/AcpiTables/src/sc8180x/common/Pptt.aslc new file mode 100644 index 0000000..2f6251c --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/Pptt.aslc @@ -0,0 +1,322 @@ +/** @file + PPTT Table + + This file contains a structure definition for the ACPI 6.x Processor + Properties Topology Table (PPTT). + + Copyright (c) 2018 Mmoclauq Technologies Inc. All rights reserved.
+ +**/ + +#include "Platform.h" +#include "Acpi.h" + +#define ACPI_PROCESSOR_PROPERTIES_DESCRIPTION_TABLE_REVISION 0x00000001 + + +// +// Types defined for Node/Cache/Id Type from Document +// + +#define offsetof(s,m) (UINT32)&(((s *)0)->m) + +#define ACPI_PROCESSOR_NODE 0 +#define ACPI_CACHE_TYPE 1 +#define ACPI_ID_TYPE 2 + +#pragma pack (1) + +typedef struct _ACPI_CACHE_TYPE_STRUCTURE { // 5-152 + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 Flags; + UINT32 NextLevelCache; + UINT32 Size; + UINT32 NumOfSets; + UINT8 Associativity; + UINT8 Attributes; + UINT16 LineSize; +} ACPI_CACHE_TYPE_STRUCTURE; + +typedef struct _ACPI_PROCESSOR_NODE_STRUCTURE { // 5-150 + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 Flags; + UINT32 Parent; // may not be required (container concept) + UINT32 AcpiProcessorId; + UINT32 numPrivateResources; + UINT32 localCacheL1D; + UINT32 LocalCacheL1I; +} ACPI_PROCESSOR_NODE_STRUCTURE; + +typedef struct _ACPI_ID_TYPE_STRUCTURE { // Table 5-154 + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 vendorId; + UINT64 level1Id; + UINT64 level2Id; + UINT16 majorRev; + UINT16 minorRev; + UINT16 spinRev; +} ACPI_ID_TYPE_STRUCTURE; + +typedef struct _ACPI_PROCESSOR_NODE_STRUCTURE_L3 { // dummy node which has L3 as next cache + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 Flags; + UINT32 Parent; // may not be required (container concept) + UINT32 AcpiProcessorId; + UINT32 numPrivateResources; + UINT32 CommonCacheL3; + UINT32 SocId; +} ACPI_PROCESSOR_NODE_STRUCTURE_L3; + +// +// ACPI 5.0 PPTT structure +// +typedef struct { + ACPI_HEADER Header; + ACPI_CACHE_TYPE_STRUCTURE localCacheL3U; + ACPI_ID_TYPE_STRUCTURE SocId; + ACPI_PROCESSOR_NODE_STRUCTURE_L3 NodeForL3; + ACPI_CACHE_TYPE_STRUCTURE localCacheL2U; + ACPI_CACHE_TYPE_STRUCTURE localCacheL1D; + ACPI_CACHE_TYPE_STRUCTURE localCacheL1I; + ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt0; + ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt1; + ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt2; + ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt3; + ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt4; + ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt5; + ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt6; + ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt7; +} ACPI_PROC_TOPOLOGY_TABLE; + +// +// +// PPTT Description Table +// +ACPI_PROC_TOPOLOGY_TABLE Pptt = +{ + // Header + { + ACPI_PPTT_SIGNATURE, //Signature + sizeof (ACPI_PROC_TOPOLOGY_TABLE), //Length + ACPI_PROCESSOR_PROPERTIES_DESCRIPTION_TABLE_REVISION, //Revision + 0, //Checksum + ACPI_OEM_ID, //OEMID + ACPI_OEM_TABLE_ID, //OEMTableID + ACPI_OEM_REVISION, //OEMRevision + ACPI_CREATOR_ID, //CreatorID + ACPI_CREATOR_REVISION //CreatorRevision + }, + + // L3 Cache Details + { + ACPI_CACHE_TYPE, // Type; + sizeof (ACPI_CACHE_TYPE_STRUCTURE), // Length; + 0, // Reserved; + 0, // flags + 0, // NextLevelCache + 0, // Size; + 0, // NumOfSets; + 0, // Associativity + 0, // Attributes + 0, // LineSize; + }, + + // id type structure + { + ACPI_ID_TYPE, // Type + sizeof (ACPI_ID_TYPE_STRUCTURE), // Length; + 0, // Reserved; + 0, // vendorId; + 0, // level1Id; + 0, // level2Id; + 0, // majorRev; + 0, // minorRev; + 0, // spinRev; + }, + + // L3 Node + { + ACPI_PROCESSOR_NODE, // type + sizeof (ACPI_PROCESSOR_NODE_STRUCTURE_L3), // length + 0x00, // Reserved + 0x01, // Flags + 0, // Parent + 0x00, // AcpiProcessorId + 2, // numPrivateResources + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL3U), + offsetof(ACPI_PROC_TOPOLOGY_TABLE, SocId), + }, + + // L2 unified Cache + { + ACPI_CACHE_TYPE, // Type + sizeof (ACPI_CACHE_TYPE_STRUCTURE), // Length + 0x00, // Reserved + 0, // flags + 0, // NextLevelCache + 0, // Size + 0, // NumOfSets + 0, // Associativity + 0, // Attributes + 0, // LineSize + }, + + // L1 Data Cache + { + ACPI_CACHE_TYPE, // Type + sizeof (ACPI_CACHE_TYPE_STRUCTURE), // Length + 0x00, // Reserved + 0, // flags + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL2U), // NextLevelCache + 0, // Size + 0, // NumOfSets + 0, // Associativity + 0, // Attributes + 0, // LineSize + }, + + // L1 Instruction Cache + { + ACPI_CACHE_TYPE, // Type + sizeof (ACPI_CACHE_TYPE_STRUCTURE), // Length + 0x00, // Reserved + 0, // flags + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL2U), // NextLevelCache + 0, // Size + 0, // NumOfSets + 0, // Associativity + 0, // Attributes + 0, // LineSize + }, + + // LocalPpt0 + { + ACPI_PROCESSOR_NODE, // Type + sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length + 0x00, // Reserved + 0x02, // Flags + offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent + 0x00, // AcpiProcessorId + 2, // numPrivateResources + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D), + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I), + }, + + // LocalPpt1 + { + // node structure + ACPI_PROCESSOR_NODE, // Type + sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length + 0x00, // Reserved + 0x02, // Flags + offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent + 0x01, // AcpiProcessorId + 2, // numPrivateResources + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D), + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I), + }, + + // LocalPpt2 + { + // node structure + ACPI_PROCESSOR_NODE, // Type + sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length + 0x00, // Reserved + 0x02, // Flags + offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent + 0x02, // AcpiProcessorId + 2, // numPrivateResources + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D), + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I), + }, + + // LocalPpt3 + { + // node structure + ACPI_PROCESSOR_NODE, // Type + sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length + 0x00, // Reserved + 0x02, // Flags + offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent + 0x03, // AcpiProcessorId + 2, // numPrivateResources + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D), + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I), + }, + + // LocalPpt4 + { + // node structure + ACPI_PROCESSOR_NODE, // Type + sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length + 0x00, // Reserved + 0x02, // Flags + offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent + 0x04, // AcpiProcessorId + 2, // numPrivateResources + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D), + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I), + }, + + // LocalPpt5 + { + // node structure + ACPI_PROCESSOR_NODE, // Type + sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length + 0x00, // Reserved + 0x02, // Flags + offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent + 0x05, // AcpiProcessorId + 2, // numPrivateResources + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D), + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I), + }, + + // LocalPpt6 + { + // node structure + ACPI_PROCESSOR_NODE, // Type + sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length + 0x00, // Reserved + 0x02, // Flags + offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent + 0x06, // AcpiProcessorId + 2, // numPrivateResources + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D), + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I), + }, + + // LocalPpt7 + { + // node structure + ACPI_PROCESSOR_NODE, // Type + sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length + 0x00, // Reserved + 0x02, // Flags + offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent + 0x07, // AcpiProcessorId + 2, // numPrivateResources + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D), + offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I), + }, +}; + +#pragma pack() + +VOID* +ReferenceAcpiTable (VOID) +{ + // + // Reference the table being generated to prevent the optimizer from removing the + // data structure from the exeutable + // + return (VOID*)&Pptt; +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/Qdss.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/Qdss.asl new file mode 100644 index 0000000..bfc4819 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/Qdss.asl @@ -0,0 +1,61 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by qdss driver. +// +// +// Copyright (c) 2010-2018 by Mmoclauq Technologies Inc. All Rights Reserved. +// Mmoclauq Confidential and Proprietary +// +//=========================================================================== + +// +// QDSS device +// +Device (QDSS) +{ + Name (_DEP, Package () { \_SB_.PEP0 }) + + Name (_HID, "HID_QDSS") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method(_STA, 0) + { + return (0xB) + } + + // It is MANDATORY to add any new resources to end of last object in the below _CRS method + // and don't screw up the existing sequence order of defined objects i.e. by adding new object at beginning + // or in b/w defined objects which will lead to driver unload. + // Adding new resource at end has an advantage of backward and forward compatibility. + Method (_CRS, 0x0, NotSerialized) + { + Return + ( + ResourceTemplate () + { + // Software uses QDSSETRIRQCTRL to set a byte count threshold for a counter that counts + // the number of bytes of trace data the ETR has moved on its AXI interface. When the + // threshold is reached an IRQ is fired. + + // reference : http://ipcatalog.qualcomm.com/irqs/chip/188/map/704 + //qdss_etrbytecnt_irq = SYS_apssQgicSPI[270] = 302 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {302} // The ETR byte counter interrupt + + // reference : http://ipcatalog.qualcomm.com/memmap/chip/188/map/693/version/3395/block/2436683 + Memory32Fixed (ReadWrite, 0x06000000, 0x0004B000) // The QDSS_QDSS address space + + // reference : http://ipcatalog.qualcomm.com/memmap/chip/188/map/693/version/3395 + Memory32Fixed (ReadWrite, 0x16000000, 0x1000000) // The QDSS_STM address 0x1000000 = 16777216d (~16MB) + + // Following memory resource is required starting from 8994. In such case, QDSS driver expects + // OFF2 control method which defines register block offsets within this address space. + //reference : http://ipcatalog.qualcomm.com/memmap/chip/188/map/693/version/3395/block/2436463 + Memory32Fixed (ReadWrite, 0x07000000, 0x00901000) // The QDSS_CPU address space. + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {67} // L3 fault interrupt + } + ) + } + +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/TPM2.aslc b/sdm845Pkg/AcpiTables/src/sc8180x/common/TPM2.aslc new file mode 100644 index 0000000..df8e722 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/TPM2.aslc @@ -0,0 +1,47 @@ +/** @file + TPM2 Table + + This file contains a structure definition for the Trusted Platform Module. + + Copyright (c) 2011 - Mmoclauq Technologies Inc. All rights reserved.
+ +**/ + +#include "Platform.h" +#include "Acpi.h" + + +#pragma pack (push, 1) + +typedef struct { + ACPI_HEADER Header; + UINT32 Flags; + UINT64 ControlAreaPA; + UINT32 Start; + UINT64 PlatformParameters[4]; +} ACPI_TPM2_TABLE; + +// +// ACPI TPM2 structure +// +ACPI_TPM2_TABLE TPM2 = +{ + //Header + { + ACPI_TPM2_SIGNATURE, //Signature + sizeof (ACPI_TPM2_TABLE), //Length + ACPI_TPM2_REVISION, //Revision + 0, //Checksum + ACPI_OEM_ID, //OEMID + ACPI_OEM_TABLE_ID, //OEMTableID + ACPI_OEM_REVISION, //OEMRevision + ACPI_CREATOR_ID, //CreatorID + ACPI_CREATOR_REVISION //CreatorRevision + }, + 0, //Flags + 0, //ControlArea + ACPI_TPM2_QCOM_START_METHOD, //Start method + {0, 0, 0, 0} //PlatformParameters[4] +}; + +#pragma pack(pop) diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/abd.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/abd.asl new file mode 100644 index 0000000..2bf0aff --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/abd.asl @@ -0,0 +1,28 @@ +// +// Copyright (c) 2015, Mmoclauq Technologies Inc. All rights reserved. +// +// This file contains ASL Bridge Device definitions +// + +// +// ASL Bridge Device +// +Device (ABD) +{ + Name (_DEP, Package(0x1) + { + \_SB_.PEP0 + }) + Name (_HID, "HID_ABD") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + OperationRegion(ROP1, GenericSerialBus, 0x00000000, 0x100) + Name(AVBL, Zero) + Method(_REG, 0x2, NotSerialized) + { + If(Lequal(Arg0, 0x9)) + { + Store(Arg1, AVBL) + } + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/abp.xsl b/sdm845Pkg/AcpiTables/src/sc8180x/common/abp.xsl new file mode 100644 index 0000000..c4a746c --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/abp.xsl @@ -0,0 +1,77 @@ + + + + + + + + + +Scope(\_SB.PEP0) +{ + +} + + + Method(UIDL) + { + Return(NIDL) + } + + Name(NIDL, + package(){ + "MICROPEP_IDLE", + , + + }) + + + + package(){ + "LPR", + "", // LPR Name + , // LPR Core Mask (0xFFFFFFFF is coordinated) + , //LastMan Adder + + }, + + + + package(){ + "MODE", + "", // Mode name + , // Mode Latency + , // Mode BreakEven + , // Mode Flags + , // Mode Clock Flags + , // Mode PSCI Flags + + }, + + + + + + + + + + + + package(){ + "DEPENDENCY_CONTAINER", + + }, + + + + package(){ + "DEPENDENCY", + "", // Dependency LPR + "", // Dependency Mode + , // Dependency Type + }, + + + + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/adsprpc.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/adsprpc.asl new file mode 100644 index 0000000..8442bdc --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/adsprpc.asl @@ -0,0 +1,30 @@ +// +// Copyright (c) 2015, Mmoclauq Technologies, Inc. All rights reserved. +// + +// +// ADSP RPC Driver +// +Device (ARPC) +{ + Name (_DEP, Package(0x3) + { + \_SB_.MMU0, + \_SB_.GLNK, + \_SB_.SCM0 + }) + Name (_HID, "HID_fastRPC_driver_to_make_RPC_from_apps_to_ADSP") + Alias(\_SB.PSUB, _SUB) +} +// ARPD AUDIO Daemon Driver +Device (ARPD) +{ + Name (_DEP, Package(0x2) + { + \_SB_.ADSP, + \_SB_.ARPC + }) + Name (_HID, "HID_ARPD") + Alias(\_SB.PSUB, _SUB) +} + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/att_signed_devices.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/att_signed_devices.asl new file mode 100644 index 0000000..7f2d934 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/att_signed_devices.asl @@ -0,0 +1,18 @@ +//-------------------------------------------------------------------------------------------------- +// Copyright (c) 2019 Mmoclauq Technologies, Inc. +// All Rights Reserved. +// Confidential and Proprietary - Mmoclauq Technologies, Inc. +//-------------------------------------------------------------------------------------------------- + + +Include("Qdss.asl") +Include("qcsp.asl") +Include("qcdb.asl") +Include("data_att.asl") +Include("win_mproc_att.asl") +Include("cust_hwn_att.asl") + + + + + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/backlightcfg.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/backlightcfg.asl new file mode 100644 index 0000000..ad16652 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/backlightcfg.asl @@ -0,0 +1,72 @@ +/// +// BLCP Method +// Backlight control packet method, returns a +// command buffer for a specific backlight level +// +// Input Parameters +// Backlight level - Integer from 0 to 0xFFFF where 0xFFFF is the highest level - must be converted to the required range (e.g. 0 - 255) in the method +// Brightness level - absolute brightness in millinits +// +// Output Parameters +// +// Packet format: +// +--32bits--+-----variable (8bit alignment)--+ +// | Header | Packet payload | +// +----------+--------------------------------+ +// +// For DSI Command packets, payload data must be in this format +// +// +-- 8 bits-+----variable (8bit alignment)----+ +// | Cmd Type | Packet Data | +// +----------+---------------------------------+ +// +// For I2C Command packets, payload data must be in this format +// +// +-- 16 bits-+----variable (8bit alignment)----+ +// | Address | Command Data | +// +-----------+---------------------------------+ +// +// All packets must follow with a DWORD header with 0x0 +// +Method (BLCP, 2, NotSerialized) { + + // Create Response buffer + Name(RBUF, Buffer(0x100){}) + + // Details to be populated by OEM based on the platform requirements + + // Return the packet data + Return(RBUF) +} + + +/// +// BLCP Method (legacy method for 100 levels) +// Backlight control packet method, returns a +// command buffer for a specific backlight level +// +// Input Parameters +// Backlight level - Integer from 0% to 100% +// +// Output Parameters +// +// Packet format: +// +--32bits--+-----variable (8bit alignment)--+ +// | Header | Packet payload | +// +----------+--------------------------------+ +// +// For DSI Command packets, payload data must be in this format +// +// +-- 8 bits-+----variable (8bit alignment)----+ +// | Cmd Type | Packet Data | +// +----------+---------------------------------+ +// +// For I2C Command packets, payload data must be in this format +// +// +-- 16 bits-+----variable (8bit alignment)----+ +// | Address | Command Data | +// +-----------+---------------------------------+ +// +// All packets must follow with a DWORD header with 0x0 +// + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/bam.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/bam.asl new file mode 100644 index 0000000..0d97950 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/bam.asl @@ -0,0 +1,165 @@ +// +// Copyright (c) 2013-2017, Mmoclauq Technologies Inc. All rights reserved. +// +// This file contains the Bus Access Modules (BAM) +// ACPI device definitions and pipe configurations +// + +// +// Device Map: +// 0x2401 - BAM +// +// List of Devices +// BAM1 - CRYPTO1 +// BAM5 - SLIMBUS1 +// BAM6 - SLIMBUS +// BAM7 - TSIF +// BAMD - USB3.0 secondary +// BAME - QDSS +// BAMF - USB3.0 primary +// BAMG - USB3.0 MP +Device (BAM1) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // CRYPTO0 register address space + Memory32Fixed (ReadWrite, 0x1DC4000, 0x00024000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {304} + }) + Return (RBUF) + } +} + +Device (BAM5) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 5) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // AUD_SLIMBUS register address space + Memory32Fixed (ReadWrite, 0x17184000, 0x00032000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {196} + }) + Return (RBUF) + } +} + + +Device (BAM6) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 6) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // QCA_SLIMBUS register address space + Memory32Fixed (ReadWrite, 0x17204000, 0x00026000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {324} + }) + Return (RBUF) + } +} + +Device (BAM7) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 7) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // TSIF register address space + Memory32Fixed (ReadWrite, 0x08884000, 0x00023000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {154} + }) + Return (RBUF) + } +} + +Device (BAMD) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 13) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // USB30 sec register address space + Memory32Fixed (ReadWrite, 0xA904000, 0x00017000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {169} + }) + Return (RBUF) + } +} + +Device (BAME) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 14) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // QDSS register address space + Memory32Fixed (ReadWrite, 0x6064000, 0x00015000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {199} + }) + Return (RBUF) + } +} + +Device (BAMF) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 15) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // USB30 PRI register address space + Memory32Fixed (ReadWrite, 0x0A704000, 0x00017000) + + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {164} + }) + Return (RBUF) + } +} + +Device (BAMG) +{ + Name (_HID, "HID_BAM0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 16) + Name (_CCA, 0) + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // USB30 MP register address space + Memory32Fixed (ReadWrite, 0x0A504000, 0x00017000) + + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {691} + }) + Return (RBUF) + } +} + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/bgrt.aslc b/sdm845Pkg/AcpiTables/src/sc8180x/common/bgrt.aslc new file mode 100644 index 0000000..3a30915 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/bgrt.aslc @@ -0,0 +1,49 @@ +/** @file + BGRT Table + + This file contains BGRT Table Definition. + + Copyright (c) 2011, 2013 - Mmoclauq Technologies Inc. All rights reserved. + +**/ + +#include "Platform.h" +#include "Acpi.h" + +/* IMAGE ADDRESS - UINT64, according to uefiplatWP.cfg */ +#define BGRT_IMAGE_ADDRESS 0 + +/* IMAGE OFFSET X - UINT32 */ +/* Sample logo is 176x182, centering (38.2% from the top) the image into 720x1280, same for CDP/MTP/QRD */ +#define BGRT_IMAGE_OFFSET_X 0x00000110 /* (720*0.5 - 176*0.5) = 272 = 0x110 */ + +/* IMAGE OFFSET Y - UINT32 */ +#define BGRT_IMAGE_OFFSET_Y 0x0000018E /* (1280*0.382 - 182*0.5) = 398 = 0x18E */ + +#pragma pack(1) + +/* ACPI 5.0 BGRT Table */ +BGRT_TABLE BGRT = +{ + /* ACPI BGRT Header */ + { + ACPI_BGRT_SIGNATURE, //Signature + sizeof (BGRT_TABLE), //Length + ACPI_BGRT_REVISION, //Revision + 0, //Checksum + ACPI_OEM_ID, //OEMID + ACPI_OEM_TABLE_ID, //OEMTableID + ACPI_OEM_REVISION, //OEMRevision + ACPI_CREATOR_ID, //CreatorID + ACPI_CREATOR_REVISION //CreatorRevision + }, + 0x0001, //Version + BGRT_IMAGE_INVALID, //Validity of Image, bit 0 = 0 (Invalid image WP Default) + BGRT_BITMAP_IMAGE, //Image Type is Bit-Map i.e 0x00 + BGRT_IMAGE_ADDRESS, + BGRT_IMAGE_OFFSET_X, + BGRT_IMAGE_OFFSET_Y +}; +#pragma pack() + + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/buses.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/buses.asl new file mode 100644 index 0000000..24f07a7 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/buses.asl @@ -0,0 +1,696 @@ +// +// Copyright (c) 2017 - 2019 Mmoclauq Technologies, Inc. All rights reserved. +// + +// +// +// Please note that not all the SE engine instances (I2C/SPI/UART) from below asl file can be used directly by icluding in the client ACPI, +// The corresponding Access Control needs to be enabled from TZ side to get the SE/usecase working End 2 End. +// +// + +// +// QUPV3_ID1_SE5 (UART Debug port) +// +Device (UARD) +{ + Name (_HID, "HID_UART") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 13) + Name (_DEP, Package() { \_SB_.PEP0 }) + Name (_CCA, 0) + + Method (_CRS) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0x00a90000, 0x0004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {389} + GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {86} // UART RX, + }) + Return (RBUF) + } +} + +// +// QUPV3_ID1_SE6 (Housekeeping UART (GPIOs 83, 84)) +// +Device (UR14) +{ + Name (_HID, "HID_UART") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 14) + Name (_DEP, Package() { \_SB_.PEP0 }) + Name (_CCA, 0) + + Method (_CRS) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0x00a94000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {390} + GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {83} // UART RX + }) + Return (RBUF) + } +} + +// +// QUPV3_ID2_SE4 (attached to BT SOC) +// +Device (UR18) +{ + Name (_HID, "HID_UART") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 18) + Name (_DEP, Package() { \_SB_.PEP0 }) + Name (_CCA, 0) + + Method (_CRS) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0x00c8c000, 0x0004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {617} + GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {46} // UART RX, + }) + Return (RBUF) + } + + Method (_STA) + { + Return (0x0B) + } +} + +// +// QUPV3_ID2_SE6 (HS UART - 5G (GPIO 29, 30)(only for OEM Superset Platform)) +// +Device (UR20) +{ + Name (_HID, "HID_UART") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 20) + Name (_DEP, Package() { \_SB_.PEP0 }) + Name (_CCA, 0) + + Method (_CRS) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0x00c94000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {619} + GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {30} // UART RX + }) + Return (RBUF) + } +} + +// +// I2C5 - "Core I2C Bus" +// +Device (I2C5) +{ + Name (_HID, "HID_I2C") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 5) + Name (_DEP, Package() { \_SB_.PEP0 }) +// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00890000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {637} + }) + Return (RBUF) + } +} + +// +// I2C8 - "OEM Dock I/O" +// +Device (I2C8) +{ + Name (_HID, "HID_I2C") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 8) + Name (_DEP, Package() { \_SB_.PEP0 }) +// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0089c000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {640} + }) + Return (RBUF) + } +} + +// +// I2C10 - "NFC Sensor" +// +Device (IC10) +{ + Name (_HID, "HID_I2C") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 10) + Name (_DEP, Package() { \_SB_.PEP0 }) +// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0}) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00a84000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {386} + }) + Return (RBUF) + } +} + + +//SPI4 - (CODEC-WCD936x / WCD9340 SPI) + +Device (SPI4) +{ + Name (_HID, "HID_SPI") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 4) + Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0,\_SB_.MMU0}) + Name (_CCA, 0) + + Method (_CRS) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0x0088c000, 0x00004000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {636} + }) + Return (RBUF) + } +} + +// +// PEP resources for buses +// +Scope(\_SB_.PEP0) +{ + Method(BSMD) + { + Return(BSRC) + } + + Name(BSRC, Package() + { + // "\\_SB.UARD" + Package() + { + "DEVICE", + 0x2, //Debug device + "\\_SB.UARD", + + Package() + { + "COMPONENT", 0, // UART resources + + Package() + { + "FSTATE", 0, // enable UART clocks + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_1", "ICBID_SLAVE_EBI1", 153600000, 1666}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_1", 148000000, 50000000}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 1}}, + }, + + Package() + { + "FSTATE", 1, // disable UART clocks + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 2}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_1", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_1", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + + Package() + { + "PSTATE", 0, // enable GPIOs + Package(){"TLMMGPIO", Package(){ 85, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 86, 0, 1, 0, 0, 0 }}, + }, + + Package() + { + "PSTATE", 1, // disable GPIOs + Package(){"TLMMGPIO", Package(){ 85, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 86, 0, 1, 0, 0, 0 }}, + }, + + Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3, 7372800, 4}}}, + Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3, 14745600, 4}}}, + Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3, 29491200, 4}}}, + Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3, 32000000, 4}}}, + Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3, 48000000, 4}}}, + Package(){"PSTATE", 7, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3, 64000000, 4}}}, + Package(){"PSTATE", 8, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3, 80000000, 4}}}, + Package(){"PSTATE", 9, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3, 96000000, 4}}}, + Package(){"PSTATE", 10, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3,102400000, 4}}}, + Package(){"PSTATE", 11, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3,112000000, 4}}}, + Package(){"PSTATE", 12, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3,117964800, 4}}}, + Package(){"PSTATE", 13, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s4_clk", 3,128000000, 4}}}, + }, + + Package() + { + "COMPONENT", 1, // DMA resources + Package(){"FSTATE", 0}, // enable DMA clocks + Package(){"FSTATE", 1}, // disable DMA clocks + }, + }, + + // "\\_SB.UR14" + Package() + { + "DEVICE", "\\_SB.UR14", + + Package() + { + "COMPONENT", 0, // UART resources + + Package() + { + "FSTATE", 0, // enable UART clocks + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_1", "ICBID_SLAVE_EBI1", 153600000, 1666}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_1", 148000000, 50000000}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk",3, 7372800, 4}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 1}}, + }, + + Package() + { + "FSTATE", 1, // disable UART clocks + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 2}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_1", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_1", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + + Package() + { + "PSTATE", 0, // enable GPIOs + Package(){"TLMMGPIO", Package(){ 83, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 84, 0, 1, 0, 0, 0 }}, + }, + + Package() + { + "PSTATE", 1, // disable GPIOs + Package(){"TLMMGPIO", Package(){ 83, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 84, 0, 1, 0, 0, 0 }}, + }, + + Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3, 7372800, 4}}}, + Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3, 14745600, 4}}}, + Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3, 29491200, 4}}}, + Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3, 32000000, 4}}}, + Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3, 48000000, 4}}}, + Package(){"PSTATE", 7, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3, 64000000, 4}}}, + Package(){"PSTATE", 8, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3, 80000000, 4}}}, + Package(){"PSTATE", 9, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3, 96000000, 4}}}, + Package(){"PSTATE", 10, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3,102400000, 4}}}, + Package(){"PSTATE", 11, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3,112000000, 4}}}, + Package(){"PSTATE", 12, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3,117964800, 4}}}, + Package(){"PSTATE", 13, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s5_clk", 3,128000000, 4}}}, + }, + + Package() + { + "COMPONENT", 1, // DMA resources + Package(){"FSTATE", 0}, // enable DMA clocks + Package(){"FSTATE", 1}, // disable DMA clocks + }, + }, + + // "\\_SB.UR18" + Package() + { + "DEVICE", "\\_SB.UR18", + + Package() + { + "COMPONENT", 0, // UART resources + + Package() + { + "FSTATE", 0, // enable UART clocks + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_2", "ICBID_SLAVE_EBI1", 153600000, 1666}}, + Package(){"BUSARB", Package(){3,"ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_2", 148000000, 50000000}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_2_m_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_2_s_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 1}}, + }, + + Package() + { + "FSTATE", 1, // disable UART clocks + Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_2_s_ahb_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_2_m_ahb_clk", 2}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_2", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_2", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + + Package() + { + "PSTATE", 0, // enable GPIOs + Package(){"TLMMGPIO", Package(){ 43, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 44, 0, 1, 0, 0, 0 }}, + Package(){"TLMMGPIO", Package(){ 45, 0, 1, 0, 0, 0 }}, + Package(){"TLMMGPIO", Package(){ 46, 0, 1, 0, 1, 0 }}, + }, + + Package() + { + "PSTATE", 1, // disable GPIOs + Package(){"TLMMGPIO", Package(){ 43, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 44, 0, 1, 0, 0, 0 }}, + Package(){"TLMMGPIO", Package(){ 45, 0, 1, 0, 0, 0 }}, + Package(){"TLMMGPIO", Package(){ 46, 0, 1, 0, 1, 0 }}, + }, + + Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3, 7372800, 4}}}, + Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3, 14745600, 4}}}, + Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3, 29491200, 4}}}, + Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3, 32000000, 4}}}, + Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3, 48000000, 4}}}, + Package(){"PSTATE", 7, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3, 64000000, 4}}}, + Package(){"PSTATE", 8, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3, 80000000, 4}}}, + Package(){"PSTATE", 9, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3, 96000000, 4}}}, + Package(){"PSTATE", 10, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3,102400000, 4}}}, + Package(){"PSTATE", 11, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3,112000000, 4}}}, + Package(){"PSTATE", 12, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3,117964800, 4}}}, + Package(){"PSTATE", 13, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s3_clk", 3,128000000, 4}}}, + }, + + Package() + { + "COMPONENT", 1, // DMA resources + Package(){"FSTATE", 0}, // enable DMA clocks + Package(){"FSTATE", 1}, // disable DMA clocks + }, + }, + + // "\\_SB.UR20" + Package() + { + "DEVICE", "\\_SB.UR20", + + Package() + { + "COMPONENT", 0, // UART resources + + Package() + { + "FSTATE", 0, // enable UART clocks + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_2", "ICBID_SLAVE_EBI1", 153600000, 1666}}, + Package(){"BUSARB", Package(){3,"ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_2", 148000000, 50000000}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_2_m_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_2_s_ahb_clk", 1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk",3, 7372800, 4}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 1}}, + }, + + Package() + { + "FSTATE", 1, // disable UART clocks + Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_2_s_ahb_clk", 2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_2_m_ahb_clk", 2}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_2", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_2", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + + Package() + { + "PSTATE", 0, // enable GPIOs + Package(){"TLMMGPIO", Package(){ 29, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 30, 0, 1, 0, 0, 0 }}, + }, + + Package() + { + "PSTATE", 1, // disable GPIOs + Package(){"TLMMGPIO", Package(){ 29, 0, 1, 0, 1, 0 }}, + Package(){"TLMMGPIO", Package(){ 30, 0, 1, 0, 0, 0 }}, + }, + + Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3, 7372800, 4}}}, + Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3, 14745600, 4}}}, + Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3, 29491200, 4}}}, + Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3, 32000000, 4}}}, + Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3, 48000000, 4}}}, + Package(){"PSTATE", 7, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3, 64000000, 4}}}, + Package(){"PSTATE", 8, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3, 80000000, 4}}}, + Package(){"PSTATE", 9, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3, 96000000, 4}}}, + Package(){"PSTATE", 10, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3,102400000, 4}}}, + Package(){"PSTATE", 11, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3,112000000, 4}}}, + Package(){"PSTATE", 12, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3,117964800, 4}}}, + Package(){"PSTATE", 13, Package(){"CLOCK", Package(){"gcc_qupv3_wrap2_s5_clk", 3,128000000, 4}}}, + }, + + Package() + { + "COMPONENT", 1, // DMA resources + Package(){"FSTATE", 0}, // enable DMA clocks + Package(){"FSTATE", 1}, // disable DMA clocks + }, + }, + + // "\\_SB.I2C5" + Package() + { + "DEVICE", + "\\_SB.I2C5", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + Package(){"BUSARB", Package(){3,"ICBID_MASTER_QUP_0", "ICBID_SLAVE_EBI1", 153600000, 1666}}, + Package(){"BUSARB", Package(){3,"ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_0", 148000000, 50000000}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s4_clk",8,19200000, 4}}, + + // Configure SDA and then SCL + package() {"TLMMGPIO", package() {51, 1, 1, 1, 3, 0}}, + package() {"TLMMGPIO", package() {52, 1, 1, 1, 3, 0}}, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s4_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",2}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_0", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_0", "ICBID_SLAVE_EBI1", 0, 0 }}, + + // Configure SCL and then SDA + package() { "TLMMGPIO", package() {51, 0, 0, 0, 3, 0}}, + package() { "TLMMGPIO", package() {52, 0, 0, 0, 3, 0}}, + }, + }, + + Package() + { + "DEVICE", "\\_SB.SPI4", + + Package() + { + "COMPONENT", 0, + + Package() {"FSTATE", 0}, + + Package(){"DISCOVERABLE_PSTATE", "CLOCK", "gcc_qupv3_wrap0_s3_clk"}, + }, + + Package() + { + "DSTATE", 0, // enable clocks, enable GPIOs + + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_0", "ICBID_SLAVE_EBI1", 153600000, 1666}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_0", 148000000, 50000000}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s3_clk",1}}, + + Package(){"TLMMGPIO", Package(){ 144, 1, 2, 0, 1, 0}}, // MISO + Package(){"TLMMGPIO", Package(){ 145, 1, 2, 1, 1, 0}}, // MOSI + Package(){"TLMMGPIO", Package(){ 146, 1, 2, 1, 1, 0}}, // CLK + Package(){"TLMMGPIO", Package(){ 147, 1, 2, 1, 1, 0}}, // CS + }, + + Package() {"DSTATE", 1,}, + Package() {"DSTATE", 2,}, + + Package() + { + "DSTATE", 3, // disable clocks, disable GPIOs + + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s3_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",2}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_0", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_0", "ICBID_SLAVE_EBI1", 0, 0}}, + + Package(){"TLMMGPIO", Package(){ 144, 0, 2, 0, 1, 0}}, // MOSI + Package(){"TLMMGPIO", Package(){ 145, 0, 2, 0, 1, 0}}, // MISO + Package(){"TLMMGPIO", Package(){ 146, 0, 2, 0, 1, 0}}, // CS + Package(){"TLMMGPIO", Package(){ 147, 0, 2, 0, 1, 0}}, // CLK + }, + }, + + // "\\_SB.I2C8" + Package() + { + "DEVICE", + "\\_SB.I2C8", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_0", "ICBID_SLAVE_EBI1", 153600000, 1666}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_0", 148000000, 50000000}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s7_clk",8,19200000, 4}}, + + // Configure SDA and then SCL + package() {"TLMMGPIO", package() {98, 1, 1, 1, 3, 0}}, + package() {"TLMMGPIO", package() {99, 1, 1, 1, 3, 0}}, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s7_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",2}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_0", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_0", "ICBID_SLAVE_EBI1", 0, 0 }}, + + // Configure SCL and then SDA + package() { "TLMMGPIO", package() {98, 0, 0, 0, 3, 0}}, + package() { "TLMMGPIO", package() {99, 0, 0, 0, 3, 0}}, + }, + }, + + // "\\_SB.IC10" + Package() + { + "DEVICE", + "\\_SB.IC10", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + + }, + Package() + { + "DSTATE", + 0x0, // D0 state + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_1", "ICBID_SLAVE_EBI1", 153600000, 1666}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_1", 148000000, 50000000}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk",8,19200000, 4}}, + + // Configure SDA and then SCL + package() {"TLMMGPIO", package() {39, 1, 1, 1, 3, 0}}, + package() {"TLMMGPIO", package() {40, 1, 1, 1, 3, 0}}, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}}, + Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_QUP_1", 0, 0}}, + Package(){"BUSARB", Package(){3, "ICBID_MASTER_QUP_1", "ICBID_SLAVE_EBI1", 0, 0 }}, + + // Configure SCL and then SDA + package() { "TLMMGPIO", package() {39, 0, 0, 0, 3, 0}}, + package() { "TLMMGPIO", package() {40, 0, 0, 0, 3, 0}}, + }, + }, + }) +} + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/cbsp_mproc.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/cbsp_mproc.asl new file mode 100644 index 0000000..d2e48eb --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/cbsp_mproc.asl @@ -0,0 +1,71 @@ +// +// Copyright (c) 2017, Mmoclauq Technologies, Inc. All rights reserved. +// + +// +// Core-BSP MPROC Drivers (IPC Router & GLINK) +// + +// +// IPC Router +// +Device (IPC0) +{ + Name (_DEP, Package(0x1) + { + \_SB_.GLNK + }) + Name (_HID, "HID_IPC0") + Alias(\_SB.PSUB, _SUB) +} + +// +// GLINK +// +// Order of incoming and outgoing interrupts depend on the number of interrupts mentioned in INTR method +Device (GLNK) +{ + Name (_DEP, Package(0x1) + { + \_SB_.RPEN + }) + Name (_HID, "HID_GLNK") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + + // Inbound SMP2P interrupt from Modem (SYS_apssQgicSPI(451)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {483} + + // Inbound SMP2P interrupt from ADSP (SYS_apssQgicSPI[158]): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {190} + + // Inbound SMP2P interrupt from SSC (SYS_apssQgicSPI(172)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {204} + + // Inbound SMP2P interrupt from CDSP (SYS_apssQgicSPI(576)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {608} + + // Inbound SMEM XPORT interrupt from Modem (SYS_apssQgicSPI(449)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {481} + + // Inbound SMEM XPORT interrupt from ADSP (SYS_apssQgicSPI[156]): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {188} + + // Inbound SMEM XPORT interrupt from SSC (SYS_apssQgicSPI(170)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {202} + + // Inbound SMEM XPORT interrupt from CDSP (SYS_apssQgicSPI(574)): + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {606} + + // Inbound SMEM XPORT interrupt from SPSS (SYS_apssQgicSPI(348)): + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {380} + + }) + Return (RBUF) + } + +} diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/corebsp_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/corebsp_resources.asl new file mode 100644 index 0000000..b76518b --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/corebsp_resources.asl @@ -0,0 +1,7965 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by core BSP drivers. +// +// +// Copyright (c) 2010-2019 by Mmoclauq Technologies Inc. All Rights Reserved. +// Mmoclauq Confidential and Proprietary +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + + Method(BPMD) + { + if(LEqual(STOR, 1)) { + if(LEqual(PUS3, 1)) { + Return (CPCC) // booting from UFS 3.0 or later + } + else { + Return (BPCC) // booting from UFS 2.1 or earlier + } + } + else { + Return (FPCC) // disabling select primary UFS resources for NVMe boot + } + } + + Method(SUMD) + { + if(LEqual(STOR, 1)) { + if(LEqual(SUS3, 1)) { + Return (EPCC) // secondary UFS 3.0 or later + } + else { + Return (DPCC) // secondary UFS 2.1 or earlier + } + } + else { + Return (GPCC) // disabling select secondary UFS resources for NVMe boot + } + } + + Method(SDMD) + { + Return (SDCC) + } + + Name(BPCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.UFS0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + Package() { "PSTATE_ADJUST", Package() { 0, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 0 } }, + }, + Package() + { + "FSTATE", + 0x1, // f1 state + Package() { "PSTATE_ADJUST", Package() { 2, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 0, 1 } }, + }, + + Package() + { + "PSTATE_SET", + 0x0, + + Package() + { + "PSTATE", + 0x0, + Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 1 }}, + }, + Package() + { + "PSTATE", + 0x1, + Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 2 }}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x1, + + Package() + { + "PSTATE", + 0x0, + + Package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 8, 300000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 8, 300000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 8, 300000000, 2}}, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 1,}}, + }, + Package() + { + "PSTATE", + 0x1, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 2,}}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x2, + + Package() + { + "PSTATE", + 0x0, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 1200000000, 1200000000}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 299000000, 0}}, + }, + Package() + { + "PSTATE", + 0x1, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 0, 0}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + + Package() {"PSTATE_ADJUST", Package() { 2, 0 } }, + + Package() {"PSTATE_ADJUST", Package() { 0, 0 } }, + + // Vcc supply = L9 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO9_C", // VREG ID + 1, // Voltage Regulator type = LDO + 2904000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq supply = L2 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO2_C", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq2 supply = L15 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO15_E", // VREG ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage is in micro volts + 1, // Force enable from software + 7, // Power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // PHY VDDA supply: L3 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO3_C", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // VDDA_UFS_CORE supply: L5 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"DELAY", package() { 35 }}, + + Package() {"PSTATE_ADJUST", Package() { 1, 0 } }, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() {"PSTATE_ADJUST", Package() { 1, 1 } }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO3_C", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO15_E", // VREG ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage is in micro volts + 1, // Force enable from software + 4, // Power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO2_C", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO9_C", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"PSTATE_ADJUST", Package() { 0, 1 } }, + Package() {"PSTATE_ADJUST", Package() { 2, 1 } }, + }, + + Package() + { + "CRASHDUMP_DSTATE", + 0, + }, + }, + }) + + Name(CPCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.UFS0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + Package() { "PSTATE_ADJUST", Package() { 0, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 0 } }, + }, + Package() + { + "FSTATE", + 0x1, // f1 state + Package() { "PSTATE_ADJUST", Package() { 2, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 0, 1 } }, + }, + + Package() + { + "PSTATE_SET", + 0x0, + + Package() + { + "PSTATE", + 0x0, + Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 1 }}, + }, + Package() + { + "PSTATE", + 0x1, + Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 2 }}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x1, + + Package() + { + "PSTATE", + 0x0, + + Package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 8, 300000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 8, 300000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 8, 300000000, 2}}, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 1,}}, + }, + Package() + { + "PSTATE", + 0x1, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 2,}}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x2, + + Package() + { + "PSTATE", + 0x0, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 2400000000, 2400000000}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 299000000, 0}}, + }, + Package() + { + "PSTATE", + 0x1, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 0, 0}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + + Package() {"PSTATE_ADJUST", Package() { 2, 0 } }, + + Package() {"PSTATE_ADJUST", Package() { 0, 0 } }, + + // Vcc supply = L9 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO9_C", // VREG ID + 1, // Voltage Regulator type = LDO + 2504000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq supply = L2 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO2_C", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq2 supply = L15 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO15_E", // VREG ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage is in micro volts + 1, // Force enable from software + 7, // Power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // PHY VDDA supply: L3 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO3_C", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // VDDA_UFS_CORE supply: L5 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"DELAY", package() { 35 }}, + + Package() {"PSTATE_ADJUST", Package() { 1, 0 } }, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() {"PSTATE_ADJUST", Package() { 1, 1 } }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO3_C", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO15_E", // VREG ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage is in micro volts + 1, // Force enable from software + 4, // Power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO2_C", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO9_C", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"PSTATE_ADJUST", Package() { 0, 1 } }, + Package() {"PSTATE_ADJUST", Package() { 2, 1 } }, + }, + + Package() + { + "CRASHDUMP_DSTATE", + 0, + }, + }, + }) + + Name(DPCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.UFS1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + Package() { "PSTATE_ADJUST", Package() { 0, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 0 } }, + }, + Package() + { + "FSTATE", + 0x1, // f1 state + Package() { "PSTATE_ADJUST", Package() { 2, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 0, 1 } }, + }, + + Package() + { + "PSTATE_SET", + 0x0, + + Package() + { + "PSTATE", + 0x0, + Package() { "FOOTSWITCH", Package() { "ufs_card_2_gdsc", 1 }}, + }, + Package() + { + "PSTATE", + 0x1, + Package() { "FOOTSWITCH", Package() { "ufs_card_2_gdsc", 2 }}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x1, + + Package() + { + "PSTATE", + 0x0, + + Package() {"CLOCK", package() {"gcc_ufs_card_2_axi_clk", 8, 300000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_card_2_unipro_core_clk", 8, 300000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_card_2_ice_core_clk", 8, 300000000, 2}}, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_card_2_axi_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_ahb_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_phy_aux_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_tx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_rx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_rx_symbol_1_clk", 1,}}, + }, + Package() + { + "PSTATE", + 0x1, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_card_2_axi_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_ahb_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_phy_aux_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_tx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_rx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_rx_symbol_1_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_card_2_ice_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_card_2_unipro_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_card_2_axi_clk", 2,}}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x2, + + Package() + { + "PSTATE", + 0x0, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_GEN4", "ICBID_SLAVE_EBI1", 1200000000, 1200000000}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_1_CFG", 299000000, 0}}, + }, + Package() + { + "PSTATE", + 0x1, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_1_CFG", 0, 0}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_GEN4", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + + Package() {"PSTATE_ADJUST", Package() { 2, 0 } }, + + Package() {"PSTATE_ADJUST", Package() { 0, 0 } }, + + // Vcc supply = L10 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO10_E", // VREG ID + 1, // Voltage Regulator type = LDO + 2904000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq supply = L6 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO6_A", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq2 supply = L7 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO7_E", // VREG ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage is in micro volts + 1, // Force enable from software + 7, // Power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // PHY VDDA supply: L3 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO3_C", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // VDDA_UFS_CORE supply: L5 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"DELAY", package() { 35 }}, + + Package() {"PSTATE_ADJUST", Package() { 1, 0 } }, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() {"PSTATE_ADJUST", Package() { 1, 1 } }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO3_C", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO7_E", // VREG ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage is in micro volts + 1, // Force enable from software + 4, // Power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO6_A", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO10_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"PSTATE_ADJUST", Package() { 0, 1 } }, + Package() {"PSTATE_ADJUST", Package() { 2, 1 } }, + }, + }, + }) + + Name(EPCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.UFS1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + Package() { "PSTATE_ADJUST", Package() { 0, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 0 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 0 } }, + }, + Package() + { + "FSTATE", + 0x1, // f1 state + Package() { "PSTATE_ADJUST", Package() { 2, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 1, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 0, 1 } }, + }, + + Package() + { + "PSTATE_SET", + 0x0, + + Package() + { + "PSTATE", + 0x0, + Package() { "FOOTSWITCH", Package() { "ufs_card_2_gdsc", 1 }}, + }, + Package() + { + "PSTATE", + 0x1, + Package() { "FOOTSWITCH", Package() { "ufs_card_2_gdsc", 2 }}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x1, + + Package() + { + "PSTATE", + 0x0, + + Package() {"CLOCK", package() {"gcc_ufs_card_2_axi_clk", 8, 300000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_card_2_unipro_core_clk", 8, 300000000, 2}}, + package() {"CLOCK", package() {"gcc_ufs_card_2_ice_core_clk", 8, 300000000, 2}}, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_card_2_axi_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_ahb_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_phy_aux_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_tx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_rx_symbol_0_clk", 1,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_rx_symbol_1_clk", 1,}}, + }, + Package() + { + "PSTATE", + 0x1, + + Package() {"CLOCK", Package() {"gcc_aggre_ufs_card_2_axi_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_ahb_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_phy_aux_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_tx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_rx_symbol_0_clk", 2,}}, + Package() {"CLOCK", Package() {"gcc_ufs_card_2_rx_symbol_1_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_card_2_ice_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_card_2_unipro_core_clk", 2,}}, + package() {"CLOCK", package() {"gcc_ufs_card_2_axi_clk", 2,}}, + }, + }, + + Package() + { + "PSTATE_SET", + 0x2, + + Package() + { + "PSTATE", + 0x0, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_GEN4", "ICBID_SLAVE_EBI1", 2400000000, 2400000000}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_1_CFG", 299000000, 0}}, + }, + Package() + { + "PSTATE", + 0x1, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_1_CFG", 0, 0}}, + Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_GEN4", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + + Package() {"PSTATE_ADJUST", Package() { 2, 0 } }, + + Package() {"PSTATE_ADJUST", Package() { 0, 0 } }, + + // Vcc supply = L10 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO10_E", // VREG ID + 1, // Voltage Regulator type = LDO + 2504000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq supply = L6 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO6_A", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Vccq2 supply = L7 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO7_E", // VREG ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage is in micro volts + 1, // Force enable from software + 7, // Power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // PHY VDDA supply: L3 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO3_C", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // VDDA_UFS_CORE supply: L5 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"DELAY", package() { 35 }}, + + Package() {"PSTATE_ADJUST", Package() { 1, 0 } }, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() {"PSTATE_ADJUST", Package() { 1, 1 } }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO3_C", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO7_E", // VREG ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage is in micro volts + 1, // Force enable from software + 4, // Power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO6_A", // VREG ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO10_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + Package() {"PSTATE_ADJUST", Package() { 0, 1 } }, + Package() {"PSTATE_ADJUST", Package() { 2, 1 } }, + }, + }, + }) + + Name(FPCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.UFS0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "PRELOAD_DSTATE", + 3, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + + // Vccq2 supply = L15 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO15_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + // Vccq supply = L2 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO2_C", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + // Vcc supply = L9 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO9_C", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + }, + }, + }) + + Name(GPCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.UFS1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "PRELOAD_DSTATE", + 3, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + // Vccq2 supply = L7 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO7_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + // Vccq supply = L6 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO6_A", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + + // Vcc supply = L10 + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO10_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + }, + }, + }) + + Name(SDCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.SDC2", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + + Package() + { + "PSTATE_SET", + 0x0, + + // + // Contract with SDBUS for card frequencies + // + // P-State Note + // -------- ----- + // 0 - 19 Reserved (Legacy) + // 20 Reset to 3.3v signal voltage (max fixed at 2.95v) + // 21 1.8v signal voltage (max fixed at 1.85v) + Package(){"PSTATE", 0, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 1, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 2, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 3, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 4, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 5, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 6, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 7, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 8, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 9, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 11, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 12, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 13, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 14, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 15, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 16, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 17, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 18, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 19, Package(){"DELAY", package() { 1 }}}, + Package(){"PSTATE", 20, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO17_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO6_C", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO17_E", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO6_C", // VREG ID + 1, // Voltage Regulator type = LDO + 2950000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + Package(){"PSTATE", 21, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO6_C", // VREG ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + Package(){"PSTATE", 22, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO17_E", // VREG ID + 1, // Voltage Regulator type = LDO + 2960000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO6_C", // VREG ID + 1, // Voltage Regulator type = LDO + 2950000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + Package(){"PSTATE", 23, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO17_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + Package() + { + "PPP_RESOURCE_ID_LDO6_C", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force disable from software + 0, // power mode - Low Power Mode + 0, // head room voltage + }, + }, + Package() {"DELAY", package() { 35 }}, + }, + }, + + // P-state set 1: APPS Clock frequencies + // 0: Disable + // 1: 20 MHz (SVS2) + // 2: 100 MHz (SVS) + // 3: 202 MHz (Nominal) + Package() + { + "PSTATE_SET", + 0x1, + + Package() + { + "PSTATE", + 0x0, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 2}}, + }, + Package() + { + "PSTATE", + 0x1, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 20000000, 2}}, + }, + Package() + { + "PSTATE", + 0x2, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 100000000, 2}}, + }, + Package() + { + "PSTATE", + 0x3, + package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 202000000, 2}}, + }, + }, + + // P-state set 2: Bus Bandwidth requests + // P0: IB = 400 MBps, AB = 200 MBps + // P1: IB = 200 MBps, AB = 100 MBps + // P2: IB = 40 MBps, AB = 20 MBps + // P3: IB = 0 MBps, AB = 0 MBps + Package() + { + "PSTATE_SET", + 0x2, + + Package() + { + "PSTATE", + 0x0, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 400000000, 200000000}}, + }, + + Package() + { + "PSTATE", + 0x1, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 200000000, 100000000}}, + }, + + Package() + { + "PSTATE", + 0x2, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 40000000, 20000000}}, + }, + + Package() + { + "PSTATE", + 0x3, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 0, 0}}, + }, + }, + + // P-state set 3: MSFT P-states + // P0: Clk = 200 MHz, IB = 400 MBps, AB = 200 MBps + // P1: Clk = 100 MHz, IB = 200 MBps, AB = 100 MBps + // P2: Clk = 20 MHz, IB = 40 MBps, AB = 20 MBps + Package() + { + "PSTATE_SET", + 0x3, + + Package() + { + "PSTATE", + 0x0, + Package() { "PSTATE_ADJUST", Package() { 1, 3 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 0 } }, + }, + Package() + { + "PSTATE", + 0x1, + Package() { "PSTATE_ADJUST", Package() { 1, 2 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 1 } }, + }, + Package() + { + "PSTATE", + 0x2, + Package() { "PSTATE_ADJUST", Package() { 1, 1 } }, + Package() { "PSTATE_ADJUST", Package() { 2, 2 } }, + }, + }, + + + // P-state set 4: AHB clock + Package() + { + "PSTATE_SET", + 0x4, + + Package() + { + "PSTATE", + 0x0, + package() {"CLOCK", package() {"gcc_sdcc2_ahb_clk", 1,}}, // AHB freq should be 100 MHz + }, + Package() + { + "PSTATE", + 0x1, + package() {"CLOCK", package() {"gcc_sdcc2_ahb_clk", 2}}, + }, + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + + Package() {"PSTATE_ADJUST", Package () { 0, 22 }}, + package() {"TLMMPORT", package() { 0x9B2000, 0x7FFF, 0x1FE4 }}, + Package() {"PSTATE_ADJUST", Package() { 2, 0 }}, + Package() {"PSTATE_ADJUST", Package() { 4, 0 }}, + Package() {"PSTATE_ADJUST", Package() { 1, 3 }}, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() {"PSTATE_ADJUST", Package() { 1, 0 }}, + Package() {"PSTATE_ADJUST", Package() { 4, 1 }}, + Package() {"PSTATE_ADJUST", Package() { 2, 3 }}, + package() {"TLMMPORT", package() { 0x9B2000, 0x7FFF, 0xA00 }}, + Package() {"PSTATE_ADJUST", Package () { 0, 23 }}, + }, + + // Consider Abandon state as D3 state. This is executed by PEP when the driver unloads. + Package() { "ABANDON_DSTATE", 3 }, + + Package() + { + "CRASHDUMP_EXCEPTION", + Package() { "EXECUTE_FUNCTION", Package() { "ExecuteOcdSdCardExceptions"}}, + }, + + Package() + { + "CRASHDUMP_DSTATE", + 0, + }, + + }, + /////////////////////////////////////////////////////////////////////////////////////// + + Package() + { + "DEVICE", + "\\_SB.ADSP.SLM1", + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + Package() + { + "DEVICE", + "\\_SB.ADSP.SLM2", + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + ///////////////////////////////////////////////////////////////////////////////////// + }) + + Name(LPCC, + package () + { + + //UCSI Type-C resources + Package() + { + "DEVICE", + "\\_SB.UCS0", + Package() + { + "COMPONENT",0, //Component 0: USB HS Rails for Charger Detection + Package(){"FSTATE", 0 }, //Dummy F-State, required for P-State operation + Package() + { + "PSTATE", 0, // P0 state - Component ON + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + // Now Enable all the clocks + //aggre_usb3_prim_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 200, 9}}, + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 200, 9}}, + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 200, 9}}, + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 9, 8,}}, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + // Now Enable all the clocks + //aggre_usb3_sec_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 200, 9}}, + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 200, 9}}, + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 200, 9}}, + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 9, 8,}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + }, + Package() + { + "PSTATE", 1, // P1 state - Component OFF + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2 }}, + + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, //2==Disable + }, + }, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2 }}, + + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, //2==Disable + }, + }, + + //Enable vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 0} + }, + }, + }, + //D states + package() { + "DSTATE", 0x0, // D0 state + }, + package() { + "DSTATE", 0x1, // D1 state + }, + package() { + "DSTATE", 0x2, // D2 state + }, + package() { + "DSTATE", 0x3, // D3 state + }, + },//UCS0 + + Package() + { + "DEVICE", + "\\_SB.URS0", + Package() + { + "COMPONENT", + Zero, + Package() {"FSTATE", 0}, + Package() {"PSTATE", 0}, + Package() {"PSTATE", 1} + }, + Package() {"DSTATE", 0 }, + Package() {"DSTATE", 1 }, + Package() {"DSTATE", 2 }, + Package() {"DSTATE", 3 } + }, + + + //USB SS/HS1 core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.URS0.USB0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM1000 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L16E - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L16 @3.072v + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L3C - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L5 @ 0.88v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + + // Now Enable all the clocks + + //aggre_usb3_prim_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 200, 9}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 200, 9}}, + + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 200, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 9, 8,}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() {"CLOCK", package() { "gcc_usb3_prim_phy_aux_clk", 2}}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L5 @ 0.88v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L5 @ 0.88v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + // Disable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L5 @ 0 v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for USB0 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB0 + + // + //************************* USB3.0 SS/HS0 core (Peripheral Stack) **************************** + // + package() + { + "DEVICE", + "\\_SB.URS0.UFN0", + package() + { + "COMPONENT", + 0x0, + // F-State placeholders + package() + { + "FSTATE", + 0x0, + }, + package() + { + "PSTATE", + 0x0, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + + package() + { // PERIPH D0 + "DSTATE", + 0x0, + //Power Grid for SDM1000 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L16E - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L16 @3.072v + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L3C - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L5 @ 0.88v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + + //aggre_usb3_prim_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 200, 9}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 200, 9}}, + + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 200, 9}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 9, 8,}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + }, + package() + { + // PERIPH D1: Not supported by USBFN driver + "DSTATE", //USB SS+HS suspend state + 0x1, + }, + package() + { // PERIPH D2 + "DSTATE", //USB DCP/HVDCP charger state + 0x2, + + // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable ; + package() {"CLOCK", package() { "gcc_usb30_prim_master_clk", 2 } }, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + //Disable gcc_usb3_prim_phy_aux_clk + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2}}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L5 @ 0.88v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { + // PERIPH D3 + "DSTATE", + 0x3, // Detach State + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + // Disable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L5 @ 0 v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for UFN0 (peripheral) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End UFN0 + + + + + ////////////////////////////////////////////////////////////////// + //USB Secondary Core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.URS1", + Package() + { + "COMPONENT", + Zero, + Package() {"FSTATE", 0}, + Package() {"PSTATE", 0}, + Package() {"PSTATE", 1} + }, + Package() {"DSTATE", 0 }, + Package() {"DSTATE", 1 }, + Package() {"DSTATE", 2 }, + Package() {"DSTATE", 3 } + }, + + Package() + { + "DEVICE", + "\\_SB.URS1.USB1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM1000 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L16E - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L16 @3.072v + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L3C - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L5 @ 0.88v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + + // Now Enable all the clocks + + //aggre_usb3_sec_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 200, 9}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 200, 9}}, + + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 200, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 9, 8,}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2 }}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L5 @ 0.88v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L5 @ 0.88v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + // Disable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L5 @ 0 v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for URS1 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End URS1.USB1 + +// + //************************* USB3.0 SS/HS 1 core (Peripheral Stack) **************************** + // + package() + { + "DEVICE", + "\\_SB.URS1.UFN1", + package() + { + "COMPONENT", + 0x0, + // F-State placeholders + package() + { + "FSTATE", + 0x0, + }, + package() + { + "PSTATE", + 0x0, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + + package() + { // PERIPH D0 + "DSTATE", + 0x0, + //Power Grid for SDM1000 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L16E - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L16 @3.072v + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L3C - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + + //aggre_usb3_sec_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 200, 9}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 200, 9}}, + + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 200, 9}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 9, 8,}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + }, + package() + { + // PERIPH D1: Not supported by USBFN driver + "DSTATE", //USB SS+HS suspend state + 0x1, + }, + package() + { // PERIPH D2 + "DSTATE", //USB DCP/HVDCP charger state + 0x2, + + // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable ; + package() {"CLOCK", package() { "gcc_usb30_sec_master_clk", 2 } }, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + //Disable gcc_usb3_sec_phy_aux_clk + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2}}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + }, + package() + { + // PERIPH D3 + "DSTATE", + 0x3, // Detach State + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + // Disable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 4, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + }, + // Define Abandon State for UFN1 (peripheral) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End UFN1 + + // Empty Test Device + /*Package() + { + "DEVICE", + "\\_SB.USB2", + Package() + { + "COMPONENT", + Zero, + Package() {"FSTATE", 0}, + Package() {"PSTATE", 0}, + Package() {"PSTATE", 1} + }, + Package() {"DSTATE", 0 }, + Package() {"DSTATE", 1 }, + Package() {"DSTATE", 2 }, + Package() {"DSTATE", 3 } + }, + */ + + //USB Multiport core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.USB2", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM1000 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L16E - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L16 @3.072v + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L3C - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L5 @ 0.88v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // Enable usb30_mp_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_mp_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_mp_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_mp_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_mp_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_mp_phy_pipe_0_clk, Sourced by QMP Phy PLL + //package() {"CLOCK", package() {"gcc_usb3_mp_phy_pipe_0_clk", 6, 0, 0, 0x0}}, + // Enable MP0 PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_mp_phy_pipe_0_clk", 1}}, + // Mark Suppressible for USB MP0 PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_mp_phy_pipe_0_clk", 9, 8,}}, + // Enable MP1 PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_mp_phy_pipe_1_clk", 1}}, + // Mark Suppressible for USB MP1 PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_mp_phy_pipe_1_clk", 9, 8,}}, + + // Now Enable all the clocks + + //aggre_usb3_mp_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_mp_axi_clk", 8, 200, 9}}, + + // gcc_cfg_noc_usb3_mp_axi_clk should be configured to the frequency as master clock + // @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_mp_axi_clk", 8, 200, 9}}, + + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 8, 200, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_mp_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_mp_phy_aux_clk", 8, 1200, 7}}, + + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_mp_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_mp_phy_com_aux_clk", 9, 8,}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_2", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_2", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + //package() {"CLOCK", package() {"gcc_usb3_mp_clkref_en", 1}}, + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + // Enable usb30_mp_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_mp_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 2}}, + + // gcc_cfg_noc_usb3_mp_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_mp_axi_clk", 2}}, + + //Disable aggre_usb3_mp_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_mp_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_2", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() {"CLOCK", package() { "gcc_usb3_mp_phy_aux_clk", 2}}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_mp_phy_com_aux_clk", 2 }}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + //package() {"CLOCK", package() {"gcc_usb3_mp_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_2",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L5 @ 0.88v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 2}}, + + // gcc_cfg_noc_usb3_mp_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_mp_axi_clk", 2}}, + + // Disable aggre_usb3_mp_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_mp_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_mp_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_mp_phy_com_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_2", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + //package() {"CLOCK", package() {"gcc_usb3_mp_clkref_en", 2}}, + + + // Enable usb30_mp_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_mp_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_2", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE & VDDA_QUSB0_HS + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L5 @ 0.88v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 2}}, + + // gcc_cfg_noc_usb3_mp_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_mp_axi_clk", 2}}, + + // Disable aggre_usb3_mp_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_mp_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_mp_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_mp_phy_com_aux_clk", 2 }}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_2", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + //package() {"CLOCK", package() {"gcc_usb3_mp_clkref_en", 2}}, + + // Disable usb30_mp_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_mp_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_2",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS + package() // Vote for L5 @ 0 v + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + }, + // Define Abandon State for MP0 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB2 + + }) + + // Added LPCD method similar to LPCC except it uses L9E in place of L5E. + // ACPI needs to vote for differently resource in case of MTP V2 and CLS with board revision >= 4 + Name(LPCD, + package () + { + //UCSI Type-C resources + Package() + { + "DEVICE", + "\\_SB.UCS0", + Package() + { + "COMPONENT",0, //Component 0: USB HS Rails for Charger Detection + Package(){"FSTATE", 0 }, //Dummy F-State, required for P-State operation + Package() + { + "PSTATE", 0, // P0 state - Component ON + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + // Now Enable all the clocks + //aggre_usb3_prim_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 200, 9}}, + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 120 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 200, 9}}, + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 200, 9}}, + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 9, 8,}}, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + // Now Enable all the clocks + //aggre_usb3_sec_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 200, 9}}, + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 200, 9}}, + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 200, 9}}, + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 9, 8,}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + }, + Package() + { + "PSTATE", 1, // P1 state - Component OFF + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2 }}, + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, //2==Disable + }, + }, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2 }}, + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, //2==Disable + }, + }, + + //Enable vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 0} + }, + }, + }, + //D states + package() { + "DSTATE", 0x0, // D0 state + }, + package() { + "DSTATE", 0x1, // D1 state + }, + package() { + "DSTATE", 0x2, // D2 state + }, + package() { + "DSTATE", 0x3, // D3 state + }, + }, //UCS0 + + Package() + { + "DEVICE", + "\\_SB.URS0", + Package() + { + "COMPONENT", + Zero, + Package() {"FSTATE", 0}, + Package() {"PSTATE", 0}, + Package() {"PSTATE", 1} + }, + Package() {"DSTATE", 0 }, + Package() {"DSTATE", 1 }, + Package() {"DSTATE", 2 }, + Package() {"DSTATE", 3 } + }, + + + //USB SS/HS1 core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.URS0.USB0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM1000 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L16E - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L16 @3.072v + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L3C - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + + // Now Enable all the clocks + + //aggre_usb3_prim_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 200, 9}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 200, 9}}, + + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 200, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 9, 8,}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() {"CLOCK", package() { "gcc_usb3_prim_phy_aux_clk", 2}}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - LPM + 0, // head room voltage + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + // Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + // Disable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE + package() // Vote for L9 @ 0 v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 4, // power mode - LPM + 0, // head room voltage + }, + }, + }, + // Define Abandon State for USB0 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB0 + + // + //************************* USB3.0 SS/HS0 core (Peripheral Stack) **************************** + // + package() + { + "DEVICE", + "\\_SB.URS0.UFN0", + package() + { + "COMPONENT", + 0x0, + // F-State placeholders + package() + { + "FSTATE", + 0x0, + }, + package() + { + "PSTATE", + 0x0, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + + package() + { // PERIPH D0 + "DSTATE", + 0x0, + //Power Grid for SDM1000 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L16E - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L16 @3.072v + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L3C - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Enable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}}, + + //aggre_usb3_prim_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 200, 9}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + // @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 200, 9}}, + + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 200, 9}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}}, + + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 9, 8,}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}}, + }, + package() + { + // PERIPH D1: Not supported by USBFN driver + "DSTATE", //USB SS+HS suspend state + 0x1, + }, + package() + { // PERIPH D2 + "DSTATE", //USB DCP/HVDCP charger state + 0x2, + + // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable ; + package() {"CLOCK", package() { "gcc_usb30_prim_master_clk", 2 } }, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + //Disable gcc_usb3_prim_phy_aux_clk + package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2}}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + }, + package() + { + // PERIPH D3 + "DSTATE", + 0x3, // Detach State + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}}, + + // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}}, + + //Disable aggre_usb3_prim_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_prim_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_0", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}}, + + + // Disable usb30_prim_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_prim_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_0",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE + package() // Vote for L9 @ 0 v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 4, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + }, + // Define Abandon State for UFN0 (peripheral) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End UFN0 + + ////////////////////////////////////////////////////////////////// + //USB Secondary Core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.URS1", + Package() + { + "COMPONENT", + Zero, + Package() {"FSTATE", 0}, + Package() {"PSTATE", 0}, + Package() {"PSTATE", 1} + }, + Package() {"DSTATE", 0 }, + Package() {"DSTATE", 1 }, + Package() {"DSTATE", 2 }, + Package() {"DSTATE", 3 } + }, + + Package() + { + "DEVICE", + "\\_SB.URS1.USB1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM1000 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L16E - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L16 @3.072v + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L3C - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + + // Now Enable all the clocks + + //aggre_usb3_sec_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 200, 9}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 200, 9}}, + + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz (Nominal for SS+) + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 200, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 9, 8,}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - LPM + 0, // head room voltage + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - LPM + 0, // head room voltage + }, + }, + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + // Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + // Disable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE + package() // Vote for L9 @ 0 v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 4, // power mode - LPM + 0, // head room voltage + }, + }, + }, + // Define Abandon State for USB1 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB1 + + // + //************************* USB3.0 SS/HS 1 core (Peripheral Stack) **************************** + // + package() + { + "DEVICE", + "\\_SB.URS1.UFN1", + package() + { + "COMPONENT", + 0x0, + // F-State placeholders + package() + { + "FSTATE", + 0x0, + }, + package() + { + "PSTATE", + 0x0, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + + package() + { // PERIPH D0 + "DSTATE", + 0x0, + //Power Grid for SDM1000 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L16E - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L16 @3.072v + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L3C - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Enable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}}, + // Enable PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}}, + // Mark Suppressible for USB PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}}, + + //aggre_usb3_sec_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 200, 9}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + // @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 200, 9}}, + + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 200, 9}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}}, + + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 9, 8,}}, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}}, + }, + package() + { + // PERIPH D1: Not supported by USBFN driver + "DSTATE", //USB SS+HS suspend state + 0x1, + }, + package() + { // PERIPH D2 + "DSTATE", //USB DCP/HVDCP charger state + 0x2, + + // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable ; + package() {"CLOCK", package() { "gcc_usb30_sec_master_clk", 2 } }, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + //Disable gcc_usb3_sec_phy_aux_clk + package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2}}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + }, + package() + { + // PERIPH D3 + "DSTATE", + 0x3, // Detach State + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}}, + + // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}}, + + //Disable aggre_usb3_sec_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_sec_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_1", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization + // No option of enabling it through ACPI + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}}, + + + // Disable usb30_sec_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_sec_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_1",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 MBps + 0 // AB=0 Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE + package() // Vote for L9 @ 0 v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // force enable from software + 4, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + }, + // Define Abandon State for UFN1 (peripheral) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End UFN1 + + + // Empty Test Device + /*Package() + { + "DEVICE", + "\\_SB.USB2", + Package() + { + "COMPONENT", + Zero, + Package() {"FSTATE", 0}, + Package() {"PSTATE", 0}, + Package() {"PSTATE", 1} + }, + Package() {"DSTATE", 0 }, + Package() {"DSTATE", 1 }, + Package() {"DSTATE", 2 }, + Package() {"DSTATE", 3 } + }, + */ + + //USB Multiport core (Host Stack) + Package() + { + "DEVICE", + "\\_SB.USB2", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() { "FSTATE", 0x0, }, + package() + { + "PSTATE", + 0x0, + }, + package() + { + "PRELOAD_PSTATE", + 0, + },// index 0 is P-state 0 here + }, + //D states + Package() + { // HOST D0 + "DSTATE", + 0x0, + //Power Grid for SDM1000 + package() + { + // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L12 @1.8v + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage 1.8V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L16E - VDDA_QUSB_HS0_3P1 + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L16 @3.072v + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // L3C - VDDA_USB_SS_1P2 (QMP PHY) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 7, // SW Power Mode = NPM + 0, // Head Room + }, + }, + + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 7, // power mode - Normal Power Mode + 0, // head room voltage + }, + }, + + // Enable usb30_mp_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_mp_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + // Enable USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_mp_sleep_clk", 1}}, + // Mark Suppressible for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_mp_sleep_clk", 9, 8,}}, + // Mark Always On for USB 3.0 Sleep Clock + package() { "CLOCK", package() { "gcc_usb30_mp_sleep_clk", 9, 12,}}, + //Select external source action for gcc_usb3_mp_phy_pipe_0_clk, Sourced by QMP Phy PLL + // package() {"CLOCK", package() {"gcc_usb3_mp_phy_pipe_0_clk", 6, 0, 0, 0x0}}, + // Enable MP0 PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_mp_phy_pipe_0_clk", 1}}, + // Mark Suppressible for USB MP0 PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_mp_phy_pipe_0_clk", 9, 8,}}, + // Enable MP1 PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_mp_phy_pipe_1_clk", 1}}, + // Mark Suppressible for USB MP1 PHY pipe Clock + package() { "CLOCK", package() { "gcc_usb3_mp_phy_pipe_1_clk", 9, 8,}}, + + // Now Enable all the clocks + + //aggre_usb3_mp_axi Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_aggre_usb3_mp_axi_clk", 8, 200, 9}}, + + // gcc_cfg_noc_usb3_mp_axi_clk should be configured to the frequency as master clock + // @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_mp_axi_clk", 8, 200, 9}}, + + // USB 3.0 Master Clock @ 200 MHz 8 = Set & Enable; 200,9 -> Atleast 200 Mhz + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 8, 200, 9}}, + + //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb30_mp_mock_utmi_clk", 8, 19200, 7}}, + + // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_mp_phy_aux_clk", 8, 1200, 7}}, + + // Phy Com Aux Clock @ 19.2 Mhz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz + package() {"CLOCK", package() {"gcc_usb3_mp_phy_com_aux_clk", 8, 19200, 7}}, + // Mark Suppressible for Phy Com Aux Clock + package() {"CLOCK", package() {"gcc_usb3_mp_phy_com_aux_clk", 9, 8,}}, + + //Vote for max freq: BUS Arbiter Request (Type-3) + // Instantaneous BW BytesPerSec = 671088640; + // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8 + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_2", // Master + "ICBID_SLAVE_EBI1", // Slave + 671088640, // IB=5Gbps + 671088640 // AB=5Gbps + } + }, + + //Nominal==block vdd_min: + package() + { + "NPARESOURCE", + Package() {1, "/arc/client/rail_cx", 256} + }, + + // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0) + // Required for gcc_usb_phy_cfg_ahb2phy_clk + //BUS Arbiter Request (Type-3) + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_2", // Slave + 400000000, // IB=400 MBps + 0 // AB=0 MBps + } + }, + + // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK) + package() {"CLOCK", package() {"gcc_usb3_mp0_clkref_en", 1}}, + package() {"CLOCK", package() {"gcc_usb3_mp1_clkref_en", 1}}, + }, + package() + { // HOST D1 + "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend) + 0x1, + + // Enable usb30_mp_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_mp_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 3, 9600, 5}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 2}}, + + // gcc_cfg_noc_usb3_mp_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_mp_axi_clk", 2}}, + + //Disable aggre_usb3_mp_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_mp_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_mock_utmi_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_2", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package() {"CLOCK", package() { "gcc_usb3_mp_phy_aux_clk", 2}}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_mp_phy_com_aux_clk", 2}}, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_mp0_clkref_en", 2}}, + package() {"CLOCK", package() {"gcc_usb3_mp1_clkref_en", 2}}, + + //BUS Arbiter Request (Type-3) + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_2",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + // L3C is used for QMP PHY + // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2) + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage 1.2V : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + // VDDA_USB_SS_CORE + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L9 @ 0.912v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 912000, // Voltage (microvolts) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - LPM + 0, // head room voltage + }, + }, + }, + package() + { // HOST D2 + "DSTATE", + 0x2, // Slave device disconnect (host cable is still connected) + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 2}}, + + // gcc_cfg_noc_usb3_mp_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_mp_axi_clk", 2}}, + + // Disable aggre_usb3_mp_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_mp_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_mp_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_mp_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_2", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_mp0_clkref_en", 2}}, + package() {"CLOCK", package() {"gcc_usb3_mp1_clkref_en", 2}}, + + + // Enable usb30_mp_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_mp_gdsc", // USB 3.0 Core Power domain + 1, //1==Enable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_USB3_2", // Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() + { + "NPARESOURCE", + package() { 1, "/arc/client/rail_cx", 0} + }, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", + package() //Vote for L12 @1.8v + { + // L12 - VDDA_QUSB_HS0_1P8 + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage : microvolts ( V ) + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @3.072v + { + // L16E - VDDA_QUSB_HS0_3P1 + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 3072000, // Voltage = 3.072 V + 1, // SW Enable = Enable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE + package() // Vote for L5 @ 0 v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 880000, // Voltage is in micro volts + 1, // force enable from software + 4, // power mode - LPM + 0, // head room voltage + }, + }, + }, + package() + { // HOST D3 + "DSTATE", + 0x3, // Abandon state + + //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 3, 9600000, 1}}, + + // Disable USB 3.0 Master Clock 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_master_clk", 2}}, + + // gcc_cfg_noc_usb3_mp_axi_clk should be configured to the frequency as master clock + package() {"CLOCK", package() {"gcc_cfg_noc_usb3_mp_axi_clk", 2}}, + + // Disable aggre_usb3_mp_axi + package() {"CLOCK", package() {"gcc_aggre_usb3_mp_axi_clk", 2}}, + + // Disable UTMI clk 2 = Disable + package() {"CLOCK", package() {"gcc_usb30_mp_mock_utmi_clk", 2}}, + + // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable; + package(){"CLOCK", package() {"gcc_usb3_mp_phy_aux_clk", 2 }}, + + // Disable Phy Com Aux Clock @ 19.2 Mhz 2 = Disable; + package() {"CLOCK", package() {"gcc_usb3_mp_phy_com_aux_clk", 2}}, + + // Remove Vote for CNOC 100 MHz + // Required for gcc_usb_phy_cfg_ahb2phy_clk + // BUS Arbiter Request (Type-3) + // Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_APPSS_PROC", // Master + "ICBID_SLAVE_USB3_2", // Slave + 0, // IB=0 MBps + 0 // AB=0 MBps + } + }, + + // Disable SS Phy Reference Clock (diff clock) 2 = Disable + package() {"CLOCK", package() {"gcc_usb3_mp0_clkref_en", 2}}, + package() {"CLOCK", package() {"gcc_usb3_mp1_clkref_en", 2}}, + + // Disable usb30_mp_gdsc power domain + package() + { + "FOOTSWITCH", // Footswitch + package() + { + "usb30_mp_gdsc", // USB 3.0 Core Power domain + 2, // 2==Disable + }, + }, + + //Vote for 0 freq + package() + { + "BUSARB", + package() + { + 3, // Req Type + "ICBID_MASTER_USB3_2",// Master + "ICBID_SLAVE_EBI1", // Slave + 0, // IB=0 Mbps + 0 // AB=0Mbps + } + }, + + //enable vdd_min + package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}}, + + //Power Grid for SDM1000 + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() // Vote for L16 @ 0V - VDDA_QUSB_HS0_3P1 + { + "PPP_RESOURCE_ID_LDO16_E", // Voltage Regulator ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8 + { + "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage : 0 microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for L3 @ 0v - VDDA_USB_SS_1P2 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage 0 V : microvolts ( V ) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE + package() // Vote for L5 @ 0 v + { + "PPP_RESOURCE_ID_LDO9_E", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (microvolts) + 0, // SW Enable = Disable + 4, // SW Power Mode = LPM + 0, // Head Room + }, + }, + // VDDA_QUSB0_HS + Package() + { + "PMICVREGVOTE", + Package() + { + "PPP_RESOURCE_ID_LDO5_E", // VREG ID + 1, // Voltage Regulator type = LDO + 0, // Voltage is in micro volts + 0, // SW Enable = Disable + 4, // power mode - LPM + 0, // head room voltage + }, + }, + }, + // Define Abandon State for MP0 (host) stack ie. Power State invoked when stack unloads/tears down + package() + { + "ABANDON_DSTATE", + 3 // Abandon D state defined as D3 + }, + }, //End USB2 + + }) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/corebsp_wa_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/corebsp_wa_resources.asl new file mode 100644 index 0000000..ede700d --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/corebsp_wa_resources.asl @@ -0,0 +1,244 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by core BSP drivers. +// +// +// Copyright (c) 2010-2011 by Mmoclauq Technologies Inc. All Rights Reserved. +// Mmoclauq Confidential and Proprietary +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + Method(LPMD) + { + Return(LPCC) + } + + Name(LPCC, + Package () + { + //Need to put under external Cfg package + //Touch + // Package() + // { + // "DEVICE", + // "\\_SB.TSC0", + // Package() + // { + // "COMPONENT", + // 0x0, // Component 0. + // Package() + // { + // "FSTATE", + // 0x0, // f0 state + // }, + + // Package() + // { + // "FSTATE", + // 0x1, // f1 state + // }, + + // }, + // Package() + // { + // "DSTATE", + // 0x0, // D0 state + + // package() + // { + // "PMICVREGVOTE", // PMICVREGVOTE resource + // package() + // { + // "PPP_RESOURCE_ID_SMPS3_A", + // 2, // Voltage Regulator type = SMPS + // 1800000, // 1.8V + // 2000000, // 2000 mA -> 2A + // 1, // Force enable from s/w + // 0, // Disable pin control enable + // 0, // Power mode - AUTO + // 0, // Disable pin control power mode + // 0, // Bypass allowed - default + // 5, // Frequency - 3.20 MHz + // 0, // Freq reason - none + // 0, // Quiet Mode - disable + // 0, // Corner Mode - none + // 0, // head room voltage + // }, + // }, + + + // package() + // { + // "TLMMGPIO", // TLMMGPIO Resource Enabling HID/I2C firmware on Touch Controller + // package() + // { + // 57, // PIN number + // 0, // State = active + // 0, // Function select = GPIO + // 1, // direction = Output + // 0, // Pull value = No Pull + // 0, // Drive Strength = 2mA + // }, + // }, + + + + // // START mxT1386E in RESET + // package() + // { + // "TLMMGPIO", // TLMMGPIO resource Touch RESET + // package() + // { + // 60, // PIN number + // 0, // State = inactive + // 0, // Function select = GPIO + // 1, // direction = Output + // 0, // Pull value = No Pull + // 0, // Drive Strength = 2mA + // }, + // }, + + // // Enable POWER to mxT1664S using LDO 22 + // package() + // { + // "PMICVREGVOTE", // PMICVREGVOTE resource + // package() + // { + // "PPP_RESOURCE_ID_LDO22_A", // VREG ID + // 1, // Voltage Regulator type = LDO + // 3000000, // 3.00V. Voltage is in micro volts on 8960 + // 300000, // 300 mA Peak current in microamps + // 1, // force enable from software + // 0, // disable pin control enable + // 1, // power mode - Normal Power Mode + // 0, // power mode pin control - disable + // 0, // bypass mode allowed + // 0, // head room voltage + // }, + // }, + + + // // WAIT for AVdd & DVdd to stabilize + // package() + // { + // "DELAY", // Delay resource + // package() + // { + // 2, // 2 Millisec delay + // }, + // }, + // // Take mxT1664S out of RESET + // package() + // { + // "TLMMGPIO", // TLMMGPIO resource Touch RESET + // package() + // { + // 60, // PIN number + // 1, // State = active + // 0, // Function select = GPIO + // 1, // direction = Output + // 0, // Pull value = No Pull + // 0, // Drive Strength = 2mA + // }, + // }, + // // WAIT for mxT1386E to be READY for I2C communication + // package() + // { + // "DELAY", // Delay resource + // package() + // { + // 100, // 100 Millisec delay + // }, + // }, + + + + // }, //End of D0 + + // Package() + // { + // "DSTATE", + // 0x3, // D3 state + + // // Turn OFF POWER to mxT1664S + // package() + // { + // "PMICVREGVOTE", // PMICVREGVOTE resource + // package() + // { + // "PPP_RESOURCE_ID_LDO22_A", + // 1, // Voltage Regulator type = LDO + // 0, // Voltage (uV) + // 0, // Peak current (uA) + // 0, // force disable from software + // 0, // disable pin control enable + // 0, // power mode - Low Power Mode + // 0, // power mode pin control - disable + // 0, // bypass mode allowed + // 0, // head room voltage + // }, + // }, + + // //Drive SMPS3A to low power mode + // package() + // { + // "PMICVREGVOTE", // PMICVREGVOTE resource + // package() + // { + // "PPP_RESOURCE_ID_SMPS3_A", + // 2, // Voltage Regulator type = SMPS + // 0, // 0V + // 0, // 0 mA + // 1, // Force enable from s/w + // 0, // Disable pin control enable + // 0, // Power mode - AUTO + // 0, // Disable pin control power mode + // 0, // Bypass allowed - default + // 5, // Frequency - 3.20 MHz + // 0, // Freq reason - none + // 0, // Quiet Mode - disable + // 0, // Corner Mode - none + // 0, // head room voltage + // }, + // }, + + + // //Drive Firmware Selection line to low power mode + // package() + // { + // "TLMMGPIO", // TLMMGPIO Resource Selecting HID/I2C firmware on Touch Controller + // package() + // { + // 57, // PIN number + // 0, // State = Inactive + // 0, // Function select = GPIO + // 0, // direction = Input + // 1, // Pull value = Pull Down + // 0, // Drive Strength = 2mA + // }, + // }, + // //Drive Reset line in low power mode + // package() + // { + // "TLMMGPIO", // TLMMGPIO resource Touch RESET + // package() + // { + // 60, // PIN number + // 0, // State = inactive + // 0, // Function select = GPIO + // 0, // direction = Output + // 1, // Pull value = Pull Down + // 0, // Drive Strength = 2mA + // }, + // }, + + // }, + // }, + ///////////////////////////////////////////////////////////////////////////////////// + }) + +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/corebsp_wp_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/corebsp_wp_resources.asl new file mode 100644 index 0000000..652b095 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/corebsp_wp_resources.asl @@ -0,0 +1,16 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by core BSP drivers. +// +// +// Copyright (c) 2010-2011, 2014 by Mmoclauq Technologies Inc. All Rights Reserved. +// Mmoclauq Confidential and Proprietary +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + +} diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/cust_dsdt_common.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/cust_dsdt_common.asl new file mode 100644 index 0000000..eaba73f --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/cust_dsdt_common.asl @@ -0,0 +1,4 @@ +// +// Copyright (c) 2015 Mmoclauq Technologies Inc. All rights reserved. +// Mmoclauq Technologies Proprietary and Confidential. +// \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/cust_wcnss_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/cust_wcnss_resources.asl new file mode 100644 index 0000000..05dfa49 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/cust_wcnss_resources.asl @@ -0,0 +1,15 @@ +//-------------------------------------------------------------------------------------------------- +// Copyright (c) 2016 Mmoclauq Technologies, Inc. +// All Rights Reserved. +// Confidential and Proprietary - Mmoclauq Technologies, Inc. +//-------------------------------------------------------------------------------------------------- + +//customizable resource for wlan/bt/fm +// PEP resources for iHelium +// END iHelium + +// PEP resources for Bluetooth SOC +// END BTH0 + +// PEP resources for FM SOC +// END FM diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/cust_win_mproc.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/cust_win_mproc.asl new file mode 100644 index 0000000..3a3afad --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/cust_win_mproc.asl @@ -0,0 +1,49 @@ +// +// Copyright (c) 2017 Mmoclauq Technologies, Inc. All Rights Reserved. +// Mmoclauq Technologies Proprietary and Confidential. +// +// =================================================================== +// EDIT HISTORY +// +// when who what, where, why +// -------- --- -------------------------------------------- +// 07/17/17 mic removed acpi info to inx file +// 08/10/15 kieranc Added sections for PIL, CDI, and RPEN for future usage +// 07/09/15 jeffreym initial file creation +// +// =================================================================== +// + +// +// MPROC Drivers (PIL Driver and Subsystem Drivers) +// + +Scope(\_SB.ADSP) +{ + +} + +Scope(\_SB.AMSS) +{ + +} + +Scope(\_SB.SCSS) +{ + +} + +Scope(\_SB.PILC) +{ + +} + +Scope(\_SB.CDI) +{ + +} + +Scope(\_SB.RPEN) +{ + +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/dbg2.aslc b/sdm845Pkg/AcpiTables/src/sc8180x/common/dbg2.aslc new file mode 100644 index 0000000..7bb7744 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/dbg2.aslc @@ -0,0 +1,604 @@ +// +// Copyright (c) 2011,2013-2017 Mmoclauq Technologies Inc. All rights reserved. +// + +#include "Platform.h" + + +#define MAX_OEM_WRITE_ENTRIES 8 + +#define DEBUG_DEVICE_PORT_TYPE_SERIAL 0x8000 +#define DEBUG_DEVICE_PORT_TYPE_USB 0x8002 +#define DEBUG_DEVICE_PORT_TYPE_NET 0x8003 + +#define DEBUG_DEVICE_PORT_SUBTYPE_SERIAL_QCOM 0x0004 +#define DEBUG_DEVICE_PORT_SUBTYPE_SERIAL_QCOM_S845 0x0011 + +#define DEBUG_DEVICE_PORT_SUBTYPE_NET_QCOM 0x5143 + +#define DEBUG_DEVICE_PORT_SUBTYPE_USB_QCOM 0x0004 +#define DEBUG_DEVICE_PORT_SUBTYPE_USB30 0x0000 + +#define DEBUG_DEVICE_OEM_PORT_USBFN 0x0001 +#define DEBUG_DEVICE_OEM_PORT_USBFN_SYNOPSYS 0x0005 + +// Subtype 3 need to be used only if unaligned access to strongly ordered memory isn't supported by hardware. +// But it works on all hardware so use this value +#define DEBUG_DEVICE_OEM_PORT_USBFN_BUFFERED 0x0003 + +#define NUMBER_OF_DBG_DEVICES 5 +#define MAX_NAME_SPACE_STRING_LENGTH 32 + +#define ACPI_DDI_V2_2_REGISTER_CNT 2 +#define ACPI_DDI_V3_REGISTER_CNT 1 + +// ACPI structure declarations. + +#pragma pack(1) + +typedef struct { + UINT8 Revision; + UINT16 Length; + UINT8 BaseAddressRegisterCount; + UINT16 NameSpaceStringLength; + UINT16 NameSpaceStringOffset; + UINT16 OemDataLength; + UINT16 OemDataOffset; + UINT16 PortType; + UINT16 PortSubtype; + UINT16 Reserved; + UINT16 BaseAddressRegisterOffset; + UINT16 AddressSizeOffset; +} ACPI_DEBUG_DEVICE_INFORMATION_V2; + +// +// v3 Debug Device Information Structure +// +typedef struct { + + UINT8 Revision; + UINT16 Length; + UINT8 BaseAddressRegisterCount; + UINT16 NameSpaceStringLength; + UINT16 NameSpaceStringOffset; + UINT16 OemDataLength; + UINT16 OemDataOffset; + UINT16 PortType; + UINT16 PortSubtype; + UINT16 Reserved; + UINT16 BaseAddressRegisterOffset; + UINT16 AddressSizeOffset; + ACPI_GAS DEVICE_ADDRESS; + UINT32 ADDRESS_SIZE; + UINT8 NameSpacestring[MAX_NAME_SPACE_STRING_LENGTH]; +} ACPI_DEBUG_DEVICE_INFORMATION_V3; + +typedef struct { + ACPI_HEADER Header; + UINT32 OffsetDbgDeviceInfo; + UINT32 NumberDbgDeviceInfo; +} ACPI_DEBUG_PORT_TABLE_V2; + +//OEM struct supported by KDNET +typedef struct { + UINT16 PortType; + UINT16 Reserved; + UINT32 Signature; + UINT32 WriteCount; + struct { + UINT8 BaseAddressRegister; + UINT8 Width; + UINT16 Offset; + UINT32 AndValue; + UINT32 OrValue; + } Data[MAX_OEM_WRITE_ENTRIES]; +} ACPI_DEBUG_DEVICE_OEM_DATA; + + +//OEM struct for SNPS controller supported by KDNET +//OEM Phase: 1 = after reset +// 2 = when configuration is done +// 3 = on connection done +typedef struct { + UINT16 PortType; + UINT16 Reserved; + UINT32 Signature; + UINT32 WriteCount; + struct { + UINT8 BaseAddressRegister; + UINT8 Phase; + UINT16 Reserved; + UINT32 Offset; + UINT32 AndValue; + UINT32 OrValue; + } Data[MAX_OEM_WRITE_ENTRIES]; +} ACPI_DEBUG_DEVICE_OEM_DATA_V2; + +// OEM Data Strucutre V3 based upon addition of secondary debugger +//OEM struct for SNPS controller supported by KDNET +//OEM Phase: 1 = after reset +// 2 = when configuration is done +// 3 = on connection done +typedef struct { + UINT16 PortType; + UINT16 Reserved; + UINT32 Signature; + UINT32 WriteCount; + struct { + UINT8 BaseAddressRegister; + UINT8 Phase; + UINT16 Reserved; + UINT32 Offset; + UINT32 AndValue; + UINT32 OrValue; + } Data[MAX_OEM_WRITE_ENTRIES]; + struct { + UINT8 UsbCore; + UINT8 Reserved1; + UINT16 Reserved2; + UINT32 Signature; // = 'USBC' + } ACPI_USB_INIT_CORE_OEM_DATA; +} ACPI_DEBUG_DEVICE_OEM_DATA_V3; + +//OEM struct supported by KDUSB, KDNET +typedef struct { + + UINT32 StructureSize; + UINT64 GpioPhysicalAddress; + UINT32 GpioBlockSize; + UINT32 WriteCount; + UINT32 Offset[12]; + UINT32 Value[12]; + +} OEM_DATA; + +typedef struct { + ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation; + + // not part of the actual structure + ACPI_GAS BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH]; +} ACPI_DEBUG_DEVICE_INFORMATION_V2_IMPL; + +typedef struct { + ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation; + + // not part of the actual structure + ACPI_GAS BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH]; + OEM_DATA OemData; +} ACPI_DEBUG_DEVICE_INFORMATION_V2_1_OEM_IMPL; + +typedef struct { + ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation; + + // not part of the actual structure + ACPI_GAS BaseAddressRegister[ACPI_DDI_V2_2_REGISTER_CNT]; + UINT32 AddressSize[ACPI_DDI_V2_2_REGISTER_CNT]; + UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH]; + ACPI_DEBUG_DEVICE_OEM_DATA OemData; +} ACPI_DEBUG_DEVICE_INFORMATION_V2_2_OEM_IMPL; + +typedef struct { + ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation; + // not part of the actual structure + ACPI_GAS BaseAddressRegister[ACPI_DDI_V2_2_REGISTER_CNT]; + UINT32 AddressSize[ACPI_DDI_V2_2_REGISTER_CNT]; + UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH]; + ACPI_DEBUG_DEVICE_OEM_DATA_V2 OemData; +} ACPI_DEBUG_DEVICE_INFORMATION_V2_3_OEM_IMPL; + +typedef struct { + ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation; + // not part of the actual structure + ACPI_GAS BaseAddressRegister[ACPI_DDI_V2_2_REGISTER_CNT]; + UINT32 AddressSize[ACPI_DDI_V2_2_REGISTER_CNT]; + UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH]; + ACPI_DEBUG_DEVICE_OEM_DATA_V3 OemData; +} ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL; +typedef struct { + ACPI_DEBUG_DEVICE_INFORMATION_V3 DebugDeviceInformation; + OEM_DATA OemData; +} ACPI_DEBUG_DEVICE_INFORMATION_V3_OEM_IMPL; + +typedef struct { + ACPI_DEBUG_PORT_TABLE_V2 DebugPortTable; + + // not part of the actual structure + ACPI_DEBUG_DEVICE_INFORMATION_V2_IMPL DebugDevice1; // UART KDCOM + ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL DebugDevice2; // KDNET on primary port on SNPS controller + ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL DebugDevice3; // KDNET on secondary port on SNPS controller + ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL DebugDevice4; // KDNET on primary port on SNPS controller - SuperSpeed + ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL DebugDevice5; // KDNET on secondary port on SNPS controller - SuperSpeed + +} ACPI_DEBUG_PORT_TABLE_V2_IMPL; + +#pragma pack() + + +// Fixed field values. +#define ACPI_DDI_V2_REVISION 1 +#define ACPI_DDI_V2_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_IMPL) +#define ACPI_DDI_V2_1_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_1_OEM_IMPL) +#define ACPI_DDI_V2_2_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_2_OEM_IMPL) +#define ACPI_DDI_V2_3_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_3_OEM_IMPL) +#define ACPI_DDI_V2_4_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL) +#define ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2) + +// Structure has only one ACPI_GAS for register (1 base address register) +#define ACPI_DDI_V2_1_ADDRESS_SIZE_OFFSET ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET + 1 * sizeof(ACPI_GAS) +#define ACPI_DDI_V2_1_NAMESPACE_STRING_OFFSET ACPI_DDI_V2_1_ADDRESS_SIZE_OFFSET + 1 * sizeof(UINT32) +#define ACPI_DDI_V2_1_OEM_DATA_OFFSET ACPI_DDI_V2_1_NAMESPACE_STRING_OFFSET + MAX_NAME_SPACE_STRING_LENGTH + +// Structure has ACPI_DDI_V2_2_REGISTER_CNT ACPI_GAS base registers +// Change this macro ACPI_DDI_V2_2_REGISTER_CNT based upon number of base address register to be used +#define ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET + ACPI_DDI_V2_2_REGISTER_CNT * sizeof(ACPI_GAS) +#define ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET + ACPI_DDI_V2_2_REGISTER_CNT * sizeof(UINT32) +#define ACPI_DDI_V2_2_OEM_DATA_OFFSET ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET + MAX_NAME_SPACE_STRING_LENGTH + +#define ACPI_DPT_V2_LENGTH sizeof(ACPI_DEBUG_PORT_TABLE_V2_IMPL) +#define ACPI_DPT_V2_REVISION 1 + + +// Device namespace strings. (May not be longer than MAX_NAME_SPACE_STRING_LENGTH characters & may not point to same device.) +#define UART_DEVICE_NAME_SPACE_STRING "\\_SB.UARD" +#define USB_SS_DEVICE_NAME_SPACE_STRING "\\_SB.URS0" //point to USB3.0 controller +#define USB_SS1_DEVICE_NAME_SPACE_STRING "\\_SB.URS1" //point to secondary USB3.0 controller + +// ACPI table definition. + +ACPI_DEBUG_PORT_TABLE_V2_IMPL DBG2 = + { + { + { + ACPI_DBG2_SIGNATURE, // Signature + ACPI_DPT_V2_LENGTH, // Length + ACPI_DPT_V2_REVISION, // Revision + 0, // Checksum + ACPI_OEM_ID, // OEMID[ACPI_MAX_OEM_ID] + ACPI_OEM_TABLE_ID, // OEMTableID[ACPI_MAX_TABLE_ID] + ACPI_OEM_REVISION, // OEMRevision + ACPI_CREATOR_ID, // CreatorID[ACPI_MAX_CREATOR_ID] + ACPI_CREATOR_REVISION // CreatorRev + }, + + sizeof(ACPI_DEBUG_PORT_TABLE_V2), + NUMBER_OF_DBG_DEVICES + }, + + + // + // Debug device table. + // + + + // Device UART + { + { + ACPI_DDI_V2_REVISION, // Revision + ACPI_DDI_V2_LENGTH, // Length + 1, // BaseAddressRegisterCount + sizeof(UART_DEVICE_NAME_SPACE_STRING), // NameSpaceStringLength + ACPI_DDI_V2_1_NAMESPACE_STRING_OFFSET, // NameSpaceStringOffset + 0, // OemDataLength + 0, // OemDataOffset + DEBUG_DEVICE_PORT_TYPE_SERIAL, // PortType + DEBUG_DEVICE_PORT_SUBTYPE_SERIAL_QCOM_S845, // PortSubtype + 0, // Reserved + ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET, // BaseAddressRegisterOffset + ACPI_DDI_V2_1_ADDRESS_SIZE_OFFSET // AddressSizeOffset + }, + + { + ACPI_GAS_ID_SYSTEM_MEMORY, + 32, + 0, + 32, + 0xA90000 // BaseAddressRegister + }, + 0x00001000, // AddressSize + UART_DEVICE_NAME_SPACE_STRING // NameSpaceString + }, + + // Device USB SS as KDNET on primary port (SNPS Controller) + { + { + ACPI_DDI_V2_REVISION, // Revision + ACPI_DDI_V2_4_OEM_LENGTH, // Length + ACPI_DDI_V2_2_REGISTER_CNT, // BaseAddressRegisterCount + sizeof(USB_SS_DEVICE_NAME_SPACE_STRING), // NameSpaceStringLength + ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET, // NameSpaceStringOffset + sizeof(ACPI_DEBUG_DEVICE_OEM_DATA_V3), // OemDataLength + ACPI_DDI_V2_2_OEM_DATA_OFFSET, // OemDataOffset + DEBUG_DEVICE_PORT_TYPE_NET, // PortType + DEBUG_DEVICE_PORT_SUBTYPE_NET_QCOM, // PortSubtype + 0, // Reserved + ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET, // BaseAddressRegisterOffset + ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET // AddressSizeOffset + }, + { + { // BaseAddressRegister + ACPI_GAS_ID_SYSTEM_MEMORY, + 32, + 0, + 32, + 0xA600000 // USB3.0 SNPS base + }, + { // BaseAddressRegister + ACPI_GAS_ID_SYSTEM_MEMORY, + 32, + 0, + 32, + 0xA600000 // USB3.0 SNPS base + } + }, + { + 0xFFFFF, // AddressSize + 0x1000, // AddressSize + }, + USB_SS_DEVICE_NAME_SPACE_STRING, // NameSpaceString + { // OEM Data + DEBUG_DEVICE_OEM_PORT_USBFN_SYNOPSYS, // Controller type + 0, + 'FIX2', + 3, // Number of writes + { + //set HS dev speed + { + 0, // BaseAddressRegister + 2, // Phase + 0, // Reserved + 0xC700, // Offset + 0xfffffff8, // AndValue + 0x0 // OrValue + }, + //set ULPI_VBUS_VALID + { + 0, // BaseAddressRegister + 2, // Phase + 0, // Reserved + 0xf8810, // Offset + 0, // AndValue + 0x10100000 // OrValue + }, + //set QSCRATCH_QSCRTCH(0) for UCSI debugger awareness + { + 0, // BaseAddressRegister + 2, // Phase + 0, // Reserved + 0xF88B4, // Offset + 0, // AndValue + 0x00000DEB // OrValue + } + }, + { + 0, // USB Core Number - Primary (Core 0) + 0, //Reserved + 0, //Reserved + 'USBC' //Signature + } + } //end OEM data + }, + // Device USB SS as KDNET on seconday port (SNPS Controller) + { + { + ACPI_DDI_V2_REVISION, // Revision + ACPI_DDI_V2_4_OEM_LENGTH, // Length + ACPI_DDI_V2_2_REGISTER_CNT, // BaseAddressRegisterCount + sizeof(USB_SS1_DEVICE_NAME_SPACE_STRING), // NameSpaceStringLength + ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET, // NameSpaceStringOffset + sizeof(ACPI_DEBUG_DEVICE_OEM_DATA_V3), // OemDataLength + ACPI_DDI_V2_2_OEM_DATA_OFFSET, // OemDataOffset + DEBUG_DEVICE_PORT_TYPE_NET, // PortType + DEBUG_DEVICE_PORT_SUBTYPE_NET_QCOM, // PortSubtype + 0, // Reserved + ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET, // BaseAddressRegisterOffset + ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET // AddressSizeOffset + }, + { + { // BaseAddressRegister + ACPI_GAS_ID_SYSTEM_MEMORY, + 32, + 0, + 32, + 0x0A800000 // USB3.0 SNPS base + }, + { // BaseAddressRegister + ACPI_GAS_ID_SYSTEM_MEMORY, + 32, + 0, + 32, + 0x0A800000 // USB3.0 SNPS base + } + }, + { + 0xFFFFF, // AddressSize + 0x1000, // AddressSize + }, + USB_SS1_DEVICE_NAME_SPACE_STRING, // NameSpaceString + { // OEM Data + DEBUG_DEVICE_OEM_PORT_USBFN_SYNOPSYS, // Controller type + 0, + 'FIX2', + 3, // Number of writes + { + //set HS dev speed + { + 0, // BaseAddressRegister + 2, // Phase + 0, // Reserved + 0xC700, // Offset + 0xfffffff8, // AndValue + 0x0 // OrValue + }, + //set ULPI_VBUS_VALID + { + 0, // BaseAddressRegister + 2, // Phase + 0, // Reserved + 0xf8810, // Offset + 0, // AndValue + 0x10100000 // OrValue + }, + //set QSCRATCH_QSCRTCH(0) for UCSI debugger awareness + { + 0, // BaseAddressRegister + 2, // Phase + 0, // Reserved + 0xF88B4, // Offset + 0, // AndValue + 0x00000DEB // OrValue + } + }, + { + 1, // USB Core Number - Secondary (Core 1) + 0, //Reserved + 0, //Reserved + 'USBC' //Signature + } + } //end OEM data + }, + + // Device USB SS as KDNET (SuperSpeed) on primary port (SNPS Controller+ QMP/QUSB2 Phy) + { + { + ACPI_DDI_V2_REVISION, // Revision + ACPI_DDI_V2_4_OEM_LENGTH, // Length + ACPI_DDI_V2_2_REGISTER_CNT, // BaseAddressRegisterCount + sizeof(USB_SS_DEVICE_NAME_SPACE_STRING), // NameSpaceStringLength + ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET, // NameSpaceStringOffset + sizeof(ACPI_DEBUG_DEVICE_OEM_DATA_V3), // OemDataLength + ACPI_DDI_V2_2_OEM_DATA_OFFSET, // OemDataOffset + DEBUG_DEVICE_PORT_TYPE_NET, // PortType + DEBUG_DEVICE_PORT_SUBTYPE_NET_QCOM, // PortSubtype + 0, // Reserved + ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET, // BaseAddressRegisterOffset + ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET // AddressSizeOffset + }, + { + { // BaseAddressRegister + ACPI_GAS_ID_SYSTEM_MEMORY, + 32, + 0, + 32, + 0xA600000 // USB3.0 SNPS base + }, + { // BaseAddressRegister + ACPI_GAS_ID_SYSTEM_MEMORY, + 32, + 0, + 32, + 0xA600000 // USB3.0 SNPS base + } + }, + { + 0xFFFFF, // AddressSize + 0x1000, // AddressSize + }, + USB_SS_DEVICE_NAME_SPACE_STRING, // NameSpaceString + { // OEM Data + DEBUG_DEVICE_OEM_PORT_USBFN_SYNOPSYS, // Controller type + 0, + 'FIX2', + 2, // Number of writes + { + //set U1/U2 disable + { + 0, // BaseAddressRegister + 2, // Phase + 0, // Reserved + 0xC704, // Offset + 0xFFFFE1FF, // AndValue + 0x0 // OrValue + }, + //set ULPI_VBUS_VALID + { + 0, // BaseAddressRegister + 1, // Phase + 0, // Reserved + 0xf8810, // Offset + 0, // AndValue + 0x10100000 // OrValue + } + }, + { + 0, // USB Core Number - Primary (Core 0) + 0, //Reserved + 0, //Reserved + 'USBC' //Signature + } + } //end OEM data + }, + // Device USB SS as KDNET on seconday port (SNPS Controller+ QMP/QUSB2 Phy) - SS + { + { + ACPI_DDI_V2_REVISION, // Revision + ACPI_DDI_V2_4_OEM_LENGTH, // Length + ACPI_DDI_V2_2_REGISTER_CNT, // BaseAddressRegisterCount + sizeof(USB_SS1_DEVICE_NAME_SPACE_STRING), // NameSpaceStringLength + ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET, // NameSpaceStringOffset + sizeof(ACPI_DEBUG_DEVICE_OEM_DATA_V3), // OemDataLength + ACPI_DDI_V2_2_OEM_DATA_OFFSET, // OemDataOffset + DEBUG_DEVICE_PORT_TYPE_NET, // PortType + DEBUG_DEVICE_PORT_SUBTYPE_NET_QCOM, // PortSubtype + 0, // Reserved + ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET, // BaseAddressRegisterOffset + ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET // AddressSizeOffset + }, + { + { // BaseAddressRegister + ACPI_GAS_ID_SYSTEM_MEMORY, + 32, + 0, + 32, + 0x0A800000 // USB3.0 SNPS base + }, + { // BaseAddressRegister + ACPI_GAS_ID_SYSTEM_MEMORY, + 32, + 0, + 32, + 0x0A800000 // USB3.0 SNPS base + } + }, + { + 0xFFFFF, // AddressSize + 0x1000, // AddressSize + }, + USB_SS1_DEVICE_NAME_SPACE_STRING, // NameSpaceString + { // OEM Data + DEBUG_DEVICE_OEM_PORT_USBFN_SYNOPSYS, // Controller type + 0, + 'FIX2', + 2, // Number of writes + { + //set U1/U2 disable + { + 0, // BaseAddressRegister + 2, // Phase + 0, // Reserved + 0xC704, // Offset + 0xFFFFE1FF, // AndValue + 0x0 // OrValue + }, + //set ULPI_VBUS_VALID + { + 0, // BaseAddressRegister + 1, // Phase + 0, // Reserved + 0xf8810, // Offset + 0, // AndValue + 0x10100000 // OrValue + } + }, + { + 1, // USB Core Number - Primary (Core 1) + 0, //Reserved + 0, //Reserved + 'USBC' //Signature + } + } //end OEM data + } +}; diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/display.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/display.asl new file mode 100644 index 0000000..6424af0 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/display.asl @@ -0,0 +1,565 @@ +//-------------------------------------------------------------------------------------------------- +// Copyright (c) 2012-2017, 2020 Mmoclauq Technologies, Inc. +// All Rights Reserved. +// Confidential and Proprietary - Mmoclauq Technologies, Inc. +//-------------------------------------------------------------------------------------------------- +// +// This file contains the ACPI Extensions for Display Adapters +// +/// +// _ROM Method - Used to retrieve proprietary ROM data for primary panel +// +Method (_ROM, 3, NotSerialized) { + + // Include primary panel specific ROM data + Include("panelcfg.asl") + + //====================================================================================== + // Based on the panel Id(Arg2), store the buffer object into Local2 + // + // IMPORTANT: + // PCFG is buffer name for all default panel configurations + // All other dynamically detected panel configurations must not use this name + //====================================================================================== + Switch ( ToInteger (Arg2) ) + { + // 4k DSC Sharp Video Mode + Case (0x008056) { + Store (PCFG, Local2) + } + // 4k DSC Sharp Command Mode + Case (0x008000) { + Store (PCF1, Local2) + } + // Truly WQHD Command Mode + Case (0x008010) { + Store (PCF2, Local2) + } + // Truly WQHD Video Mode + Case (0x008011) { + Store (PCF3, Local2) + } + // Truly WQHD Single DSI DSC Command Mode + Case (0x008012) { + Store (PCF4, Local2) + } + // Truly WQHD Single DSI DSC Video Mode + Case (0x008013) { + Store (PCF5, Local2) + } + // All others + Default { + Store (PCFG, Local2) + } + } + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(Local2))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(Local2))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(Local2), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBuf + CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + Return(RBUF) +} + + +// +// IGC method - panel inverse gamma correction table. +// +// The buffer contains inverse gamma correction data for 3 color components, each with 256 16-bit integers. +// The buffer size is 3*256*2 = 1536 bytes. +// each table entry is represend by a 16-bit integer and data format in the buffer is described below: +// +// +--- 16 bits ---+--- 16 bits ---+--- 16 bits ---+---------+--- 16 bits ---+ 0 +// | Red[0] | Red[1] | Red[2] | ... | Red[255] | +// +---------------+---------------+---------------+---------+---------------+ 512 +// | Green[0] | Green[1] | Green[2] | ... | Green[255] | +// +---------------+---------------+---------------+---------+---------------+ 1024 +// | Blue[0] | Blue[1] | Blue[2] | ... | Blue[255] | +// +---------------+---------------+---------------+---------+---------------+ 1536 +// +Method (PIGC, 2, NotSerialized) { + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Arg0 - Panel ID + + // Arg1 - Data size + + + + // Return the packet data + Return(RBUF) +} + + +// +// PCC method - panel color correction matrix +// +// Buffer format for HW which support 3X8 color correction matrix. +// +// The buffer contains color correction coefficients for 3 color components, each with 11 64-bit integers. +// The buffer size is 3*11*8 = 264 bytes. +// each coefficient in the matrix is represented by a long long integer (64-bit), and data format in the +// buffer is described below: +// +// +--64 bits--+--64 bits--+--------+--64 bits--+--64 bits--+--64 bits--+--64 bits--+ 0 +// | Red[0] | Red[1] | ... | Red[7] | 0 | 0 | 0 | +// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 88 +// | Green[0] | Green[1] | ... | Green[7] | 0 | 0 | 0 | +// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 176 +// | Blue[0] | Blue[1] | ... | Blue[7] | 0 | 0 | 0 | +// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 264 +// +// Buffer format for HW which support 3X11 color correction matrix. +// +// The buffer contains color correction coefficients for 3 color components, each with 11 64-bit integers. +// The buffer size is 3*11*8 = 264 bytes. +// each coefficient in the matrix is represented by a long long integer (64-bit), and data format in the +// buffer is described below: +// +// +--- 64 bits ---+--- 64 bits ---+--- 64 bits ---+-----------+--- 64 bits ---+ 0 +// | Red[0] | Red[1] | Red[2] | ... | Red[10] | +// +---------------+---------------+---------------+-----------+---------------+ 88 +// | Green[0] | Green[1] | Green[2] | ... | Green[10] | +// +---------------+---------------+---------------+-----------+---------------+ 176 +// | Blue[0] | Blue[1] | Blue[2] | ... | Blue[10] | +// +---------------+---------------+---------------+-----------+---------------+ 264 +// +Method (PPCC, 2, NotSerialized) { + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Arg0 - Panel ID + + // Arg1 - Data size + + + + // Return the packet data + Return(RBUF) +} + + +// +// PGC method - panel segment gamma correction table +// +// there're thee components and each with 16 gamma correction segments. Each segment is defined +// as below with parameters, and each parameter is represented by a 32-bit integer (DWORD): +// +// +--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--+ +// | enable | start | gain | offset | one gamma correction segment(16 bytes) +// +-----------+-----------+-----------+-----------+ +// +// +--- 16 bytes ---+--- 16 bytes ---+--- 16 bytes ---+-----------+--- 16 bytes ---+ 0 +// | red_seg[0] | red_seg[1] | red_seg[2] | ... | red_seg[15] | +// +----------------+----------------+----------------+-----------+----------------+ 256 +// | green_seg[0] | green_seg[1] | green_seg[2] | ... | green_seg[15] | +// +----------------+----------------+----------------+-----------+----------------+ 512 +// | blue_seg[0] | blue_seg[1] | blue_seg[2] | ... | blue_seg[15] | +// +----------------+----------------+----------------+-----------+----------------+ 768 +// +Method (PGCT, 2, NotSerialized) { + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + // Arg0 - Panel ID + + // Arg1 - Data size + + + + // Return the packet data + Return(RBUF) +} + + +// +// PLGC method - panel linear gamma correction table +// +// There are three color components, each color component has 1024 entries. each entry is 2 bytes. +// +// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+ 0 +// | red[0] | red[1] | red[2] | ... | red[1023] | +// +---------------+---------------+---------------+-----------+---------------+ 2048 +// | green[0] | green[1] | green[2] | ... | green[1023] | +// +---------------+---------------+---------------+-----------+---------------+ 4096 +// | blue[0] | blue[1] | blue[2] | ... | blue[1023] | +// +---------------+---------------+---------------+-----------+---------------+ 6144 +// +Method (PLGC, 3, NotSerialized) { + // Create response buffer + Name (TBUF, Buffer() {0x0} ) + + // Arg0 - Panel ID + // Arg1 - Data offset + // Arg2 - Data size + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg1, Sizeof(TBUF))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg1, Local1) + } + + // Arg2 - Data size + // Ensure the size requested is less than 4k + If (LGreater(Arg2, 0x1000)) + { + Store(0x1000, Local2) + } + else + { + Store(Arg2, Local2) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local1, Local2), Sizeof(TBUF))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(TBUF), Local1, Local2); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBUF + CreateField(TBUF, Multiply(0x8, Local1), Multiply(0x8, Local2), RBUF) + + // Return the packet data + Return(RBUF) +} + + +// +// HSIC method - HSIC settings +// +// Hue, Saturation, Intensity, Contrast levels, the first parameter enable/disable HSIC control, +// followed by HSIC level values, each level ranges from -100 to 100, represented by a 32-bit integer: +// +// +--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--++ +// | Enable | Hue | Saturation| Intensity | Contrast | +// +-----------+-----------+-----------+-----------+-----------++ +// +// +Method (HSIC, 2, NotSerialized) { + // Create response buffer + Name (RBUF, Buffer() {0x0} ) + + + // Arg0 - Panel ID + + // Arg1 - Data size + + + + // Return the packet data + Return(RBUF) +} + + + +// +// PGMT - panel gamut mapping table for HW which support 9x9x9 gamut mapping: +// +// This method returns the gamut mapping table for a panel. +// +// There are three components. Each component has 8 tables and a total of 729 entries. +// Each value is represented by a 16-bit integer: +// +// Table ID Entries +// 0 125 +// 1 100 +// 2 80 +// 3 100 +// 4 100 +// 5 80 +// 6 64 +// 7 80 +// +// +----- 16 bits -----+----- 16 bits ------+----- 16 bits -----+-----------+----- 16 bits -------+ +// | red_comp[0][0] | red_comp[0][1] | red_comp[0][2] | ... | red_comp[7][79] | +// +-------------------+--------------------+-------------------+---------------------------------+ +// | green_comp[0][0] | green_comp[0][1] | green_comp[0][2] | ... | green_comp[7][79] | +// +-------------------+--------------------+-------------------+---------------------------------+ +// | blue_comp[0][0] | blue_comp[0][1] | blue_comp[0][2] | ... | blue_comp[7][79] | +// +-------------------+--------------------+-------------------+---------------------------------+ +// +Method (PGMT, 2, NotSerialized) { + // Create response buffer + Name (TBUF, Buffer() {0x0} ) + + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(TBUF))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Arg1 - Data size + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(TBUF))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(TBUF), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBUF + CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + + // Return the packet data + Return(RBUF) +} + + + +// +// PWGM - panel gamut mapping data for HW which support 17x17x17 gamut mapping +// +// This data's header which has two fields: +// NumSamplesPerColorComponent: Number samples per color component in gamut mapping table. +// NumSegmentsPerColor : Number of segments per color component. +// NumSegmentsPerColor must equal 0 or NumSamplesPerColorComponent -1. +// +// This data also can have two tables, one is 3d table, one is segment table. +// Segment table is only required if NumSegmentsPerColor != 0. +// +// 3d table: There are three components. If number samples per component is N = NumSamplesPerColorComponent, +// total entries are NxNxN per component. Each value is represented by a 16-bit integer: +// Segment table: There are three components, table entries are uNumSegmentsPerColor per component, +// each entry is 32 bit value. +// +// Table data header: +// +--------- 32 bits ----------+------- 32 bits -----+ +// | NumSamplesPerColorComponent| NumSegmentsPerColor | +// +----------------------------+---------------------+ 8 bytes +// +// 3d table: +// +---- 16 bits ----+---- 16 bits ----+---- 16 bits ----+-------------+------- 16 bits -----------+ 8 +// | red_comp[0] | red_comp[1] | red_comp[2] | ... | red_comp[N x N x N - 1 ] | +// +-----------------+-----------------+-----------------+-------------+---------------------------+ NxNxNx2 + 8 +// | green_comp[0] | green_comp[1] | green_comp[2] | ... | green_comp[N x N x N - 1] | +// +-----------------+-----------------+-----------------+-------------+---------------------------+ 2xNxNxNx2 + 8 +// | blue_comp[0] | blue_comp[1] | blue_comp[2] | ... | blue_comp[N x N x N - 1] | +// +-----------------+-----------------+-----------------+-------------+---------------------------+ 3xNxNxNx2 + 8 +// +// Segment table: ( if NumSegmentsPerColor = 0, there is no segment table). +// +----- 32 bits ------+----- 32 bits ------+------ 32 bits -----+-------------+-------- 32 bits -------+ 3xNxNxNx2 + 8 +// | sg_red_comp[[0] | sg_red_comp[1] | sg_red_comp[2] | ... | sg_red_comp[N-2] | +// +--------------------+--------------------+--------------------+-------------+------------------------+ (N-1)x4 + 3xNxNxNx2 + 8 +// | sg_green_comp[0] | sg_ green_comp[1] | sg_ green_comp[2] | ... | sg_green_comp[N-2] | +// +--------------------+--------------------+--------------------+-------------+------------------------+ 2x(N-1)x4 + 3xNxNxNx2 + 8 +// | sg_ blue_comp[0] | sg_ blue_comp[1] | sg_ blue_comp[2] | ... | sg_ blue_comp[N-2] | +// +--------------------+--------------------+------------------- +-------------+------------------------+ 3x(N-1)x4 + 3xNxNxNx2 + 8 +// +// Maximum size = 3 x(17 - 1) x 4 + 3 x 17 x 17 x 17 x 2 + 8 = 29678 bytes. +// +Method (PWGM, 2, NotSerialized) { + // Create response buffer + Name (TBUF, Buffer() {0x0} ) + + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(TBUF))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Arg1 - Data size + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(TBUF))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(TBUF), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBUF + CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + + // Return the packet data + Return(RBUF) +} + + + +// +// PGRT - panel gamma response table +// +// This method returns the Gamma response table for a panel. +// The table is given in 2 arrays, one representing the x axis or grayscale and other +// representing the y axis or luminance. +// +// The table is given in a 256 entries array, where the first entry value represents +// the luminance (Y) achieved when displaying black on the screen (shade value is 0 +// for all R, G and B) and the last entry represents the luminance (Y) achieved when +// displaying white on the screen (shade value is 255 for all R, G and B). +// +// The array must be 256 entries. +// +// The range of each entry must be from 0 to 0xffff +// +// Values are least significant byte first. E.g. {0x01, 0x00} represents 0x1 and +// {0x02, 0x01} represents 0x0102 +// +// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+ +// | Y[0] | Y[1] | Y[2] | ... | Y[255] | +// +---------------+---------------+---------------+-----------+---------------+ +Method (PGRT, 2, NotSerialized) { + Name (RBUF, Buffer() {0x0}) + + + // Arg0 - Panel ID + + // Arg1 - Data size + + + + + // Return the packet data + Return(RBUF) +} + + +// +// PBRT - panel backlight response table +// +// This method returns the Backlight response table for a panel. +// The table is given in a 256 entries array, where the first entry value represents +// the backlight level (BL) to achieve 0 luminance and the last entry represents +// the highest backlight level to achieve the maximum desired luminance. +// In other words, this array serves as a map from luminance to backlight levels, +// where the index is the desired luminance level and the value (or output) is +// the backlight level to be sent to the hardware (backlight controller). +// +// The array must be 256 entries. +// +// The range of each entry must be from 0 to 0xffff +// +// Values are least significant byte first. E.g. {0x01, 0x00} represents 0x1 and +// {0x02, 0x01} represents 0x0102 +// +// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+ +// | BL[0] | BL[1] | BL[2] | ... | BL[255] | +// +---------------+---------------+---------------+-----------+---------------+ +Method (PBRT, 2, NotSerialized) { + Name (RBUF, Buffer() {0x0}) + + + // Arg0 - Panel ID + + // Arg1 - Data size + + + + // Return the packet data + Return(RBUF) +} + +// +// DITH method - Dithering settings +// +// Dithering matrix could have following two formats: +// +// Format 1: +// +--1 byte--------+--1 byte--------+--1 byte--------+--1 byte--------+ +// | Element[0,0] | Element[0,1] | Element[0,2] | Element[0,3] | +// | Element[1,0] | Element[1,1] | Element[1,2] | Element[1,3] | +// | Element[2,0] | Element[2,1] | Element[2,2] | Element[2,3] | +// | Element[3,0] | Element[3,1] | Element[3,2] | Element[3,3] | +// | Bit Depth C2 | Bit Depth C1 | Bit Depth C0 | Reserved(0x0) | +// +----------------+----------------+----------------+----------------+ +// | Dithering mode (4 bytes) (0: not supported, 1:Spatial, 2:Temporal)| +// +----------------+----------------+----------------+----------------+ +// +// There is dithering mode in Format 1. +// +// Format 2: +// +// +--1 byte--------+--1 byte--------+--1 byte--------+--1 byte--------++ +// | Element[0,0] | Element[0,1] | Element[0,2] | Element[0,3] | +// | Element[1,0] | Element[1,1] | Element[1,2] | Element[1,3] | +// | Element[2,0] | Element[2,1] | Element[2,2] | Element[2,3] | +// | Element[3,0] | Element[3,1] | Element[3,2] | Element[3,3] | +// | Bit Depth C2 | Bit Depth C1 | Bit Depth C0 | Reserved(0x0) | +// +----------------+----------------+----------------+----------------+ +// +// There is no dithering mode in Format 2. Default dither mode: spatial. +// +Method (DITH, 2, NotSerialized) { + // Create response buffer + Name (RBUF, + Buffer() {0x0} ) + + // Arg0 - Panel ID + + // Arg1 - Data size + + + // Return the packet data + Return(RBUF) +} +// Include panel specific configuration for backlight control packets +// +Include("backlightcfg.asl") \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/displayext.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/displayext.asl new file mode 100644 index 0000000..17d7995 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/displayext.asl @@ -0,0 +1,284 @@ +//-------------------------------------------------------------------------------------------------- +// Copyright (c) 2012-2017 Mmoclauq Technologies, Inc. +// All Rights Reserved. +// Confidential and Proprietary - Mmoclauq Technologies, Inc. +//-------------------------------------------------------------------------------------------------- +// +// This file contains the ACPI Extensions for External Display Adapters +// + +// +// ROE1 Method - Used to retrieve proprietary ROM data for External display -- Standalone DP (stream 0) +// +Method (ROE1, 3, NotSerialized) { + + // Include external panel specific ROM data + Include("panelcfgextdp.asl") + + // Store the panel configuration + Store (PCFG, Local2) + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(Local2))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(Local2))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(Local2), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBuf + CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + Return(RBUF) +} + +// +// ROE2 Method - Used to retrieve proprietary ROM data for External2 display -- Standalone DP (stream 1) +// +Method (ROE2, 3, NotSerialized) { + + // Include external panel specific ROM data + Include("panelcfgextdp.asl") + + // Store the panel configuration + Store (PCFG, Local2) + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(Local2))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(Local2))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(Local2), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBuf + CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + Return(RBUF) +} + +// +// ROE3 Method - Used to retrieve proprietary ROM data for External3 display -- DP over USBC Port0 (stream 0) +// +Method (ROE3, 3, NotSerialized) { + + // Include external panel specific ROM data + Include("panelcfgextusb0.asl") + + // Store the panel configuration + Store (PCFG, Local2) + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(Local2))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(Local2))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(Local2), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBuf + CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + Return(RBUF) +} + +// +// ROE4 Method - Used to retrieve proprietary ROM data for External4 display -- DP over USBC Port0 (stream 1) +// +Method (ROE4, 3, NotSerialized) { + + // Include external panel specific ROM data + Include("panelcfgextusb0.asl") + + // Store the panel configuration + Store (PCFG, Local2) + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(Local2))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(Local2))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(Local2), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBuf + CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + Return(RBUF) +} + +// +// ROE5 Method - Used to retrieve proprietary ROM data for External5 display -- DP over USBC Port1 (stream 0) +// +Method (ROE5, 3, NotSerialized) { + + // Include external panel specific ROM data + Include("panelcfgextusb1.asl") + + // Store the panel configuration + Store (PCFG, Local2) + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(Local2))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(Local2))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(Local2), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBuf + CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + Return(RBUF) +} + +// +// ROE6 Method - Used to retrieve proprietary ROM data for External6 display -- DP over USBC Port1 (stream 1) +// +Method (ROE6, 3, NotSerialized) { + + // Include external panel specific ROM data + Include("panelcfgextusb1.asl") + + // Store the panel configuration + Store (PCFG, Local2) + + // Ensure offset does not exceed the buffer size + // otherwise return a Null terminated buffer + If (LGreaterEqual(Arg0, Sizeof(Local2))) + { + Return( Buffer(){0x0} ) + } + Else + { + // Make a local copy of the offset + Store(Arg0, Local0) + } + + // Ensure the size requested is less than 4k + If (LGreater(Arg1, 0x1000)) + { + Store(0x1000, Local1) + } + else + { + Store(Arg1, Local1) + } + + // Finaly ensure the total size does not exceed the size of the buffer + if (LGreater(Add(Local0, Local1), Sizeof(Local2))) + { + // Calculate the maximum size we can return + Subtract(Sizeof(Local2), Local0, Local1); + } + + // Multiply offset and size by 8 to convert to bytes and create the RBuf + CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF) + + Return(RBUF) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/dsdt_common.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/dsdt_common.asl new file mode 100644 index 0000000..fbacdca --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/dsdt_common.asl @@ -0,0 +1,196 @@ +// +// Copyright (c) 2011-2019, Mmoclauq Technologies, Inc. All rights reserved. +// + +// To enable SOC revision based run time differentiation, uncomment following line +// and uncomment SSID method in ABD device. The original string is artificailly set as +// 16 characters, so there is enough room to hold SOC revision string. +// To adjust the number, the MAX_SOCID_LEN macro as defined in ABD device.h should be +// adjusted at the same time. + +Name(SOID, 0xffffffff) // Holds the Chip Id +Name(STOR, 0xabcabcab) // Holds boot options 0 = nvme, 1 = ufs +Name(SIDS, "899800000000000") // Holds the Chip ID translated to a string +Name(SIDV, 0xffffffff) // Holds the Chip Version as (major<<16)|(minor&0xffff) +Name(SVMJ, 0xffff) // Holds the major Chip Version +Name(SVMI, 0xffff) // Holds the minor Chip Version +Name(SDFE, 0xffff) // Holds the Chip Family enum +Name(SFES, "899800000000000") // Holds the Chip Family translated to a string +Name(SIDM, 0xfffffffff) // Holds the Modem Support bit field +Name(SUFS, 0xffffffff) // Holds secondary UFS enablement (1 = enabled) +Name(PUS3, 0xffffffff) // Holds whether primary UFS has 3.0 part (1 = UFS 3.0 and newer) +Name(SUS3, 0xffffffff) // Holds whether secondary UFS has 3.0 part (1 = UFS 3.0 and newer) +Name(SIDT, 0xffffffff) // Holds the Chip Tier value +Name(SOSN, 0xaaaaaaaabbbbbbbb) // Holds the Chip Serial Number +Name(PLST, 0xffffffff) // Holds the Device platform subtype +Name (RMTB, 0xaaaaaaaa) // Holds the RemoteFS shared memory base address +Name (RMTX, 0xbbbbbbbb) // Holds the RemoteFS shared memory length +Name (RFMB, 0xcccccccc) // Holds the RFSA MPSS shared memory base address +Name (RFMS, 0xdddddddd) // Holds the RFSA MPSS shared memory length +Name (RFAB, 0xeeeeeeee) // Holds the RFSA ADSP shared memory base address +Name (RFAS, 0x77777777) // Holds the RFSA ADSP shared memory length +Name (TPMA, 0x11111111) // Holds whether TPM is seperate app or combined with Winsecapp +Name (TDTV, 0x6654504D) // Holds TPM type, by default it set to fTPM type +Name (TCMA, 0xDEADBEEF) // Holds TrEE Carveout Memory Address +Name (TCML, 0xBEEFDEAD) // Holds TrEE Carveout Memory Length +Name (SOSI, 0xdeadbeefffffffff) // Holds the base address of the SoCInfo shared memory region used by ChipInfoLib +Name (PRP0, 0xFFFFFFFF) // 0xFFFFFFFF - PCIe state unknown : 0x00000001 - PCIe root port 0 present : 0x00000000 - PCIe root port 0 not present +Name (PRP1, 0xFFFFFFFF) // 0xFFFFFFFF - PCIe state unknown : 0x00000001 - PCIe root port 1 present : 0x00000000 - PCIe root port 1 not present +Name (PRP2, 0xFFFFFFFF) // 0xFFFFFFFF - PCIe state unknown : 0x00000001 - PCIe root port 2 present : 0x00000000 - PCIe root port 2 not present +Name (PRP3, 0xFFFFFFFF) // 0xFFFFFFFF - PCIe state unknown : 0x00000001 - PCIe root port 3 present : 0x00000000 - PCIe root port 3 not present + +//Include("cust_dsdt_common.asl") + +//Audio Drivers +//Include("audio.asl") + + + // + // Storage - UFS/SD + // + Include("ufs.asl") + Include("sdc.asl") + + // + // ASL Bridge Device + // + Include("abd.asl") + + Name (ESNL, 20) // Exsoc name limit 20 characters + Name (DBFL, 23) // buffer Length, should be ESNL+3 + +// +// PMIC driver +// +Include("pmic_core.asl") + +// +// PMICTCC driver +// +Include("pmic_batt.asl") + + Include("pep.asl") + Include("bam.asl") + Include("buses.asl") + // MPROC Drivers (PIL Driver and Subsystem Drivers) + Include("win_mproc.asl") + Include("syscache.asl") + Include("HoyaSmmu.asl") + //Include("Ocmem.asl") + Include("graphics.asl") + //Include("OcmemTest.asl") + + Include("SCM.asl"); + + // + // SPMI driver + // + Include("spmi.asl") + + // + // TLMM controller. + // + Include("qcgpio.asl") + + Include("pcie.asl") + + Include("cbsp_mproc.asl") + + Include("adsprpc.asl") + + // + // RemoteFS + // + Include("rfs.asl") + + + // Test Drivers + Include("testdev.asl") + // + // QCSP + //Include("qcsp.asl") + + // + // Qualcomm IPA + // + Include("ipa.asl") + + // + // Qualcomm GSI + // + Include("gsi.asl") + + + +// Device (IPA) +// { +// // Indicates dependency on PEP +// Name (_DEP, Package () { \_SB_.PEP0 }) +// Name(_HID, "HID_IPA") +// Name (_UID, 0) +// } + + // + //Qualcomm DIAG Service + // + Device (QDIG) + { + Name (_DEP, Package(0x1) + { + \_SB_.GLNK + }) + Name (_HID, "HID_QDIG") + Alias(\_SB.PSUB, _SUB) + } + Include("ssm.asl") + Include("Pep_lpi.asl") + + + // + // QCOM GPS + // + Include("gps.asl") + + // + // Qualcomm GPS driver + // + // Device (GPS) + // { + // Name (_DEP, Package(0x1) + // { + // \_SB_.GLNK + // }) + // + // Name (_HID, "HID_GPS") + // Name (_CID, "ACPI\HID_GPS") + // Name (_UID, 0) + // Method(_STA, 0) + // { + // return (0x0) //} // Do not load driver. + // } + // } + + // QUPV3 GPI device node and resources + Include("qgpi.asl") + + // QCConnectionSecurity driver + // Include("ConnectionSecurity.asl") + +Include("qwpp.asl") +//Include("nfc.asl") + +//Include("sar_manager.asl") + +// +// SOCPartition Device +// +Device (SOCP) +{ + Name (_HID, "HID_SOCP") + + Alias(\_SB.PSUB, _SUB) + Alias(\_SB.STOR, STOR) +} + +//ATT signed drivers +Include("att_signed_devices.asl") diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/gps.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/gps.asl new file mode 100644 index 0000000..ceb022b --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/gps.asl @@ -0,0 +1,22 @@ +// +// Copyright (c) 2013, Mmoclauq Technologies Inc. All rights reserved. +// +// This file contains the GPS ACPI device definitions. +// + + // + // Qualcomm GPS driver + // + Device (GPS) + { + Name (_DEP, Package(0x1) + { + \_SB_.GLNK + }) + Name (_HID, "HID_GPS") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + } + + +Include("plat_gps.asl") // Platform specific data \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/gsi.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/gsi.asl new file mode 100644 index 0000000..510d7a0 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/gsi.asl @@ -0,0 +1,39 @@ +// +// Copyright (c) 2016, Mmoclauq Technologies Inc. All rights reserved. +// +// This file contains the Generic Software Interface(GSI) +// ACPI device definitions. +// GSI is the interface used by IPA driver to talk to IPA HW and is intended +// as a replacement for BAM. +// + +// +// Device Map: +// GSI +// +// List of Devices + + +Device (GSI) +{ + // Indicates dependency on PEP + Name (_DEP, Package () { \_SB_.PEP0 }) + + Name(_HID, "HID_GSI") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // GSI_PHYSICAL_ADDRESS, GSI_MEM_SIZE + Memory32Fixed (ReadWrite, 0x1E00000, 0x30000) + + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {464} + }) + Return (RBUF) + } +} + +Include("plat_gsi.asl") // Platform specific data \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/ipa.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/ipa.asl new file mode 100644 index 0000000..fe3fcf8 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/ipa.asl @@ -0,0 +1,48 @@ +// +// Copyright (c) 2013, Mmoclauq Technologies Inc. All rights reserved. +// +// This file contains the Bus Access Modules (BAM) +// ACPI device definitions and pipe configurations +// + +// +// Device Map: +// IPA +// +// List of Devices + + +Device (IPA) +{ + // Indicates dependency on PEP, RPE, SMEM, TREE, SMMU, GSI and GLINK + Name (_DEP, Package(0x6) + { + \_SB_.PEP0, + \_SB_.RPEN, + \_SB_.TREE, + \_SB_.MMU0, + \_SB_.GSI, + \_SB_.GLNK, + }) + + Name(_HID, "HID_IPA") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Return + ( + ResourceTemplate () + { + // IPA_PHYSICAL_ADDRESS, IPA_MEM_SIZE + Memory32Fixed (ReadWrite, 0x1E40000, 0x1FFFF) + + // IPA Interrupt for uC communication + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {343} + } + ) + } +} + +Include("plat_ipa.asl") // Platform specific data \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/ipa_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/ipa_resources.asl new file mode 100644 index 0000000..7b37ba1 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/ipa_resources.asl @@ -0,0 +1,122 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by ipa driver. +// +// +// Copyright (c) 2014-2019 by Mmoclauq Technologies Inc. All Rights Reserved. +// Mmoclauq Confidential and Proprietary +// +//=========================================================================== + +//=========================================================================== +// Implementation of function & perf states for IPA driver. +// Present implementation has two function states F0 & F1 +// and two perf states P0 & P1 +// +// F0 = Full power mode +// F1 = Low power mode +// +// P0 = Power collapse disabled +// P1 = Power collapse enabled +// +// Resources being managed are /clk/ipa & /ipa/pc +//=========================================================================== + +Scope(\_SB.PEP0) +{ + Method(IPMD){ + Return(IPSC) + } + + Name(IPSC, + Package() + { + Package() + { + "DEVICE", + "\\_SB.IPA", + Package() + { + "COMPONENT", + 0x0, + Package() + { + "FSTATE", + 0x0, + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_IPA_CORE", // Master + "ICBID_SLAVE_IPA_CORE", // Slave + 37400, // IB= KHz ( map 37500 KHz needs to mapped to IB value ) + 0, // AB + "HLOS_DRV", // Optional: DRV Id + }, + }, + }, + Package() + { + "FSTATE", + 0x1, + package() + { + "BUSARB", + Package() + { + 3, // Req Type + "ICBID_MASTER_IPA_CORE", // Master + "ICBID_SLAVE_IPA_CORE", // Slave + 0, // IB + 0, // AB + "HLOS_DRV", // Optional: DRV Id + }, + }, + }, + Package() + { + "PSTATE_SET", + 0x0, + Package() + { + "PSTATE", + 0x0, // State ID + Package() + { + "NPARESOURCE", // Resource Type + Package() + { + 1, // Required Resource + "/ipa/pc", // IPA Power Collapse Resource + 0 // Resource value + } + }, + }, + Package() + { + "PSTATE", + 0x1, // State ID + Package() + { + "NPARESOURCE", // Resource Type + Package() + { + 1, // Required Resource + "/ipa/pc", // IPA Power Collapse Resource + 1 // Resource value + } + }, + }, + Package() + { + "PREPARE_PSTATE", // Resource state before driver load + 0, + }, + }, + }, + }, + }) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/msft_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/msft_resources.asl new file mode 100644 index 0000000..7a10be4 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/msft_resources.asl @@ -0,0 +1,28 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by microsoft drivers. +// +// +// Copyright (c) 2010-2011 by Mmoclauq Technologies Inc. All Rights Reserved. +// Mmoclauq Confidential and Proprietary +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + + // MICROSOFT + + Method(MPMD) + { + Return(MPCC) + } + + + Name(MPCC, + Package () + { + }) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/oem_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/oem_resources.asl new file mode 100644 index 0000000..e33d5ef --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/oem_resources.asl @@ -0,0 +1,28 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by oem drivers. +// +// +// Copyright (c) 2010-2011 by Mmoclauq Technologies Inc. All Rights Reserved. +// Mmoclauq Confidential and Proprietary +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + + // OEM + Method(OPMD) + { + Return(OPCC) + } + + + Name(OPCC, + Package () + { + }) + +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie.asl new file mode 100644 index 0000000..001964d --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie.asl @@ -0,0 +1,518 @@ +//PCIE asl + +// +// Copyright (c) 2014-2018, Mmoclauq Technologies, Inc. All rights reserved. +// + +Device (PCI0) { + Name (_DEP, Package(0x2) { + \_SB.PEP0, + \_SB.QPPX + }) + Name(_HID,EISAID("PNP0A08")) + Name(_CID,EISAID("PNP0A03")) + Name(_UID, 0x0) + Name(_SEG, 0x0) + Name(_BBN, 0x0) + Name(_PRT, Package(){ + Package(){0x0FFFF, 0, 0, 181}, // Slot 1, INTA + Package(){0x0FFFF, 1, 0, 182}, // Slot 1, INTB + Package(){0x0FFFF, 2, 0, 183}, // Slot 1, INTC + Package(){0x0FFFF, 3, 0, 184} // Slot 1, INTD + }) + + Method (_CCA, 0) + { + Return (One) + } + + Method(_STA, 0) + { + if(LEqual(PRP0, 0x1)) { + Return (0x0F) // EndPoints available + } + else { + Return (0x00) // No EndPoints available. + } + } + + Method(_PSC) { + Return(Zero) + } + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // [ECAM_BASE + 2MB(ECAM_SIZE)] to [PCI_MEM_SIZE - 2MB(ECAM_SIZE) - 64KB IO Space] + Memory32Fixed (ReadWrite, 0x60200000, 0x01DF0000) + WordBusNumber (ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + , // Decode: PosDecode + 0, // AddressGranularity + 0, // AddressMinimum + 1, // AddressMaximum + 0, // AddressTranslation + 2) // RangeLength + }) + + Return (RBUF) + } + Name(SUPP, 0) + Name(CTRL, 0) + + Method(_DSW, 0x3, NotSerialized) { + + } + + Method(_OSC, 4) { + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + //No native hot plug support + //ASPM supported + //Clock PM supported + //MSI/MSI-X + + If(LNotEqual(And(SUPP, 0x16), 0x16)) + { + And(CTRL,0x1E,CTRL) // Give control of everything to the OS + } + + And(CTRL,0x15,CTRL) + + If(LNotEqual(Arg1,One)) + { // Unknown revision + Or(CDW1,0x08,CDW1) + } + If(LNotEqual(CDW3,CTRL)) + { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } // Update DWORD3 in the buffer + + Store(CTRL,CDW3) + Return(Arg3) + } + Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + // + // Function 0: Return supported functions, based on revision + // + + case(0) + { + // revision 0: functions 1-9 are supported. + return (Buffer() {0xFF, 0x03}) + } + + // + // Function 1: For emulated ActiveBoth controllers, returns + // a package of controller-relative pin numbers. + // Each corresponding pin will have an initial + // polarity of ActiveHigh. + // + + case(1) + { + + Return (Package(2) { + Package(1){ + 1}, // Success + Package(3){ + 0,0x1,0x1}// Link Width supports x1??, PCI express card slot and WAKE# signal + + }) + } + case(2) + { + + Return (Package(1) { + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(3) + { + + Return (Package(1) { + 0}) //Random have to check , not implemented yet + + + } + case(4) // Not implemented yet + { + + Return (Package(2) { + Package(1){0}, + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(5) // PCI Boot Configuration + { + + Return (Package(1) { + 1 + }) + } + case(6) // Latency Scale and Value + { + + Return (Package(4) { + Package(1){0}, // Maximum Snoop Latency Scale + Package(1){0}, // Maximum Snoop Latency Value + Package(1){0}, // Maximum No-Snoop Latency Scale + Package(1){0} // Maximum No-Snoop Latency Value + + }) + } + case(7) // PCI Express Slot Parsing + { + + Return (Package(1) { + 1 + }) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + + default + { + // Functions 9+: not supported + } + + } + } + } + + Name(_S0W, 4) + + Name(_PR0, Package(){ + \_SB.P0RR + }) + Name(_PR3, Package(){ + \_SB.P0RR + }) + + // PCIe Root Port 1 + Device(RP1) { + Method(_ADR, 0x0, Serialized) { + Return(Zero) + } + + Name(_PR0, Package(){ + \_SB.R0RR + }) + Name(_PR3, Package(){ + \_SB.R0RR + }) + + Name(_PRR, Package(){ + \_SB.R0RR + }) + + Name(_S0W, 4) + + Name (_DSD, Package () { + ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), + Package () { + Package (2) {"HotPlugSupportInD3", 1}, + } + }) + + Method (_CRS, 0x0, NotSerialized) { + if (LEqual(PSUB, "CLS08180")) + { + Name (RBF0, ResourceTemplate () + { + }) + Return (RBF0) + } + Else + { + Name (RBF1, ResourceTemplate () + { + GpioInt(Edge, ActiveLow, ExclusiveAndWake, PullUp, 0, "\\_SB.GIO0", 0 , ResourceConsumer, , ) {384} + }) + Return (RBF1) + } + } + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + case(0) + { + // revision 0: functions 1-7 are not supported. + return (Buffer() {0x01, 0x03}) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + default + { + // Functions 1-7: not supported + } + } + } + } + } +} // End PCI0 + +// Empty power resource for handling in Platform extension +PowerResource(P0RR, 0x5, 0) { + Method(_STA){Return(0)} + Method(_ON) { + } + Method(_OFF) { + } +} + +// Empty power resource for handling in Platform extension +PowerResource(R0RR, 0x5, 0) { + Method(_STA){Return(0)} + Method(_ON) { + } + Method(_OFF) { + } + Method(_RST){ + } +} + +Device (QPPX) +{ + Name (_HID, "HID_QPPX") + Name (_UID, 0) + Name (_CCA, 0) + Alias(\_SB.PSUB, _SUB) + + Method (_STA, 0) { + Return(0xF) + } + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + // TCSR_PCIEPHY_LINK_CONFIG + Memory32Fixed (ReadWrite, 0x01FEC004, 0x4) + + // + // Following are the PERST GPIO assignment for four PCIe cores. + // The Method _QPG(), will return a package in the same order + // as the following GPIO resource definitions with 0x00, if the + // GPIO resource listed below is not applicable to this platform, + // else, will return 0x01 in the corresponding index for the GPIOIO + // resource + // + GpioIo (Shared, PullNone, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , RawDataBuffer(0x1){0x01}) {35} // PCI0_PERST + GpioIo (Shared, PullNone, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 1, ResourceConsumer, , RawDataBuffer(0x1){0x01}) {175} // PCI1_PERST + GpioIo (Shared, PullNone, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 2, ResourceConsumer, , RawDataBuffer(0x1){0x01}) {102} // PCI2_PERST + GpioIo (Shared, PullNone, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 3, ResourceConsumer, , RawDataBuffer(0x1){0x01}) {178} // PCI3_PERST + } ) + Return (RBUF) + } + + Method (_QPG, 0x0, Serialized) + { + If (LEqual(\_SB.PSUB, "CLS08180")) + { + // CLS Platform + Return( Package() + { + // 0x00 - INVALID FOR THIS PLATFORM, 0x01 - VALID FOR THIS PLATFORM + 0x00, //PCI0-PERST INVALID + 0x01, //PCI1-PERST VALID + 0x01, //PCI2-PERST VALID + 0x01, //PCI3-PERST VALID + }) + } + Else + { + // Rest of the Platform + Return( Package() + { + // 0x00 - INVALID FOR THIS PLATFORM, 0x01 - VALID FOR THIS PLATFORM + 0x01, //PCI0-PERST VALID + 0x01, //PCI1-PERST VALID + 0x01, //PCI2-PERST VALID + 0x01, //PCI3-PERST VALID + }) + } + } + + //WLAN EN GPIO resource + Name (GWLE, ResourceTemplate () + { + GpioIo (Exclusive,PullNone,0,0, ,"\\_SB.GIO0") {169} // WL_EN + }) + + //SDX55 PON GPIO resource + Name (GMDM, ResourceTemplate () + { + GpioIo (Exclusive,PullNone,0,0, ,"\\_SB.GIO0") {185} // SDX Power ON + }) + //SDX55 Reset PMIC GPIO resource + Name (GMDR, ResourceTemplate () + { + GpioIo(Exclusive, PullNone,0,0, ,"\\_SB.PM01") {528} // PMIC GPIO9C + }) + //SDX55 PON Switch PMIC GPIO resource + Name (GMDS, ResourceTemplate () + { + GpioIo (Exclusive,PullNone,0,0, ,"\\_SB.PM01") {677} // PMIC GPIO6E + }) + + Scope(\_SB.GIO0) { + OperationRegion(WLEN, GeneralPurposeIO, 0, 1) + OperationRegion(MPON, GeneralPurposeIO, 0, 1) + } + + Scope(\_SB.PM01) { + OperationRegion(PMDR, GeneralPurposeIO, 0, 1) + OperationRegion(PMON, GeneralPurposeIO, 0, 1) + } + + // TLMM GPIO resource fields + Field(\_SB.GIO0.WLEN, ByteAcc, NoLock, Preserve) + { + Connection (\_SB.QPPX.GWLE), + WLEN, 1, // WLAN_EN + } + + // TLMM GPIO resource SDX PON + Field(\_SB.GIO0.MPON, ByteAcc, NoLock, Preserve) + { + Connection (\_SB.QPPX.GMDM), + MPON, 1, // SDX PON + } + + // PMIC GPIO resource field for SDX reset + Field(\_SB.PM01.PMDR, ByteAcc, NoLock, Preserve) + { + Connection (\_SB.QPPX.GMDR), + PMDR, 1, // SDX Reset + } + + // PMIC GPIO resource field for SDX PON + Field(\_SB.PM01.PMON, ByteAcc, NoLock, Preserve) + { + Connection (\_SB.QPPX.GMDS), + PMON, 1, // SDX PON Switch + } + + Method (_RST, 0x1, Serialized) + { + switch(ToInteger(Arg0)) + { + Case (0) + { + If (Lequal(\_SB_.PSUB,"MTP08180")) // MTP + { + If (Lequal(\_SB_.PLST, 1) || Lequal(\_SB_.PLST, 4)) // Hastings + { + Store (0x00, \_SB.QPPX.WLEN) + Sleep(5) + Store (0x01, \_SB.QPPX.WLEN) + } + } + ElseIf (Lequal(\_SB_.PSUB,"CLS08180")) // CLS + { + If(Lequal(\_SB_.SOID, 404) && ( LEqual(BSID, 0x2) || LEqual(BSID, 0x3) )) // Hastings + { + Store (0x00, \_SB.QPPX.WLEN) + Sleep(5) + Store (0x01, \_SB.QPPX.WLEN) + } + } + } + Case (1) + { + + } + Case (2) + { + + } + Case (3) + { + If (LEqual(\_SB_.PSUB,"CLS08180")) + { + // To see if it is a EVT3 board, only then the following sequence will apply + // For EVT3 both GPIO 41 and 42 will be 0x0 + If(LEqual(BREV, 0x0)) + { + Store(0x0, \_SB.QPPX.PMON) //PMIC GPIO 6E for SDX55 power switch OFF + Store(0x0, \_SB.QPPX.PMDR) //PMIC GPIO 9C for SDX55 Assert Reset + Store(0x0, \_SB.QPPX.MPON) // TLMM GPIO 185 for SDX Power supply + Sleep(400) //Delay 400 ms for M.2 3.3 V power to discharge to 0 Volts + Store(0x1, \_SB.QPPX.MPON) // TLMM GPIO 185 for SDX Power supply + Store(0x1, \_SB.QPPX.PMDR) //PMIC GPIO 9C for SDX55 De-Assert Reset + Sleep(100) //Delay 100 ms for SDX55 to process cold reset + Store(0x1, \_SB.QPPX.PMON) //PMIC GPIO 6E for SDX55 power switch ON + Sleep(30) //Delay 30 ms for SDX55 to process cold boot + } + } + } + Default + { + Store("Invalid PCIe port number passed to QPPX reset helper", Debug) + } + } + } +} + +Include("pcie1.asl") +Include("pcie2.asl") +Include("pcie3.asl") \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie1.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie1.asl new file mode 100644 index 0000000..b83f4a4 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie1.asl @@ -0,0 +1,322 @@ +//PCIE1 asl + +// +// Copyright (c) 2018, Mmoclauq Technologies, Inc. All rights reserved. +// + +Device (PCI1) { + Name (_DEP, Package(0x2) { + \_SB.PEP0, + \_SB.QPPX + }) + Name(_HID,EISAID("PNP0A08")) + Name(_CID,EISAID("PNP0A03")) + Name(_UID, 0x1) + Name(_SEG, 0x1) + Name(_BBN, 0x0) + Name(_PRT, Package(){ + Package(){0x0FFFF, 0, 0, 779}, // Slot 1, INTA + Package(){0x0FFFF, 1, 0, 778}, // Slot 1, INTB + Package(){0x0FFFF, 2, 0, 777}, // Slot 1, INTC + Package(){0x0FFFF, 3, 0, 776} // Slot 1, INTD + }) + + Method (_CCA, 0) + { + Return (One) + } + + Method(_STA, 0) + { + if(LEqual(PRP1, 0x1)) { + Return (0x0F) // EndPoints available + } + else { + Return (0x00) // No EndPoints available. + } + } + + Method(_PSC) { + Return(Zero) + } + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // [ECAM_BASE + 2MB(ECAM_SIZE)] to [PCI_MEM_SIZE - 2MB(ECAM_SIZE) - 64KB IO Space] + Memory32Fixed (ReadWrite, 0x68200000, 0x1DF0000) + WordBusNumber (ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + , // Decode: PosDecode + 0, // AddressGranularity + 0, // AddressMinimum + 1, // AddressMaximum + 0, // AddressTranslation + 2) // RangeLength + }) + + Return (RBUF) + } + Name(SUPP, 0) + Name(CTRL, 0) + + Method(_DSW, 0x3, NotSerialized) { + + } + + Method(_OSC, 4) { + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + //No native hot plug support + //ASPM supported + //Clock PM supported + //MSI/MSI-X + + If(LNotEqual(And(SUPP, 0x16), 0x16)) + { + And(CTRL,0x1E,CTRL) // Give control of everything to the OS + } + + And(CTRL,0x15,CTRL) + + If(LNotEqual(Arg1,One)) + { // Unknown revision + Or(CDW1,0x08,CDW1) + } + If(LNotEqual(CDW3,CTRL)) + { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } // Update DWORD3 in the buffer + + Store(CTRL,CDW3) + Return(Arg3) + } + Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + // + // Function 0: Return supported functions, based on revision + // + + case(0) + { + // revision 0: functions 1-9 are supported. + return (Buffer() {0xFF, 0x03}) + } + + // + // Function 1: For emulated ActiveBoth controllers, returns + // a package of controller-relative pin numbers. + // Each corresponding pin will have an initial + // polarity of ActiveHigh. + // + + case(1) + { + + Return (Package(2) { + Package(1){ + 1}, // Success + Package(3){ + 0,0x1,0x1}// Link Width supports x1??, PCI express card slot and WAKE# signal + + }) + } + case(2) + { + + Return (Package(1) { + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(3) + { + + Return (Package(1) { + 0}) //Random have to check , not implemented yet + + + } + case(4) // Not implemented yet + { + + Return (Package(2) { + Package(1){0}, + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(5) // PCI Boot Configuration + { + + Return (Package(1) { + 1 + }) + } + case(6) // Latency Scale and Value + { + + Return (Package(4) { + Package(1){0}, // Maximum Snoop Latency Scale + Package(1){0}, // Maximum Snoop Latency Value + Package(1){0}, // Maximum No-Snoop Latency Scale + Package(1){0} // Maximum No-Snoop Latency Value + + }) + } + case(7) // PCI Express Slot Parsing + { + + Return (Package(1) { + 2 + }) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + + default + { + // Functions 9+: not supported + } + + } + } + } + + Name(_S0W, 4) + + Name(_PR0, Package(){ + \_SB.P1RR + }) + Name(_PR3, Package(){ + \_SB.P1RR + }) + + // PCIe Root Port 1 + Device(RP1) { + Method(_ADR, 0x0, Serialized) { + Return(Zero) + } + + Name(_PR0, Package(){ + \_SB.R1RR + }) + Name(_PR3, Package(){ + \_SB.R1RR + }) + + Name(_PRR, Package(){ + \_SB.R1RR + }) + + Name(_S0W, 4) + + Name (_DSD, Package () { + ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), + Package () { + Package (2) {"HotPlugSupportInD3", 1}, + } + }) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + //WAKE + GpioInt(Edge, ActiveLow, ExclusiveAndWake, PullUp, 0, "\\_SB.GIO0", 0 , ResourceConsumer, , ) {448} + }) + Return (RBUF) + } + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + case(0) + { + // revision 0: functions 1-7 are not supported. + return (Buffer() {0x01, 0x03}) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + default + { + // Functions 1-7: not supported + } + } + } + } + } +} // End PCI1 + +// Empty power resource for handling in Platform extension +PowerResource(P1RR, 0x5, 0) { + Method(_STA){Return(0)} + Method(_ON) { + } + Method(_OFF) { + } +} + +// Empty power resource for handling in Platform extension +PowerResource(R1RR, 0x5, 0) { + Method(_STA){Return(0)} + Method(_ON) { + } + Method(_OFF) { + } + Method(_RST){ + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie2.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie2.asl new file mode 100644 index 0000000..3bd4cfe --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie2.asl @@ -0,0 +1,322 @@ +//PCIE3 asl + +// +// Copyright (c) 2018, Mmoclauq Technologies, Inc. All rights reserved. +// + +Device (PCI2) { + Name (_DEP, Package(0x2) { + \_SB.PEP0, + \_SB.QPPX + }) + Name(_HID,EISAID("PNP0A08")) + Name(_CID,EISAID("PNP0A03")) + Name(_UID, 0x2) + Name(_SEG, 0x2) + Name(_BBN, 0x0) + Name(_PRT, Package(){ + Package(){0x0FFFF, 0, 0, 695}, // Slot 1, INTA + Package(){0x0FFFF, 1, 0, 694}, // Slot 1, INTB + Package(){0x0FFFF, 2, 0, 693}, // Slot 1, INTC + Package(){0x0FFFF, 3, 0, 692} // Slot 1, INTD + }) + + Method (_CCA, 0) + { + Return (One) + } + + Method(_STA, 0) + { + if(LEqual(PRP2, 0x1)) { + Return (0x0F) // EndPoints available + } + else { + Return (0x00) // No EndPoints available. + } + } + + Method(_PSC) { + Return(Zero) + } + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // [ECAM_BASE + 2MB(ECAM_SIZE)] to [PCI_MEM_SIZE - 2MB(ECAM_SIZE) - 64KB IO Space] + Memory32Fixed (ReadWrite, 0x70200000, 0x1DF0000) + WordBusNumber (ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + , // Decode: PosDecode + 0, // AddressGranularity + 0, // AddressMinimum + 1, // AddressMaximum + 0, // AddressTranslation + 2) // RangeLength + }) + + Return (RBUF) + } + Name(SUPP, 0) + Name(CTRL, 0) + + Method(_DSW, 0x3, NotSerialized) { + + } + + Method(_OSC, 4) { + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + //No native hot plug support + //ASPM supported + //Clock PM supported + //MSI/MSI-X + + If(LNotEqual(And(SUPP, 0x16), 0x16)) + { + And(CTRL,0x1E,CTRL) // Give control of everything to the OS + } + + And(CTRL,0x15,CTRL) + + If(LNotEqual(Arg1,One)) + { // Unknown revision + Or(CDW1,0x08,CDW1) + } + If(LNotEqual(CDW3,CTRL)) + { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } // Update DWORD3 in the buffer + + Store(CTRL,CDW3) + Return(Arg3) + } + Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + // + // Function 0: Return supported functions, based on revision + // + + case(0) + { + // revision 0: functions 1-9 are supported. + return (Buffer() {0xFF, 0x03}) + } + + // + // Function 1: For emulated ActiveBoth controllers, returns + // a package of controller-relative pin numbers. + // Each corresponding pin will have an initial + // polarity of ActiveHigh. + // + + case(1) + { + + Return (Package(2) { + Package(1){ + 1}, // Success + Package(3){ + 0,0x1,0x1}// Link Width supports x1??, PCI express card slot and WAKE# signal + + }) + } + case(2) + { + + Return (Package(1) { + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(3) + { + + Return (Package(1) { + 0}) //Random have to check , not implemented yet + + + } + case(4) // Not implemented yet + { + + Return (Package(2) { + Package(1){0}, + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(5) // PCI Boot Configuration + { + + Return (Package(1) { + 1 + }) + } + case(6) // Latency Scale and Value + { + + Return (Package(4) { + Package(1){0}, // Maximum Snoop Latency Scale + Package(1){0}, // Maximum Snoop Latency Value + Package(1){0}, // Maximum No-Snoop Latency Scale + Package(1){0} // Maximum No-Snoop Latency Value + + }) + } + case(7) // PCI Express Slot Parsing + { + + Return (Package(1) { + 3 + }) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + + default + { + // Functions 9+: not supported + } + + } + } + } + + Name(_S0W, 4) + + Name(_PR0, Package(){ + \_SB.P2RR + }) + Name(_PR3, Package(){ + \_SB.P2RR + }) + + // PCIe Root Port 1 + Device(RP1) { + Method(_ADR, 0x0, Serialized) { + Return(Zero) + } + + Name(_PR0, Package(){ + \_SB.R2RR + }) + Name(_PR3, Package(){ + \_SB.R2RR + }) + + Name(_PRR, Package(){ + \_SB.R2RR + }) + + Name(_S0W, 4) + + Name (_DSD, Package () { + ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), + Package () { + Package (2) {"HotPlugSupportInD3", 1}, + } + }) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + //WAKE + GpioInt(Edge, ActiveLow, ExclusiveAndWake, PullUp, 0, "\\_SB.GIO0", 0 , ResourceConsumer, , ) {512} + }) + Return (RBUF) + } + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + case(0) + { + // revision 0: functions 1-7 are not supported. + return (Buffer() {0x01, 0x03}) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + default + { + // Functions 1-7: not supported + } + } + } + } + } +} // End PCI2 + +// Empty power resource for handling in Platform extension +PowerResource(P2RR, 0x5, 0) { + Method(_STA){Return(0)} + Method(_ON) { + } + Method(_OFF) { + } +} + +// Empty power resource for handling in Platform extension +PowerResource(R2RR, 0x5, 0) { + Method(_STA){Return(0)} + Method(_ON) { + } + Method(_OFF) { + } + Method(_RST){ + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie3.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie3.asl new file mode 100644 index 0000000..a514db8 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie3.asl @@ -0,0 +1,322 @@ +//PCIE3 asl + +// +// Copyright (c) 2018, Mmoclauq Technologies, Inc. All rights reserved. +// + +Device (PCI3) { + Name (_DEP, Package(0x2) { + \_SB.PEP0, + \_SB.QPPX + }) + Name(_HID,EISAID("PNP0A08")) + Name(_CID,EISAID("PNP0A03")) + Name(_UID, 0x3) + Name(_SEG, 0x3) + Name(_BBN, 0x0) + Name(_PRT, Package(){ + Package(){0x0FFFF, 0, 0, 466}, // Slot 1, INTA + Package(){0x0FFFF, 1, 0, 467}, // Slot 1, INTB + Package(){0x0FFFF, 2, 0, 470}, // Slot 1, INTC + Package(){0x0FFFF, 3, 0, 471} // Slot 1, INTD + }) + + Method (_CCA, 0) + { + Return (One) + } + + Method(_STA, 0) + { + if(LEqual(PRP3, 0x1)) { + Return (0x0F) // EndPoints available + } + else { + Return (0x00) // No EndPoints available. + } + } + + Method(_PSC) { + Return(Zero) + } + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // [ECAM_BASE + 2MB(ECAM_SIZE)] to [PCI_MEM_SIZE - 2MB(ECAM_SIZE) - 64KB IO Space] + Memory32Fixed (ReadWrite, 0x40200000, 0x1DF0000) + WordBusNumber (ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + , // Decode: PosDecode + 0, // AddressGranularity + 0, // AddressMinimum + 1, // AddressMaximum + 0, // AddressTranslation + 2) // RangeLength + }) + + Return (RBUF) + } + Name(SUPP, 0) + Name(CTRL, 0) + + Method(_DSW, 0x3, NotSerialized) { + + } + + Method(_OSC, 4) { + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + //No native hot plug support + //ASPM supported + //Clock PM supported + //MSI/MSI-X + + If(LNotEqual(And(SUPP, 0x16), 0x16)) + { + And(CTRL,0x1E,CTRL) // Give control of everything to the OS + } + + And(CTRL,0x15,CTRL) + + If(LNotEqual(Arg1,One)) + { // Unknown revision + Or(CDW1,0x08,CDW1) + } + If(LNotEqual(CDW3,CTRL)) + { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } // Update DWORD3 in the buffer + + Store(CTRL,CDW3) + Return(Arg3) + } + Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + // + // Function 0: Return supported functions, based on revision + // + + case(0) + { + // revision 0: functions 1-9 are supported. + return (Buffer() {0xFF, 0x03}) + } + + // + // Function 1: For emulated ActiveBoth controllers, returns + // a package of controller-relative pin numbers. + // Each corresponding pin will have an initial + // polarity of ActiveHigh. + // + + case(1) + { + + Return (Package(2) { + Package(1){ + 1}, // Success + Package(3){ + 0,0x1,0x1}// Link Width supports x1??, PCI express card slot and WAKE# signal + + }) + } + case(2) + { + + Return (Package(1) { + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(3) + { + + Return (Package(1) { + 0}) //Random have to check , not implemented yet + + + } + case(4) // Not implemented yet + { + + Return (Package(2) { + Package(1){0}, + Package(4){ + 1,3,0,7} //Random have to check + + }) + } + case(5) // PCI Boot Configuration + { + + Return (Package(1) { + 1 + }) + } + case(6) // Latency Scale and Value + { + + Return (Package(4) { + Package(1){0}, // Maximum Snoop Latency Scale + Package(1){0}, // Maximum Snoop Latency Value + Package(1){0}, // Maximum No-Snoop Latency Scale + Package(1){0} // Maximum No-Snoop Latency Value + + }) + } + case(7) // PCI Express Slot Parsing + { + + Return (Package(1) { + 4 + }) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + + default + { + // Functions 9+: not supported + } + + } + } + } + + Name(_S0W, 4) + + Name(_PR0, Package(){ + \_SB.P3RR + }) + Name(_PR3, Package(){ + \_SB.P3RR + }) + + // PCIe Root Port 1 + Device(RP1) { + Method(_ADR, 0x0, Serialized) { + Return(Zero) + } + + Name(_PR0, Package(){ + \_SB.R3RR + }) + Name(_PR3, Package(){ + \_SB.R3RR + }) + + Name(_PRR, Package(){ + \_SB.R3RR + }) + + Name(_S0W, 4) + + Name (_DSD, Package () { + ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), + Package () { + Package (2) {"HotPlugSupportInD3", 1}, + } + }) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + //WAKE + GpioInt(Edge, ActiveLow, ExclusiveAndWake, PullUp, 0, "\\_SB.GIO0", 0 , ResourceConsumer, , ) {576} + }) + Return (RBUF) + } + + Method(_DSM, 0x4, NotSerialized) { + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) + { + // DSM Function + switch(ToInteger(Arg2)) + { + case(0) + { + // revision 0: functions 1-7 are not supported. + return (Buffer() {0x01, 0x03}) + } + case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + { + Return (Package(1) { + 1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow + }) + } + case(9) // DSM for Specifying Device Readiness Durations + { + Return (Package(5) { + 0xFFFFFFFF, // FW Reset Time + 0xFFFFFFFF, // FW DL_Up Time + 0xFFFFFFFF, // FW FLR Reset Time + 0x00000000, // FW D3hot to D0 Time + 0xFFFFFFFF // FW VF Enable Time + }) + } + default + { + // Functions 1-7: not supported + } + } + } + } + } +} // End PCI3 + +// Empty power resource for handling in Platform extension +PowerResource(P3RR, 0x5, 0) { + Method(_STA){Return(0)} + Method(_ON) { + } + Method(_OFF) { + } +} + +// Empty power resource for handling in Platform extension +PowerResource(R3RR, 0x5, 0) { + Method(_STA){Return(0)} + Method(_ON) { + } + Method(_OFF) { + } + Method(_RST){ + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie_resources.asl new file mode 100644 index 0000000..97f3863 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/pcie_resources.asl @@ -0,0 +1,1901 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by pcie subsystem. +// +// +// Copyright (c) 2017 by Mmoclauq Technologies Inc. All Rights Reserved. +// Mmoclauq Confidential and Proprietary +// +//=========================================================================== + + +Scope(\_SB_.PEP0) +{ + // PCIe Intra-Soc ports + Method(PEMD) + { + // Check chip major revision + If(LGreaterEqual(\_SB_.SVMJ, 0x0000000000000002)) + { + Return (PEMC) + } + else + { + Return(PEMX) //disable NVMe power management for v1 devices + } + } + + Name(PEMC, + package() + { + Package() + { + "DEVICE", + "\\_SB.PCI0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 @0.88V + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 880000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Headroom + }, + }, + + /* Turning on PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_0_gdsc", 1}}, + + /* ICB votes through PSTATE */ + /* vote for 75 MB/s config NOC bandwidth */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_0_CFG", 75000000, 0}}, + /* vote for 980 MB/s SNOC bandwidth for x1 */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 980000000, 980000000}}, + + /* Votes CX to nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}}, + + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}}, + + package() {"CLOCK", package() {"gcc_pcie_0_pipe_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_q2a_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_mstr_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_cfg_ahb_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_aux_clk", 8, 19200000, 3}}, + package() {"CLOCK", package() {"gcc_pcie0_phy_refgen_clk", 8, 100000000, 3}}, + + /* CLKREQ */ + package() + { + "TLMMGPIO", // TLMM resource + package() + { + 36, // PIN Number + 0, // State: 0: Low, 1: High + 1, // Function select: 1 + 0, // direction 0: Input, 1: Output. + 3, // Pull value: 0: No Pull, 1: Pull Down, 2: Keeper, 3: Pull Up + 0, // Drive Strength: 0: 2mA, 1: 4mA, 2: 6mA, 3: 8mA, 4: 10mA, 5: 12mA, 6: 14mA, 7: 16mA + 0, // Enable low power state + }, + }, + + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + package() {"CLOCK", package() {"gcc_pcie_0_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_q2a_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_mstr_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_cfg_ahb_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie0_phy_refgen_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_pipe_clk", 2}}, + + /* common clocks */ + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}}, + + /* Suppress the votes for CX nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 16, "SUPPRESSIBLE"}}, + + /* ICB votes */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_0_CFG", 0, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 0, 0}}, + + /* Turn off PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_0_gdsc", 2}}, + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Headroom + }, + }, + }, + + Package() + { + "CRASHDUMP_EXCEPTION", + Package() { "EXECUTE_FUNCTION", Package() { "ExecuteOcdPCIeExceptions"}}, + }, + + Package() + { + "CRASHDUMP_DSTATE", + 0, + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI0.RP1", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + /* NVMe power rail */ + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() + { + "PPP_RESOURCE_ID_SMPS8_C", + 2, // Voltage Regulator type = SMPS + 1800000,// 1.8V + 1, // Software enable - Enable + 0, // Software power mode - AUTO + 0, // Head room voltage + }, + }, + + /* NVMe DBB1 & DBU4 */ + package() + { + "PMICGPIO", + package() + { + "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", // GPIO or GPIO IOCTL + 2, // PMIC_C + 10,// GPIO 11 + 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS + 1, // PM_GPIO_VIN1 + 10,// PM_GPIO_SOURCE_HIGH + 3, // PM_GPIO_OUT_BUFFER_HIGH + 4, // PM_GPIO_I_SOURCE_PULL_DOWN_10uA + }, + }, + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 @0.88V + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 880000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Headroom + }, + }, + + /* Turning on PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_1_gdsc", 1}}, + + /* ICB votes through PSTATE */ + /* vote for 75 MB/s config NOC bandwidth */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_1_CFG", 75000000, 0}}, + /* vote for 1960 MB/s SNOC bandwidth for x2 */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_1", "ICBID_SLAVE_EBI1", 1960000000, 1960000000}}, + + /* Votes CX to nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}}, + + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}}, + + package() {"CLOCK", package() {"gcc_pcie_1_pipe_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_q2a_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_mstr_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_cfg_ahb_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_aux_clk", 8, 19200000, 3}}, + package() {"CLOCK", package() {"gcc_pcie1_phy_refgen_clk", 8, 100000000, 3}}, + + /* CLKREQ */ + package() + { + "TLMMGPIO", // TLMM resource + package() + { + 103, // PIN Number + 0, // State: 0: Low, 1: High + 1, // Function select: 1 + 0, // direction 0: Input, 1: Output. + 3, // Pull value: 0: No Pull, 1: Pull Down, 2: Keeper, 3: Pull Up + 0, // Drive Strength: 0: 2mA, 1: 4mA, 2: 6mA, 3: 8mA, 4: 10mA, 5: 12mA, 6: 14mA, 7: 16mA + 0, // Enable low power state + }, + }, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + package() {"CLOCK", package() {"gcc_pcie_1_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_q2a_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_mstr_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_cfg_ahb_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie1_phy_refgen_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_pipe_clk", 2}}, + + /* common clocks */ + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}}, + + /* Suppress the votes for CX nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 16, "SUPPRESSIBLE"}}, + + /* ICB votes */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_1_CFG", 0, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_1", "ICBID_SLAVE_EBI1", 0, 0}}, + + /* Turn off PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_1_gdsc", 2}}, + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Headroom + }, + }, + + /* NVMe power rail */ + package() + { + "PMICVREGVOTE", // PMICVREGVOTE resource + package() + { + "PPP_RESOURCE_ID_SMPS8_C", + 2, // Voltage Regulator type = SMPS + 0, // 0V + 0, // Software enable - Enable + 0, // Software power mode - AUTO + 0, // Head room voltage + }, + }, + + /* NVMe DBB1 & DBU4 */ + package() + { + "PMICGPIO", + package() + { + "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", // GPIO or GPIO IOCTL + 2, // PMIC_C + 10,// GPIO 11 + 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS + 1, // PM_GPIO_VIN1 + 0, // PM_GPIO_SOURCE_LOW + 3, // PM_GPIO_OUT_BUFFER_HIGH + 4, // PM_GPIO_I_SOURCE_PULL_DOWN_10uA + }, + }, + }, + + Package() + { + "CRASHDUMP_EXCEPTION", + Package() { "EXECUTE_FUNCTION", Package() { "ExecuteOcdPCIeExceptions"}}, + }, + + Package() + { + "CRASHDUMP_DSTATE", + 0, + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI1.RP1", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI2", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 @0.88V + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 880000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Headroom + }, + }, + + /* Turning on PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_2_gdsc", 1}}, + + /* ICB votes through PSTATE */ + /* vote for 75 MB/s config NOC bandwidth */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_2_CFG", 75000000, 0}}, + /* vote for 1960 MB/s SNOC bandwidth for x2 */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_2", "ICBID_SLAVE_EBI1", 3920000000, 3920000000}}, + + /* Votes CX to nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}}, + + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}}, + + package() {"CLOCK", package() {"gcc_pcie_2_pipe_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_2_slv_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_2_slv_q2a_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_2_mstr_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_2_cfg_ahb_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_2_aux_clk", 8, 19200000, 3}}, + package() {"CLOCK", package() {"gcc_pcie2_phy_refgen_clk", 8, 100000000, 3}}, + + /* CLKREQ */ + package() + { + "TLMMGPIO", // TLMM resource + package() + { + 176, // PIN Number + 0, // State: 0: Low, 1: High + 1, // Function select: 1 + 0, // direction 0: Input, 1: Output. + 3, // Pull value: 0: No Pull, 1: Pull Down, 2: Keeper, 3: Pull Up + 0, // Drive Strength: 0: 2mA, 1: 4mA, 2: 6mA, 3: 8mA, 4: 10mA, 5: 12mA, 6: 14mA, 7: 16mA + 0, // Enable low power state + }, + }, + + /* WIGIG_EN + package() + { + "TLMMGPIO", // TLMM resource + package() + { + 131, // PIN Number + 1, // State: 0: Low, 1: High + 0, // Function select + 1, // direction 0: Input, 1: Output. + 0, // Pull value: 0: No Pull, 1: Pull Down, 2: Keeper, 3: Pull Up + 0, // Drive Strength: 0: 2mA, 1: 4mA, 2: 6mA, 3: 8mA, 4: 10mA, 5: 12mA, 6: 14mA, 7: 16mA + 0, // Enable low power state + }, + },*/ + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + package() {"CLOCK", package() {"gcc_pcie_2_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_2_slv_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_2_slv_q2a_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_2_mstr_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_2_cfg_ahb_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie2_phy_refgen_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_2_pipe_clk", 2}}, + + /* common clocks */ + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}}, + + /* Suppress the votes for CX nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 16, "SUPPRESSIBLE"}}, + + // /* ICB votes */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_2_CFG", 0, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_2", "ICBID_SLAVE_EBI1", 0, 0}}, + + /* Turn off PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_2_gdsc", 2}}, + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Headroom + }, + }, + }, + + Package() + { + "CRASHDUMP_EXCEPTION", + Package() { "EXECUTE_FUNCTION", Package() { "ExecuteOcdPCIeExceptions"}}, + }, + + Package() + { + "CRASHDUMP_DSTATE", + 0, + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI2.RP1", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI3", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 @0.88V + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 880000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Headroom + }, + }, + + // /* Turning on PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_3_gdsc", 1}}, + + // /* ICB votes */ + // /* vote for 75 MB/s config NOC bandwidth */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_3_CFG", 75000000, 0}}, + /* vote for 3920 MB/s SNOC bandwidth for x4 */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_3", "ICBID_SLAVE_EBI1", 3920000000, 3920000000}}, + + /* Votes CX to nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}}, + + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}}, + + package() {"CLOCK", package() {"gcc_pcie_3_pipe_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_3_slv_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_3_slv_q2a_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_3_mstr_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_3_cfg_ahb_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_3_aux_clk", 8, 19200000, 3}}, + package() {"CLOCK", package() {"gcc_pcie3_phy_refgen_clk", 8, 100000000, 3}}, + + /* CLKREQ */ + package() + { + "TLMMGPIO", // TLMM resource + package() + { + 179, // PIN Number + 0, // State: 0: Low, 1: High + 1, // Function select: 1 + 0, // direction 0: Input, 1: Output. + 3, // Pull value: 0: No Pull, 1: Pull Down, 2: Keeper, 3: Pull Up + 0, // Drive Strength: 0: 2mA, 1: 4mA, 2: 6mA, 3: 8mA, 4: 10mA, 5: 12mA, 6: 14mA, 7: 16mA + 0, // Enable low power state + }, + }, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + package() {"CLOCK", package() {"gcc_pcie_3_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_3_slv_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_3_slv_q2a_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_3_mstr_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_3_cfg_ahb_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie3_phy_refgen_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_3_pipe_clk", 2}}, + + /* common clocks */ + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}}, + + /* Suppress the votes for CX nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 16, "SUPPRESSIBLE"}}, + + /* ICB votes */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_3_CFG", 0, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_3", "ICBID_SLAVE_EBI1", 0, 0}}, + + /* Turn off PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_3_gdsc", 2}}, + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Headroom + }, + }, + }, + + Package() + { + "CRASHDUMP_EXCEPTION", + Package() { "EXECUTE_FUNCTION", Package() { "ExecuteOcdPCIeExceptions"}}, + }, + + Package() + { + "CRASHDUMP_DSTATE", + 0, + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI3.RP1", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + }) + + Name(PEMX, + package() + { + Package() + { + "DEVICE", + "\\_SB.PCI0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 @0.88V + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 880000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Headroom + }, + }, + + /* Turning on PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_0_gdsc", 1}}, + + /* ICB votes through PSTATE */ + /* vote for 75 MB/s config NOC bandwidth */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_0_CFG", 75000000, 0}}, + /* vote for 980 MB/s SNOC bandwidth for x1 */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 980000000, 980000000}}, + + /* Votes CX to nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}}, + + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}}, + /* TODO: Remove on V2 SC8180X hardware */ + package() {"CLOCK", package() {"gcc_rx2_qlink_clkref_en", 1}}, + package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 1}}, + package() {"CLOCK", package() {"gcc_ufs_card_clkref_en", 1}}, + /* Marking Suppressible */ + package() {"CLOCK", package() {"gcc_rx2_qlink_clkref_en", 9,8}}, + package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 9,8}}, + package() {"CLOCK", package() {"gcc_ufs_card_clkref_en", 9,8}}, + + package() {"CLOCK", package() {"gcc_pcie_0_pipe_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_q2a_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_mstr_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_cfg_ahb_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_0_aux_clk", 8, 19200000, 3}}, + package() {"CLOCK", package() {"gcc_pcie0_phy_refgen_clk", 8, 100000000, 3}}, + + /* CLKREQ */ + package() + { + "TLMMGPIO", // TLMM resource + package() + { + 36, // PIN Number + 0, // State: 0: Low, 1: High + 1, // Function select: 1 + 0, // direction 0: Input, 1: Output. + 3, // Pull value: 0: No Pull, 1: Pull Down, 2: Keeper, 3: Pull Up + 0, // Drive Strength: 0: 2mA, 1: 4mA, 2: 6mA, 3: 8mA, 4: 10mA, 5: 12mA, 6: 14mA, 7: 16mA + 0, // Enable low power state + }, + }, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + package() {"CLOCK", package() {"gcc_pcie_0_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_slv_q2a_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_mstr_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_cfg_ahb_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie0_phy_refgen_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_0_pipe_clk", 2}}, + + /* common clocks */ + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}}, + + /* Suppress the votes for CX nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 16, "SUPPRESSIBLE"}}, + + /* ICB votes */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_0_CFG", 0, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 0, 0}}, + + /* Turn off PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_0_gdsc", 2}}, + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Headroom + }, + }, + }, + + Package() + { + "CRASHDUMP_EXCEPTION", + Package() { "EXECUTE_FUNCTION", Package() { "ExecuteOcdPCIeExceptions"}}, + }, + + Package() + { + "CRASHDUMP_DSTATE", + 0, + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI0.RP1", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI1", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 @0.88V + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 880000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Headroom + }, + }, + + /* Turning on PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_1_gdsc", 1}}, + + /* ICB votes through PSTATE */ + /* vote for 75 MB/s config NOC bandwidth */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_1_CFG", 75000000, 0}}, + /* vote for 1960 MB/s SNOC bandwidth for x2 */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_1", "ICBID_SLAVE_EBI1", 1960000000, 1960000000}}, + + /* Votes CX to nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}}, + + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}}, + /* TODO: Remove on V2 SC8180X hardware */ + package() {"CLOCK", package() {"gcc_rx2_qlink_clkref_en", 1}}, + package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 1}}, + package() {"CLOCK", package() {"gcc_ufs_card_clkref_en", 1}}, + /* Marking Suppressible */ + package() {"CLOCK", package() {"gcc_rx2_qlink_clkref_en", 9,8}}, + package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 9,8}}, + package() {"CLOCK", package() {"gcc_ufs_card_clkref_en", 9,8}}, + + package() {"CLOCK", package() {"gcc_pcie_1_pipe_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_q2a_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_mstr_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_cfg_ahb_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_1_aux_clk", 8, 19200000, 3}}, + package() {"CLOCK", package() {"gcc_pcie1_phy_refgen_clk", 8, 100000000, 3}}, + + /* CLKREQ */ + package() + { + "TLMMGPIO", // TLMM resource + package() + { + 103, // PIN Number + 0, // State: 0: Low, 1: High + 1, // Function select: 1 + 0, // direction 0: Input, 1: Output. + 3, // Pull value: 0: No Pull, 1: Pull Down, 2: Keeper, 3: Pull Up + 0, // Drive Strength: 0: 2mA, 1: 4mA, 2: 6mA, 3: 8mA, 4: 10mA, 5: 12mA, 6: 14mA, 7: 16mA + 0, // Enable low power state + }, + }, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + package() {"CLOCK", package() {"gcc_pcie_1_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_slv_q2a_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_mstr_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_cfg_ahb_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie1_phy_refgen_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_1_pipe_clk", 2}}, + + /* common clocks */ + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}}, + + /* Suppress the votes for CX nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 16, "SUPPRESSIBLE"}}, + + /* ICB votes */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_1_CFG", 0, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_1", "ICBID_SLAVE_EBI1", 0, 0}}, + + /* Turn off PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_1_gdsc", 2}}, + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Headroom + }, + }, + }, + + Package() + { + "CRASHDUMP_EXCEPTION", + Package() { "EXECUTE_FUNCTION", Package() { "ExecuteOcdPCIeExceptions"}}, + }, + + Package() + { + "CRASHDUMP_DSTATE", + 0, + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI1.RP1", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI2", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 @0.88V + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 880000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Headroom + }, + }, + + /* Turning on PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_2_gdsc", 1}}, + + /* ICB votes through PSTATE */ + /* vote for 75 MB/s config NOC bandwidth */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_2_CFG", 75000000, 0}}, + /* vote for 1960 MB/s SNOC bandwidth for x2 */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_2", "ICBID_SLAVE_EBI1", 1960000000, 1960000000}}, + + /* Votes CX to nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}}, + + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}}, + /* TODO: Remove on V2 SC8180X hardware */ + package() {"CLOCK", package() {"gcc_rx2_qlink_clkref_en", 1}}, + package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 1}}, + package() {"CLOCK", package() {"gcc_ufs_card_clkref_en", 1}}, + /* Marking Suppressible */ + package() {"CLOCK", package() {"gcc_rx2_qlink_clkref_en", 9,8}}, + package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 9,8}}, + package() {"CLOCK", package() {"gcc_ufs_card_clkref_en", 9,8}}, + + package() {"CLOCK", package() {"gcc_pcie_2_pipe_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_2_slv_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_2_slv_q2a_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_2_mstr_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_2_cfg_ahb_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_2_aux_clk", 8, 19200000, 3}}, + package() {"CLOCK", package() {"gcc_pcie2_phy_refgen_clk", 8, 100000000, 3}}, + + /* CLKREQ */ + package() + { + "TLMMGPIO", // TLMM resource + package() + { + 176, // PIN Number + 0, // State: 0: Low, 1: High + 1, // Function select: 1 + 0, // direction 0: Input, 1: Output. + 3, // Pull value: 0: No Pull, 1: Pull Down, 2: Keeper, 3: Pull Up + 0, // Drive Strength: 0: 2mA, 1: 4mA, 2: 6mA, 3: 8mA, 4: 10mA, 5: 12mA, 6: 14mA, 7: 16mA + 0, // Enable low power state + }, + }, + + /* WIGIG_EN + package() + { + "TLMMGPIO", // TLMM resource + package() + { + 131, // PIN Number + 1, // State: 0: Low, 1: High + 0, // Function select + 1, // direction 0: Input, 1: Output. + 0, // Pull value: 0: No Pull, 1: Pull Down, 2: Keeper, 3: Pull Up + 0, // Drive Strength: 0: 2mA, 1: 4mA, 2: 6mA, 3: 8mA, 4: 10mA, 5: 12mA, 6: 14mA, 7: 16mA + 0, // Enable low power state + }, + },*/ + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + package() {"CLOCK", package() {"gcc_pcie_2_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_2_slv_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_2_slv_q2a_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_2_mstr_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_2_cfg_ahb_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie2_phy_refgen_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_2_pipe_clk", 2}}, + + /* common clocks */ + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}}, + + /* Suppress the votes for CX nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 16, "SUPPRESSIBLE"}}, + + // /* ICB votes */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_2_CFG", 0, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_2", "ICBID_SLAVE_EBI1", 0, 0}}, + + /* Turn off PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_2_gdsc", 2}}, + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Headroom + }, + }, + }, + + Package() + { + "CRASHDUMP_EXCEPTION", + Package() { "EXECUTE_FUNCTION", Package() { "ExecuteOcdPCIeExceptions"}}, + }, + + Package() + { + "CRASHDUMP_DSTATE", + 0, + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI2.RP1", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI3", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 @1.2v + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 1200000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 @0.88V + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 880000, // Voltage (uV) + 1, // Enable = Enable + 1, // Power Mode = NPM + 0, // Headroom + }, + }, + + // /* Turning on PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_3_gdsc", 1}}, + + // /* ICB votes */ + // /* vote for 75 MB/s config NOC bandwidth */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_3_CFG", 75000000, 0}}, + /* vote for 3920 MB/s SNOC bandwidth for x4 */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_3", "ICBID_SLAVE_EBI1", 3920000000, 3920000000}}, + + /* Votes CX to nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}}, + + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}}, + /* TODO: Remove on V2 SC8180X hardware */ + package() {"CLOCK", package() {"gcc_rx2_qlink_clkref_en", 1}}, + package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 1}}, + package() {"CLOCK", package() {"gcc_ufs_card_clkref_en", 1}}, + /* Marking Suppressible */ + package() {"CLOCK", package() {"gcc_rx2_qlink_clkref_en", 9,8}}, + package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 9,8}}, + package() {"CLOCK", package() {"gcc_ufs_card_clkref_en", 9,8}}, + + package() {"CLOCK", package() {"gcc_pcie_3_pipe_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_3_slv_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_3_slv_q2a_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_3_mstr_axi_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_3_cfg_ahb_clk", 1}}, + package() {"CLOCK", package() {"gcc_pcie_3_aux_clk", 8, 19200000, 3}}, + package() {"CLOCK", package() {"gcc_pcie3_phy_refgen_clk", 8, 100000000, 3}}, + + /* CLKREQ */ + package() + { + "TLMMGPIO", // TLMM resource + package() + { + 179, // PIN Number + 0, // State: 0: Low, 1: High + 1, // Function select: 1 + 0, // direction 0: Input, 1: Output. + 3, // Pull value: 0: No Pull, 1: Pull Down, 2: Keeper, 3: Pull Up + 0, // Drive Strength: 0: 2mA, 1: 4mA, 2: 6mA, 3: 8mA, 4: 10mA, 5: 12mA, 6: 14mA, 7: 16mA + 0, // Enable low power state + }, + }, + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + package() {"CLOCK", package() {"gcc_pcie_3_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_3_slv_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_3_slv_q2a_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_3_mstr_axi_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_3_cfg_ahb_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie3_phy_refgen_clk", 2}}, + package() {"CLOCK", package() {"gcc_pcie_3_pipe_clk", 2}}, + + /* common clocks */ + package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}}, + package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}}, + + /* Suppress the votes for CX nominal */ + package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 16, "SUPPRESSIBLE"}}, + + /* ICB votes */ + package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_3_CFG", 0, 0}}, + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_3", "ICBID_SLAVE_EBI1", 0, 0}}, + + /* Turn off PCIe core */ + Package() { "FOOTSWITCH", Package() { "pcie_3_gdsc", 2}}, + + /* PCIE Analog */ + package() + { + "PMICVREGVOTE", // PMIC VREG resource + package() // Vote for LDO3 + { + "PPP_RESOURCE_ID_LDO3_C", // Voltage Regulator ID + 1, // Voltage Regulator type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Head Room + }, + }, + + /* PCIE Core */ + Package() + { + "PMICVREGVOTE", // PMIC VREG resource + Package() // Vote for LDO5 + { + "PPP_RESOURCE_ID_LDO5_E", // Voltage Regulator ID + 1, // Voltage Regulator Type = LDO + 0, // Voltage (uV) + 0, // Enable = Disable + 0, // Power Mode = NPM + 0, // Headroom + }, + }, + }, + + Package() + { + "CRASHDUMP_EXCEPTION", + Package() { "EXECUTE_FUNCTION", Package() { "ExecuteOcdPCIeExceptions"}}, + }, + + Package() + { + "CRASHDUMP_DSTATE", + 0, + }, + }, + + Package() + { + "DEVICE", + "\\_SB.PCI3.RP1", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "FSTATE", + 0x1, // f1 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + }, + Package() + { + "DSTATE", + 0x1, // D1 state + }, + Package() + { + "DSTATE", + 0x2, // D2 state + }, + Package() + { + "DSTATE", + 0x3, // D3 state + }, + }, + }) +} diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/pep_common.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/pep_common.asl new file mode 100644 index 0000000..4b2ba05 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/pep_common.asl @@ -0,0 +1,476 @@ +// +// The PEP Device & Driver Related Configuration +// + +Device (PEP0) +{ + Name (_HID, "HID_PEP0") + Name (_CID, "PNP0D80") + //Alias(\_SB.PSUB, _SUB) + Include("thz.asl") + + Method(_SUB) + { + If (LEqual(\_SB.PSUB, "MTP08180")) { + + If (LEqual(PPID, 0x1)){ + Return("HAZD8180") + } + Else { + If(Lequal(\_SB_.SOID, 404) && Lequal(\_SB_.PLST,1)){ + Return("MTPC8180") + } + Else { + Return("MTP08180") + } + } + + } + ElseIf (LEqual(\_SB.PSUB, "CLS08180")){ + If (LEqual(_BID, 0x0)) { + If(Lequal(\_SB_.SOID, 404) && Lequal(\_SB_.PLST,1)){ + Return("CLS28180") + } + Else { + Return("CLS08180") + } + } + Else { + If(Lequal(\_SB_.SOID, 404) && Lequal(\_SB_.PLST,1)){ + Return("CLS38180") + } + Else { + Return("CLS18180") + } + } + } + ElseIf (LEqual(\_SB.PSUB, "CDP08180")){ + Return("CDP08180") + } + } + + Method(_CRS) + { + // List interrupt resources in the order they are used in PEP_Driver.c + Return + ( + ResourceTemplate () + { + // TSENS threshold interrupts + // Controller 0: Low / high + Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {538} + // Controller 0: Critical + Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {540} + // Controller 1: Low / high + Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {539} + // Controller 1: Critical + Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {541} + + // apss amc finish irq + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {37} + // apss epcb timeout irq + //Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {34} + // mdss amc finish irq + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {161} + // mdss epcb timeout irq + //Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {160} + + // Inbound interrupt from AOP to Apps PEP Glink: + //SYS_apssQgicSPI[389] = 421 + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {421} + + //rpm_to_kpss_ipc_irq0 = SYSApcsQgicSpi169 = 201 (MPM) + //Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {201} + + //rpm_to_kpss_ipc_irq0 = SYSApcsQgicSpi171 = 203 (wakeup) + //Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {203} + + //o_pwr_dcvsh_interrupt or silver_dcvsh_interrupt: LMH debug interrupt for power cluster + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {64} + + //o_perf_dcvsh_interrupt or gold_dcvsh_interrupt: LMH debug interrupt for perf cluster + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {65} + + //8998v1BU + + // CPR HMSS + //Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {80} + // CPR GFX + //Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {198} + //8998v1BU - + + //o_bimc_intr: BIMC BWMON + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {613} + } + ) + } + + + // need 20 char and 1 D state info + Field(\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve) + { + /* Connection Object - 0x007C is the unique identifier */ + Connection(I2CSerialBus( 0x0001,,0x0,, "\\_SB.ABD",,,,)), + AccessAs(BufferAcc, AttribRawBytes(21)), + FLD0, 168 + } + //Get port to connect to + Method(GEPT) + { + Name(BUFF, Buffer(4){}) + CreateByteField(BUFF, 0x00, STAT) + CreateWordField(BUFF, 0x02, DATA) + Store(0x1, DATA) //in this example we will connect to ABDO + Return(DATA) + } + + Name(ROST, 0x0) + // Number of CPUs to Park + Method(NPUR, 0x1, NotSerialized) + { + Store(Arg0, Index(\_SB_.AGR0._PUR, 1)) + Notify(\_SB_.AGR0, 0x80) + } + + + // ACPI method to return intr descriptor + Method(INTR, 0x0, NotSerialized) { + Name(RBUF, Package() + { + // Version + 0x00000002, + // Number of hosts + 0x00000001, + // number of memory regions + 0x00000003, + // number of IPC registers + 0x00000001, + + // Rpm: APCS_IPC(0) + // Host = SMEM_RPM + 0x00000006, + // Physical address + 0x17911008, + // Value + 0x00000001, + // Reserved + 0x00000000, + + // Shared memory + // Start address + 0x86000000, + // Size + 0x00200000, + // Reserved + 0x00000000, + // Reserved + 0x00000000, + + // MSG RAM + // Start address + 0x0C300000, + // Size + 0x00001000, + // Reserved + 0x00000000, + // Reserved + 0x00000000, + + // IMEM or TZ_WONCE + // Start address + 0x01fd4000, + // Size + 0x00000008, + // Reserved + 0x00000000, + // Reserved + 0x00000000, + + // IPC register 1 + // Physical addr + 0x17C0000C, + // Reserved + 0x00000000, + // Reserved + 0x00000000, + // Reserved + 0x00000000, + }) + Return (RBUF) + } + + Method(STND) + { + return (STNX) + } + + Name(STNX, + Package() + { + // Power resources for devices + // Names are reversed (so method OCMD becomes DMCO) + // + // Following format must be followed for name: + // DMxx -- Exists on QCOM SoC. Will use normal PoFX for power mgmt + // XMxx -- Exists off QCOM SoC and uses legacy power mgmt (_PS1, _PS2, etc) + // + // The files where these methods are declared must be included + // at the bottom of this file and must exists inside the scope: \_SB.PEP0 + "DMPO", //oem dummy + "MMVD", // Discrete Vreg Mapping Package + "DMSB", // buses resources + "DMMS", // SMMU + "DMPA", //AUDIO + "DM0C", //CAMERA JPGE + "DM1C", //CAMERA MPCS + "DM2C", //CAMERA VFE0 + "DMPB", //COREBSP_STORAGE-UFS primary + "DMUS", //COREBSP_STORAGE-UFS secondary + "DMDS", //COREBSP_STORAGE-SD + "DM0G", //GRAPHICS + "DM1G", //GRAPHICS + "DM2G", //GRAPHICS + "DM3G", //GRAPHICS + "DM4G", //GRAPHICS + "DM5G", //GRAPHICS + "DM6G", //GRAPHICS + "DM7G", //GRAPHICS + "DM8G", //GRAPHICS + "DM9G", //GRAPHICS + "DMKG", //GRAPHICS + "DMLG", //GRAPHICS + "DMMG", //GRAPHICS + "DMPL", // PLATFORM + //"DMTB", //BAMTestClient + "DMDQ", //QDSS + //"DMMT", //SMMUTestClient + "DMPI", //IPA + "DMWE", //EXTERNAL WIRELESS CONNECTIVITY + "XMPC", //CAMERA + "XMPL", // PLATFORM + "XMPN", //SENSORS + "DMEP", //PCIE-Resources + } + ) + // + // Core topology + // + Method(CTPM){ + Name( CTPN, package(){ + "CORE_TOPOLOGY", + 8 // Kyro cores + }) + + return(CTPN) + } + + // CPU cap for DCVS Packages + Name(DCVS,0x0) + + // Method to return CPU cap for DCVS Package + Method(PGDS) + { + Return(DCVS) + } + + // PPP Supported Resources Package + Name (PPPP, + Package() + { + // Resource ID + //------------------------ + Package () { "PPP_RESOURCE_ID_SMPS5_A" }, + Package () { "PPP_RESOURCE_ID_SMPS10_A" }, + + Package () { "PPP_RESOURCE_ID_SMPS1_C" }, + Package () { "PPP_RESOURCE_ID_SMPS2_C" }, + Package () { "PPP_RESOURCE_ID_SMPS3_C" }, + Package () { "PPP_RESOURCE_ID_SMPS5_C" }, + Package () { "PPP_RESOURCE_ID_SMPS6_C" }, + Package () { "PPP_RESOURCE_ID_SMPS7_C" }, + Package () { "PPP_RESOURCE_ID_SMPS8_C" }, + + Package () { "PPP_RESOURCE_ID_SMPS3_E" }, + Package () { "PPP_RESOURCE_ID_SMPS4_E" }, + Package () { "PPP_RESOURCE_ID_SMPS5_E" }, + + Package () { "PPP_RESOURCE_ID_LDO1_A" }, + Package () { "PPP_RESOURCE_ID_LDO2_A" }, + Package () { "PPP_RESOURCE_ID_LDO3_A" }, + Package () { "PPP_RESOURCE_ID_LDO5_A" }, + Package () { "PPP_RESOURCE_ID_LDO6_A" }, + Package () { "PPP_RESOURCE_ID_LDO7_A" }, + Package () { "PPP_RESOURCE_ID_LDO9_A" }, + Package () { "PPP_RESOURCE_ID_LDO10_A" }, + Package () { "PPP_RESOURCE_ID_LDO11_A" }, + Package () { "PPP_RESOURCE_ID_LDO12_A" }, + Package () { "PPP_RESOURCE_ID_LDO13_A" }, + Package () { "PPP_RESOURCE_ID_LDO14_A" }, + Package () { "PPP_RESOURCE_ID_LDO15_A" }, + Package () { "PPP_RESOURCE_ID_LDO16_A" }, + Package () { "PPP_RESOURCE_ID_LDO17_A" }, + Package () { "PPP_RESOURCE_ID_LDO18_A" }, + + Package () { "PPP_RESOURCE_ID_LDO1_C" }, + Package () { "PPP_RESOURCE_ID_LDO2_C" }, + Package () { "PPP_RESOURCE_ID_LDO3_C" }, + Package () { "PPP_RESOURCE_ID_LDO4_C" }, + Package () { "PPP_RESOURCE_ID_LDO6_C" }, + Package () { "PPP_RESOURCE_ID_LDO7_C" }, + Package () { "PPP_RESOURCE_ID_LDO8_C" }, + Package () { "PPP_RESOURCE_ID_LDO9_C" }, + Package () { "PPP_RESOURCE_ID_LDO10_C" }, + Package () { "PPP_RESOURCE_ID_LDO11_C" }, + + Package () { "PPP_RESOURCE_ID_LDO1_E" }, + Package () { "PPP_RESOURCE_ID_LDO2_E" }, + Package () { "PPP_RESOURCE_ID_LDO4_E" }, + Package () { "PPP_RESOURCE_ID_LDO5_E" }, + Package () { "PPP_RESOURCE_ID_LDO7_E" }, + Package () { "PPP_RESOURCE_ID_LDO8_E" }, + Package () { "PPP_RESOURCE_ID_LDO9_E" }, + Package () { "PPP_RESOURCE_ID_LDO10_E" }, + Package () { "PPP_RESOURCE_ID_LDO12_E" }, + Package () { "PPP_RESOURCE_ID_LDO13_E" }, + Package () { "PPP_RESOURCE_ID_LDO14_E" }, + Package () { "PPP_RESOURCE_ID_LDO15_E" }, + Package () { "PPP_RESOURCE_ID_LDO16_E" }, + Package () { "PPP_RESOURCE_ID_LDO17_E" }, + + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK1_A" }, + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK2_A" }, + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK3_A" }, + + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK1_D" }, + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK2_D" }, + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK3_D" }, + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK4_D" }, + + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK1_A" }, + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK2_A" }, + + Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK1_C" }, + + Package () { "PPP_RESOURCE_ID_BUCK_BOOST1_C" }, + + Package () { "PPP_RESOURCE_ID_PMIC_GPIO_DV1" }, + Package () { "PPP_RESOURCE_ID_PMIC_GPIO_DV2" }, + Package () { "PPP_RESOURCE_ID_PMIC_GPIO_DV3" }, + + Package () { "PPP_RESOURCE_ID_TLMM_GPIO_DV1" }, + Package () { "PPP_RESOURCE_ID_TLMM_GPIO_DV2" }, + Package () { "PPP_RESOURCE_ID_TLMM_GPIO_DV3" }, + }) + + + // Method to return PPP Package + Method(PPPM) + { + Return (PPPP) + } + + // Method to return System Default config packages + Name (PRRP, + Package() + { + // Resource type range Initial supported resource Last supported resource + //-------------------- -------------------------- ------------------------- + "PPP_RESOURCE_RANGE_INFO_SMPS_A", "PPP_RESOURCE_ID_SMPS1_A", "PPP_RESOURCE_ID_SMPS10_A", + "PPP_RESOURCE_RANGE_INFO_SMPS_C", "PPP_RESOURCE_ID_SMPS1_C", "PPP_RESOURCE_ID_SMPS8_C", + "PPP_RESOURCE_RANGE_INFO_SMPS_E", "PPP_RESOURCE_ID_SMPS1_E", "PPP_RESOURCE_ID_SMPS10_E", + "PPP_RESOURCE_RANGE_INFO_LDO_A", "PPP_RESOURCE_ID_LDO1_A", "PPP_RESOURCE_ID_LDO18_A", + "PPP_RESOURCE_RANGE_INFO_LDO_C", "PPP_RESOURCE_ID_LDO1_C", "PPP_RESOURCE_ID_LDO11_C", + "PPP_RESOURCE_RANGE_INFO_LDO_E", "PPP_RESOURCE_ID_LDO1_E", "PPP_RESOURCE_ID_LDO18_E", + "PPP_RESOURCE_RANGE_INFO_CXO_BUFFERS_A", "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK1_A", "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK2_A", + "PPP_RESOURCE_RANGE_INFO_CXO_BUFFERS_C", "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK1_C", "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK1_C", + "PPP_RESOURCE_RANGE_INFO_CXO_BUFFERS_D", "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK1_D", "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK1_D", + "PPP_RESOURCE_RANGE_INFO_BUCK_BOOST_C", "PPP_RESOURCE_ID_BUCK_BOOST1_C", "PPP_RESOURCE_ID_BUCK_BOOST1_C", + "PPP_RESOURCE_RANGE_INFO_PMIC_GPIO_DV", "PPP_RESOURCE_ID_PMIC_GPIO_DV1", "PPP_RESOURCE_ID_PMIC_GPIO_DV3", + "PPP_RESOURCE_RANGE_INFO_TLMM_GPIO_DV", "PPP_RESOURCE_ID_TLMM_GPIO_DV1", "PPP_RESOURCE_ID_TLMM_GPIO_DV3", + }) + + // Method to return Pep Ppp Resource Range Package + Method(PPRR) + { + Return (PRRP) + } + + // Full PEP Device Package + Name(FPDP,0x0) + + // Method to return Full PEP Managed Device List Package + Method(FPMD) + { + Return(FPDP) + } + + // Methods to read USB DP & DM interrupts polarity + // The return names should match with buffers + // declared and defined in usb.asl file. + + // This method allows PEP to read Polarity of + // eud_p0_dmse_int_mx & eud_p0_dpse_int_mx + // interrupts which belong to Primary USB Port (P0) + Method(DPRF) { + // Return DPRF + Return(\_SB.DPP0) + } + + // This method allows PEP to read Polarity of + // eud_p1_dmse_int_mx & eud_p1_dpse_int_mx + // interrupts which belong to Secondary USB Port (P1) + Method(DMRF) { + // Return DMRF + Return(\_SB.DPP1) + } + + // This method allows PEP to read Polarity of + // usb2_dmse & usb2_dpse + // interrupts which belong to USB Multiport 0 + Method(MPRF) { + // Return MPRF + Return(\_SB.MPP0) + } + + // This method allows PEP to read Polarity of + // usb2_dmse & usb2_dpse + // interrupts which belong to USB Multiport 1 + Method(MMRF) { + // Return MMRF + Return(\_SB.MPP1) + } +} + + //// need 20 char and 1 D state info +// Field(\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve) +// { + ///* Connection Object - 0x007C is the unique identifier */ +// Connection(I2CSerialBus( 0x0001,,0x0,, "\\_SB.ABD",,,,)), +// AccessAs(BufferAcc, AttribRawBytes(21)), +// FLD0, 168 +// } + ////Get port to connect to +// Method(GEPT) +// { +// Name(BUFF, Buffer(4){}) +// CreateByteField(BUFF, 0x00, STAT) +// CreateWordField(BUFF, 0x02, DATA) +// Store(0x1, DATA) +// Return(DATA) +// } +//} + +// DO NOT comment next line, since pep_tsens.asl is needed for PEP DeviceAdd +Include("pep_tsens.asl") +Include("pep_dvreg.asl") + +// Resources by area +Include("audio_resources.asl") +Include("graphics_resources.asl") +Include("msft_resources.asl") +Include("oem_resources.asl") +Include("usb_resources.asl") +Include("corebsp_resources.asl") +Include("ipa_resources.asl") +Include("wcnss_resources.asl") +Include("cust_wcnss_resources.asl") +Include("pcie_resources.asl") \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/pep_dvreg.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/pep_dvreg.asl new file mode 100644 index 0000000..7ccc182 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/pep_dvreg.asl @@ -0,0 +1,109 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contains the default discrete VREG mapping and method names +// +// +// Copyright (c) 2014-2020 Mmoclauq Technologies, Inc. +// All Rights Reserved. +// Confidential and Proprietary - Mmoclauq Technologies, Inc. +// +//=========================================================================== + +// NOTE: this file is included in the platform level pep.asl and can be replaced with platform +// specific discrete VREG definitions + +Scope(\_SB.PEP0) +{ + // Discrete Vreg Mapping Package + Name(DVMP, + Package() + { + // + // Discrete DisplayPort regulator (3.3V) + // PME8180 GPIO #1 - High to VDD3P3_SW/DP_REG_EN + // + Package() + { + "PPP_RESOURCE_ID_PMIC_GPIO_DV1", + "PPP_RESOURCE_TYPE_DISCRETE_PMIC_GPIO", // PMIC GPIO + Package() + { + "PM_DISCRETE_VREG_STATE_ON", // Mapping for VREG ON + package() + { + 4, // PME8180 + 0, // GPIO #1 : DP_REG_EN + 0, // Output Mode + 1, // PM_GPIO_VIN1 + 10, // PM_GPIO_SOURCE_HIGH + 0, // PM_GPIO_OUT_BUFFER_CONFIG_PMOS + 1, // PM_GPIO_OUT_BUFFER_LOW + 0, // Invert + 1, // PM_GPIO_PERPH_EN_ENABLE + 5, // PM_GPIO_I_SOURCE_PULL_NO_PULL + }, + }, + Package() + { + "PM_DISCRETE_VREG_STATE_OFF", // Mapping for VREG OFF + package() + { + 4, // PME8180 + 0, // GPIO #1 : DP_REG_EN + 1, // Input Mode + 0, // PM_GPIO_VIN0 + 0, // PM_GPIO_SOURCE_LOW + 0, // PM_GPIO_OUT_BUFFER_CONFIG_PMOS + 1, // PM_GPIO_OUT_BUFFER_LOW + 0, // No inversion + 0, // PM_GPIO_PERPH_EN_DISABLE + 4, // PM_GPIO_I_SOURCE_PULL_DOWN_10uA + }, + }, + }, + // + // Function control for Mini-DP HPD + // TLMM GPIO #189 - DP_HPD_GPIO + // + Package() + { + "PPP_RESOURCE_ID_TLMM_GPIO_DV3", + "PPP_RESOURCE_TYPE_DISCRETE_TLMM_GPIO", // TLMM GPIO + Package() + { + "PM_DISCRETE_VREG_STATE_ON", // Route HPD to controller + package() + { + 189, // TLMM GPIO : 189 = DP HPD GPIO + 0, // State : 0 = LOW + 1, // Function Select : 1 = DP_HPD_SELECT + 0, // Direction : 0 = INPUT + 0, // Pull Type : 0 = NOPULL + 0, // Drive Strength : 0 = 2mA + }, + + }, + Package() + { + "PM_DISCRETE_VREG_STATE_OFF", // Configure as GPIO + package() + { + 189, // TLMM GPIO : 189 = DP HPD GPIO + 0, // State : 0 = LOW + 0, // Function Select : 0 = GPIO + 0, // Direction : 0 = INPUT + 1, // Pull Type : 1 = PULLDOWN + 0, // Drive Strength : 0 = 2mA + }, + }, + }, + }) + + // Method to return Discrete Vreg Mapping Package + Method(DVMM) + { + Return(DVMP) + } +} + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/pep_tsens.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/pep_tsens.asl new file mode 100644 index 0000000..a66524a --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/pep_tsens.asl @@ -0,0 +1,12 @@ + + +Scope(\_SB.PEP0) +{ + Method(PEPH) + { + Return(Package() + { + "HID_PEP0", + }) + } +} diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/pmic_batt.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/pmic_batt.asl new file mode 100644 index 0000000..769d9d2 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/pmic_batt.asl @@ -0,0 +1,281 @@ +// +// Copyright (c) 2017, Mmoclauq Technologies Inc. All rights reserved. +// +// This file contains the Power Management IC (PMIC) +// ACPI device definitions, configuration and look-up tables. +// + +// Include("cust_pmic_batt.asl") + + + + // + // PMIC Battery Miniclass Driver + // + Device (PMBM) { + Name (_HID, "HID_PMBM") + Alias(\_SB.PSUB, _SUB) + Name (_DEP, Package(0x1) + { + \_SB_.PMGK + }) + + Method (_STA) { + Return (0xF) // Device is installable, functional & should be visible in OSPM/Device Manager + } + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + }) + Return (RBUF) + } +} + +// +//FGBCL Driver +// +Device (BCL1) { + Name (_HID, "HID_BCL1") + Alias(\_SB.PSUB, _SUB) + Name (_DEP, Package(0x1) + { + \_SB_.PMIC + }) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + GpioInt(Edge, ActiveLow, Shared, PullUp, 0, "\\_SB.PM01",,,,) {488} // PM_INT__PM3_BCLBIG_LVL0 listen to active low to go to level_sys_ok + GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {489} // PM_INT__PM3_BCLBIG_LVL1 + GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {490} // PM_INT__PM3_BCLBIG_LVL2 + GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {491} // PM_INT__PM3_BCLBIG_BAN + GpioInt(Edge, ActiveLow, Shared, PullUp, 0, "\\_SB.PM01",,,,) {288} // PM_INT__PM2_BCLBIG_LVL0 listen to active low to go to level_sys_ok + GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {289} // PM_INT__PM2_BCLBIG_LVL1 + GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {290} // PM_INT__PM2_BCLBIG_LVL2 + GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {291} // PM_INT__PM2_BCLBIG_BA + + }) + Return (RBUF) + } + //ACPI methods for Interrupt Name + Method (BCLQ) { + Name (CFG0, + Package(){ + "PM3_BCLBIG_LVL0", //pmic3 bclbig_level0 IRQ + "PM3_BCLBIG_LVL1", //pmic3 bclbig_level1 IRQ + "PM3_BCLBIG_LVL2", //pmic3 bclbig_level2 IRQ + "PM3_BCLBIG_BAN", //pmic3 bclbig_ban IRQ + "PM2_BCLBIG_LVL0", //pmic2 bclbig_level0 IRQ + "PM2_BCLBIG_LVL1", //pmic2 bclbig_level1 IRQ + "PM2_BCLBIG_LVL2", //pmic2 bclbig_level2 IRQ + "PM2_BCLBIG_BAN" //pmic2 bclbig_ban IRQ + }) + Return (CFG0) + } +} + +// // +// // PMIC Glink Driver +// // +Device (PMGK) { + Name (_HID, "HID_PMGK") + Alias(\_SB.PSUB, _SUB) + Name (_DEP, Package(0x2) + { + \_SB_.GLNK, + \_SB_.ABD + }) + Name (LKUP, 0x00); + + Method (_STA) { + Return (0xB) + } + + // Get pseudo SPB controller port which is used to handle the ACPI operation region access + Method(GEPT) + { + Name(BUFF, Buffer(4){}) + CreateByteField(BUFF, 0x00, STAT) + CreateWordField(BUFF, 0x02, DATA) + Store(0x3, DATA) + Return(DATA) + } + + //Declare Data Buffer to exchange data + Name(BUFF, Buffer(50){}) //50 bytes, STAT(1), SIZE(1), UCSI Payload (48) + CreateField(BUFF, 0, 8, BSTA) // Create the BSTA Field for STAT (Offset = 0-bit, size = 8-bit) + CreateField(BUFF, 8, 8, BSIZ) // Create the BSIZ Field for SIZE (Offset = 8-bit, size = 8-bit) + CreateField(BUFF, 16, 16, BVER) // Create the BVER Field for DATA-Version (Offset = 16-bit, size = 16-bit) + //Reserve 16bit here + CreateField(BUFF, 48, 32, BCCI) // Create the BCCI Field for DATA-CCI (Offset = 16-bit, size = 32-bit) + CreateField(BUFF, 80, 64, BCTL) // Create the BCTL Field for DATA-Control (Offset = 16-bit, size = 64-bit) + CreateField(BUFF, 144, 128, BMGI) // Create the BMGI Field for DATA-MessageIn (Offset = 16-bit, size = 128-bit) + CreateField(BUFF, 272, 128, BMGO) // Create the BMGO Field for DATA-MessageOut (Offset = 16-bit, size = 128-bit) + + Method(USBN, 1) + { + //Read mailbox from buffer + Store(UCSI, BUFF) + + //Update Mailbox content with buffer (only the field PPM->OPM) + Store(BVER, \_SB.UCSI.VERS) + Store(BCCI, \_SB.UCSI.CCI) + Store(BMGI, \_SB.UCSI.MSGI) + + //Notify UCSI Driver for Mailbox Update + Notify(\_SB.UCSI, Arg0) + Return(0) + } + + Method(UPAN, 1) + { + Name (VNTF, 0xFFFFFFFF) //Variable for Notification + Name (VPRT, 0x04) //Variable for Port + Name (VMUX, 0x00) //Variable for Mux + Name (VCCS, 0x02) //Variable for CC State + Name (VDPP, 0x00) //Variable for DP Pin + Name (VHPD, 0x00) //Variable for HPD State + Name (VHSF, 0x02) //Variable for High-Speed flag + Name (VHIQ, 0x00) //Variable for HPD IRQ + + Name (BCCX, 0x00) //Create variable for CC Status, Mux and HS Flag + Name (BDIX, 0x00) //Create variable for Pin Assignment, HPD Status, IRQ_HPD Status + + Store(Arg0,VNTF) + //Arg0 is 4 bytes content for pin assignment + //byte 0: port_index + AND(VNTF,0xFF,VPRT) + + //byte 1: orientation + ShiftRight(VNTF,8,VNTF) + AND(VNTF,0xFF,VCCS) + + //byte 2: mux_ctrl + ShiftRight(VNTF,8,VNTF) + AND(VNTF,0xFF,VMUX) + + switch(VMUX) + { + case(0) + { + Store(0,VHSF) + break; + } + case(1) + { + Store(0,VHSF) + break; + } + case(2) + { + Store(1,VHSF) + break; + } + case(3) + { + Store(0,VHSF) + break; + } + } + + //byte 3: dpam_hpd (bit7: IrqHPD, bit6: HPDState, bit 0-5: Pin Assignment) + ShiftRight(VNTF,8,VNTF) + AND(VNTF,0x80,VHIQ) + If(LEqual(VHIQ,0)) + { + Store(0,VHIQ) + } + Else + { + Store(1,VHIQ) + } + + AND(VNTF,0x40,VHPD) + If(LEqual(VHPD,0)) + { + Store(0,VHPD) + } + Else + { + Store(1,VHPD) + } + + AND(VNTF,0x3F,VDPP) + //If VDPP is 0, report TYPEC_DISPLAYPORT_PINASSIGNMENTINVALID(0x0) + If(LEqual(VDPP,0)) + { + Store(0, VDPP) + } + //If VDPP is Non-zero, add 6(USBGRAPHICS_NOTIFICATION_CC1_PIN_F) if CC status is CC2 + ElseIf(LEqual(VCCS,1)) + { + Add(VDPP,0x6,VDPP) + } + + //CC Status(0:1), Mux (2:3), High Speed Flag(4:5), Reserved(6:7) + Store(VCCS, BCCX) + + ShiftLeft(VMUX,2,VMUX) + OR(VMUX, BCCX, BCCX) + + ShiftLeft(VHSF,4,VHSF) + OR(VHSF, BCCX, BCCX) + //Display Info - PINA(0:3), HPD(4), IRQ_HPD(5), Reserved(6:7) + Store(VDPP, BDIX) + + ShiftLeft(VHPD,4,VHPD) + OR(VHPD, BDIX, BDIX) + + ShiftLeft(VHIQ,5,VHIQ) + OR(VHIQ, BDIX, BDIX) + + //Update USB Driver + Store(0x2, \_SB.UCS0.EINF)//2 ports + switch(VPRT) + { + case(0) + { + //1st Port + OR(0x1, \_SB.UCS0.EUPD, \_SB.UCS0.EUPD) //Set Bit 0 + Store(BCCX, \_SB.UCS0.ECC0) + Store(BDIX, \_SB.UCS0.EDI0) + \_SB.UCS0.USBR() + break; + } + case(1) + { + //2nd Port + OR(0x2, \_SB.UCS0.EUPD, \_SB.UCS0.EUPD) //Set Bit 1 + Store(BCCX, \_SB.UCS0.ECC1) + Store(BDIX, \_SB.UCS0.EDI1) + \_SB.UCS0.USBR() + break; + } + } + + //Sent Notify for PAN ACK - Uncomment for loop back testing + //Notify(\_SB.PMGK, VPRT) + Return(0) + } + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + }) + Return (RBUF) + } + + Method(LKST, 1) + { + Store(Arg0, LKUP) + Notify(\_SB.UCSI, 0x0) //Send Bus Check Notification for UCSI Re-enumeration + Return(0) + } + + //Virtual Bus (ABD) and its register map + Field (\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve) + { + Connection(I2CSerialBus(0x3,,0x0,, "\\_SB.ABD",,,,)), + AccessAs (BufferAcc, AttribRawBytes(48)), + UCSI, 384 + } +} + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/pmic_core.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/pmic_core.asl new file mode 100644 index 0000000..9bdfa12 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/pmic_core.asl @@ -0,0 +1,230 @@ +// +// Copyright (c) 2017, Mmoclauq Technologies Inc. All rights reserved. +// +// This file contains common Power Management IC (PMIC) ACPI device definitions +// + +// +// +//PMIC KMDF +// +Device (PMIC) +{ + Name (_DEP, + Package(0x1) { + \_SB_.SPMI + } + ) + Name (_HID, "HID_PMIC") + Name (_CID, "PNP0CA3") + Alias(\_SB.PSUB, _SUB) + + Method (PMCF) { + Name (CFG0, + Package() + { + // PMIC Info + 6, // Number of PMICs, must match the number of info packages + Package() + { + 0, + 1, + }, + Package() + { + 2, + 3, + }, + Package() + { + 4, + 5, + }, + Package() + { + 6, + 7, + }, + Package() + { + 8, + 9, + }, + Package() + { + 0xA, + 0xB, + }, + }) + Return (CFG0) + } +} + +// +// PMIC GPIO +// +Device (PM01) +{ + Name (_HID, "HID_PM01") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + Name (_DEP, + Package(0x1) { + \_SB_.PMIC + } + ) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, + ResourceTemplate() { + // QGIC Interrupt Resource + // Register for SPMI Interrupt 513 + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , ,) {513} + } + ) + Return (RBUF) + } + + // _DSM method to mark PM01's ActiveBoth interrupts + Method(_DSM, 0x4, NotSerialized) { + // DSM UUID + switch(ToBuffer(Arg0)) + { + // ACPI DSM UUID for GPIO + case(ToUUID("4F248F40-D5E2-499F-834C-27758EA1CD3F")) + { + // DSM Function + switch(ToInteger(Arg2)) + { + // Function 0: Return supported functions, based on revision + case(0) + { + // revision 0: function 0 & 1 are supported. + return (Buffer() {0x3}) + } + + // Function 1: For emulated ActiveBoth controllers, returns + // a package of controller-relative pin numbers. + // Each corresponding pin will have an initial + // polarity of ActiveHigh. + case(1) + { + // Marks pins KPDPWR_ON, RESIN_ON to be ActiveHigh. + Return (Package() {0, 1}) + } + + default + { + // Functions 2+: not supported + } + } + } + + default + { + // No other GUIDs supported + Return(Buffer(One) { 0x00 }) + } + } + } +} + +// +// PMIC Apps Driver +// +Device (PMAP) +{ + Name (_HID, "HID_PMAP") + Alias(\_SB.PSUB, _SUB) + Name(_DEP, + Package(0x3) { + \_SB_.PMIC, + \_SB.ABD, + \_SB.SCM0 + } + ) + //PMAP is dependent on ABD for operation region access + + // Get pseudo SPB controller port which is used to handle the ACPI operation region access + Method(GEPT) + { + Name(BUFF, Buffer(4){}) + CreateByteField(BUFF, 0x00, STAT) + CreateWordField(BUFF, 0x02, DATA) + Store(0x2, DATA) + Return(DATA) + } + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + //Interrupts must be in this order to match PmicAppsDevice.c OnPrepareHardware + //LAB Vreg OK interrupt + //GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {448} // 0xEF0 - PM_INT__LAB__VREG_OK + //WLED SC fault interrupt + //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {418} // 0xEC2 - PM_INT__WLED_CTRL__SC_FAULT + //IBB SC fault interrupt + //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {434} // 0xEE2 - PM_INT__IBB__SC_ERROR + //LAB SC fault interrupt + //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {449} // 0xEF1 - PM_INT__LAB__SC_ERROR + }) + Return (RBUF) + } +} + +// +// PMIC Apps Real Time Clock (RTC) +// +Device (PRTC) +{ + Name(_HID, "ACPI000E") + Name(_DEP, + Package() { + "\\_SB.PMAP" + } + ) + // PRTC is dependent on PMAP which implements the RTC Functions + + //Get the capabilities of the time and alarm device + Method(_GCP) + { + Return (0x04) //Bit 2 set indicating Get Set Supported + } + + Field(\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve) + { + Connection(I2CSerialBus( 0x0002,,0x0,, "\\_SB.ABD",,,,)), + AccessAs(BufferAcc, AttribRawBytes(24)), + FLD0,192 + } + + Method(_GRT) // Get the Real time + { + Name(BUFF, Buffer(26){}) // 18 bytes STAT(1), SIZE(1), Time(16) + CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time + CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field + CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field + Store(FLD0, BUFF) + Return(TME1) + } + + Method(_SRT, 1) // Set the Real time + { + Name(BUFF, Buffer(50){}) // 18 bytes STAT(1), SIZE(1), Time(16) + CreateByteField(BUFF, 0x0, STAT) // Create the STAT Field + CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time + CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field + CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field + Store(0x0, ACT1) + Store(Arg0, TME1) + Store(0x0, ACW1) + Store(Store(BUFF, FLD0),BUFF) // Write the transaction to the Psuedo I2C Port + + // Return the status + If(LNotEqual(STAT,0x00)) { + Return(1) // Call to OpRegion failed + } + Return(0) //success + } +} diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/qcdb.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/qcdb.asl new file mode 100644 index 0000000..b2381fc --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/qcdb.asl @@ -0,0 +1,8 @@ +// +// Qualcomm DIAG Bridge +// +Device (QCDB) +{ + Name (_HID, "HID_QCDB") + Alias(\_SB.PSUB, _SUB) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/qcgpio.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/qcgpio.asl new file mode 100644 index 0000000..a386ec2 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/qcgpio.asl @@ -0,0 +1,66 @@ +// +// Copyright (c) 2015-2018, Mmoclauq Technologies, Inc. All rights reserved. +// + +// +// TLMM controller. +// +Device (GIO0) +{ + Name (_HID, "HID_GIO0") + Name (_UID, 0) + Alias(\_SB.PSUB, _SUB) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // TLMM register address space + Memory32Fixed (ReadWrite, 0x03000000, 0x00DDC000) + + // Summary Interrupt shared by all banks + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {585} // GPIO 96 + Interrupt(ResourceConsumer, Edge, ActiveHigh, Shared, , , ) {603} // GPIO 123 + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {601} // GPIO 121 + // PCIe PDC Wake GPIO mapping + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {556} + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {590} + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {658} + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {569} + } ) + + Return (RBUF) + } + // ACPI method to return Num pins + Method(OFNI, 0x0, NotSerialized) { + Name(RBUF, Buffer() + { + 0xBE, // 0: TOTAL_GPIO_PINS + 0x00 // 1: TOTAL_GPIO_PINS + }) + Return (RBUF) + } + + Name(GABL, Zero) + Method(_REG, 0x2, NotSerialized) + { + If(LEqual(Arg0, 0x8)) + { + Store(Arg1, GABL) + } + } + + // ACPI event-based notification method for detecting Mini DP hot plug-in event + Name (_AEI, ResourceTemplate() + { + GpioInt(Edge, ActiveHigh, Exclusive, PullDown, 500,"\\_SB.GIO0"){189} + }) + Method (_EBD, 0x0, NotSerialized) + { + // Notify event ID - 0x92 to GFX driver on a hot plug-in event + Notify(\_SB.GPU0, 0x92) + } + +} diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/qcsp.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/qcsp.asl new file mode 100644 index 0000000..19eceb9 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/qcsp.asl @@ -0,0 +1,25 @@ +// +// Copyright (c) 2017-2018, Mmoclauq Technologies, Inc. All rights reserved. +// + +// +// Qualcomm Secure Procesor (QCSP) Driver +// +Device (QCSP) +{ + Name (_DEP, Package(0x3) + { + \_SB_.GLNK, + \_SB_.TREE, + \_SB_.SPSS + }) + Name (_HID, "HID_QCSP") + Alias(\_SB.PSUB, _SUB) + + // Disable QCSP + Method(_STA, 0) + { + return (0x0) + } + +} diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/qgpi.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/qgpi.asl new file mode 100644 index 0000000..c1d0da6 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/qgpi.asl @@ -0,0 +1,121 @@ +// +// Copyright (c) 2017,2019 Mmoclauq Technologies Inc. All rights reserved. +// +// This file contains the QUPv3 ACPI device definitions. +// GPI is the interface used by buses drivers for different peripherals. +// + +// +// Device Map: +// QGPI +// +// List of Devices + +Device (QGP0) +{ + // Indicates dependency on PEP + //Name (_DEP, Package () { \_SB_.PEP0 }) + + Name (_HID, "HID_QGPI") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + // QUPV3_0 address space + Memory32Fixed (ReadWrite, 0x00804000, 0x50000) + + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {276} // GPII-ID 0x0 + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {277} // GPII-ID 0x1 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {278} // GPII-ID 0x2 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {279} // GPII-ID 0x3 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {280} // GPII-ID 0x4 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {281} // GPII-ID 0x5 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {282} // GPII-ID 0x6 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {283} // GPII-ID 0x7 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {284} // GPII-ID 0x8 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {285} // GPII-ID 0x9 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {286} // GPII-ID 0xA + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {287} // GPII-ID 0xB + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {288} // GPII-ID 0xC + }) + Return (RBUF) + } + +} + +Device (QGP1) +{ + // Indicates dependency on PEP + //Name (_DEP, Package () { \_SB_.PEP0 }) + + Name (_HID, "HID_QGPI") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + // QUPV3_1 address space + Memory32Fixed (ReadWrite, 0x00A04000, 0x50000) + + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {311} // GPII-ID : 0x0 + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {312} // GPII-ID : 0x1 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {313} // GPII-ID : 0x2 + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {314} // GPII-ID : 0x3 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {315} // GPII-ID : 0x4 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {316} // GPII-ID : 0x5 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {325} // GPII-ID : 0x6 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {326} // GPII-ID : 0x7 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {327} // GPII-ID : 0x8 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {328} // GPII-ID : 0x9 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {329} // GPII-ID : 0xA + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {330} // GPII-ID : 0xB + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {331} // GPII-ID : 0xC + + }) + Return (RBUF) + } + +} + +Device (QGP2) +{ + // Indicates dependency on PEP + //Name (_DEP, Package () { \_SB_.PEP0 }) + + Name (_HID, "HID_QGPI") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 2) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + // QUPV3_0 address space + Memory32Fixed (ReadWrite, 0x00C04000, 0x50000) + + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {620} // GPII-ID 0x0 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {621} // GPII-ID 0x1 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {622} // GPII-ID 0x2 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {623} // GPII-ID 0x3 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {624} // GPII-ID 0x4 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {625} // GPII-ID 0x5 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {626} // GPII-ID 0x6 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {627} // GPII-ID 0x7 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {628} // GPII-ID 0x8 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {629} // GPII-ID 0x9 + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {630} // GPII-ID 0xA + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {631} // GPII-ID 0xB + //Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {632} // GPII-ID 0xC + }) + Return (RBUF) + } + +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/qwpp.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/qwpp.asl new file mode 100644 index 0000000..c0de3e3 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/qwpp.asl @@ -0,0 +1,25 @@ +Device (QWPP) +{ + Name (_DEP, Package () { \_SB_.PEP0 }) + + Name (_HID, "HID_QWPP") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method(_STA, 0) + { + return (0xB) // Loaded, but hidden + } + + Method (_CRS, 0x0, NotSerialized) + { + Return + ( + ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x09200000, 0x00400000) // The LLCC0-7 and CABO0-7 address space + Memory32Fixed (ReadWrite, 0x09680000, 0x00070000) // The GEMNOC address space + } + ) + } +} diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/rfs.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/rfs.asl new file mode 100644 index 0000000..bffdee4 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/rfs.asl @@ -0,0 +1,49 @@ +// +// Copyright (c) 2015, Mmoclauq Technologies, Inc. All rights reserved. +// + +// +// RemoteFS +// +Device (RFS0) +{ + Name (_DEP, Package(0x1) + { + \_SB_.IPC0, + }) + + Name (_HID, "HID_RFS0") + Alias(\_SB.PSUB, _SUB) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // RemoteFS Shared Memory + Memory32Fixed (ReadWrite, 0x88888888, 0x99999999, RMTS) + + // RFSA MPSS Shared Memory + Memory32Fixed (ReadWrite, 0x11111111, 0x22222222, RFSM) + + // RFSA ADSP Shared Memory + Memory32Fixed (ReadWrite, 0x33333333, 0x44444444, RFSA) + }) + + CreateDWordField (RBUF, RMTS._BAS, RMTA) + CreateDWordField (RBUF, RMTS._LEN, RMTL) + CreateDWordField (RBUF, RFSM._BAS, RFMA) + CreateDWordField (RBUF, RFSM._LEN, RFML) + CreateDWordField (RBUF, RFSA._BAS, RFAA) + CreateDWordField (RBUF, RFSA._LEN, RFAL) + + Store(\_SB_.RMTB, RMTA) + Store(\_SB_.RMTX, RMTL) + Store(\_SB_.RFMB, RFMA) + Store(\_SB_.RFMS, RFML) + Store(\_SB_.RFAB, RFAA) + Store(\_SB_.RFAS, RFAL) + + Return (RBUF) + } +} + +Include("plat_rfs.asl") // Platform specific data diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/slimbus.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/slimbus.asl new file mode 100644 index 0000000..72a8c24 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/slimbus.asl @@ -0,0 +1,44 @@ +// +// SLIMbus controller +// +Device (SLM1) +{ + Name (_ADR, 0) + Name (_CCA, 0) + Alias(\_SB.PSUB, _SUB) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // SLIMbus register address space + Memory32Fixed (ReadWrite, 0x171C0000, 0x0002c000) + + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {195} + }) + Return (RBUF) + } + + Include("audio_bus.asl") + +} + +Device (SLM2) +{ + Name (_ADR, 1) + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // SLIMbus register address space + Memory32Fixed (ReadWrite, 0x17240000, 0x0002c000) + + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {323} + }) + Return (RBUF) + } +} + + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/spmi.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/spmi.asl new file mode 100644 index 0000000..a934024 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/spmi.asl @@ -0,0 +1,26 @@ +// +// Copyright (c) 2014-2017, Mmoclauq Technologies, Inc. All rights reserved. +// + +// +//SPMI driver. +// +Device(SPMI) +{ + Name(_HID, "HID_SPMI") + Alias(\_SB.PSUB, _SUB) + Name (_CID, "PNP0CA2") + Name(_UID, One) + Name(_CCA, 0) + + Method(_CRS, 0x0, NotSerialized) + { + Name(RBUF, ResourceTemplate () + { + Memory32Fixed(ReadWrite, 0x0C400000, 0x02800000) + }) + Return(RBUF) + } + + Include("spmi_conf.asl") +} diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/spmi_conf.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/spmi_conf.asl new file mode 100644 index 0000000..050aa93 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/spmi_conf.asl @@ -0,0 +1,31 @@ +// +// Copyright (c) 2016 - 2017, Mmoclauq Technologies, Inc. All rights reserved. +// + +// +//SPMI driver configuration. +// +Method(CONF) +{ + Name(XBUF, + Buffer () { + 0x00, // uThisOwnerNumber + 0x01, // polling mode + 0x01, // reserved channel enable + 0x01, 0xFF, // reserved channel number (upper byte, lower byte) + 0x00, // dynamic channel mode enable + 0x02, 0x00, // number of channels (upper byte, lower byte) + 0x0A, // number of port priorities + 0x07, // number of PVC ports + 0x04, // number of PVC port PPIDs + 0x07, // number of masters + 0x01, 0xFF, // number of mapping table entries (upper byte, lower byte) + 0x10, // number of PIC accumulated status registers + 0x01, 0x00, // number of Program RAM REGS (upper byte, lower byte) + 0x01, // number of SPMI bus controllers + 0x0C, 0x40, 0x00, 0x00, // physical address 0 (byte3, byte2, byte1, byte0) + 0x02, 0x80, 0x00, 0x00 // physical size 0 (byte3, byte2, byte1, byte0) + } + ) + Return(XBUF) +} diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/ssm.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/ssm.asl new file mode 100644 index 0000000..47187a6 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/ssm.asl @@ -0,0 +1,18 @@ + +// +// SSM Driver +// +Device (SSM) +{ + Name (_DEP, Package(0x2) + { + \_SB_.GLNK, + \_SB_.TREE + }) + Name (_HID, "HID_SSM") + Alias(\_SB.PSUB, _SUB) + Method(_STA, 0) + { + return (0x0) //} // Do not load driver. + } +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/ssm_ce_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/ssm_ce_resources.asl new file mode 100644 index 0000000..b26b190 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/ssm_ce_resources.asl @@ -0,0 +1,80 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by pep drivers. +// +// +// Copyright (c) 2010-2011 by Mmoclauq Technologies Inc. All Rights Reserved. +// Mmoclauq Confidential and Proprietary +// +//=========================================================================== + + + +Scope(\_SB_.PEP0) +{ + // CRYPTO + Method(SSMD) + { + Return(CSCC) + } + + Name(CSCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.SSM", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + package() { "BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE0", "ICBID_SLAVE_EBI1", 200000000, 200000000}}, + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce1", 100000000 } }, + }, + + Package() + { + "FSTATE", + 0x1, // f1 state + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/snoc", 0x0}}, + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/cnoc", 0x0}}, + package() { "BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE0", "ICBID_SLAVE_EBI1", 0, 0}}, + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce1", 0 } }, + }, + }, + + Package() + { + "COMPONENT", + 0x1, // Component 1. + Package() + { + "FSTATE", + 0x0, // f0 state + //package() {"REQUIRED_RESOURCE", package() { 1, "/clk/snoc", 0xffffffff}}, + //package() {"REQUIRED_RESOURCE", package() { 1, "/clk/cnoc", 0xffffffff}}, + package() { "BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE1", "ICBID_SLAVE_EBI1", 200000000, 200000000}}, + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce2", 100000000 } }, + }, + + Package() + { + "FSTATE", + 0x1, // f1 state + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/snoc", 0x0}}, + //package() {"REQUIRED_RESOURCE", package() { 0, "/clk/cnoc", 0x0}}, + package() { "BUSARB", Package() { 3, "ICBID_MASTER_CRYPTO_CORE1", "ICBID_SLAVE_EBI1", 0, 0}}, + package(){ "REQUIRED_RESOURCE", package(){ 1, "/clk/ce2", 0 } }, + }, + }, + }, + ///////////////////////////////////////////////////////////////////////////////////// + }) + +} diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/syscache.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/syscache.asl new file mode 100644 index 0000000..6ca8e1b --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/syscache.asl @@ -0,0 +1,31 @@ +// +// System Cache Driver +// + + +Device (LLC) +{ + Name (_DEP, Package(0x1) + { + \_SB_.PEP0 + }) + Name (_HID, "HID_QLLC") + Alias(\_SB.PSUB, _SUB) + Alias(\_SB.SVMJ, _HRV) + Method (_CRS, 0x0, NotSerialized) + { + Return (ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x09600000, 0x50000) + //TCSR_TIMEOUT_INTR_STATUS address to read DDR4ch or 8ch selection + //http://ipcatalog.qualcomm.com/swi/chip/188/version/4066/module/3096475#TCSR_TIMEOUT_INTR_STATUS + Memory32Fixed (ReadOnly, 0x1FC8020, 0x4) + // reference : http://ipcatalog.qualcomm.com/irqs/chip/99/map/678 + //ddrss_apps_interrupt[2] = SYS_apssQgicSPI[582] = 614 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {614} // LLCC ECC interrupt + + }) + } + +} + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/testbam_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/testbam_resources.asl new file mode 100644 index 0000000..ae3a856 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/testbam_resources.asl @@ -0,0 +1,40 @@ +Scope(\_SB_.PEP0) +{ + // SoC Devices + Method(BTMD) + { + Return(BTCC) + } + Name(BTCC, + Package () + { + Package() + { + "DEVICE", + "\\_SB.BAT0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + Package() + { + "PSTATE", + 0x0, // P0 state + package() {"CLOCK", package() {"gcc_bam_dma_ahb_clk", 1, 100000000, 1}}, + }, + + Package() + { + "PSTATE", + 0x1, // P1 state + package() {"CLOCK", package() {"gcc_bam_dma_ahb_clk", 2, 100000000, 1}}, + }, + }, + }, + }) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/thz.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/thz.asl new file mode 100644 index 0000000..f53cb72 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/thz.asl @@ -0,0 +1,1395 @@ +// +// The Driver for Dynamically Changing Thresholds +// of Thermal Zones +// + +Method(THTZ, 0x4, NotSerialized) +{ + + // Switch based on thermal zone number + Switch(toInteger(Arg0)) + { + Case(1) + { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ1.TPSV) + Notify(\_SB.TZ1, 0x81) + } + Return(\_SB.TZ1._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ1.TTSP) + Notify(\_SB.TZ1, 0x81) + } + Return(\_SB.TZ1._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ1.TTC1) + Notify(\_SB.TZ1, 0x81) + } + Return(\_SB.TZ1._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ1.TTC2) + Notify(\_SB.TZ1, 0x81) + } + Return(\_SB.TZ1._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(3) + { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ3.TPSV) + Notify(\_SB.TZ3, 0x81) + } + Return(\_SB.TZ3._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ3.TTSP) + Notify(\_SB.TZ3, 0x81) + } + Return(\_SB.TZ3._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ3.TTC1) + Notify(\_SB.TZ3, 0x81) + } + Return(\_SB.TZ3._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ3.TTC2) + Notify(\_SB.TZ3, 0x81) + } + Return(\_SB.TZ3._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(5) + { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ5.TPSV) + Notify(\_SB.TZ5, 0x81) + } + Return(\_SB.TZ5._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ5.TTSP) + Notify(\_SB.TZ5, 0x81) + } + Return(\_SB.TZ5._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ5.TTC1) + Notify(\_SB.TZ5, 0x81) + } + Return(\_SB.TZ5._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ5.TTC2) + Notify(\_SB.TZ5, 0x81) + } + Return(\_SB.TZ5._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(7) + { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ7.TPSV) + Notify(\_SB.TZ7, 0x81) + } + Return(\_SB.TZ7._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ7.TTSP) + Notify(\_SB.TZ7, 0x81) + } + Return(\_SB.TZ7._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ7.TTC1) + Notify(\_SB.TZ7, 0x81) + } + Return(\_SB.TZ7._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ7.TTC2) + Notify(\_SB.TZ7, 0x81) + } + Return(\_SB.TZ7._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(9) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ9.TPSV) + Notify(\_SB.TZ9, 0x81) + } + Return(\_SB.TZ9._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ9.TTSP) + Notify(\_SB.TZ9, 0x81) + } + Return(\_SB.TZ9._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ9.TTC1) + Notify(\_SB.TZ9, 0x81) + } + Return(\_SB.TZ9._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ9.TTC2) + Notify(\_SB.TZ9, 0x81) + } + Return(\_SB.TZ9._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(15) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ15.TPSV) + Notify(\_SB.TZ15, 0x81) + } + Return(\_SB.TZ15._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ15.TTSP) + Notify(\_SB.TZ15, 0x81) + } + Return(\_SB.TZ15._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ15.TTC1) + Notify(\_SB.TZ15, 0x81) + } + Return(\_SB.TZ15._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ15.TTC2) + Notify(\_SB.TZ15, 0x81) + } + Return(\_SB.TZ15._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(16) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ16.TPSV) + Notify(\_SB.TZ16, 0x81) + } + Return(\_SB.TZ16._PSV) + } + + Case(1) + { + If(Arg2) + { + Store(Arg1, \_SB.TZ16.TCRT) + Notify(\_SB.TZ16, 0x81) + } + Return(\_SB.TZ16._CRT) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ16.TTSP) + Notify(\_SB.TZ16, 0x81) + } + Return(\_SB.TZ16._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ16.TTC1) + Notify(\_SB.TZ16, 0x81) + } + Return(\_SB.TZ16._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ16.TTC2) + Notify(\_SB.TZ16, 0x81) + } + Return(\_SB.TZ16._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(17) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ17.TPSV) + Notify(\_SB.TZ17, 0x81) + } + Return(\_SB.TZ17._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ17.TTSP) + Notify(\_SB.TZ17, 0x81) + } + Return(\_SB.TZ17._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ17.TTC1) + Notify(\_SB.TZ17, 0x81) + } + Return(\_SB.TZ17._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ17.TTC2) + Notify(\_SB.TZ17, 0x81) + } + Return(\_SB.TZ17._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(18) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ18.TPSV) + Notify(\_SB.TZ18, 0x81) + } + Return(\_SB.TZ18._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ18.TTSP) + Notify(\_SB.TZ18, 0x81) + } + Return(\_SB.TZ18._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ18.TTC1) + Notify(\_SB.TZ18, 0x81) + } + Return(\_SB.TZ18._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ18.TTC2) + Notify(\_SB.TZ18, 0x81) + } + Return(\_SB.TZ18._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(19) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ19.TPSV) + Notify(\_SB.TZ19, 0x81) + } + Return(\_SB.TZ19._PSV) + } + + Case(1) + { + If(Arg2) + { + Store(Arg1, \_SB.TZ19.TCRT) + Notify(\_SB.TZ19, 0x81) + } + Return(\_SB.TZ19._CRT) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ19.TTSP) + Notify(\_SB.TZ19, 0x81) + } + Return(\_SB.TZ19._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ19.TTC1) + Notify(\_SB.TZ19, 0x81) + } + Return(\_SB.TZ19._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ19.TTC2) + Notify(\_SB.TZ19, 0x81) + } + Return(\_SB.TZ19._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(20) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ20.TPSV) + Notify(\_SB.TZ20, 0x81) + } + Return(\_SB.TZ20._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ20.TTSP) + Notify(\_SB.TZ20, 0x81) + } + Return(\_SB.TZ20._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ20.TTC1) + Notify(\_SB.TZ20, 0x81) + } + Return(\_SB.TZ20._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ20.TTC2) + Notify(\_SB.TZ20, 0x81) + } + Return(\_SB.TZ20._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(21) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ21.TPSV) + Notify(\_SB.TZ21, 0x81) + } + Return(\_SB.TZ21._PSV) + } + + Case(1) + { + If(Arg2) + { + Store(Arg1, \_SB.TZ21.TCRT) + Notify(\_SB.TZ21, 0x81) + } + Return(\_SB.TZ21._CRT) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ21.TTSP) + Notify(\_SB.TZ21, 0x81) + } + Return(\_SB.TZ21._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ21.TTC1) + Notify(\_SB.TZ21, 0x81) + } + Return(\_SB.TZ21._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ21.TTC2) + Notify(\_SB.TZ21, 0x81) + } + Return(\_SB.TZ21._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(22) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ22.TPSV) + Notify(\_SB.TZ22, 0x81) + } + Return(\_SB.TZ22._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ22.TTSP) + Notify(\_SB.TZ22, 0x81) + } + Return(\_SB.TZ22._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ22.TTC1) + Notify(\_SB.TZ22, 0x81) + } + Return(\_SB.TZ22._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ22.TTC2) + Notify(\_SB.TZ22, 0x81) + } + Return(\_SB.TZ22._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(38) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ38.TPSV) + Notify(\_SB.TZ38, 0x81) + } + Return(\_SB.TZ38._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ38.TTSP) + Notify(\_SB.TZ38, 0x81) + } + Return(\_SB.TZ38._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ38.TTC1) + Notify(\_SB.TZ38, 0x81) + } + Return(\_SB.TZ38._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ38.TTC2) + Notify(\_SB.TZ38, 0x81) + } + Return(\_SB.TZ38._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(40) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ40.TPSV) + Notify(\_SB.TZ40, 0x81) + } + Return(\_SB.TZ40._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ40.TTSP) + Notify(\_SB.TZ40, 0x81) + } + Return(\_SB.TZ40._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ40.TTC1) + Notify(\_SB.TZ40, 0x81) + } + Return(\_SB.TZ40._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ40.TTC2) + Notify(\_SB.TZ40, 0x81) + } + Return(\_SB.TZ40._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(41) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ41.TPSV) + Notify(\_SB.TZ41, 0x81) + } + Return(\_SB.TZ41._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ41.TTSP) + Notify(\_SB.TZ41, 0x81) + } + Return(\_SB.TZ41._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ41.TTC1) + Notify(\_SB.TZ41, 0x81) + } + Return(\_SB.TZ41._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ41.TTC2) + Notify(\_SB.TZ41, 0x81) + } + Return(\_SB.TZ41._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(51) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ51.TPSV) + Notify(\_SB.TZ51, 0x81) + } + Return(\_SB.TZ51._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ51.TTSP) + Notify(\_SB.TZ51, 0x81) + } + Return(\_SB.TZ51._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ51.TTC1) + Notify(\_SB.TZ51, 0x81) + } + Return(\_SB.TZ51._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ51.TTC2) + Notify(\_SB.TZ51, 0x81) + } + Return(\_SB.TZ51._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(52) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ52.TPSV) + Notify(\_SB.TZ52, 0x81) + } + Return(\_SB.TZ52._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ52.TTSP) + Notify(\_SB.TZ52, 0x81) + } + Return(\_SB.TZ52._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ52.TTC1) + Notify(\_SB.TZ52, 0x81) + } + Return(\_SB.TZ52._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ52.TTC2) + Notify(\_SB.TZ52, 0x81) + } + Return(\_SB.TZ52._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(53) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ53.TPSV) + Notify(\_SB.TZ53, 0x81) + } + Return(\_SB.TZ53._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ53.TTSP) + Notify(\_SB.TZ53, 0x81) + } + Return(\_SB.TZ53._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ53.TTC1) + Notify(\_SB.TZ53, 0x81) + } + Return(\_SB.TZ53._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ53.TTC2) + Notify(\_SB.TZ53, 0x81) + } + Return(\_SB.TZ53._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(54) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ54.TPSV) + Notify(\_SB.TZ54, 0x81) + } + Return(\_SB.TZ54._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ54.TTSP) + Notify(\_SB.TZ54, 0x81) + } + Return(\_SB.TZ54._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ54.TTC1) + Notify(\_SB.TZ54, 0x81) + } + Return(\_SB.TZ54._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ54.TTC2) + Notify(\_SB.TZ54, 0x81) + } + Return(\_SB.TZ54._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(55) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ55.TPSV) + Notify(\_SB.TZ55, 0x81) + } + Return(\_SB.TZ55._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ55.TTSP) + Notify(\_SB.TZ55, 0x81) + } + Return(\_SB.TZ55._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ55.TTC1) + Notify(\_SB.TZ55, 0x81) + } + Return(\_SB.TZ55._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ55.TTC2) + Notify(\_SB.TZ55, 0x81) + } + Return(\_SB.TZ55._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(56) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ56.TPSV) + Notify(\_SB.TZ56, 0x81) + } + Return(\_SB.TZ56._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ56.TTSP) + Notify(\_SB.TZ56, 0x81) + } + Return(\_SB.TZ56._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ56.TTC1) + Notify(\_SB.TZ56, 0x81) + } + Return(\_SB.TZ56._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ56.TTC2) + Notify(\_SB.TZ56, 0x81) + } + Return(\_SB.TZ56._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(57) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ57.TPSV) + Notify(\_SB.TZ57, 0x81) + } + Return(\_SB.TZ57._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ57.TTSP) + Notify(\_SB.TZ57, 0x81) + } + Return(\_SB.TZ57._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ57.TTC1) + Notify(\_SB.TZ57, 0x81) + } + Return(\_SB.TZ57._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ57.TTC2) + Notify(\_SB.TZ57, 0x81) + } + Return(\_SB.TZ57._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(58) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ58.TPSV) + Notify(\_SB.TZ58, 0x81) + } + Return(\_SB.TZ58._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ58.TTSP) + Notify(\_SB.TZ58, 0x81) + } + Return(\_SB.TZ58._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ58.TTC1) + Notify(\_SB.TZ58, 0x81) + } + Return(\_SB.TZ58._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ58.TTC2) + Notify(\_SB.TZ58, 0x81) + } + Return(\_SB.TZ58._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(59) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ59.TPSV) + Notify(\_SB.TZ59, 0x81) + } + Return(\_SB.TZ59._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ59.TTSP) + Notify(\_SB.TZ59, 0x81) + } + Return(\_SB.TZ59._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ59.TTC1) + Notify(\_SB.TZ59, 0x81) + } + Return(\_SB.TZ59._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ59.TTC2) + Notify(\_SB.TZ59, 0x81) + } + Return(\_SB.TZ59._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(60) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ60.TPSV) + Notify(\_SB.TZ60, 0x81) + } + Return(\_SB.TZ60._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ60.TTSP) + Notify(\_SB.TZ60, 0x81) + } + Return(\_SB.TZ60._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ60.TTC1) + Notify(\_SB.TZ60, 0x81) + } + Return(\_SB.TZ60._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ60.TTC2) + Notify(\_SB.TZ60, 0x81) + } + Return(\_SB.TZ60._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(61) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ61.TPSV) + Notify(\_SB.TZ61, 0x81) + } + Return(\_SB.TZ61._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ61.TTSP) + Notify(\_SB.TZ61, 0x81) + } + Return(\_SB.TZ61._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ61.TTC1) + Notify(\_SB.TZ61, 0x81) + } + Return(\_SB.TZ61._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ61.TTC2) + Notify(\_SB.TZ61, 0x81) + } + Return(\_SB.TZ61._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(62) { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ62.TPSV) + Notify(\_SB.TZ62, 0x81) + } + Return(\_SB.TZ62._PSV) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ62.TTSP) + Notify(\_SB.TZ62, 0x81) + } + Return(\_SB.TZ62._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ62.TTC1) + Notify(\_SB.TZ62, 0x81) + } + Return(\_SB.TZ62._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ62.TTC2) + Notify(\_SB.TZ62, 0x81) + } + Return(\_SB.TZ62._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Case(99) + { + Switch(toInteger(Arg3)) + { + Case(0) { + If(Arg2) + { + Store(Arg1, \_SB.TZ99.TPSV) + Notify(\_SB.TZ99, 0x81) + } + Return(\_SB.TZ99._PSV) + } + + Case(1) { + If(Arg2) + { + Store(Arg1, \_SB.TZ99.TCRT) + Notify(\_SB.TZ99, 0x81) + } + Return(\_SB.TZ99._CRT) + } + + Case(2) { + If(Arg2) + { + Store(Arg1, \_SB.TZ99.TTSP) + Notify(\_SB.TZ99, 0x81) + } + Return(\_SB.TZ99._TSP) + } + + Case(3) { + If(Arg2) + { + Store(Arg1, \_SB.TZ99.TTC1) + Notify(\_SB.TZ99, 0x81) + } + Return(\_SB.TZ99._TC1) + } + + Case(4) { + If(Arg2) + { + Store(Arg1, \_SB.TZ99.TTC2) + Notify(\_SB.TZ99, 0x81) + } + Return(\_SB.TZ99._TC2) + } + + Default + { + Return(0xFFFF) + } + } + } + + Default { + Return(0xFFFF) + } + } +} + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/tmm_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/tmm_resources.asl new file mode 100644 index 0000000..c6048a6 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/tmm_resources.asl @@ -0,0 +1,298 @@ +//=========================================================================== +// +// DESCRIPTION +// This file contans the resources needed by SMMU test driver. +// +// +// Copyright (c) 2010-2013 by Mmoclauq Technologies Inc. All Rights Reserved. +// Mmoclauq Confidential and Proprietary +// +//=========================================================================== + +Scope(\_SB_.PEP0){ + // SMMU + Method(TMMD){ + Return(TMMC) + } + Name(TMMC, + Package(){ + Package(){ + "DEVICE", + "\\_SB.TMM0", + Package(){ + "COMPONENT", + 0, + Package(){ + "FSTATE", + 0, + package(){ + "FOOTSWITCH", + package(){ + "VDD_CAMSS_VFE", // Footswitch Name - VDD_CAMSS_VFE + 1, // Action - 1 - Enable + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_cpp_ahb_clk", // Clock Name - camss_vfe_cpp_ahb_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_cpp_clk", // Clock Name - camss_vfe_cpp_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe0_clk", // Clock Name - camss_vfe_vfe0_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe1_clk", // Clock Name - camss_vfe_vfe1_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe_ahb_clk", // Clock Name - camss_vfe_vfe_ahb_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe_axi_clk", // Clock Name - camss_vfe_vfe_axi_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_top_ahb_clk", // Clock Name - camss_top_ahb_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_ahb_clk", // Clock Name - camss_ahb_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "FOOTSWITCH", + package(){ + "VDD_VENUS0", // Footswitch Name - VDD_VENUS0 + 1, // Action - 1 - Enable + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_vcodec0_clk", // Clock Name - venus0_vcodec0_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_axi_clk", // Clock Name - venus0_axi_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_ahb_clk", // Clock Name - venus0_ahb_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_ocmemnoc_clk", // Clock Name - venus0_ocmemnoc_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "ocmemcx_ocmemnoc_clk", // Clock Name - ocmemcx_ocmemnoc_clk + 1, // Action - 1 - Enable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + }, + Package(){ + "FSTATE", + 1, + package(){ + "CLOCK", + package(){ + "camss_vfe_cpp_ahb_clk", // Clock Name - camss_vfe_cpp_ahb_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_cpp_clk", // Clock Name - camss_vfe_cpp_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe0_clk", // Clock Name - camss_vfe_vfe0_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe1_clk", // Clock Name - camss_vfe_vfe1_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe_ahb_clk", // Clock Name - camss_vfe_vfe_ahb_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_vfe_vfe_axi_clk", // Clock Name - camss_vfe_vfe_axi_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_top_ahb_clk", // Clock Name - camss_top_ahb_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "camss_ahb_clk", // Clock Name - camss_ahb_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "FOOTSWITCH", + package(){ + "VDD_CAMSS_VFE", // Footswitch Name - VDD_CAMSS_VFE + 2, // Action - 2 - Disable + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_vcodec0_clk", // Clock Name - venus0_vcodec0_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_axi_clk", // Clock Name - venus0_axi_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_ahb_clk", // Clock Name - venus0_ahb_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "venus0_ocmemnoc_clk", // Clock Name - venus0_ocmemnoc_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "CLOCK", + package(){ + "ocmemcx_ocmemnoc_clk", // Clock Name - ocmemcx_ocmemnoc_clk + 2, // Action - 2 - Disable + 0, // Frequency - 0 + 1, // Match Type - At Least (Hz) + }, + }, + package(){ + "FOOTSWITCH", + package(){ + "VDD_VENUS0", // Footswitch Name - VDD_VENUS0 + 2, // Action - 2 - Disable + }, + }, + }, + }, + }, + }) +} \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/ufs.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/ufs.asl new file mode 100644 index 0000000..d27093f --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/ufs.asl @@ -0,0 +1,112 @@ +// +// Copyright (c) 2017, Mmoclauq Technologies, Inc. All rights reserved. +// + +// UFS Controller +Device (UFS0) +{ + + Method(_STA, 0) + { + if(LEqual(STOR, 1)) { + Return (0xF) // booting from UFS so ufs.asl is enabled + } + else { + Return (0x0) // ufs.asl is diabled + } + } + + Name (_DEP, Package(0x1) + { + \_SB.PEP0, + }) + + Name (_HID, "HID_UFS0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + Name (_CCA, 1) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // UFS register address space + Memory32Fixed (ReadWrite, 0x1D84000, 0x14000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {297} + }) + Return (RBUF) + } + + // UFS Device + Device (DEV0) + { + // Memory Type + Method (_ADR) + { + Return (8) + } + + // Non-removable + Method (_RMV) + { + Return (0) + } + } + } + +Device (UFS1) +{ + Method(_STA, 0) + { + if(LEqual(SUFS, 1)) { + if(LEqual(STOR, 1)) { + Return (0xF) // Secondary UFS enabled and booting from UFS + } + else { + Return (0x0) // Not booting from UFS + } + } + else { + Return (0x0) // Secondary UFS diabled + } + } + + Name (_DEP, Package(0x1) + { + \_SB.PEP0, + }) + + Name (_HID, "HID_UFS0") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + Name (_CCA, 1) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // UFS register address space + Memory32Fixed (ReadWrite, 0x1D64000, 0x14000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {681} + }) + Return (RBUF) + } + + // UFS Device + Device (DEV0) + { + // Memory Type + Method (_ADR) + { + Return (8) + } + + // Non-removable + Method (_RMV) + { + Return (0) + } + } + } + + + + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/usb.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/usb.asl new file mode 100644 index 0000000..11a7b5c --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/usb.asl @@ -0,0 +1,1164 @@ +// +// Copyright (c) 2018-2019 Mmoclauq Technologies, Inc. All Rights Reserved. +// Mmoclauq Technologies Proprietary and Confidential. +// + +Name(QUFN, 0x0 ) //enable flag for QcUsbFN driver stack +//Name(FGEN, Buffer(){0x0}) //Flag for Forcing Gen1 only for USB controller. 0-disable, 1-enable + +//Flag to enable/disable Multiport re-driver for USB MP controller +//0-disable, 1-enable +//Name(MPRF, Buffer(){0x0}) + + +// HPD Notification Event in Display Driver +// HPD_STATUS_LOW_NOTIFY_EVENT - 0x92 +// HPD_STATUS_HIGH_NOTIFY_EVENT - 0x93 +// All other valus are invalid +Name(HPDB, 0x00000000) + +// Holds the HPD Status +// TYPEC_DISPLAYPORT_HPD_STATUSLOW = 0x0 +// TYPEC_DISPLAYPORT_HPD_STATUSHIGH = 0x1 +Name(HPDS, Buffer(){0x00}) + +// DP Pin Assignment +// TYPEC_DISPLAYPORT_PINASSIGNMENTINVALID = 0x0 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTA = 0x01 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTB = 0x02 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTC = 0x03 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTD = 0x04 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTE = 0x05 +// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTF = 0x06 +// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTA = 0x07 +// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTB = 0x08 +// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTC = 0x09 +// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTD = 0x0A +// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTE = 0x0B +Name(PINA, 0x00000000) + +//USBGRAPHICS_NOTIFICATION_INVALID = 0x0, // External display hot plug-out ACPI notification +//USBGRAPHICS_NOTIFICATION_CC1_PIN_A, // External display ACPI notification, CC1, Pin assignment A +//USBGRAPHICS_NOTIFICATION_CC1_PIN_B, // External display ACPI notification, CC1, Pin assignment B +//USBGRAPHICS_NOTIFICATION_CC1_PIN_C, // External display ACPI notification, CC1, Pin assignment C +//USBGRAPHICS_NOTIFICATION_CC1_PIN_D, // External display ACPI notification, CC1, Pin assignment D +//USBGRAPHICS_NOTIFICATION_CC1_PIN_E, // External display ACPI notification, CC1, Pin assignment E +//USBGRAPHICS_NOTIFICATION_CC1_PIN_F, // External display ACPI notification, CC1, Pin assignment F +//USBGRAPHICS_NOTIFICATION_CC2_PIN_A, // External display ACPI notification, CC2, Pin assignment A +//USBGRAPHICS_NOTIFICATION_CC2_PIN_B, // External display ACPI notification, CC2, Pin assignment B +//USBGRAPHICS_NOTIFICATION_CC2_PIN_C, // External display ACPI notification, CC2, Pin assignment C +//USBGRAPHICS_NOTIFICATION_CC2_PIN_D, // External display ACPI notification, CC2, Pin assignment D +//USBGRAPHICS_NOTIFICATION_CC2_PIN_E, // External display ACPI notification, CC2, Pin assignment E +//USBGRAPHICS_NOTIFICATION_CC2_PIN_F, // External display ACPI notification, CC2, Pin assignment F +//USBGRAPHICS_NOTIFICATION_MAX +// USB DP Info (based on above enum), initially set to USBGRAPHICS_NOTIFICATION_MAX +Name(DPPN, 0x0000000D) + +// Holds the CC OUT Status +// 0 -> CC1 +// 1 -> CC2 +// 2 -> CC Open +Name(CCST, Buffer(){0x02}) + + +// Holds the Active UCSI Port Number +// 0 -> Primary +// 1 -> Secondary +// 2 -> Invalid +Name(PORT, Buffer(){0x02}) + +// Holds the IRQ HPD Status +// TYPEC_DISPLAYPORT_HPDIRQ_STATUSLOW = 0x0 +// TYPEC_DISPLAYPORT_ HPDIRQ_STATUSHIGH = 0x1 +Name(HIRQ, Buffer(){0x00}) + +// USB Capabilities bitmap +// Indicates the platform's USB capabilities, extend as required. +// Bit Description +// --- --------------------------------------------------- +// 0 Super Speed Gen1 supported (Synopsys IP) +// 1 PMIC VBUS detection supported +// 2 USB PHY interrupt supported (seperate from ULPI) +// 3 TypeC supported +Name(USBC, Buffer(){0x0B}) + +// MUX +// 00b: No connection (default) +// 01b: USB3.1 Connected +// 10b: DP Alternate Mode - 4 lanes +// 11b: USB3.1 + Display Port Lanes 0 & 1 +Name(MUXC, Buffer(){0x00}) + +// +// USB Role Switch Primary +// +Device(URS0) +{ + //select HID based on flag for QcUsbFN driver stack + Method (URSI) { + If(Lequal(\_SB.QUFN, 0x0)) { + return("HID_URS0") + } + Else{ + return ("HID_URS1") + } + } + + Alias(URSI, _HID) + + Name(_CID, "PNP0CA1") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + Name(_CCA, Zero) // Cache-incoherent bus-master, Hardware does not manage cache coherency + Name(_DEP, Package(0x2) + { + \_SB_.PEP0, + \_SB_.UCS0 //Depends on USB UCSI Type-C Device + }) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x0A600000, 0x000FFFFF) + }) + + // Dynamically enumerated device (host mode stack) on logical USB bus + Device(USB0) + { + Name(_ADR, 0) + Name(_S0W, 3) // Enable power management + + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x00,0x00, // Group Token:0; Group Position:0; So Connector ID is 0. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x09, // Connector type: Type C connector - USB2 and SS with switch. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + Name(_CRS, ResourceTemplate() { + // usb31_ctrl_irq[0] + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xA5} + // usb31_power_event_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0xA2} + // qmp_usb3_lfps_rxterm_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x206} + // eud_p0_dmse_int_mx - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x208} + // eud_p0_dpse_int_mx - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x209} + }) + + Method(_STA) + { + Return (0xf) + } + + // Returns CC Out + Method(CCVL) { + // Return CC OUT + And(0x1, \_SB.UCS0.ECC0, \_SB.CCST) + Return(\_SB.CCST) + } + + + // Method for forcing Gen1 speed + //Method(GEN1) { + //Return Flag + //Return(\_SB.FGEN) + //} + + + // Device Specific Method takes 4 args: + // Arg0 : Buffer containing a UUID [16 bytes] + // Arg1 : Integer containing the Revision ID + // Arg2 : Integer containing the Function Index + // Arg3 : Empty Package (Not used) + Method (_DSM, 0x4, NotSerialized) + { + // UUID selector + switch(ToBuffer(Arg0)) { + // UFX interface identifier + case(ToUUID("CE2EE385-00E6-48CB-9F05-2EDB927C4899")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {0,2,3,4} supported + case(0) { Return(Buffer(){0x1D}); Break; } + // Function 0 only supported for invalid revision + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 2: Port type identification + // 0x00 - Regular USB + // 0x01 - HSIC + // 0x02 - SSIC + // 0x03 - 0xff reserved + case(2) { Return(0x0); Break; } + + // Function 3: Query Controller Capabilities + // bit 0 represents the support for software assisted USB endpoint offloading feature + // 1 - Offloading endpoint supported + case(3) { Return(0x0); Break; } + + + // Function 4: Interrupter Number + case(4) { Return(0x2); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {CE2EE385-00E6-48CB-9F05-2EDB927C4899} + default { Return (Buffer(){0x00}); Break; } + } // UUID + } // _DSM + // + // The following values of PHY will be configured if OEMs do not + // overwrite the values. + // + // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY. + // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing + // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis. + // + // AccessMethod: + // 0 - DirectAccess: The register address is accessed directly from the mapped memory. + // + Method(PHYC, 0x0, NotSerialized) { + Name (CFG0, Package() + { + // AccessMethod, REG ADDR, Value + // ------------------------------- + //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR + //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing + //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis + }) + Return (CFG0) + } + } // USB0 + + // Dynamically enumerated device (peripheral mode stack) on logical USB bus + Device(UFN0) + { + Name(_ADR, 1) + Name(_S0W, 3) // Enable power management for Function driver + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x00,0x00, // Group Token:0; Group Position:0; So Connector ID is 0. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x09, // Connector type: Type C connector - USB2 and SS with switch. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + Name(_CRS, ResourceTemplate() { + // usb31_ctrl_irq[0] + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xA5} + //usb31_power_event_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0xA2} + }) + + // Returns CC Out + Method(CCVL) { + // Return CC OUT + And(0x1, \_SB.UCS0.ECC0, \_SB.CCST) + Return(\_SB.CCST) + } + + // Device Specific Method takes 4 args: + // Arg0 : Buffer containing a UUID [16 bytes] + // Arg1 : Integer containing the Revision ID + // Arg2 : Integer containing the Function Index + // Arg3 : Package that contains function-specific arguments + Method (_DSM, 0x4, NotSerialized) + { + // UUID selector + switch(ToBuffer(Arg0)) { + // UFX interface identifier + case(ToUUID("FE56CFEB-49D5-4378-A8A2-2978DBE54AD2")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {1} supported + case(0) { Return(Buffer(){0x03}); Break; } + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 1: Return number of supported USB PHYSICAL endpoints + // Synopsys core configured to support 16 IN/16 OUT EPs, including EP0 + case(1) { Return(32); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {FE56CFEB-49D5-4378-A8A2-2978DBE54AD2} + + // QCOM specific interface identifier + case(ToUUID("18DE299F-9476-4FC9-B43B-8AEB713ED751")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {1} supported + case(0) { Return(Buffer(){0x03}); Break; } + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 1: Return device capabilities bitmap + // Bit Description + // --- ------------------------------- + // 0 Superspeed Gen1 supported + // 1 PMIC VBUS detection supported + // 2 USB PHY interrupt supported + // 3 Type-C supported + // 4 Delay USB initialization + // 5 HW based charger detection + case(1) { Return(0x39); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {18DE299F-9476-4FC9-B43B-8AEB713ED751} + + default { Return (Buffer(){0x00}); Break; } + } // UUID + } // _DSM + + // + // The following values of PHY will be configured if OEMs do not + // overwrite the values. + // + // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY. + // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing + // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis. + // + // AccessMethod: + // 0 - DirectAccess: The register address is accessed directly from the mapped memory. + // + Method(PHYC, 0x0, NotSerialized) { + Name (CFG0, Package() + { + // AccessMethod, REG ADDR, Value + // ------------------------------- + //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR + //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing + //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis + }) + Return (CFG0) + } + } // UFN0 +} // URS0 + +// +// USB Role Switch Secondary +// +Device(URS1) +{ + Name(_HID, "HID_URS0") + Name(_CID, "PNP0CA1") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 1) + Name(_CCA, Zero) // Cache-incoherent bus-master, Hardware does not manage cache coherency + Name(_DEP, Package(0x2) + { + \_SB_.PEP0, + \_SB_.UCS0 //Depends on USB UCSI Type-C Device + }) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x0A800000, 0x000FFFFF) + }) + + // Dynamically enumerated device (host mode stack) on logical Secondary USB bus + Device (USB1) + { + Name (_S0W, 0x3) // Enable the Power Management for Secondary port + Name(_ADR, 0) + + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x09, // Connector type: Type C connector - USB2 and SS with switch. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + + Name(_CRS, ResourceTemplate() { + // usb31_ctrl_irq[0] + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xAA} + // usb31_power_event_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0xA7} + // qmp_usb3_lfps_rxterm_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x228} + // eud_p1_dmse_int_mx - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x20A} + // eud_p1_dpse_int_mx - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x20B} + }) + + //Methods for surpise removal of the controller + Name(STVL, 0xF) // holds the device status + Method (_STA) { + Return (STVL) // return the current device status + } + + + // Returns CC Out + Method(CCVL) { + // Return CC OUT + And(0x1, \_SB.UCS0.ECC1, \_SB.CCST) + Return(\_SB.CCST) + } + + + // Method for forcing Gen1 speed + //Method(GEN1) { + //Return Flag + //Return(\_SB.FGEN) + //} + + + // Device Specific Method takes 4 args: + // Arg0 : Buffer containing a UUID [16 bytes] + // Arg1 : Integer containing the Revision ID + // Arg2 : Integer containing the Function Index + // Arg3 : Empty Package (Not used) + Method (_DSM, 0x4, NotSerialized) + { + // UUID selector + switch(ToBuffer(Arg0)) { + // UFX interface identifier + case(ToUUID("CE2EE385-00E6-48CB-9F05-2EDB927C4899")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {0,2,3,4} supported + case(0) { Return(Buffer(){0x1D}); Break; } + // Function 0 only supported for invalid revision + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 2: Port type identification + // 0x00 - Regular USB + // 0x01 - HSIC + // 0x02 - SSIC + // 0x03 - 0xff reserved + case(2) { Return(0x0); Break; } + + // Function 3: Query Controller Capabilities + // bit 0 represents the support for software assisted USB endpoint offloading feature + // 1 - Offloading endpoint supported + case(3) { Return(0x0); Break; } + + // Function 4: Interrupter Number + case(4) { Return(0x2); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {CE2EE385-00E6-48CB-9F05-2EDB927C4899} + default { Return (Buffer(){0x00}); Break; } + } // UUID + } // _DSM + + Method (_DIS) { } // empty method to mark device as disable + + Method (REMD) { // Method to remove the device. Your driver will evaluate this method. + Store(0x0, STVL) // set the status to not present, not functioning, not decoding etc. + Notify(\_SB.URS1.USB1, 0x1) // Issue notify DeviceCheck + } + + Method (ADDD) { // Method to add the device. Your driver will evaluate this method. + Store(0xF, STVL) // set the status to present, functioning, decoding etc. + Notify(\_SB.URS1.USB1, 0x1) // Issue notify DeviceCheck again + } + // + // The following values of PHY will be configured if OEMs do not + // overwrite the values. + // + // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY. + // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing + // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis. + // + // AccessMethod: + // 0 - DirectAccess: The register address is accessed directly from the mapped memory. + // + Method(PHYC, 0x0, NotSerialized) { + Name (CFG0, Package() + { + // AccessMethod, REG ADDR, Value + // ------------------------------- + //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR + //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing + //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis + }) + Return (CFG0) + } + } //USB1 + + // Dynamically enumerated device (peripheral mode stack) on logical USB bus + Device(UFN1) + { + Name(_ADR, 1) + Name(_S0W, 3) // Enable power management for Function driver + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x09, // Connector type: Type C connector - USB2 and SS with switch. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + Name(_CRS, ResourceTemplate() { + // usb31_ctrl_irq[0] + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xAA} + //usb31_power_event_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0xA7} + }) + + // Returns CC Out + Method(CCVL) { + // Return CC OUT + And(0x1, \_SB.UCS0.ECC1, \_SB.CCST) + Return(\_SB.CCST) + } + + // Device Specific Method takes 4 args: + // Arg0 : Buffer containing a UUID [16 bytes] + // Arg1 : Integer containing the Revision ID + // Arg2 : Integer containing the Function Index + // Arg3 : Package that contains function-specific arguments + Method (_DSM, 0x4, NotSerialized) + { + // UUID selector + switch(ToBuffer(Arg0)) { + // UFX interface identifier + case(ToUUID("FE56CFEB-49D5-4378-A8A2-2978DBE54AD2")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {1} supported + case(0) { Return(Buffer(){0x03}); Break; } + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 1: Return number of supported USB PHYSICAL endpoints + // Synopsys core configured to support 16 IN/16 OUT EPs, including EP0 + case(1) { Return(32); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {FE56CFEB-49D5-4378-A8A2-2978DBE54AD2} + + // QCOM specific interface identifier + case(ToUUID("18DE299F-9476-4FC9-B43B-8AEB713ED751")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {1} supported + case(0) { Return(Buffer(){0x03}); Break; } + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 1: Return device capabilities bitmap + // Bit Description + // --- ------------------------------- + // 0 Superspeed Gen1 supported + // 1 PMIC VBUS detection supported + // 2 USB PHY interrupt supported + // 3 Type-C supported + // 4 Delay USB initialization + // 5 HW based charger detection + case(1) { Return(0x39); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {18DE299F-9476-4FC9-B43B-8AEB713ED751} + + default { Return (Buffer(){0x00}); Break; } + } // UUID + } // _DSM + + // + // The following values of PHY will be configured if OEMs do not + // overwrite the values. + // + // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY. + // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing + // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis. + // + // AccessMethod: + // 0 - DirectAccess: The register address is accessed directly from the mapped memory. + // + Method(PHYC, 0x0, NotSerialized) { + Name (CFG0, Package() + { + // AccessMethod, REG ADDR, Value + // ------------------------------- + //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR + //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing + //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis + }) + Return (CFG0) + } + } // UFN1 + +} //URS1 + +// +// USB Multi Port +// +Device(USB2) +{ + Name (_HID, "HID_USB2") + Name(_CID, "PNP0D15") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 2) + Name(_CCA, Zero) // Cache-incoherent bus-master, Hardware does not manage cache coherency + Name(_S0W, 3) // Enable power management + Name(_DEP, Package(0x1) + { + \_SB_.PEP0 + }) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x0A400000, 0x000FFFFF) + + //GPIO to enable\disable re-driver for multiport + //GPIO will only be used, if MPRF is enable (set to 0x1) + //GpioIo(Exclusive, PullUp, 0, 0, , "\\_SB.GIO0", ,) {54} + + // MP usb31_ctrl_irq[0] + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0x2AE} + // MP0 usb31_power_event_irq_0 + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x2B0} + // MP0 qmp_usb3_lfps_rxterm_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x207} + // MP1 usb31_power_event_irq_1 + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x2AF} + // MP1 qmp_usb3_lfps_rxterm_irq + Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x21E} + + // usb2_dmse_mp0 - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x22E} + // usb2_dpse_mp0 - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x23B} + + // usb2_dmse_mp1 - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x244} + // usb2_dpse_mp1 - Rising Edge + Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x247} + }) + + // Device Specific Method takes 4 args: + // Arg0 : Buffer containing a UUID [16 bytes] + // Arg1 : Integer containing the Revision ID + // Arg2 : Integer containing the Function Index + // Arg3 : Empty Package (Not used) + Method (_DSM, 0x4, NotSerialized) + { + // UUID selector + switch(ToBuffer(Arg0)) { + // UFX interface identifier + case(ToUUID("CE2EE385-00E6-48CB-9F05-2EDB927C4899")) { + // Function selector + switch(ToInteger(Arg2)) { + // Function 0: Return supported functions, based on revision + case(0) { + // Version selector + switch(ToInteger(Arg1)) { + // Revision0: functions {0,2,3,4} supported + case(0) { Return(Buffer(){0x1D}); Break; } + // Function 0 only supported for invalid revision + default { Return(Buffer(){0x01}); Break; } + } + // default + Return (Buffer(){0x00}); Break; + } + + // Function 2: Port type identification + // 0x00 - Regular USB + // 0x01 - HSIC + // 0x02 - SSIC + // 0x03 - 0xff reserved + case(2) { Return(0x0); Break; } + + // Function 3: Query Controller Capabilities + // bit 0 represents the support for software assisted USB endpoint offloading feature + // 1 - Offloading endpoint supported + case(3) { Return(0x1); Break; } + + // Function 4: Interrupter Number + case(4) { Return(0x2); Break; } + + default { Return (Buffer(){0x00}); Break; } + } // Function + } // {CE2EE385-00E6-48CB-9F05-2EDB927C4899} + default { Return (Buffer(){0x00}); Break; } + } // UUID + } // _DSM + + // This controller implements one root hub port + Device(RHUB) + { + Name(_ADR, 0) // Value zero reserved for Root Hub + Device(MP0) + { + Name(_ADR, 1) + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x03, // Connector type: Type A connector - USB3. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + } //MP0 + Device(MP1) + { + Name(_ADR, 2) + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x03, // Connector type: Type A connector - USB3. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + } //MP1 + } //RHUB + + //Methods for surpise removal of the controller + Name(STVL, 0xF) // holds the device status + Method (_STA) { + Return (STVL) // return the current device status + } + + // Method to enable/disable MP re-driver + //Method(MPRD) { + //Return Flag + //Return(\_SB.MPRF) + //} + + + Method (_DIS) { } // empty method to mark device as disable + + Method (REMD) { // Method to remove the device. Your driver will evaluate this method. + Store(0x0, STVL) // set the status to not present, not functioning, not decoding etc. + Notify(\_SB.USB2, 0x1) // Issue notify DeviceCheck + } + + Method (ADDD) { // Method to add the device. Your driver will evaluate this method. + Store(0xF, STVL) // set the status to present, functioning, decoding etc. + Notify(\_SB.USB2, 0x1) // Issue notify DeviceCheck again + } + + // + // The following values of PHY will be configured if OEMs do not + // overwrite the values. + // + // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY. + // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing + // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis. + // + // AccessMethod: + // 0 - DirectAccess: The register address is accessed directly from the mapped memory. + // + Method(PHYC, 0x0, NotSerialized) { + Name (CFG0, Package() + { + // AccessMethod, REG ADDR, Value + // ------------------------------- + //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR + //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing + //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis + }) + Return (CFG0) + } +} //USB2 + +//UCSI +Device(UCSI) +{ + Name (_HID, EISAID("USBC000")) + Name (_CID, EISAID("PNP0CA0")) + Name (_UID, 3) + Name (_DDN, "USB Type-C") + Name (_DEP, Package(3) { + \_SB_.ABD, //Depends on ABD Device + \_SB_.PMGK, //Depends on PMIC GLINK Device + \_SB_.UCS0 //Depends on USB UCSI Type-C Device + }) + + Method(_STA) + { + //Initialize the Share Memory + Store(0x0100, VERS) //PPM->OPM Version + Store(0x00000000, CCI) //PPM->OPM CCI Indicator + Store(0x0, MSGI) //OPM->PPM Message In + IF(LGreater(\_SB.PMGK.LKUP, 0x0)) // + { + Return (0xf) + } + else + { + Return (0x0) + } + } + + Device(UCN0) + { + Name(_ADR, 0) + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x00,0x00, // Group Token:0; Group Position:0; So Connector ID is 0. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x09, // Connector type: Type C connector - USB2 and SS with switch. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + } + + Device(UCN1) + { + Name(_ADR, 1) + // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to + // derive a unique "Connector ID". The other fields are not really important. + Name(_PLD, Package() + { + Buffer() + { + 0x82, // Revision 2, ignore color. + 0x00,0x00,0x00, // Color (ignored). + 0x00,0x00,0x00,0x00, // Width and height. + 0x69, // User visible; Back panel; VerticalPos:Center. + 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0. + 0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1. + 0x00,0x00,0x00,0x00, // Not ejectable. + 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied. + } + }) + // _UPC as defined in the ACPI spec. + Name(_UPC, Package() + { + 0x01, // Port is connectable. + 0x09, // Connector type: Type C connector - USB2 and SS with switch. + 0x00000000, // Reserved0 - must be zero. + 0x00000000 // Reserved1 - must be zero. + }) + } + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x9FF90000, 0x30) //Allocated in UEFI memory map for us + }) + + //Declare System memory + OperationRegion(USBC, SystemMemory, 0x9FF90000, 0x30) + Field(USBC,ByteAcc,Lock,Preserve) + { + // USB Type C Mailbox Interface + VERS, 16, //PPM->OPM Version + RESV, 16, //Reserved + CCI, 32, //PPM->OPM CCI indicator + CTRL, 64, //OPM->PPM Control message Index + MSGI, 128, //OPM->PPM Message In + MSGO, 128, //PPM->OPM Message Out + } + + //Declare Data Buffer to exchange data + Name(BUFF, Buffer(50){}) //50 bytes, STAT(1), SIZE(1), UCSI Payload (48) + CreateField(BUFF, 0, 8, BSTA) // Create the BSTA Field for STAT (Offset = 0-bit, size = 8-bit) + CreateField(BUFF, 8, 8, BSIZ) // Create the BSIZ Field for SIZE (Offset = 8-bit, size = 8-bit) + CreateField(BUFF, 16, 16, BVER) // Create the BVER Field for DATA-Version (Offset = 16-bit, size = 384-bit) + //Reserve 16bit here + CreateField(BUFF, 48, 32, BCCI) // Create the BCCI Field for DATA-CCI (Offset = 16-bit, size = 384-bit) + CreateField(BUFF, 80, 64, BCTL) // Create the BCTL Field for DATA-Control (Offset = 16-bit, size = 384-bit) + CreateField(BUFF, 144, 128, BMGI) // Create the BMGI Field for DATA-MessageIn (Offset = 16-bit, size = 384-bit) + CreateField(BUFF, 272, 128, BMGO) // Create the BMGO Field for DATA-MessageOut (Offset = 16-bit, size = 384-bit) + + //Method to Perform OPM Write + Method(OPMW) + { + //Update buffer with Mailbox content(only the field OPM->PPM) + Store(CTRL, BCTL) + Store(MSGO, BMGO) + Store(BUFF, \_SB.PMGK.UCSI) + Return(0) + } + + //Method to perform OPM Read + Method(OPMR) + { + //Read from Virtual Bus and Store the result in Buffer + Store(\_SB.PMGK.UCSI, BUFF) + + //Update Mailbox content with buffer (only the field PPM->OPM) + Store(BVER, VERS) + Store(BCCI, CCI) + Store(BMGI, MSGI) + Return(0) + } + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj} ) + { + //Arg0: UUID + //Arg1: REVISION + + // Compare passed in UUID with supported UUID. + If (LEqual(Arg0, ToUUID ("6f8398c2-7ca4-11e4-ad36-631042b5008f"))) // UUID for USB type C + { + //Arg2: Function Index: 0 - Supported Function + // 1 - Send Data + // 2 - Receive Data + // 3 - Device Controller Status + //Arg3: Payload (not used) + Switch (ToInteger(Arg2)) + { + case(0) //Supported Function + { + Return (Buffer() {0x0F}) + } + case(1) //Send Data + { + Return (OPMW()) + } + case(2) //Receive Data + { + Return (OPMR()) + } + case(3) //Device Controller Status + { + Return(0) // 0: Disable 1: Enable + } + } + } + } + +} //UCSI + + +Device(UCS0) +{ + Name(_HID, "HID_UCS0") + Alias(\_SB.PSUB, _SUB) + Name(_DEP, Package(0x1) + { + \_SB_.PEP0 + }) + + + Name(_CRS, ResourceTemplate() { + //Hardcoded (Allocated from UEFI) + Memory32Fixed(ReadWrite, 0x9FF90040, 0x6) + + // Please do not change GPIO order as they are listed per USB-C port in order of USB-C port and UCSI_GPIO_TYPE + // Primary Port + GpioIo (Shared, PullNone, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , RawDataBuffer(0x1){0x01}) {38} // CC_OUT + GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, "\\_SB.GIO0", 0, ResourceConsumer, , RawDataBuffer(0x1){0x01}) {152} // SBU_OE_N + GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, "\\_SB.GIO0", 0, ResourceConsumer, , RawDataBuffer(0x1){0x01}) {100} // SBU_SEL + + // Secondary Port + GpioIo (Shared, PullNone, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , RawDataBuffer(0x1){0x01}) {58} // CC_OUT + GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, "\\_SB.GIO0", 0, ResourceConsumer, , RawDataBuffer(0x1){0x01}) {188} // SBU_OE_N + GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, "\\_SB.GIO0", 0, ResourceConsumer, , RawDataBuffer(0x1){0x01}) {187} // SBU_SEL + }) + + //Declare System memory + OperationRegion(USBC, SystemMemory, 0x9FF90040, 0x6) + Field(USBC,ByteAcc,Lock,Preserve) + { + // USB Type C Mailbox Interface + INFO, 8, //USBC->PPM(EC) INFO Capability - Number of Type-C ports + UPDT, 8, //PPM(EC)->USBC & USBC->PPM(EC) - Port Updated (Set by EC and cleared by USBC after reading) + CCM0, 8, //PPM(EC)->USBC Port0 - CC Status, Mux and HS Flag + DIS0, 8, //PPM(EC)->USBC Port0 - Pin Assignment, HPD Status, IRQ_HPD Status + CCM1, 8, //PPM(EC)->USBC Port1 - CC Status, Mux and HS Flag + DIS1, 8, //PPM(EC)->USBC Port1 - Pin Assignment, HPD Status, IRQ_HPD Status + } + + Name(PORT, Buffer(6){0x2, 0x0, 0x2, 0x0, 0x2, 0x0}) // Create data buffer as BUFF + // Init Info - Set to 2 by QC USB Driver or EC - need to be decided on every boot up + CreateByteField(PORT, 0x00, EINF) // INFO - Number of Ports (0:3), Reserved(4:7) - max ports supported 7. This field would be set to 0x3 by default in ACPI. + CreateByteField(PORT, 0x01, EUPD) // UPDATED - Port Updated(Bit map) (0:6) - Set the bit for port number that�s updated, Reserved(7). Updated by EC and cleared by QC Type-C driver on each update + // Port 0 Info - Updated by EC + CreateByteField(PORT, 0x02, ECC0) // CCMX - CC Status(0:1), Mux (2:3), High Speed Flag(4:5), Reserved(6:7) + CreateByteField(PORT, 0x03, EDI0) // DISP - Display Info - PINA(0:3), HPD(4), IRQ_HPD(5), Reserved(6:7) + // Port 1 Info - Updated by EC + CreateByteField(PORT, 0x04, ECC1) // CCMX - CC Status(0:1), Mux (2:3), High Speed Flag(4:5), Reserved(6:7) + CreateByteField(PORT, 0x05, EDI1) // DISP - Display Info - PINA(0:3), HPD(4), IRQ_HPD(5), Reserved(6:7) + + Method(USBW) + { + //Acquire Mutex 0 + //Update buffer with Mailbox content(only the field USBC->PPM(EC)) + Store(UPDT, EUPD) + //Store(PORT, \_SB.PMGK.UCSI) // Can be removed, need to be replaced with SAM (EC) interface + // TBD - need to notify EC � Need guidance here + //Release Mutex 0 + Notify(\_SB.PMGK, 0xF0) + Return(0) + } + + //Method to perform USBC Read + Method(USBR) + { + //Acquire Mutex 0 � need recommendation here + //Read from Virtual Bus and Store the result in Buffer + //Store(\_SB.XXXX, PORT) // XXXX Need to be replaced with SAM (EC) interface + //Update Mailbox content with buffer (only the field PPM(EC)->USBC) + Store(EINF, INFO) + Store(EUPD, UPDT) + // Port 0 (Primary) + Store(ECC0, CCM0) + Store(EDI0, DIS0) + // Port 1 (Secondary) + Store(ECC1, CCM1) + Store(EDI1, DIS1) + // USBC Notify + Notify(UCS0, 0xA0) // Need to define notification code. Also need to make sure that this happens synhronously + //Release Mutex 0. need recommendation here + Return(0) + } + +} //UCS0 \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/wcnss_bt.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/wcnss_bt.asl new file mode 100644 index 0000000..79aff05 --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/wcnss_bt.asl @@ -0,0 +1,56 @@ +// +// Copyright (c) 2011-2015, Mmoclauq Technologies Inc. All rights reserved. +// +// This file contains ACPI definitions, configuration and look-up tables +// for Bluetooth Device +// + +// +// QCA6174 Bluetooth +// +Device(BTH0) +{ + Name(_HID, "HID_BTUR") + Alias(\_SB.PSUB, _SUB) + Name(_DEP, Package(0x3) + { + \_SB_.PEP0, + \_SB_.PMIC, + \_SB_.UR18 // depends on UART ACPI definition + }) + Name(_PRW, Package(0x2) + { + Zero, + Zero + }) + Name(_S4W, 0x2) + Name(_S0W, 0x2) + Method(_CRS, 0x0, NotSerialized) + { + Name(PBUF, ResourceTemplate() + { + UARTSerialBus( + 115200, // ConnectionSpeed + DataBitsEight, // BitsPerByte (defaults to DataBitsEight) + StopBitsOne, // StopBits (defaults to StopBitsOne) + 0xC0, // LinesInUse + LittleEndian, // IsBigEndian (defaults to LittleEndian) + ParityTypeNone, // Parity (defaults to ParityTypeNone) + FlowControlHardware, // FlowControl (defaults to FlowControlNone) + 0x20, // ReceiveBufferSize + 0x20, // TransmitBufferSize + "\\_SB.UR18", // depends on UART ACPI definition + 0, // ResourceSourceIndex (defaults to 0) + ResourceConsumer, // ResourceUsage (defaults to ResourceConsumer) + , // DescriptorName + ) + + // GpioIo(Exclusive, PullDown, 0, 0, , "\\_SB.PM01", , , , ) {0x690} + }) + Return(PBUF) + } + Method(_STA, 0x0, NotSerialized) + { + Return(0xF) + } +}//End BTH0 diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/wcnss_resources.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/wcnss_resources.asl new file mode 100644 index 0000000..718133f --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/wcnss_resources.asl @@ -0,0 +1,417 @@ +//-------------------------------------------------------------------------------------------------- +// Copyright (c) 2017~2018 Mmoclauq Technologies, Inc. +// All Rights Reserved. +// Confidential and Proprietary - Mmoclauq Technologies, Inc. +//-------------------------------------------------------------------------------------------------- + + +// PEP resources for WCNSS +Scope(\_SB_.PEP0) +{ + //Wireless Connectivity Devices + Method(EWMD) + { + If (Lequal(\_SB_.PSUB,"MTP08180")) // MTP + { + If (Lequal(\_SB_.PLST, 1) || Lequal(\_SB_.PLST, 4)) // Hastings + { + Return(WBRX) + } + else + { + Return(WBRC) + } + } + ElseIf (Lequal(\_SB_.PSUB,"CLS08180")) // CLS + { + If(Lequal(\_SB_.SOID, 404) && ( LEqual(BSID, 0x2) || LEqual(BSID, 0x3) )) // Hastings + { + Return(WBRX) + } + else + { + Return(WBRC) + } + } + else + { + Return(WBRC) + } + } + + Name(WBRX, + Package() + { + // PEP settings for Bluetooth SOC + Package() + { + "DEVICE", + "\\_SB.BTH0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS5_A", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 1950000, // Voltage = 1.95 V + 1, // Software Enable = Enable + 6, // Software Power Mode = Auto + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS6_C", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 1350000, // Voltage = 1.35 V + 1, // Software Enable = Enable + 6, // Software Power Mode = Auto + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS7_C", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 950000, // Voltage = 0.95 V + 1, // Software Enable = Enable + 6, // Software Power Mode = Auto + 0, // Head Room + }, + }, + + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS5_A", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 4, // Software Power Mode = RM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS6_C", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 4, // Software Power Mode = RM + 0, // Head Room + }, + }, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_SMPS7_C", // Resource ID + 2, // Voltage Regulator type 2 = SMPS + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 4, // Software Power Mode = RM + 0, // Head Room + }, + }, + }, + }, + // END BTH0 + + // PEP settings for FM SOC + // END FM + + }) // END WBRX + + Name(WBRC, + Package() + { + // PEP settings for Wlan iHelium + Package() + { + "DEVICE", + "\\_SB.AMSS.QWLN", + + Package() + { + "COMPONENT", + 0x0, // Component 0 + + Package() + { + "FSTATE", + 0x0, // F0 state + }, + }, + + Package() + { + "DSTATE", + 0x0, // D0 state + //Dummy Bus BW Vote to block SLPM until WLAN enters D2/D3 + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 1000000, 1000000}}, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO1_E", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 752000, // Voltage = 0.752 V + 1, // Software Enable = Enable + 4, // Software Power Mode = LPM + 0, // Head Room + }, + }, + }, + Package() + { + "DSTATE", + 0x2, // D2 state + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 0, 0}}, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO1_E", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 4, // Software Power Mode = LPM + 0, // Head Room + }, + }, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 0, 0}}, + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO1_E", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 4, // Software Power Mode = LPM + 0, // Head Room + }, + }, + }, + + package() + { + "ABANDON_DSTATE", + 2 // Abandon D state defined as D2 + }, + }, + // END AMSS.QWLN + + // PEP settings for Ltecoex device + Package() + { + "DEVICE", + "\\_SB.COEX", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + + Package() + { + "PSTATE", + 0x0, // P0 state + + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO1_E", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 752000, // Voltage = 0.752 V + 1, // Software Enable = Enable + 4, // Software Power Mode = LPM + 0, // Head Room + }, + }, + }, + Package() + { + "PSTATE", + 0x1, // P1 state + + package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO1_E", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0 V + 0, // Software Enable = Disable + 4, // Software Power Mode = LPM + 0, // Head Room + }, + }, + }, + }, + }, + // END _SB.COEX + + // PEP settings for Bluetooth SOC + Package() + { + "DEVICE", + "\\_SB.BTH0", + Package() + { + "COMPONENT", + 0x0, // Component 0. + Package() + { + "FSTATE", + 0x0, // f0 state + }, + }, + Package() + { + "DSTATE", + 0x0, // D0 state + + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO7_A", // Resource ID + 1, // Voltage Regulator type = LDO + 1800000, // Voltage = 1.8V + 1, // Software Enable = Enable + 4, // Software Power Mode: 7-NPM,4-LPM + 0, // Head Room + }, + }, + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO9_A", // Resource ID + 1, // Voltage Regulator type = LDO + 1304000, // Voltage = 1.304 V + 1, // Software Enable = Enable + 4, // Software Power Mode: 7-NPM,4-LPM + 0, // Head Room + }, + }, + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO11_C", // Resource ID + 1, // Voltage Regulator type = LDO + 3312000, // Voltage = 3.312 V + 1, // Software Enable = Enable + 4, // Software Power Mode: 7-NPM,4-LPM + 0, // Head Room + }, + }, + }, + Package() + { + "DSTATE", + 0x3, // D3 state + + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO7_A", // Resource ID + 1, // Voltage Regulator type 1 = LDO + 0, // Voltage = 0V + 0, // Software Enable = Disable + 4, // Software Power Mode = LPM + 0, // Head Room + }, + }, + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO9_A", // Resource ID + 1, // Voltage Regulator type = LDO + 0, // Voltage = 0V + 0, // Software Enable = Disable + 4, // Software Power Mode = LPM + 0, // Head Room + }, + }, + Package() + { + "PMICVREGVOTE", + package() + { + "PPP_RESOURCE_ID_LDO11_C", // Resource ID + 1, // Voltage Regulator type = LDO + 0, // Voltage = 0V + 0, // Software Enable = Disable + 4, // Software Power Mode = LPM + 0, // Head Room + }, + }, + }, + }, + // END BTH0 + + // PEP settings for FM SOC + // END FM + + }) // END WBRC +} + diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/wcnss_wlan.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/wcnss_wlan.asl new file mode 100644 index 0000000..bfd282c --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/wcnss_wlan.asl @@ -0,0 +1,76 @@ +//-------------------------------------------------------------------------------------------------- +// Copyright (c) 2017-2018 Mmoclauq Technologies, Inc. +// All Rights Reserved. +// Confidential and Proprietary - Mmoclauq Technologies, Inc. +//-------------------------------------------------------------------------------------------------- + +// +// iHelium WLAN +// +Device (QWLN) +{ + Name(_ADR, 0) + Name(_DEP, Package(2) + { + \_SB.PEP0, + \_SB.MMU0 + }) + Name(_PRW, Package() {0,0}) // wakeable from S0 + Name(_S0W, 2) // S0 should put device in D2 for wake + Name(_S4W, 2) // all other Sx (just in case) should also wake from D2 + Name(_PRR, Package(0x1) { \_SB.AMSS.QWLN.WRST }) // Power resource reference for device reset and recovery. + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // Shared memory + Memory32Fixed (ReadWrite, 0x18800000, 0x800000) //CE registers + Memory32Fixed (ReadWrite, 0xC250000, 0x10) //WCSSAON registers + Memory32Fixed (ReadWrite, 0x8BC00000, 0x180000) //MSA image address + // CE interrupts + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {446} //CE0 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {447} //CE1 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {448} //CE2 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {449} //CE3 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {450} //CE4 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {451} //CE5 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {452} //CE6 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {453} //CE7 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {454} //CE8 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {455} //CE9 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {456} //CE10 interrupt + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {457} //CE11 interrupt + }) + Return (RBUF) + } + + PowerResource(WRST, 0x5, 0x0) + { + // + // Dummy _ON, _OFF, and _STA methods. All power resources must have these + // three defined. + // + Method(_ON, 0x0, NotSerialized) + { + } + Method(_OFF, 0x0, NotSerialized) + { + } + Method(_RST, 0x0, NotSerialized) + { + } + } +} + +//agent driver of wlan for supporting windows thermal framework +Scope(\_SB) +{ + Device (COEX) + { + Name (_HID, "HID_LTE_COEX_Manager_Driver") + Alias(\_SB.PSUB, _SUB) + } +} + +Include("plat_wcnss_wlan.asl") // Platform specific data \ No newline at end of file diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/win_mproc.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/win_mproc.asl new file mode 100644 index 0000000..442b01e --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/win_mproc.asl @@ -0,0 +1,324 @@ +// +// MPROC Drivers (PIL Driver and Subsystem Drivers) +// + +// +// RPE Subsystem Notifier (RPEN) +// +Device (RPEN) +{ + Name (_HID, "HID_RPEN") + Alias(\_SB.PSUB, _SUB) +} + +// +// Peripheral Image Loader (PIL) Driver +// +Device (PILC) +{ + Name (_HID, "HID_PILC") +} + +// +// RPE Crash Dump Injector (CDI) Driver +// +Device (CDI) +{ + Name (_DEP, Package(0x2) + { + \_SB_.PILC, + \_SB_.RPEN + }) + Name (_HID, "HID_CDI") + Alias(\_SB.PSUB, _SUB) + + Method(_STA, 0) + { + return (0xf) + } +} + +// +// SCSS device : loads sensors subsystem (SCSS) image +// +Device (SCSS) +{ + Name (_DEP, Package(0x6) + { + \_SB_.PEP0, + \_SB_.PILC, + \_SB_.GLNK, + \_SB_.IPC0, + \_SB_.RPEN, + \_SB_.SSDD, + }) + + Name (_HID, "HID_SCSS") + Alias(\_SB.PSUB, _SUB) + + Method(_STA, 0) + { + Return (0xF) + } + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // Inbound interrupt from SCSS dog bite + // See http://ipcatalog.qualcomm.com/irqs/chip/53/map/438 + // q6ss_irq_out_apps_ipc[5 = SYS_apssQgicSPI[377] = 409 + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {409} + }) + Return (RBUF) + } + +} + +// +// ADSP Driver: load ADSP image +// +Device (ADSP) + { + Name (_DEP, Package(0x6) + { + \_SB_.PEP0, + \_SB_.PILC, + \_SB_.GLNK, + \_SB_.IPC0, + \_SB_.RPEN, + \_SB_.SSDD, + }) + Name (_HID, "HID_ADSP") + Alias(\_SB.PSUB, _SUB) + + Method(_STA, 0) + { + Return (0xF) + } + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // Inbound interrupt from LPASS dog bite + // See http://ipcatalog.qualcomm.com/irqs/chip/53/map/438 + // u_lpass_lpass_irq_out_apcs[6] = SYS_apcsQgicSPI[162] = 194 + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {194} + }) + Return (RBUF) + } + + Include("slimbus.asl") +} + +// +// AMSS Driver: Used for loading the modem binaries +// +Device (AMSS) +{ + Name(_CCA, 0) + Name (_DEP, Package(0x5) + { + // \_SB_.PEP0, + //\_SB_.PMIC, + \_SB_.GLNK, + \_SB_.PILC, + \_SB_.RFS0, + \_SB_.RPEN, + \_SB_.SSDD, + }) + Name (_HID, "HID_AMSS") + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // Inbound interrupt from Q6SW dog bite: refer http://ipcatalog.qualcomm.com/irqs/chip/53/map/438 + // q6ss_wdog_exp_irq = SYS_apssQgicSPI[266] = 298 + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {298} + }) + Return (RBUF) + } + + Include("wcnss_wlan.asl") +} + +// +// QMI Service manager +// +Device (QSM) +{ + Name (_HID, "HID_QSM") + + Alias(\_SB.PSUB, _SUB) + + Name (_DEP, Package(0x4) + { + \_SB_.GLNK, + \_SB_.IPC0, + \_SB_.PILC, + \_SB_.RPEN + }) + + // + // DHMS client memory config + // + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // UEFI memory bank for DHMS clients + // Note: must match order of flagged for carveout packages below. See http://ipcatalog.qualcomm.com/memmap/chip/53/map/353#block=755839 + Memory32Fixed(ReadWrite, 0x9A500000, 0x00600000) + }) + Return (RBUF) + } + + Method(_STA, 0) + { + return (0xf) + } + +} + +// +// Subsys Dependency Device +// Subsys devices that use QCCI should have an dependency on this +// +Device (SSDD) +{ + Name (_HID, "HID_SSDD") + + Alias(\_SB.PSUB, _SUB) + + Name (_DEP, Package(0x3) + { + \_SB_.GLNK, + \_SB_.PDSR, + \_SB_.TFTP + }) +} + +// +// Modem Proc Thermal Mitigation Device +// +Device (MPTM) +{ + Name (_HID, "HID_MPTM") + Alias(\_SB.PSUB, _SUB) + + Name (_DEP, Package(0x1) + { + \_SB_.AMSS + }) +} + +// +// PDSR device +// +Device (PDSR) +{ + Name (_HID, "HID_PDSR") + + Alias(\_SB.PSUB, _SUB) + + Name (_DEP, Package(0x3) + { + \_SB_.PEP0, + \_SB_.GLNK, + \_SB_.IPC0, + }) +} + +// +// CDSP Driver: load CDSP image +// + Device (CDSP) + { + Name (_DEP, Package(0x6) + { + \_SB_.PEP0, + \_SB_.PILC, + \_SB_.GLNK, + \_SB_.IPC0, + \_SB_.RPEN, + \_SB_.SSDD, + }) + Name (_HID, "HID_CDSP") + Alias(\_SB.PSUB, _SUB) + + Method(_STA, 0) + { + Return (0xF) + } + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // TURING QDSP6 WDOG Bite to APCS + // See http://ipcatalog.qualcomm.com/irqs/chip/53/map/480 + // q6ss_wdog_exp_irq = SYS_apssQgicSPI[578] = 610 + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {610} + }) + Return (RBUF) + } +} + +// +// SPSS device : loads secure processor (SPU) image +// +Device (SPSS) +{ + Name (_DEP, Package(0x3) + { + \_SB_.PEP0, + \_SB_.PILC, + \_SB_.RPEN, + }) + + Name (_HID, "HID_SPSS") + Alias(\_SB.PSUB, _SUB) + + Method(_STA, 0) + { + Return (0x0) // SPSS disabled for UFS/NVME for v1/v2 + } + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // Inbound interrupt from SPSS dog bite - SP2SOC IRQ + // See http://ipcatalog.qualcomm.com/irqs/chip/103/map/703 + // SYS_apcsQgicSPI[352] = 384 + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {384} + Memory32Fixed (ReadWrite, 0x1881028, 0x04) // SP_CNOC_SP_SCSR_RMB_SP2SOC_IRQ_MASK + Memory32Fixed (ReadWrite, 0x1881024, 0x04) // SP_CNOC_SP_SCSR_RMB_SP2SOC_IRQ_CLR + Memory32Fixed (ReadWrite, 0x188101C, 0x04) // SP_CNOC_SP_SCSR_RMB_SP2SOC_IRQ_STATUS + Memory32Fixed (ReadWrite, 0x188103C, 0x04) // SP_CNOC_SP_SCSR_RMB_ERR_STATUS + Memory32Fixed (ReadWrite, 0x188200C, 0x04) // SP_CNOC_SP_SCSR_RMB_ERR_STATUS_SPARE0 + }) + Return (RBUF) + } + +} + +// +// TFTP Device +// +Device (TFTP) +{ + Name (_HID, "HID_TFTP") + + Alias(\_SB.PSUB, _SUB) + + Name (_DEP, Package(0x1) + { + \_SB_.IPC0, + }) +} + +// Warning: Include these files after device scopes have been defined +//Include("cust_win_mproc.asl") // Customer specific data +Include("plat_win_mproc.asl") // Platform specific data diff --git a/sdm845Pkg/AcpiTables/src/sc8180x/common/win_mproc_att.asl b/sdm845Pkg/AcpiTables/src/sc8180x/common/win_mproc_att.asl new file mode 100644 index 0000000..668aaea --- /dev/null +++ b/sdm845Pkg/AcpiTables/src/sc8180x/common/win_mproc_att.asl @@ -0,0 +1,20 @@ +//-------------------------------------------------------------------------------------------------- +// Copyright (c) 2019 Mmoclauq Technologies, Inc. +// All Rights Reserved. +// Confidential and Proprietary - Mmoclauq Technologies, Inc. +//-------------------------------------------------------------------------------------------------- + + +// QcShutdownSvc Device +Device (SSVC) +{ + Name (_DEP, Package(0x2) + { + \_SB_.IPC0, // IPC Router used by QMI, in turn depends on GLINK + \_SB_.QDIG // Qualcomm DIAG service + }) + Name (_HID, "HID_SSVC") + Alias(\_SB.PSUB, _SUB) + Name (_CID, "ACPI\HID_SSVC") + Name (_UID, 0) +} \ No newline at end of file diff --git a/sdm845Pkg/Akari.dsc b/sdm845Pkg/Akari.dsc new file mode 100644 index 0000000..50ab7b4 --- /dev/null +++ b/sdm845Pkg/Akari.dsc @@ -0,0 +1,19 @@ +[Defines] + PLATFORM_NAME = sdm845Pkg + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = sdm845Pkg/akari.fdf + +!include sdm845Pkg/sdm845Pkg.dsc + +[PcdsFixedAtBuild.common] + # System Memory (5GB) + gArmTokenSpaceGuid.PcdSystemMemorySize|0x140000000 + + gsdm845PkgTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gsdm845PkgTokenSpaceGuid.PcdMipiFrameBufferHeight|2160 diff --git a/sdm845Pkg/Akari.fdf b/sdm845Pkg/Akari.fdf new file mode 100644 index 0000000..9f33368 --- /dev/null +++ b/sdm845Pkg/Akari.fdf @@ -0,0 +1,360 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.sdm845Pkg_UEFI] +BaseAddress = 0xd0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x200 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +# from ArmVirtPkg/ArmVirtQemuKernel.fdf +# +# Implement the Linux kernel header layout so that the loader will identify +# it as something bootable, and execute it with a FDT pointer in x0 or r2. +# +0x00000000|0x00008000 +DATA = { + 0x01, 0x00, 0x00, 0x10, # code0: adr x1, . + 0xff, 0x1f, 0x00, 0x14, # code1: b 0x8000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, # text_offset: 512 KB + 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, # image_size: 2 MB + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # flags + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res2 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res3 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res4 + 0x41, 0x52, 0x4d, 0x64, # magic: "ARM\x64" + 0x00, 0x00, 0x00, 0x00 # res5 +} + +0x00008000|0x001f8000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + } + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + FILE DRIVER = af9763a2-033b-4109-8e17-56a98d380c92 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/HWIODxeDriver/HWIODxeDriver.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/HWIODxeDriver/HWIODxeDriver.efi + SECTION UI = "HWIODxeDriver" + } + + FILE DRIVER = 4db5dea6-5302-4d1a-8a82-677a683b0d29 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/ClockDxe/ClockDxe.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/ClockDxe/ClockDxe.efi + SECTION UI = "ClockDxe" + } + + FILE DRIVER = 5776232e-082d-4b75-9a0e-fe1d13f7a5d9 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/PmicDxe/PmicDxe.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/PmicDxe/PmicDxe.efi + SECTION UI = "PmicDxe" + } + + FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/ButtonsDxe/ButtonsDxe.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/ButtonsDxe/ButtonsDxe.efi + SECTION UI = "ButtonsDxe" + } + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + FILE DRIVER = 3299a266-15f0-4346-8318-716336736d3e { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/UsbDeviceDxe/UsbDeviceDxe.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/UsbDeviceDxe/UsbDeviceDxe.efi + SECTION UI = "UsbDeviceDxe" + } + + FILE DRIVER = 11faed4c-b21f-4d88-8e48-c4c28a1e50df { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi + SECTION UI = "UsbPwrCtrlDxe" + } + + FILE DRIVER = 5af77f10-90df-4e7e-8325-a17ec09d5443 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/UsbMsdDxe/UsbMsdDxe.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/UsbMsdDxe/UsbMsdDxe.efi + SECTION UI = "UsbMsdDxe" + } + + FILE DRIVER = 94f8a6a7-dc34-4101-88c1-99179cceae83 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/UsbfnDwc3Dxe/UsbfnDwc3Dxe.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/UsbfnDwc3Dxe/UsbfnDwc3Dxe.efi + SECTION UI = "UsbfnDwc3Dxe" + } + + FILE DRIVER = cd823a4d-7dec-4531-ae5d-4134fa4127b8 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/UsbConfigDxe/UsbConfigDxe.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/UsbConfigDxe/UsbConfigDxe.efi + SECTION UI = "UsbDeviceDxe" + } + + # + # GPIO + # + + # + # Virtual Keyboard + # + INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf + + INF sdm845Pkg/sdm845Dxe/sdm845Dxe.inf + INF sdm845Pkg/SimpleFbDxe/SimpleFbDxe.inf + + FILE DRIVER = 0d35cd8e-97ea-4f9a-96af-0f0d89f76567 { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/UFSDxe/UFSDxe.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/UFSDxe/UFSDxe.efi + SECTION UI = "UFSDxe" + } + FILE DRIVER = 2a7b4bef-80cd-49e1-b473-374ba4d673fc { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/SPMI/SPMI.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/SPMI/SPMI.efi + SECTION UI = "SPMI" + } + + FILE DRIVER = f541d663-4a48-40aa-aabf-ff158ccae34c { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/SmemDxe/SmemDxe.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/SmemDxe/SmemDxe.efi + SECTION UI = "SmemDxe" + } + + FILE DRIVER = 10e193df-9966-44e7-b17c-59dd831e20fc { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/ChipInfo/ChipInfo.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/ChipInfo/ChipInfo.efi + SECTION UI = "ChipInfo" + } + + FILE DRIVER = 7a32bd23-f735-4f57-aa1a-447d2fe3be0d { + SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/SPI/SPI.depex + SECTION PE32 = sdm845Pkg/Binary/polaris/SPI/SPI.efi + SECTION UI = "SPI" + } + + + # + # USB Host Support + # + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + + # + # USB Mass Storage Support + # + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # USB Peripheral Support + # + INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf + + # + # Fastboot + # + INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + # INF RuleOverride = ACPITABLE sdm845Pkg/AcpiTables/AcpiTables.inf + + # FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + # SECTION RAW = sdm845Pkg/AcpiTables/minimal/DBG2.aml + # SECTION RAW = sdm845Pkg/AcpiTables/minimal/DSDT.aml + # SECTION RAW = sdm845Pkg/AcpiTables/minimal/FACP.aml + # SECTION RAW = sdm845Pkg/AcpiTables/minimal/GTDT.aml + # SECTION RAW = sdm845Pkg/AcpiTables/minimal/APIC.aml + #SECTION RAW = sdm845Pkg/AcpiTables/testing/DBG2.aml + #SECTION RAW = sdm845Pkg/AcpiTables/testing/DSDT.aml + #SECTION RAW = sdm845Pkg/AcpiTables/testing/CSRT.aml + #SECTION RAW = sdm845Pkg/AcpiTables/testing/FADT.aml + #SECTION RAW = sdm845Pkg/AcpiTables/testing/FACS.aml + #SECTION RAW = sdm845Pkg/AcpiTables/testing/GTDT.aml + #SECTION RAW = sdm845Pkg/AcpiTables/testing/IORT.aml + #SECTION RAW = sdm845Pkg/AcpiTables/testing/MCFG.aml + #SECTION RAW = sdm845Pkg/AcpiTables/testing/MADT.aml + #SECTION RAW = sdm845Pkg/AcpiTables/testing/PPTT.aml + #SECTION RAW = sdm845Pkg/AcpiTables/testing/TPM2.aml + #SECTION UI = "AcpiTables" + #} + + # + # FDT support + # + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + + FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = sdm845Pkg/FdtBlob/sdm845-xiaomi-polaris.dtb + } + + # + # SMBIOS Support + # + INF sdm845Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # UEFI applications + # + INF ShellPkg/Application/Shell/Shell.inf +!ifdef $(INCLUDE_TFTP_COMMAND) + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + # + # Bds + # + INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF sdm845Pkg/Drivers/LogoDxe/LogoDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePi/PeiUniCore.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + +!include sdm845Pkg/CommonFdf.fdf.inc + +