--- /dev/null
+//
+// NOTE: The 3rd parameter (i.e. ComplianceRevision) must be >=2 for 64-bit integer support.
+//
+DefinitionBlock("DSDT.AML", "DSDT", 0x02, "QCOMM ", "SDM850 ", 3)
+{
+ Scope(\_SB_) {
+
+ Include("../Common/addSub.asl")
+ Include("dsdt_common.asl")
+ Include("cust_dsdt.asl")
+
+ Include("usb.asl")
+
+ // Thermal Zone devices depend on PEP (included in dsdt_common). Please be CAREFUL on location
+ Include("cust_thermal_zones.asl")
+
+ //
+ // Hardware Notifications
+ //
+ Include("cust_hwn.asl")
+
+ //
+ // Touch
+ //
+ Include("cust_touch.asl")
+
+ //
+ // Buttons
+ //
+ Include("cust_arraybutton.asl")
+
+ //
+ // Data components
+ //
+ Include("../Common/data.asl")
+
+ //
+ //Qualcomm Diagnostic Consumer Interface
+ //
+ Device (QDCI)
+ {
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.GLNK
+ })
+ Name (_HID, "QCOM0224")
+ Alias(\_SB.PSUB, _SUB)
+ }
+
+ //
+ // Bluetooth
+ //
+ Include("../Common/wcnss_bt.asl")
+
+ //
+ // ADC driver
+ //
+ Include("adc.asl")
+ }
+
+}
--- /dev/null
+/*============================================================================
+ FILE: adc.asl
+
+ OVERVIEW: This file contains the board-specific configuration info for
+ ADC1 - qcadc analog-to-digital converter (ADC): ACPI device
+ definitions, common settings, etc.
+
+ DEPENDENCIES: None
+
+============================================================================*/
+
+/*----------------------------------------------------------------------------
+ * QCADC
+ * -------------------------------------------------------------------------*/
+
+Device(ADC1)
+{
+ /*----------------------------------------------------------------------------
+ * Dependencies
+ * -------------------------------------------------------------------------*/
+ Name(_DEP, Package(0x2)
+ {
+ \_SB_.SPMI,
+ \_SB_.PMIC
+ })
+
+ /*----------------------------------------------------------------------------
+ * HID
+ * -------------------------------------------------------------------------*/
+ Name(_HID, "QCOM0221")
+ Alias(\_SB.PSUB, _SUB)
+ Name(_UID, 0)
+
+ /*----------------------------------------------------------------------------
+ * ADC Resources
+ * -------------------------------------------------------------------------*/
+ Method(_CRS)
+ {
+ /*
+ * Interrupts
+ */
+ Name (INTB, ResourceTemplate()
+ {
+ // VAdc - EOC
+ // ID = {slave id}{perph id}{int} = {0}{0011 0001}{000} = 0x188
+ GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {32} // 0x188 - PM_INT__VADC_HC1_USR__EOC
+
+ // VAdc TM - All interrupts
+ // ID = {slave id}{perph id}{int} = {0}{0011 0100}{000} = 0x1A0
+ GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {40} // 0x1A0 - PM_INT__VADC_HC7_BTM__THR
+
+ // FgAdc - All interrupts
+ // ID = {slave id}{perph id}{int} = {10}{0100 0101}{000} = 0x1228
+ GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {360} // 0x1228 - PM_INT__FG_ADC__BT_ID
+ })
+
+ /*
+ * SPMI peripherals
+ */
+ Name(NAM, Buffer() {"\\_SB.SPMI"})
+
+ // VAdc
+ Name(VUSR, Buffer()
+ {
+ 0x8E, // SPB Descriptor
+ 0x13, 0x00, // Length including NAM above
+ 0x01, // +0x00 SPB Descriptor Revision
+ 0x00, // +0x01 Resource Source Index
+ 0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff
+ 0x02, // +0x03 Consumer + controller initiated
+ 0x00, 0x31, // +0x04 Type specific flags . Slave id, Upper8 bit address
+ 0x01, // +0x06 Type specific revision
+ 0x00, 0x00 // +0x07 type specific data length
+ // +0x09 - 0xd bytes for NULL-terminated NAM
+ // Length = 0x13
+ })
+
+ // VAdc TM
+ Name(VBTM, Buffer()
+ {
+ 0x8E, // SPB Descriptor
+ 0x13, 0x00, // Length including NAM above
+ 0x01, // +0x00 SPB Descriptor Revision
+ 0x00, // +0x01 Resource Source Index
+ 0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff
+ 0x02, // +0x03 Consumer + controller initiated
+ 0x00, 0x34, // +0x04 Type specific flags . Slave id, Upper8 bit address
+ 0x01, // +0x06 Type specific revision
+ 0x00, 0x00 // +0x07 type specific data length
+ // +0x09 - 0xd bytes for NULL-terminated NAM
+ // Length = 0x13
+ })
+
+ // FgAdc
+ Name(FGRR, Buffer()
+ {
+ 0x8E, // SPB Descriptor
+ 0x13, 0x00, // Length including NAM above
+ 0x01, // +0x00 SPB Descriptor Revision
+ 0x00, // +0x01 Resource Source Index
+ 0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff
+ 0x02, // +0x03 Consumer + controller initiated
+ 0x02, 0x45, // +0x04 Type specific flags . Slave id, Upper8 bit address
+ 0x01, // +0x06 Type specific revision
+ 0x00, 0x00 // +0x07 type specific data length
+ // +0x09 - 0xd bytes for NULL-terminated NAM
+ // Length = 0x13
+ })
+
+ // Name(END, Buffer() {0x79, 0x00})
+
+ // {VUSR, NAM, VBTM, NAM, FGRR, NAM, INTB}
+ // {Local1, Local2, Local3, INTB}
+ // {Local4, Local5}
+ // {Local0}
+ Concatenate(VUSR, NAM, Local1)
+ Concatenate(VBTM, NAM, Local2)
+ Concatenate(FGRR, NAM, Local3)
+ Concatenate(Local1, Local2, Local4)
+ Concatenate(Local3, INTB, Local5)
+ Concatenate(Local4, Local5, Local0)
+
+ Return(Local0)
+ }
+
+ /*----------------------------------------------------------------------------
+ * Device configuration
+ * -------------------------------------------------------------------------*/
+ /*
+ * General ADC properties
+ *
+ * bHasVAdc:
+ * Whether or not TM is supported.
+ * 0 - Not supported
+ * 1 - Supported
+ *
+ * bHasTM:
+ * Whether or not TM is supported.
+ * 0 - Not supported
+ * 1 - Supported
+ *
+ * bHasFgAdc:
+ * Whether or not FGADC is supported.
+ * 0 - Not supported
+ * 1 - Supported
+ *
+ */
+ Method (ADDV)
+ {
+ Return (Package()
+ {
+ /* .bHasVAdc = */ 1,
+ /* .bHasTM = */ 1,
+ /* .bHasFgAdc = */ 1,
+ })
+ }
+
+ /*----------------------------------------------------------------------------
+ * Voltage ADC (VADC) Configuration
+ * -------------------------------------------------------------------------*/
+ /*
+ * General VADC properties
+ *
+ * bUsesInterrupts:
+ * End-of-conversion interrupt mode.
+ * 0 - Polling mode
+ * 1 - Interrupt mode
+ *
+ * uFullScale_code:
+ * Full-scale ADC code.
+ *
+ * uFullScale_uV:
+ * Full-scale ADC voltage in uV.
+ *
+ * uReadTimeout_us:
+ * Timeout for reading ADC channels in us.
+ *
+ * uLDOSettlingTime_us:
+ * LDO settling time in us.
+ *
+ * ucMasterID:
+ * Master ID to send the interrupt to.
+ *
+ * ucPmicDevice:
+ * PMIC which has the VAdc.
+ *
+ * usMinDigRev:
+ * Minimum digital version <major> <minor>
+ *
+ * usMinAnaRev:
+ * Minimum analog version <major> <minor>
+ *
+ * ucPerphType:
+ * ADC peripheral type.
+ *
+ */
+ Method (GENP)
+ {
+ Return (Package()
+ {
+ /* .bUsesInterrupts = */ 0,
+ /* .uFullScale_code = */ 0x4000,
+ /* .uFullScale_uV = */ 1875000,
+ /* .uReadTimeout_us = */ 500000,
+ /* .uLDOSettlingTime_us = */ 17,
+ /* .ucMasterID = */ 0,
+ /* .ucPmicDevice = */ 0,
+ /* .usMinDigRev = */ 0x300,
+ /* .usMinAnaRev = */ 0x100,
+ /* .ucPerphType = */ 0x8,
+ })
+ }
+
+ /*===========================================================================
+
+ FUNCTION PTCF
+
+ DESCRIPTION Scales the ADC result from millivolts to 0.001 degrees
+ Celsius using the PMIC thermistor conversion equation.
+
+ DEPENDENCIES None
+
+ PARAMETERS Arg0 [in] ADC result data (uMicroVolts)
+
+ RETURN VALUE Scaled result in mDegC
+
+ SIDE EFFECTS None
+
+ ===========================================================================*/
+ Method (PTCF, 1)
+ {
+ /*
+ * Divide by two to convert from microvolt reading to micro-Kelvin.
+ *
+ * Subtract 273160 to convert the temperature from Kelvin to
+ * 0.001 degrees Celsius.
+ */
+ ShiftRight (Arg0, 1, Local0)
+ Subtract (Local0, 273160, Local0)
+ Return (Local0)
+ }
+
+ /*===========================================================================
+
+ FUNCTION PTCI
+
+ DESCRIPTION Inverse of PTCF - scaled PMIC temperature to microvolts.
+
+ DEPENDENCIES None
+
+ PARAMETERS Arg0 [in] temperature in mDegC
+
+ RETURN VALUE ADC result data (uMicroVolts)
+
+ SIDE EFFECTS None
+
+ ===========================================================================*/
+ Method (PTCI, 1)
+ {
+ Add (Arg0, 273160, Local0)
+ ShiftLeft (Local0, 1, Local0)
+ Return (Local0)
+ }
+
+ /*
+ * VADC channel to GPIO mapping
+ *
+ */
+ Method (VGIO)
+ {
+ Return (Package()
+ {
+ Package()
+ {
+ /* .GPIO = */ 8,
+ /* .aucChannels = */ Buffer(){0x12, 0x32, 0x52, 0x72},
+ },
+
+ Package()
+ {
+ /* .GPIO = */ 9,
+ /* .aucChannels = */ Buffer(){0x13, 0x33, 0x53, 0x73},
+ },
+
+ Package()
+ {
+ /* .GPIO = */ 10,
+ /* .aucChannels = */ Buffer(){0x14, 0x34, 0x54, 0x74},
+ },
+
+ Package()
+ {
+ /* .GPIO = */ 11,
+ /* .aucChannels = */ Buffer(){0x15, 0x35, 0x55, 0x75},
+ },
+
+ Package()
+ {
+ /* .GPIO = */ 12,
+ /* .aucChannels = */ Buffer(){0x16, 0x36, 0x56, 0x76},
+ },
+
+ Package()
+ {
+ /* .GPIO = */ 21,
+ /* .aucChannels = */ Buffer(){0x17, 0x37, 0x57, 0x77, 0x97},
+ },
+
+ Package()
+ {
+ /* .GPIO = */ 22,
+ /* .aucChannels = */ Buffer(){0x18, 0x38, 0x58, 0x78, 0x98},
+ },
+
+ Package()
+ {
+ /* .GPIO = */ 23,
+ /* .aucChannels = */ Buffer(){0x19, 0x39, 0x59, 0x79, 0x99},
+ },
+ })
+ }
+
+ /*----------------------------------------------------------------------------
+ * Voltage ADC Threshold Monitor (VADCTM) Configuration
+ * -------------------------------------------------------------------------*/
+ /*
+ * General VADCTM properties
+ *
+ * eAverageMode:
+ * Obtains N ADC readings and averages them together.
+ * 0 - VADCTM_AVERAGE_1_SAMPLE
+ * 1 - VADCTM_AVERAGE_2_SAMPLES
+ * 2 - VADCTM_AVERAGE_4_SAMPLES
+ * 3 - VADCTM_AVERAGE_8_SAMPLES
+ * 4 - VADCTM_AVERAGE_16_SAMPLES
+ *
+ * eDecimationRatio:
+ * The decimation ratio.
+ * 0 - VADCTM_DECIMATION_RATIO_256
+ * 1 - VADCTM_DECIMATION_RATIO_512
+ * 2 - VADCTM_DECIMATION_RATIO_1024
+ *
+ * uFullScale_code:
+ * Full-scale ADC code.
+ *
+ * uFullScale_uV:
+ * Full-scale ADC voltage in uV.
+ *
+ * ucMasterID:
+ * Master ID to send the interrupt to.
+ *
+ * ucPmicDevice:
+ * PMIC which has the VAdc.
+ *
+ * usMinDigRev:
+ * Minimum digital version <major> <minor>
+ *
+ * usMinAnaRev:
+ * Minimum analog version <major> <minor>
+ *
+ * ucPerphType:
+ * ADC peripheral type.
+ *
+ */
+ Method (VTGN)
+ {
+ Return (Package()
+ {
+ /* .eAverageMode = */ 2,
+ /* .eDecimationRatio = */ 2,
+ /* .uFullScale_code = */ 0x4000,
+ /* .uFullScale_uV = */ 1875000,
+ /* .ucMasterID = */ 0,
+ /* .ucPmicDevice = */ 0,
+ /* .usMinDigRev = */ 0x300,
+ /* .usMinAnaRev = */ 0x100,
+ /* .ucPerphType = */ 0x8,
+ })
+ }
+
+ /*----------------------------------------------------------------------------
+ * Fuel Gauge ADC (FGADC) Configuration
+ * -------------------------------------------------------------------------*/
+ /*
+ * General FGADC properties
+ *
+ * skinTempThreshRange:
+ * Range for skin temperature thresholds
+ *
+ * chgTempThreshRange:
+ * Range for charger temperature thresholds
+ *
+ * uFullScale_code:
+ * Full scale ADC value in code.
+ *
+ * uFullScale_uV:
+ * Full scale ADC value in microvolts.
+ *
+ * uMicroVoltsPerMilliAmps:
+ * Microvolts per milliamp scaling factor.
+ *
+ * uCodePerKelvin:
+ * Code per Kelvin scaling factor.
+ *
+ * uBattIdClipThresh:
+ * Max code for a BATT ID channel.
+ *
+ * uMaxWaitTimeus:
+ * Maximum time to wait for a reading to complete in microseconds.
+ *
+ * uSlaveId:
+ * PMIC slave ID.
+ *
+ * ucPmicDevice:
+ * PMIC which has the VAdc.
+ *
+ * ucPerphType:
+ * ADC peripheral type.
+ *
+ */
+ Method (GENF)
+ {
+ Return (Package()
+ {
+ /* .skinTempThreshRange.nMin = */ 0xFFFFFFE2, // -30
+ /* .skinTempThreshRange.nMax = */ 97,
+ /* .chgTempThreshRange.nMin = */ 0xFFFFFFCE, // -50
+ /* .chgTempThreshRange.nMax = */ 160,
+ /* .uFullScale_code = */ 0x3ff,
+ /* .uFullScale_uV = */ 2500000,
+ /* .uMicroVoltsPerMilliAmps = */ 500,
+ /* .uCodePerKelvin = */ 4,
+ /* .uBattIdClipThresh = */ 820,
+ /* .uMaxWaitTimeUs = */ 5000000,
+ /* .uSlaveId = */ 2,
+ /* .ucPmicDevice = */ 1,
+ /* .ucPerphType = */ 0xD,
+ })
+ }
+
+ /*
+ * FGADC Channel Configuration Table
+ *
+ * The following table is the list of channels the FGADC can read. Below is
+ * a description of each field:
+ *
+ * sName:
+ * Appropriate string name for the channel from AdcInputs.h.
+ *
+ * eChannel:
+ * Which channel.
+ * 0 - FGADC_CHAN_SKIN_TEMP
+ * 1 - FGADC_CHAN_BATT_ID
+ * 2 - FGADC_CHAN_BATT_ID_FRESH
+ * 3 - FGADC_CHAN_BATT_ID_5
+ * 4 - FGADC_CHAN_BATT_ID_15
+ * 5 - FGADC_CHAN_BATT_ID_150
+ * 6 - FGADC_CHAN_BATT_THERM
+ * 7 - FGADC_CHAN_AUX_THERM
+ * 8 - FGADC_CHAN_USB_IN_V
+ * 9 - FGADC_CHAN_USB_IN_I
+ * 10 - FGADC_CHAN_DC_IN_V
+ * 11 - FGADC_CHAN_DC_IN_I
+ * 12 - FGADC_CHAN_DIE_TEMP
+ * 13 - FGADC_CHAN_CHARGER_TEMP
+ * 14 - FGADC_CHAN_GPIO
+ *
+ * eEnable:
+ * Whether or not to enable the channel.
+ * 0 - FGADC_DISABLE
+ * 1 - FGADC_ENABLE
+ *
+ * ucTriggers:
+ * Mask of triggers. Use 0x0 for default trigger configuration.
+ *
+ * scalingFactor.num:
+ * Numerator of the channel scaling
+ *
+ * scalingFactor.den:
+ * Denominator of the channel scaling
+ *
+ * eScaling:
+ * The scaling method to use.
+ * 0 - FGADC_SCALE_TO_MILLIVOLTS
+ * 1 - FGADC_SCALE_BATT_ID_TO_OHMS
+ * 2 - FGADC_SCALE_INTERPOLATE_FROM_MILLIVOLTS (requires uInterpolationTableName)
+ * 3 - FGADC_SCALE_THERMISTOR
+ * 4 - FGADC_SCALE_CURRENT_TO_MILLIAMPS
+ *
+ * uInterpolationTableName:
+ * The name of the lookup table in ACPI that will be interpolated to obtain
+ * a physical value. Note that the physical value (which has default units
+ * of millivolts unless custom scaling function is used) is passed as the
+ * input. This value corresponds to the first column of the table. The
+ * scaled output appears in the physical adc result.
+ * 0 - No interpolation table
+ * WXYZ - Where 'WXYZ' is the interpolation table name
+ *
+ */
+ Method (FCHN)
+ {
+ Return (Package()
+ {
+ /* BATT_ID_OHMS (BATT_ID pin) */
+ Package()
+ {
+ /* .sName = */ "BATT_ID_OHMS",
+ /* .eChannel = */ 1,
+ /* .eEnable = */ 1,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScaling = */ 1,
+ /* .uInterpolationTableName = */ 0,
+ },
+
+ /* BATT_ID_OHMS_FRESH (BATT_ID pin) */
+ Package()
+ {
+ /* .sName = */ "BATT_ID_OHMS_FRESH",
+ /* .eChannel = */ 2,
+ /* .eEnable = */ 1,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScaling = */ 1,
+ /* .uInterpolationTableName = */ 0,
+ },
+
+ /* BATT_THERM (BATT_THERM pin) */
+ Package()
+ {
+ /* .sName = */ "BATT_THERM",
+ /* .eChannel = */ 6,
+ /* .eEnable = */ 1,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScaling = */ 3,
+ /* .uInterpolationTableName = */ 0,
+ },
+
+ /* AUX_THERM (AUX_THERM pin) */
+ Package()
+ {
+ /* .sName = */ "AUX_THERM",
+ /* .eChannel = */ 7,
+ /* .eEnable = */ 1,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScaling = */ 3,
+ /* .uInterpolationTableName = */ 0,
+ },
+
+ /* SKIN_THERM (AUX_THERM pin) */
+ Package()
+ {
+ /* .sName = */ "SKIN_THERM",
+ /* .eChannel = */ 0,
+ /* .eEnable = */ 1,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScaling = */ 3,
+ /* .uInterpolationTableName = */ 0,
+ },
+
+ /* PMIC_TEMP2 (internal sensor) */
+ Package()
+ {
+ /* .sName = */ "PMIC_TEMP2",
+ /* .eChannel = */ 12,
+ /* .eEnable = */ 1,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 3,
+ /* .scalingFactor.den = */ 2,
+ /* .eScaling = */ 2,
+ /* .uInterpolationTableName = */ FGDT,
+ },
+
+ /* CHG_TEMP (internal sensor) */
+ Package()
+ {
+ /* .sName = */ "CHG_TEMP",
+ /* .eChannel = */ 13,
+ /* .eEnable = */ 1,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 3,
+ /* .scalingFactor.den = */ 2,
+ /* .eScaling = */ 2,
+ /* .uInterpolationTableName = */ FGCT,
+ },
+
+ /* USB_IN (USB_IN pin) */
+ Package()
+ {
+ /* .sName = */ "USB_IN",
+ /* .eChannel = */ 8,
+ /* .eEnable = */ 1,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 8,
+ /* .eScaling = */ 0,
+ /* .uInterpolationTableName = */ 0,
+ },
+
+ /* USB_IN_I (USB_IN pin) */
+ Package()
+ {
+ /* .sName = */ "USB_IN_I",
+ /* .eChannel = */ 9,
+ /* .eEnable = */ 1,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScaling = */ 4,
+ /* .uInterpolationTableName = */ 0,
+ },
+
+ /* DC_IN (DC_IN pin) */
+ Package()
+ {
+ /* .sName = */ "DC_IN",
+ /* .eChannel = */ 10,
+ /* .eEnable = */ 1,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 8,
+ /* .eScaling = */ 0,
+ /* .uInterpolationTableName = */ 0,
+ },
+
+ /* DC_IN_I (DC_IN pin) */
+ Package()
+ {
+ /* .sName = */ "DC_IN_I",
+ /* .eChannel = */ 11,
+ /* .eEnable = */ 1,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScaling = */ 4,
+ /* .uInterpolationTableName = */ 0,
+ },
+
+ /* FG_GPIO */
+ Package()
+ {
+ /* .sName = */ "FG_GPIO",
+ /* .eChannel = */ 14,
+ /* .eEnable = */ 0,
+ /* .ucTriggers = */ 0x0,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 2,
+ /* .eScaling = */ 0,
+ /* .uInterpolationTableName = */ 0,
+ },
+ })
+ }
+
+ /*
+ * Die temperature sensor scaling table
+ *
+ * The first column in the table is sensor voltage in millivolts and the
+ * second column is the temperature in milli degrees C.
+ *
+ * Scaling equation:
+ *
+ * milliDegC = (uV - 600000) / 2 + 25000
+ *
+ */
+ Method (FGDT)
+ {
+ Return (Package()
+ {
+ Package(){ 450, 0xFFFF3CB0}, // -50000
+ Package(){ 870, 160000}
+ })
+ }
+
+ /*
+ * NOTE: CHG_TEMP on PMI8998 uses fab-dependent scaling in the driver.
+ * This is the default scaling if no fab-dependent scaling is found.
+ * It corresponds to GF.
+ */
+ /*
+ * Charger temperature sensor scaling table
+ *
+ * The first column in the table is sensor voltage in millivolts and the
+ * second column is the temperature in milli degrees C.
+ *
+ * Scaling equation:
+ *
+ * milliDegC = (1303168 - uV) / 3.784 + 25000
+ *
+ */
+ Method (FGCT)
+ {
+ Return (Package()
+ {
+ Package(){ 1587, 0xFFFF3CB0}, // -50000
+ Package(){ 792, 160000}
+ })
+ }
+}
+
+Include("cust_adc.asl")
--- /dev/null
+// This file contains the Audio Drivers
+// ACPI device definitions, configuration and look-up tables.
+//
--- /dev/null
+// This file contains the Audio Drivers
+// ACPI device definitions, configuration and look-up tables.
+//
+
+//
+//ADCM
+//
+Device (ADCM)
+{
+ Alias(\_SB.PSUB, _SUB)
+
+ // Address object for acpi device enumerated device (ADCM) on parent device bus
+ // Used to identify multiple child if present
+ Name (_ADR, 0)
+
+ // Adding dependency for LPASS SMMU (Defined in HoneyBadgerSmmu_Resources.asl)
+ //Added new dependency for 845+
+ Name (_DEP, Package()
+ {
+ \_SB_.MMU0,
+ \_SB_.IMM0,
+ })
+
+
+ // Child Method lists immediate child of ADCM - That is AUDD (Codec Driver)
+ Method (CHLD)
+ {
+ Return (Package()
+ {
+ "ADCM\\QCOM0240"
+ })
+ }
+
+ // AUDD Driver Configurations
+
+ Device (AUDD)
+ {
+ // Address object for acpi device enumerated device (AUDD) on parent device bus
+ // Used to identify multiple child if present
+ Name (_ADR, 0)
+ Alias(\_SB.PSUB, _SUB)
+
+ // Adding dependency for SPI BUS
+ Name (_DEP, Package()
+ {
+ \_SB_.SPI9,
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ GpioIo(Exclusive, PullNone, 0, 1600, , "\\_SB.GIO0", ,) {64} //RESET
+ GpioInt(Edge, ActiveHigh, Exclusive, PullDown, 0, "\\_SB.GIO0", ,) {256} // GPIO number for interrupt changed for wakeup capability
+ // on target it is GPIO 54
+ GpioIo(Shared, PullUp, 0, 200, IoRestrictionOutputOnly, "\\_SB.GIO0", ,) {49} //USB_AUDIO_EN1
+ // SPI
+ SPISerialBus(
+ 0, // DeviceSelection: chip-select, GPIO, or other line selection
+ , // DeviceSelectionPolarity: defaults to PolarityLow (optional)
+ , // WireMode: defaults to FourWireMode (optional)
+ 8, // DataBitLength
+ , // SlaveMode: defaults to ControllerInitiated (optional)
+ 24000000, // ConnectionSpeed: in Hz (24MHz, wcd supports SPI clock up tp 26MHz)
+ ClockPolarityLow, // ClockPolarity
+ ClockPhaseFirst, // ClockPhase
+ "\\_SB.SPI9", // ResourceSource: SPI bus controller name
+ , // ResourceSourceIndex: defaults to 0 (optional)
+ , // ResourceUsage: defaults to ResourceConsumer (optional)
+ , // DescriptorName: creates name for offset of resource descriptor
+ RawDataBuffer(){
+ 0x00, // Reserved; must be 0
+ 0x00, // spi_mode
+ 0x00, // inter_word_delay_cycles
+ 0x00, // loopback_mode
+ 0x00, // cs_toggle
+ 0x00, // endianness
+ 0x00, // cs_clk_delay_cycles
+ }) // VendorData
+ })
+ Return (RBUF)
+ }
+
+ Method (CHLD)
+ {
+ Name(CH, Package()
+ {
+ "AUDD\\QCOM0277",
+ "AUDD\\QCOM0262",
+ })
+ Return(CH)
+ }
+
+ //
+ //MBHC
+ //
+ Device (MBHC)
+ {
+ // Address object for acpi device enumerated device (MBHC) on parent device bus
+ // Used to identify multiple child if present
+ Name (_ADR, 0)
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate () {
+ //GpioIo(Shared, Pullup, 0, 200, IoRestrictionOutputOnly, "\\_SB.GIO0", ,) {51} //HSJ_US_EURO_SEL/EN2
+ })
+ Return (RBUF)
+ }
+ } // MBHC Device Configurations end
+
+ // Miniport Device Configurations
+ Device (QCRT)
+ {
+ // Address object for acpi device enumerated device (QCRT) on parent device bus
+ // Used to identify multiple child if present
+ // Since, QCRT is second child of AUDD, we have assigned slot-1
+ Name (_ADR, 1)
+ }// Miniport Device Configurations end
+ } // AUDD Driver Configurations end
+} // end Device (ADCM)
--- /dev/null
+///
+// BLCP Method - Backlight control packet method, returns a
+// command buffer for a specific backlight level
+//
+// Input Parameters
+// Backlight level - Integer from 0% to 100%
+//
+// Output Parameters
+//
+// Packet format:
+// +--32bits--+-----variable (8bit alignment)--+
+// | Header | Packet payload |
+// +----------+--------------------------------+
+//
+// For DSI Command packets, payload data must be in this format
+//
+// +-- 8 bits-+----variable (8bit alignment)----+
+// | Cmd Type | Packet Data |
+// +----------+---------------------------------+
+//
+// For I2C Command packets, payload data must be in this format
+//
+// +-- 16 bits-+----variable (8bit alignment)----+
+// | Address | Command Data |
+// +-----------+---------------------------------+
+//
+// All packets must follow with a DWORD header with 0x0
+//
+Name (BLBK, Zero)
+Method (BLCP, 1, Serialized)
+{
+ Name (RBUF, Buffer (0x0100){})
+ Local0 = Zero
+ CreateField (RBUF, (Local0 * 0x08), 0x20, PKHR)
+ Local0 += 0x04
+ CreateField (RBUF, (Local0 * 0x08), 0x08, PKCM)
+ Local0 += One
+ CreateField (RBUF, (Local0 * 0x08), 0x08, PKDS)
+ Local0 += One
+ CreateField (RBUF, (Local0 * 0x08), 0x08, PKUB)
+ Local0 += One
+ CreateField (RBUF, (Local0 * 0x08), 0x08, PKLB)
+ Local0 += One
+ Name (BON, Buffer (0x03)
+ {
+ 0x39, 0x53, 0x28 // 9S$
+ })
+ CreateField (RBUF, (Local0 * 0x08), 0x20, PKH2)
+ Local0 += 0x04
+ CreateField (RBUF, (Local0 * 0x08), 0x20, PKP2)
+ PKH2 = SizeOf (BON)
+ PKP2 = BON /* \_SB_.GPU0.BLCP.BON_ */
+ Local0 += SizeOf (BON)
+ CreateDWordField (RBUF, (Local0 * 0x08), EOF)
+ Local1 = 0;
+ Local2 = 0;
+ If(LLessEqual(Arg0, 0x300))
+ {
+ Local1 = (BLBK / 0x188)
+ Local2 = (BLBK / 0x188)
+ }
+ Else
+ {
+ Local1 = (Arg0 / 0x188)
+ Local2 = (Arg0 / 0x188)
+ BLBK = Arg0
+ }
+ Local1 &= 0xFF
+ ShiftRight(Local2, 8, Local2)
+ Local2 &= 0x03
+ PKHR = 0x04
+ PKCM = 0x39
+ PKDS = 0x51
+ PKUB = Local2
+ PKLB = Local1
+ EOF = Zero
+ Return (RBUF) /* \_SB_.GPU0.BLCP.RBUF */
+}
+
--- /dev/null
+//
+// BLCP Method - Secondary display backlight control packet method, returns a
+// command buffer for a specific backlight level
+//
+// Backlight configuration format is same as BLCP of primary panel in backlightcfg.asl
+//
+Method (BLC2, 1, NotSerialized) {
+
+ // Create Response buffer
+ Name(RBUF, Buffer(0x100){})
+
+ // Details to be populated by OEM based on the platform requirements
+
+ // Return the packet data
+ Return(RBUF)
+}
--- /dev/null
+//
+// Please note that not all the SE engine instances (I2C/SPI/UART) from below asl file can be used directly by icluding in the client ACPI,
+// The corresponding Access Control needs to be enabled from TZ side to get the SE/usecase working End 2 End.
+//
+
+//
+// QUPV3_ID0_SE7 (attached to BT SOC)
+//
+Device (UAR7)
+{
+ Name (_HID, "QCOM0236")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 7)
+ Name (_DEP, Package() { \_SB_.PEP0 })
+ Name (_CCA, 0)
+
+ Method (_CRS)
+ {
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed(ReadWrite, 0x00898000, 0x0004000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {639}
+ GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {48} // UART RX,
+ })
+ Return (RBUF)
+ }
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
+
+//
+// QUPV3_ID1_SE2 (UART Debug port)
+//
+ Device (UARD)
+ {
+ Name (_HID, "QCOM0236")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 10)
+ Name (_DEP, Package() { \_SB_.PEP0 })
+ Name (_CCA, 0)
+
+ Method (_CRS)
+ {
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed(ReadWrite, 0x00A84000, 0x00004000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {386}
+ GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {5} // UART RX
+ })
+ Return (RBUF)
+ }
+ }
+
+//
+// I2C4 - "Core I2C Bus"
+//
+Device (I2C4)
+{
+ Name (_HID, "QCOM0220")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 4)
+ Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
+ Name (_CCA, 0)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0088C000, 0x00004000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {636}
+ })
+ Return (RBUF)
+ }
+}
+
+//
+// I2C5 - "Core I2C Bus"
+//
+Device (I2C6)
+{
+ Name (_HID, "QCOM0220")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 6)
+ Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
+ Name (_CCA, 0)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x894000, 0x00004000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {638}
+ })
+ Return (RBUF)
+ }
+}
+
+//
+// I2C11 - "Core I2C Bus"
+//
+Device (IC11)
+{
+ Name (_HID, "QCOM0220")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 11)
+ Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
+ Name (_CCA, 0)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x00A88000, 0x00004000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {387}
+ })
+ Return (RBUF)
+ }
+}
+
+
+//
+// I2C15 - "Core I2C Bus"
+//
+Device (IC15)
+{
+ Name (_HID, "QCOM0220")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 15)
+ Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
+ Name (_CCA, 0)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x00A98000, 0x00004000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {391}
+ })
+ Return (RBUF)
+ }
+}
+
+
+//SPI9 - EPM
+
+Device (SPI9)
+{
+ Name (_HID, "QCOM021E")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 9)
+ Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP1})
+ Name (_CCA, 0)
+
+ Method (_CRS)
+ {
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed(ReadWrite, 0xA80000, 0x00004000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {385}
+ })
+ Return (RBUF)
+ }
+}
+
+//
+// PEP resources for buses
+//
+Scope(\_SB_.PEP0)
+{
+ Method(BSMD)
+ {
+ Return(BSRC)
+ }
+
+ Method(PQMD)
+ {
+ If (LLess(\_SB.SIDV,0x00020000))
+ {
+ Return(DFS1)
+ }
+ Else
+ {
+ Return(DFS2)
+ }
+ }
+
+ Name(BSRC, Package()
+ {
+ // "\\_SB.UAR7"
+ Package()
+ {
+ "DEVICE", "\\_SB.UAR7",
+
+ Package()
+ {
+ "COMPONENT", 0, // UART resources
+
+ Package()
+ {
+ "FSTATE", 0, // enable UART clocks
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk", 1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk", 1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 1}},
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 1400000000,1666}},
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 148000000, 50000000}},
+ },
+
+ Package()
+ {
+ "FSTATE", 1, // disable UART clocks
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk", 2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk", 2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 2}},
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 0, 0}},
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 0, 0}},
+ },
+
+ Package()
+ {
+ "PSTATE", 0, // enable GPIOs
+ Package(){"TLMMGPIO", Package(){ 45, 0, 1, 0, 1, 0 }},
+ Package(){"TLMMGPIO", Package(){ 46, 0, 1, 0, 0, 0 }},
+ Package(){"TLMMGPIO", Package(){ 47, 0, 1, 0, 0, 0 }},
+ Package(){"TLMMGPIO", Package(){ 48, 0, 1, 0, 1, 0 }},
+ },
+
+ Package()
+ {
+ "PSTATE", 1, // disable GPIOs
+ Package(){"TLMMGPIO", Package(){ 45, 0, 1, 0, 1, 0 }},
+ Package(){"TLMMGPIO", Package(){ 46, 0, 1, 0, 0, 0 }},
+ Package(){"TLMMGPIO", Package(){ 47, 0, 1, 0, 0, 0 }},
+ Package(){"TLMMGPIO", Package(){ 48, 0, 1, 0, 1, 0 }},
+ },
+
+ Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 7372800, 4}}},
+ Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 14745600, 4}}},
+ Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 29491200, 4}}},
+ Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 32000000, 4}}},
+ Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 48000000, 4}}},
+ Package(){"PSTATE", 7, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 64000000, 4}}},
+ Package(){"PSTATE", 8, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 80000000, 4}}},
+ Package(){"PSTATE", 9, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 96000000, 4}}},
+ Package(){"PSTATE", 10, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,102400000, 4}}},
+ Package(){"PSTATE", 11, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,112000000, 4}}},
+ Package(){"PSTATE", 12, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,117964800, 4}}},
+ Package(){"PSTATE", 13, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,128000000, 4}}},
+ },
+
+ Package()
+ {
+ "COMPONENT", 1, // DMA resources
+ Package(){"FSTATE", 0}, // enable DMA clocks
+ Package(){"FSTATE", 1}, // disable DMA clocks
+ },
+ },
+
+ // "\\_SB.UARD"
+ Package()
+ {
+ "DEVICE", 0x2, //Debug device
+ "\\_SB.UARD",
+
+ Package()
+ {
+ "COMPONENT", 0, // UART resources
+
+ Package()
+ {
+ "FSTATE", 0, // enable UART clocks
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk",3, 7372800, 4}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 1}},
+
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}},
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000, 50000000}},
+ },
+
+ Package()
+ {
+ "FSTATE", 1, // disable UART clocks
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 2}},
+
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0}},
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0}},
+ },
+
+ Package()
+ {
+ "PSTATE", 0, // enable GPIOs
+ Package(){"TLMMGPIO", Package(){ 5, 0, 1, 0, 1, 0 }},
+ Package(){"TLMMGPIO", Package(){ 4, 0, 1, 0, 0, 0 }},
+ },
+
+ Package()
+ {
+ "PSTATE", 1, // disable GPIOs
+ Package(){"TLMMGPIO", Package(){ 5, 0, 1, 0, 1, 0 }},
+ Package(){"TLMMGPIO", Package(){ 4, 0, 1, 0, 0, 0 }},
+ },
+
+ Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 7372800, 4}}},
+ Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 14745600, 4}}},
+ Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 29491200, 4}}},
+ Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 32000000, 4}}},
+ Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 48000000, 4}}},
+ Package(){"PSTATE", 7, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 64000000, 4}}},
+ Package(){"PSTATE", 8, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 80000000, 4}}},
+ Package(){"PSTATE", 9, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 96000000, 4}}},
+ Package(){"PSTATE", 10, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,102400000, 4}}},
+ Package(){"PSTATE", 11, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,112000000, 4}}},
+ Package(){"PSTATE", 12, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,117964800, 4}}},
+ Package(){"PSTATE", 13, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,128000000, 4}}},
+ },
+
+ Package()
+ {
+ "COMPONENT", 1, // DMA resources
+ Package(){"FSTATE", 0}, // enable DMA clocks
+ Package(){"FSTATE", 1}, // disable DMA clocks
+ },
+ },
+
+ // "\\_SB.I2C4"
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.I2C4",
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0.
+ Package()
+ {
+ "FSTATE",
+ 0x0, // f0 state
+ },
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x0, // D0 state
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s3_clk",8,19200000, 4}},
+
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 1400000000,1666}},
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 148000000, 50000000}},
+
+ // Configure SDA and then SCL
+ package() {"TLMMGPIO", package() {41, 1, 1, 1, 3, 0}},
+ package() {"TLMMGPIO", package() {42, 1, 1, 1, 3, 0}},
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x1, // D1 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x2, // D2 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x3, // D3 state
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s3_clk",2}},
+
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 0, 0 }},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 0, 0 }},
+
+ // Configure SCL and then SDA
+ package() { "TLMMGPIO", package() {41, 0, 0, 0, 3, 0}},
+ package() { "TLMMGPIO", package() {42, 0, 0, 0, 3, 0}},
+ },
+ },
+
+ // "\\_SB.I2C6"
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.I2C6",
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0.
+ Package()
+ {
+ "FSTATE",
+ 0x0, // f0 state
+ },
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x0, // D0 state
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s5_clk",8,19200000, 4}},
+
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 1400000000,1666}},
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 148000000, 50000000}},
+
+ // Configure SDA and then SCL
+ package() {"TLMMGPIO", package() {85, 1, 1, 1, 3, 0}},
+ package() {"TLMMGPIO", package() {86, 1, 1, 1, 3, 0}},
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x1, // D1 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x2, // D2 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x3, // D3 state
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s5_clk",2}},
+
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 0, 0 }},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 0, 0 }},
+
+ // Configure SCL and then SDA
+ package() { "TLMMGPIO", package() {85, 0, 0, 0, 3, 0}},
+ package() { "TLMMGPIO", package() {86, 0, 0, 0, 3, 0}},
+ },
+ },
+
+ // "\\_SB.IC11"
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.IC11",
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0.
+ Package()
+ {
+ "FSTATE",
+ 0x0, // f0 state
+ },
+
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x0, // D0 state
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s2_clk",8,19200000, 4}},
+
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000}},
+
+ // Configure SDA and then SCL
+ package() {"TLMMGPIO", package() {55, 1, 1, 1, 3, 0}},
+ package() {"TLMMGPIO", package() {56, 1, 1, 1, 3, 0}},
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x1, // D1 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x2, // D2 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x3, // D3 state
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s2_clk",2}},
+
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0 }},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0 }},
+
+ // Configure SCL and then SDA
+ package() { "TLMMGPIO", package() {55, 0, 0, 0, 3, 0}},
+ package() { "TLMMGPIO", package() {56, 0, 0, 0, 3, 0}},
+ },
+ },
+
+ // "\\_SB.IC15"
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.IC15",
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0.
+ Package()
+ {
+ "FSTATE",
+ 0x0, // f0 state
+ },
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x0, // D0 state
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",8,19200000, 4}},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666 }},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000 }},
+
+ // Configure SDA and then SCL
+ package() {"TLMMGPIO", package() {33, 1, 2, 1, 3, 0}},
+ package() {"TLMMGPIO", package() {34, 1, 2, 1, 3, 0}},
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x1, // D1 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x2, // D2 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x3, // D3 state
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",2}},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0 }},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0 }},
+
+ // Configure SCL and then SDA
+ package() { "TLMMGPIO", package() {33, 0, 0, 0, 3, 0}},
+ package() { "TLMMGPIO", package() {34, 0, 0, 0, 3, 0}},
+ },
+ },
+ })
+
+ Name(DFS1, Package()
+ {
+ Package()
+ {
+ "DEVICE", "\\_SB.SPI9",
+
+ Package()
+ {
+ "COMPONENT", 0,
+
+ Package() {"FSTATE", 0},
+
+ Package(){"PSTATE", 0, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 19200000, 3}}},
+ Package(){"PSTATE", 1, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 32000000, 3}}},
+ Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 38400000, 3}}},
+ Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 48000000, 3}}},
+ Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 64000000, 3}}},
+ Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 96000000, 3}}},
+ Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 100000000, 3}}},
+ },
+
+ Package()
+ {
+ "DSTATE", 0, // enable clocks, enable GPIOs
+
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",1}},
+
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000}},
+
+ Package(){"TLMMGPIO", Package(){ 65, 1, 2, 0, 1, 0}}, // MISO
+ Package(){"TLMMGPIO", Package(){ 66, 1, 2, 1, 1, 0}}, // MOSI
+ Package(){"TLMMGPIO", Package(){ 67, 1, 2, 1, 1, 0}}, // CLK
+ Package(){"TLMMGPIO", Package(){ 68, 1, 2, 1, 1, 0}}, // CS
+ },
+
+ Package() {"DSTATE", 1,},
+ Package() {"DSTATE", 2,},
+
+ Package()
+ {
+ "DSTATE", 3, // disable clocks, disable GPIOs
+
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",2}},
+
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0}},
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0}},
+
+ Package(){"TLMMGPIO", Package(){ 65, 0, 2, 0, 1, 0}}, // MOSI
+ Package(){"TLMMGPIO", Package(){ 66, 0, 2, 0, 1, 0}}, // MISO
+ Package(){"TLMMGPIO", Package(){ 67, 0, 2, 0, 1, 0}}, // CS
+ Package(){"TLMMGPIO", Package(){ 68, 0, 2, 0, 1, 0}}, // CLK
+ },
+ },
+ })
+
+ Name(DFS2, Package()
+ {
+ Package()
+ {
+ "DEVICE", "\\_SB.SPI9",
+
+ Package()
+ {
+ "COMPONENT", 0,
+
+ Package() {"FSTATE", 0},
+
+ Package(){"PSTATE", 0, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 19200000, 3}}},
+ Package(){"PSTATE", 1, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 32000000, 3}}},
+ Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 48000000, 3}}},
+ Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 64000000, 3}}},
+ Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 96000000, 3}}},
+ Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 100000000, 3}}},
+ Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 120000000, 3}}},
+ },
+
+ Package()
+ {
+ "DSTATE", 0, // enable clocks, enable GPIOs
+
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",1}},
+
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000}},
+
+
+ Package(){"TLMMGPIO", Package(){ 65, 1, 2, 0, 1, 0}}, // MISO
+ Package(){"TLMMGPIO", Package(){ 66, 1, 2, 1, 1, 0}}, // MOSI
+ Package(){"TLMMGPIO", Package(){ 67, 1, 2, 1, 1, 0}}, // CLK
+ Package(){"TLMMGPIO", Package(){ 68, 1, 2, 1, 1, 0}}, // CS
+ },
+
+ Package() {"DSTATE", 1,},
+ Package() {"DSTATE", 2,},
+
+ Package()
+ {
+ "DSTATE", 3, // disable clocks, disable GPIOs
+
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",2}},
+
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0}},
+ Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0}},
+
+ Package(){"TLMMGPIO", Package(){ 65, 0, 2, 0, 1, 0}}, // MOSI
+ Package(){"TLMMGPIO", Package(){ 66, 0, 2, 0, 1, 0}}, // MISO
+ Package(){"TLMMGPIO", Package(){ 67, 0, 2, 0, 1, 0}}, // CS
+ Package(){"TLMMGPIO", Package(){ 68, 0, 2, 0, 1, 0}}, // CLK
+ },
+ },
+ })
+}
--- /dev/null
+/*============================================================================
+ FILE: cust_adc.asl
+
+ OVERVIEW: This file contains the board-specific configuration info for
+ ADC1 - qcadc analog-to-digital converter (ADC): channel
+ configurations, scaling functions, look-up tables, etc.
+
+ DEPENDENCIES: None
+
+============================================================================*/
+
+/*----------------------------------------------------------------------------
+ * QCADC
+ * -------------------------------------------------------------------------*/
+
+Scope(\_SB.ADC1)
+{
+ /*----------------------------------------------------------------------------
+ * Voltage ADC (VADC) Configuration
+ * -------------------------------------------------------------------------*/
+ /*
+ * VADC Channel Configuration Table
+ *
+ * The following table is the list of channels the ADC can read. Channels may
+ * be added or removed. Below is a description of each field:
+ *
+ * sName:
+ * Appropriate string name for the channel from AdcInputs.h.
+ *
+ * uAdcHardwareChannel:
+ * AMUX channel.
+ *
+ * eSettlingDelay:
+ * Holdoff time to allow the voltage to settle before reading the channel.
+ * 0 - VADC_SETTLING_DELAY_0_US
+ * 1 - VADC_SETTLING_DELAY_100_US
+ * 2 - VADC_SETTLING_DELAY_200_US
+ * 3 - VADC_SETTLING_DELAY_300_US
+ * 4 - VADC_SETTLING_DELAY_400_US
+ * 5 - VADC_SETTLING_DELAY_500_US
+ * 6 - VADC_SETTLING_DELAY_600_US
+ * 7 - VADC_SETTLING_DELAY_700_US
+ * 8 - VADC_SETTLING_DELAY_800_US
+ * 9 - VADC_SETTLING_DELAY_900_US
+ * 10 - VADC_SETTLING_DELAY_1_MS
+ * 11 - VADC_SETTLING_DELAY_2_MS
+ * 12 - VADC_SETTLING_DELAY_4_MS
+ * 13 - VADC_SETTLING_DELAY_6_MS
+ * 14 - VADC_SETTLING_DELAY_8_MS
+ * 15 - VADC_SETTLING_DELAY_10_MS
+ *
+ * eAverageMode:
+ * Obtains N ADC readings and averages them together.
+ * 0 - VADC_AVERAGE_1_SAMPLE
+ * 1 - VADC_AVERAGE_2_SAMPLES
+ * 2 - VADC_AVERAGE_4_SAMPLES
+ * 3 - VADC_AVERAGE_8_SAMPLES
+ * 4 - VADC_AVERAGE_16_SAMPLES
+ *
+ * eDecimationRatio:
+ * The decimation ratio.
+ * 0 - VADC_DECIMATION_RATIO_256
+ * 1 - VADC_DECIMATION_RATIO_512
+ * 2 - VADC_DECIMATION_RATIO_1024
+ *
+ * eCalMethod:
+ * Calibration method.
+ * 0 - VADC_CAL_METHOD_NO_CAL
+ * 1 - VADC_CAL_METHOD_RATIOMETRIC
+ * 2 - VADC_CAL_METHOD_ABSOLUTE
+ *
+ * scalingFactor.num:
+ * Numerator of the channel scaling
+ *
+ * scalingFactor.den:
+ * Denominator of the channel scaling
+ *
+ * eScalingMethod:
+ * The scaling method to use.
+ * 0 - VADC_SCALE_TO_MILLIVOLTS
+ * 1 - VADC_SCALE_INTERPOLATE_FROM_MILLIVOLTS (requires uInterpolationTableName)
+ * 2 - VADC_SCALE_THERMISTOR (requires uPullUp and uInterpolationTableName)
+ *
+ * uPullUp:
+ * The pull up resistor value. Use with eScalingMethod == VADC_SCALE_THERMISTOR,
+ * otherwise, 0.
+ *
+ * uInterpolationTableName:
+ * The name of the lookup table in ACPI that will be interpolated to obtain
+ * a physical value. Note that the physical value (which has default units
+ * of millivolts unless custom scaling function is used) is passed as the
+ * input. This value corresponds to the first column of the table. The
+ * scaled output appears in the physical adc result.
+ * 0 - No interpolation table
+ * WXYZ - Where 'WXYZ' is the interpolation table name
+ *
+ * uScalingFunctionName:
+ * The name of the function to call in the ACPI table to perform custom
+ * scaling. The input to the custom scaling function is defined by
+ * eScalingFunctionInput. The output of the custom scaling function is
+ * the physical value.
+ * 0 - No scaling function
+ * WXYZ - Where 'WXYZ' is the scaling function name
+ *
+ * Note: if both a custon scaling function & interpolation table are used
+ * the custom scaling function is called first.
+ *
+ * eScalingFunctionInput:
+ * Defines which ADC result is passed to the custom scaling function.
+ * 0 - VADC_SCALING_FUNCTION_INPUT_PHYSICAL
+ * 1 - VADC_SCALING_FUNCTION_INPUT_PERCENT
+ * 2 - VADC_SCALING_FUNCTION_INPUT_MICROVOLTS
+ * 3 - VADC_SCALING_FUNCTION_INPUT_CODE
+ *
+ */
+ Method (CHAN)
+ {
+ Return (Package()
+ {
+ /* VPH_PWR (VPH_PWR_SNS pin) */
+ Package()
+ {
+ /* .sName = */ "VPH_PWR",
+ /* .uAdcHardwareChannel = */ 0x83,
+ /* .eSettlingDelay = */ 0,
+ /* .eAverageMode = */ 0,
+ /* .eDecimationRatio = */ 2,
+ /* .eCalMethod = */ 2,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 3,
+ /* .eScalingMethod = */ 0,
+ /* .uPullUp = */ 0,
+ /* .uInterpolationTableName = */ 0,
+ /* .uScalingFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ },
+
+ /* VCOIN (VCOIN pin) */
+ Package()
+ {
+ /* .sName = */ "VCOIN",
+ /* .uAdcHardwareChannel = */ 0x85,
+ /* .eSettlingDelay = */ 0,
+ /* .eAverageMode = */ 0,
+ /* .eDecimationRatio = */ 2,
+ /* .eCalMethod = */ 2,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 3,
+ /* .eScalingMethod = */ 0,
+ /* .uPullUp = */ 0,
+ /* .uInterpolationTableName = */ 0,
+ /* .uScalingFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ },
+
+ /* PMIC_TEMP1 (internal sensor) */
+ Package()
+ {
+ /* .sName = */ "PMIC_THERM",
+ /* .uAdcHardwareChannel = */ 0x6,
+ /* .eSettlingDelay = */ 0,
+ /* .eAverageMode = */ 0,
+ /* .eDecimationRatio = */ 2,
+ /* .eCalMethod = */ 2,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 0,
+ /* .uPullUp = */ 0,
+ /* .uInterpolationTableName = */ 0,
+ /* .uScalingFunctionName = */ PTCF,
+ /* .eScalingFunctionInput = */ 2,
+ },
+
+ /* XO_THERM (XO_THERM pin) */
+ Package()
+ {
+ /* .sName = */ "XO_THERM",
+ /* .uAdcHardwareChannel = */ 0x4c,
+ /* .eSettlingDelay = */ 8,
+ /* .eAverageMode = */ 0,
+ /* .eDecimationRatio = */ 2,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ XTTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ },
+
+ /* XO_THERM_GPS (XO_THERM pin) */
+ Package()
+ {
+ /* .sName = */ "XO_THERM_GPS",
+ /* .uAdcHardwareChannel = */ 0x4c,
+ /* .eSettlingDelay = */ 8,
+ /* .eAverageMode = */ 2,
+ /* .eDecimationRatio = */ 2,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ XTTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ },
+
+ /* SYS_THERM1 (AMUX_1 pin) */
+ Package()
+ {
+ /* .sName = */ "SYS_THERM1",
+ /* .uAdcHardwareChannel = */ 0x4d,
+ /* .eSettlingDelay = */ 1,
+ /* .eAverageMode = */ 0,
+ /* .eDecimationRatio = */ 2,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ SYTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ },
+
+ /* SYS_THERM2 (AMUX_2 pin) */
+ Package()
+ {
+ /* .sName = */ "SYS_THERM2",
+ /* .uAdcHardwareChannel = */ 0x4e,
+ /* .eSettlingDelay = */ 1,
+ /* .eAverageMode = */ 0,
+ /* .eDecimationRatio = */ 2,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ SYTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ },
+
+ /* PA_THERM (AMUX_3 pin) */
+ Package()
+ {
+ /* .sName = */ "PA_THERM",
+ /* .uAdcHardwareChannel = */ 0x4f,
+ /* .eSettlingDelay = */ 1,
+ /* .eAverageMode = */ 0,
+ /* .eDecimationRatio = */ 2,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ SYTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ },
+
+ /* PA_THERM1 (AMUX_4 pin) */
+ Package()
+ {
+ /* .sName = */ "PA_THERM1",
+ /* .uAdcHardwareChannel = */ 0x50,
+ /* .eSettlingDelay = */ 1,
+ /* .eAverageMode = */ 0,
+ /* .eDecimationRatio = */ 2,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ SYTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ },
+
+ /* SYS_THERM3 (AMUX_5 pin) */
+ Package()
+ {
+ /* .sName = */ "SYS_THERM3",
+ /* .uAdcHardwareChannel = */ 0x51,
+ /* .eSettlingDelay = */ 1,
+ /* .eAverageMode = */ 0,
+ /* .eDecimationRatio = */ 2,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ SYTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ },
+ })
+ }
+
+ /*
+ * System Thermistor Table
+ *
+ * The first column in the table is thermistor resistance R_T in ohms
+ * and the second column is the temperature in degrees C.
+ *
+ * VDD ___
+ * |
+ * >
+ * P_PU <
+ * >
+ * |
+ * |
+ * |- - - V_T
+ * |
+ * >
+ * R_T < 100 kOhms (NTCG104EF104FB)
+ * >
+ * |
+ * |
+ * Gnd
+ *
+ */
+ Method (SYTB)
+ {
+ Return (Package()
+ {
+ Package(){4251000, 0xFFFFFFD8}, // -40
+ Package(){3004900, 0xFFFFFFDD}, // -35
+ Package(){2148900, 0xFFFFFFE2}, // -30
+ Package(){1553800, 0xFFFFFFE7}, // -25
+ Package(){1135300, 0xFFFFFFEC}, // -20
+ Package(){ 837800, 0xFFFFFFF1}, // -15
+ Package(){ 624100, 0xFFFFFFF6}, // -10
+ Package(){ 469100, 0xFFFFFFFB}, // -5
+ Package(){ 355600, 0},
+ Package(){ 271800, 5},
+ Package(){ 209400, 10},
+ Package(){ 162500, 15},
+ Package(){ 127000, 20},
+ Package(){ 100000, 25},
+ Package(){ 79200, 30},
+ Package(){ 63200, 35},
+ Package(){ 50700, 40},
+ Package(){ 40900, 45},
+ Package(){ 33200, 50},
+ Package(){ 27100, 55},
+ Package(){ 22200, 60},
+ Package(){ 18300, 65},
+ Package(){ 15200, 70},
+ Package(){ 12600, 75},
+ Package(){ 10600, 80},
+ Package(){ 8890, 85},
+ Package(){ 7500, 90},
+ Package(){ 6360, 95},
+ Package(){ 5410, 100},
+ Package(){ 4620, 105},
+ Package(){ 3970, 110},
+ Package(){ 3420, 115},
+ Package(){ 2950, 120},
+ Package(){ 2560, 125}
+ })
+ }
+
+ /*
+ * XO Thermistor Table
+ *
+ * This lookup table is used to convert the XO thermistor reading to temperature
+ * in degrees C multiplied by a factor of 1024.
+ *
+ * The first column in the table is thermistor resistance R_T in ohms
+ *
+ * The second column is the temperature in degrees Celsius multiplied by a factor
+ * of 1024.
+ *
+ * VDD ___
+ * |
+ * >
+ * P_PU < 100 kOhms
+ * >
+ * |
+ * |
+ * |- - - V_T
+ * |
+ * >
+ * R_T < 100 kOhms (NTCG104EF104FB)
+ * >
+ * |
+ * |
+ * Gnd
+ *
+ */
+ Method (XTTB)
+ {
+ Return (Package()
+ {
+ Package(){4250657, 0xFFFF6000}, // -40960
+ Package(){3962085, 0xFFFF6400}, // -39936
+ Package(){3694875, 0xFFFF6800}, // -38912
+ Package(){3447322, 0xFFFF6C00}, // -37888
+ Package(){3217867, 0xFFFF7000}, // -36864
+ Package(){3005082, 0xFFFF7400}, // -35840
+ Package(){2807660, 0xFFFF7800}, // -34816
+ Package(){2624405, 0xFFFF7C00}, // -33792
+ Package(){2454218, 0xFFFF8000}, // -32768
+ Package(){2296094, 0xFFFF8400}, // -31744
+ Package(){2149108, 0xFFFF8800}, // -30720
+ Package(){2012414, 0xFFFF8C00}, // -29696
+ Package(){1885232, 0xFFFF9000}, // -28672
+ Package(){1766846, 0xFFFF9400}, // -27648
+ Package(){1656598, 0xFFFF9800}, // -26624
+ Package(){1553884, 0xFFFF9C00}, // -25600
+ Package(){1458147, 0xFFFFA000}, // -24576
+ Package(){1368873, 0xFFFFA400}, // -23552
+ Package(){1285590, 0xFFFFA800}, // -22528
+ Package(){1207863, 0xFFFFAC00}, // -21504
+ Package(){1135290, 0xFFFFB000}, // -20480
+ Package(){1067501, 0xFFFFB400}, // -19456
+ Package(){1004155, 0xFFFFB800}, // -18432
+ Package(){ 944935, 0xFFFFBC00}, // -17408
+ Package(){ 889550, 0xFFFFC000}, // -16384
+ Package(){ 837731, 0xFFFFC400}, // -15360
+ Package(){ 789229, 0xFFFFC800}, // -14336
+ Package(){ 743813, 0xFFFFCC00}, // -13312
+ Package(){ 701271, 0xFFFFD000}, // -12288
+ Package(){ 661405, 0xFFFFD400}, // -11264
+ Package(){ 624032, 0xFFFFD800}, // -10240
+ Package(){ 588982, 0xFFFFDC00}, // -9216
+ Package(){ 556100, 0xFFFFE000}, // -8192
+ Package(){ 525239, 0xFFFFE400}, // -7168
+ Package(){ 496264, 0xFFFFE800}, // -6144
+ Package(){ 469050, 0xFFFFEC00}, // -5120
+ Package(){ 443480, 0xFFFFF000}, // -4096
+ Package(){ 419448, 0xFFFFF400}, // -3072
+ Package(){ 396851, 0xFFFFF800}, // -2048
+ Package(){ 375597, 0xFFFFFC00}, // -1024
+ Package(){ 355598, 0},
+ Package(){ 336775, 1024},
+ Package(){ 319052, 2048},
+ Package(){ 302359, 3072},
+ Package(){ 286630, 4096},
+ Package(){ 271806, 5120},
+ Package(){ 257829, 6144},
+ Package(){ 244646, 7168},
+ Package(){ 232209, 8192},
+ Package(){ 220471, 9216},
+ Package(){ 209390, 10240},
+ Package(){ 198926, 11264},
+ Package(){ 189040, 12288},
+ Package(){ 179698, 13312},
+ Package(){ 170868, 14336},
+ Package(){ 162519, 15360},
+ Package(){ 154622, 16384},
+ Package(){ 147150, 17408},
+ Package(){ 140079, 18432},
+ Package(){ 133385, 19456},
+ Package(){ 127046, 20480},
+ Package(){ 121042, 21504},
+ Package(){ 115352, 22528},
+ Package(){ 109960, 23552},
+ Package(){ 104848, 24576},
+ Package(){ 100000, 25600},
+ Package(){ 95402, 26624},
+ Package(){ 91038, 27648},
+ Package(){ 86897, 28672},
+ Package(){ 82965, 29696},
+ Package(){ 79232, 30720},
+ Package(){ 75686, 31744},
+ Package(){ 72316, 32768},
+ Package(){ 69114, 33792},
+ Package(){ 66070, 34816},
+ Package(){ 63176, 35840},
+ Package(){ 60423, 36864},
+ Package(){ 57804, 37888},
+ Package(){ 55312, 38912},
+ Package(){ 52940, 39936},
+ Package(){ 50681, 40960},
+ Package(){ 48531, 41984},
+ Package(){ 46482, 43008},
+ Package(){ 44530, 44032},
+ Package(){ 42670, 45056},
+ Package(){ 40897, 46080},
+ Package(){ 39207, 47104},
+ Package(){ 37595, 48128},
+ Package(){ 36057, 49152},
+ Package(){ 34590, 50176},
+ Package(){ 33190, 51200},
+ Package(){ 31853, 52224},
+ Package(){ 30577, 53248},
+ Package(){ 29358, 54272},
+ Package(){ 28194, 55296},
+ Package(){ 27082, 56320},
+ Package(){ 26020, 57344},
+ Package(){ 25004, 58368},
+ Package(){ 24033, 59392},
+ Package(){ 23104, 60416},
+ Package(){ 22216, 61440},
+ Package(){ 21367, 62464},
+ Package(){ 20554, 63488},
+ Package(){ 19776, 64512},
+ Package(){ 19031, 65536},
+ Package(){ 18318, 66560},
+ Package(){ 17636, 67584},
+ Package(){ 16982, 68608},
+ Package(){ 16355, 69632},
+ Package(){ 15755, 70656},
+ Package(){ 15180, 71680},
+ Package(){ 14628, 72704},
+ Package(){ 14099, 73728},
+ Package(){ 13592, 74752},
+ Package(){ 13106, 75776},
+ Package(){ 12640, 76800},
+ Package(){ 12192, 77824},
+ Package(){ 11762, 78848},
+ Package(){ 11350, 79872},
+ Package(){ 10954, 80896},
+ Package(){ 10574, 81920},
+ Package(){ 10209, 82944},
+ Package(){ 9858, 83968},
+ Package(){ 9521, 84992},
+ Package(){ 9197, 86016},
+ Package(){ 8886, 87040},
+ Package(){ 8587, 88064},
+ Package(){ 8299, 89088},
+ Package(){ 8023, 90112},
+ Package(){ 7757, 91136},
+ Package(){ 7501, 92160},
+ Package(){ 7254, 93184},
+ Package(){ 7017, 94208},
+ Package(){ 6789, 95232},
+ Package(){ 6570, 96256},
+ Package(){ 6358, 97280},
+ Package(){ 6155, 98304},
+ Package(){ 5959, 99328},
+ Package(){ 5770, 100352},
+ Package(){ 5588, 101376},
+ Package(){ 5412, 102400},
+ Package(){ 5243, 103424},
+ Package(){ 5080, 104448},
+ Package(){ 4923, 105472},
+ Package(){ 4771, 106496},
+ Package(){ 4625, 107520},
+ Package(){ 4484, 108544},
+ Package(){ 4348, 109568},
+ Package(){ 4217, 110592},
+ Package(){ 4090, 111616},
+ Package(){ 3968, 112640},
+ Package(){ 3850, 113664},
+ Package(){ 3736, 114688},
+ Package(){ 3626, 115712},
+ Package(){ 3519, 116736},
+ Package(){ 3417, 117760},
+ Package(){ 3317, 118784},
+ Package(){ 3221, 119808},
+ Package(){ 3129, 120832},
+ Package(){ 3039, 121856},
+ Package(){ 2952, 122880},
+ Package(){ 2868, 123904},
+ Package(){ 2787, 124928},
+ Package(){ 2709, 125952},
+ Package(){ 2633, 126976},
+ Package(){ 2560, 128000},
+ Package(){ 2489, 129024},
+ Package(){ 2420, 130048}
+ })
+ }
+
+ /*----------------------------------------------------------------------------
+ * Voltage ADC Threshold Monitor (VADCTM) Configuration
+ * -------------------------------------------------------------------------*/
+ /*
+ * VADCTM Measurement Configuration Table
+ *
+ * The following is a list of periodic measurements that the VADCTM
+ * can periodically monitor. Thresholds for these measurements are set
+ * in software.
+ *
+ * sName:
+ * Appropriate string name for the channel from AdcInputs.h.
+ *
+ * uAdcHardwareChannel:
+ * AMUX channel.
+ *
+ * eSettlingDelay:
+ * Holdoff time to allow the voltage to settle before reading the channel.
+ * 0 - VADCTM_SETTLING_DELAY_0_US
+ * 1 - VADCTM_SETTLING_DELAY_100_US
+ * 2 - VADCTM_SETTLING_DELAY_200_US
+ * 3 - VADCTM_SETTLING_DELAY_300_US
+ * 4 - VADCTM_SETTLING_DELAY_400_US
+ * 5 - VADCTM_SETTLING_DELAY_500_US
+ * 6 - VADCTM_SETTLING_DELAY_600_US
+ * 7 - VADCTM_SETTLING_DELAY_700_US
+ * 8 - VADCTM_SETTLING_DELAY_800_US
+ * 9 - VADCTM_SETTLING_DELAY_900_US
+ * 10 - VADCTM_SETTLING_DELAY_1_MS
+ * 11 - VADCTM_SETTLING_DELAY_2_MS
+ * 12 - VADCTM_SETTLING_DELAY_4_MS
+ * 13 - VADCTM_SETTLING_DELAY_6_MS
+ * 14 - VADCTM_SETTLING_DELAY_8_MS
+ * 15 - VADCTM_SETTLING_DELAY_10_MS
+ *
+ * eMeasIntervalTimeSelect:
+ * The interval timer to use for the measurement period.
+ * 0 - VADCTM_MEAS_INTERVAL_TIME1
+ * 1 - VADCTM_MEAS_INTERVAL_TIME2
+ * 2 - VADCTM_MEAS_INTERVAL_TIME3
+ *
+ * bAlwaysOn:
+ * Keep the measurement always sampling even if no thresholds are set.
+ * 0 - FALSE
+ * 1 - TRUE
+ *
+ * eCalMethod:
+ * Calibration method.
+ * 0 - VADC_CAL_METHOD_NO_CAL
+ * 1 - VADC_CAL_METHOD_RATIOMETRIC
+ * 2 - VADC_CAL_METHOD_ABSOLUTE
+ *
+ * scalingFactor.num:
+ * Numerator of the channel scaling
+ *
+ * scalingFactor.den:
+ * Denominator of the channel scaling
+ *
+ * eScalingMethod:
+ * The scaling method to use.
+ * 0 - VADC_SCALE_TO_MILLIVOLTS
+ * 1 - VADC_SCALE_INTERPOLATE_FROM_MILLIVOLTS (requires uInterpolationTableName)
+ * 2 - VADC_SCALE_THERMISTOR (requires uPullUp and uInterpolationTableName)
+ *
+ * uPullUp:
+ * The pull up resistor value. Use with eScalingMethod == VADC_SCALE_THERMISTOR,
+ * otherwise, 0.
+ *
+ * uInterpolationTableName:
+ * The name of the lookup table in ACPI that will be interpolated to obtain
+ * a physical value. Note that the physical value (which has default units
+ * of millivolts unless custom scaling function is used) is passed as the
+ * input. This value corresponds to the first column of the table. The
+ * scaled output appears in the physical adc result.
+ * 0 - No interpolation table
+ * WXYZ - Where 'WXYZ' is the interpolation table name
+ *
+ * uScalingFunctionName:
+ * The name of the function to call in the ACPI table to perform custom
+ * scaling. The input to the custom scaling function is defined by
+ * eScalingFunctionInput. The output of the custom scaling function is
+ * the physical value.
+ * 0 - No scaling function
+ * WXYZ - Where 'WXYZ' is the scaling function name
+ *
+ * Note: if both a custon scaling function & interpolation table are used
+ * the custom scaling function is called first.
+ *
+ * uInverseFunctionName:
+ * The name of the inverse scaling for uScalingFunctionName.
+ * 0 - No scaling function
+ * WXYZ - Where 'WXYZ' is the scaling function name
+ *
+ * eScalingFunctionInput:
+ * Defines which ADC result is passed to the custom scaling function.
+ * 0 - VADC_SCALING_FUNCTION_INPUT_PHYSICAL
+ * 1 - VADC_SCALING_FUNCTION_INPUT_PERCENT
+ * 2 - VADC_SCALING_FUNCTION_INPUT_MICROVOLTS
+ * 3 - VADC_SCALING_FUNCTION_INPUT_CODE
+ *
+ * nPhysicalMin:
+ * Minimum threshold value in physical units.
+ *
+ * nPhysicalMax:
+ * Maximum threshold value in physical units.
+ *
+ */
+ Method (VTCH)
+ {
+ Return (Package()
+ {
+ /* VPH_PWR (VPH_PWR_SNS pin) */
+ Package()
+ {
+ /* .sName = */ "VPH_PWR",
+ /* .uAdcHardwareChannel = */ 0x83,
+ /* .eSettlingDelay = */ 0,
+ /* .eMeasIntervalTimeSelect = */ 1,
+ /* .bAlwaysOn = */ 0,
+ /* .eCalMethod = */ 2,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 3,
+ /* .eScalingMethod = */ 0,
+ /* .uPullUp = */ 0,
+ /* .uInterpolationTableName = */ 0,
+ /* .uScalingFunctionName = */ 0,
+ /* .uInverseFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ /* .nPhysicalMin = */ 0,
+ /* .nPhysicalMax = */ 5625,
+ },
+
+ /* PMIC_TEMP1 (internal sensor) */
+ Package()
+ {
+ /* .sName = */ "PMIC_THERM",
+ /* .uAdcHardwareChannel = */ 0x6,
+ /* .eSettlingDelay = */ 0,
+ /* .eMeasIntervalTimeSelect = */ 0,
+ /* .bAlwaysOn = */ 0,
+ /* .eCalMethod = */ 2,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 0,
+ /* .uPullUp = */ 0,
+ /* .uInterpolationTableName = */ 0,
+ /* .uScalingFunctionName = */ PTCF,
+ /* .uInverseFunctionName = */ PTCI,
+ /* .eScalingFunctionInput = */ 2,
+ /* .nPhysicalMin = */ 0xFFFF3CB0, // -50000
+ /* .nPhysicalMax = */ 150000,
+ },
+
+ /* SYS_THERM1 (AMUX_1 pin) */
+ Package()
+ {
+ /* .sName = */ "SYS_THERM1",
+ /* .uAdcHardwareChannel = */ 0x4d,
+ /* .eSettlingDelay = */ 1,
+ /* .eMeasIntervalTimeSelect = */ 0,
+ /* .bAlwaysOn = */ 0,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ SYTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .uInverseFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ /* .nPhysicalMin = */ 0xFFFFFFD8, // -40
+ /* .nPhysicalMax = */ 125,
+ },
+
+ /* SYS_THERM2 (AMUX_2 pin) */
+ Package()
+ {
+ /* .sName = */ "SYS_THERM2",
+ /* .uAdcHardwareChannel = */ 0x4e,
+ /* .eSettlingDelay = */ 1,
+ /* .eMeasIntervalTimeSelect = */ 0,
+ /* .bAlwaysOn = */ 0,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ SYTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .uInverseFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ /* .nPhysicalMin = */ 0xFFFFFFD8, // -40
+ /* .nPhysicalMax = */ 125,
+ },
+
+ /* PA_THERM (AMUX_3 pin) */
+ Package()
+ {
+ /* .sName = */ "PA_THERM",
+ /* .uAdcHardwareChannel = */ 0x4f,
+ /* .eSettlingDelay = */ 1,
+ /* .eMeasIntervalTimeSelect = */ 0,
+ /* .bAlwaysOn = */ 0,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ SYTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .uInverseFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ /* .nPhysicalMin = */ 0xFFFFFFD8, // -40
+ /* .nPhysicalMax = */ 125,
+ },
+
+ /* PA_THERM1 (AMUX_4 pin) */
+ Package()
+ {
+ /* .sName = */ "PA_THERM1",
+ /* .uAdcHardwareChannel = */ 0x50,
+ /* .eSettlingDelay = */ 1,
+ /* .eMeasIntervalTimeSelect = */ 0,
+ /* .bAlwaysOn = */ 0,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ SYTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .uInverseFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ /* .nPhysicalMin = */ 0xFFFFFFD8, // -40
+ /* .nPhysicalMax = */ 125,
+ },
+
+ /* SYS_THERM3 (AMUX_5 pin) */
+ Package()
+ {
+ /* .sName = */ "SYS_THERM3",
+ /* .uAdcHardwareChannel = */ 0x51,
+ /* .eSettlingDelay = */ 1,
+ /* .eMeasIntervalTimeSelect = */ 0,
+ /* .bAlwaysOn = */ 0,
+ /* .eCalMethod = */ 1,
+ /* .scalingFactor.num = */ 1,
+ /* .scalingFactor.den = */ 1,
+ /* .eScalingMethod = */ 2,
+ /* .uPullUp = */ 100000,
+ /* .uInterpolationTableName = */ SYTB,
+ /* .uScalingFunctionName = */ 0,
+ /* .uInverseFunctionName = */ 0,
+ /* .eScalingFunctionInput = */ 0,
+ /* .nPhysicalMin = */ 0xFFFFFFD8, // -40
+ /* .nPhysicalMax = */ 125,
+ },
+ })
+ }
+
+ /*
+ * General VADCTM measurement timer properties
+ *
+ * eMeasIntervalTime1:
+ * Interval timer 1 periodic value.
+ * 0 - VADCTM_MEAS_INTERVAL_TIME1_0_MS
+ * 1 - VADCTM_MEAS_INTERVAL_TIME1_1P0_MS
+ * 2 - VADCTM_MEAS_INTERVAL_TIME1_2P0_MS
+ * 3 - VADCTM_MEAS_INTERVAL_TIME1_3P9_MS
+ * 4 - VADCTM_MEAS_INTERVAL_TIME1_7P8_MS
+ * 5 - VADCTM_MEAS_INTERVAL_TIME1_15P6_MS
+ * 6 - VADCTM_MEAS_INTERVAL_TIME1_31P1_MS
+ * 7 - VADCTM_MEAS_INTERVAL_TIME1_62P5_MS
+ * 8 - VADCTM_MEAS_INTERVAL_TIME1_125_MS
+ * 9 - VADCTM_MEAS_INTERVAL_TIME1_250_MS
+ * 10 - VADCTM_MEAS_INTERVAL_TIME1_500_MS
+ * 11 - VADCTM_MEAS_INTERVAL_TIME1_1000_MS
+ * 12 - VADCTM_MEAS_INTERVAL_TIME1_2000_MS
+ * 13 - VADCTM_MEAS_INTERVAL_TIME1_4000_MS
+ * 14 - VADCTM_MEAS_INTERVAL_TIME1_8000_MS
+ * 15 - VADCTM_MEAS_INTERVAL_TIME1_16000_MS
+ *
+ * eMeasIntervalTime2:
+ * Interval timer 2 periodic value.
+ * 0 - VADCTM_MEAS_INTERVAL_TIME2_0_MS
+ * 1 - VADCTM_MEAS_INTERVAL_TIME2_100_MS
+ * 2 - VADCTM_MEAS_INTERVAL_TIME2_200_MS
+ * 3 - VADCTM_MEAS_INTERVAL_TIME2_300_MS
+ * 4 - VADCTM_MEAS_INTERVAL_TIME2_400_MS
+ * 5 - VADCTM_MEAS_INTERVAL_TIME2_500_MS
+ * 6 - VADCTM_MEAS_INTERVAL_TIME2_600_MS
+ * 7 - VADCTM_MEAS_INTERVAL_TIME2_700_MS
+ * 8 - VADCTM_MEAS_INTERVAL_TIME2_800_MS
+ * 9 - VADCTM_MEAS_INTERVAL_TIME2_900_MS
+ * 10 - VADCTM_MEAS_INTERVAL_TIME2_1000_MS
+ * 11 - VADCTM_MEAS_INTERVAL_TIME2_1100_MS
+ * 12 - VADCTM_MEAS_INTERVAL_TIME2_1200_MS
+ * 13 - VADCTM_MEAS_INTERVAL_TIME2_1300_MS
+ * 14 - VADCTM_MEAS_INTERVAL_TIME2_1400_MS
+ * 15 - VADCTM_MEAS_INTERVAL_TIME2_1500_MS
+ *
+ * eMeasIntervalTime3:
+ * Interval timer 3 periodic value.
+ * 0 - VADCTM_MEAS_INTERVAL_TIME3_0_S
+ * 1 - VADCTM_MEAS_INTERVAL_TIME3_1_S
+ * 2 - VADCTM_MEAS_INTERVAL_TIME3_2_S
+ * 3 - VADCTM_MEAS_INTERVAL_TIME3_3_S
+ * 4 - VADCTM_MEAS_INTERVAL_TIME3_4_S
+ * 5 - VADCTM_MEAS_INTERVAL_TIME3_5_S
+ * 6 - VADCTM_MEAS_INTERVAL_TIME3_6_S
+ * 7 - VADCTM_MEAS_INTERVAL_TIME3_7_S
+ * 8 - VADCTM_MEAS_INTERVAL_TIME3_8_S
+ * 9 - VADCTM_MEAS_INTERVAL_TIME3_9_S
+ * 10 - VADCTM_MEAS_INTERVAL_TIME3_10_S
+ * 11 - VADCTM_MEAS_INTERVAL_TIME3_11_S
+ * 12 - VADCTM_MEAS_INTERVAL_TIME3_12_S
+ * 13 - VADCTM_MEAS_INTERVAL_TIME3_13_S
+ * 14 - VADCTM_MEAS_INTERVAL_TIME3_14_S
+ * 15 - VADCTM_MEAS_INTERVAL_TIME3_15_S
+ *
+ */
+ Method (VTMT)
+ {
+ Return (Package()
+ {
+ /* .eMeasIntervalTime1 = */ 11, // 1000 ms
+ /* .eMeasIntervalTime2 = */ 1, // 100 ms
+ /* .eMeasIntervalTime3 = */ 5, // 5000 ms
+ })
+ }
+}
--- /dev/null
+Device (BTNS)
+{
+ Name(_HID, "ACPI0011")
+
+ Alias(\_SB.PSUB, _SUB)
+
+ Name(_UID, 0)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ //Power Button
+ GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullDown, 0, "\\_SB.PM01", ,) {0} // 0x40 - PM_INT__PON__KPDPWR_ON
+
+ // Volume Up button
+ GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {133} // 0x628 - PM_INT__PM1_GPIO6__GPIO_IN_STS
+
+ // Volume Down button
+ GpioInt(Edge, ActiveBoth, Exclusive, PullDown, 0, "\\_SB.PM01", ,) {1} // 0x41 - PM_INT__PON__RESIN_ON
+
+ // Camera Focus
+ // GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {135} // 0x638 - PM_INT__PM1_GPIO8__GPIO_IN_STS
+
+ //Camera Snapshot
+ // GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {134} // 0x630 - PM_INT__PM1_GPIO7__GPIO_IN_STS
+ })
+ Return (RBUF)
+ }
+
+ Name(_DSD, Package(2) {
+ ToUUID("FA6BD625-9CE8-470D-A2C7-B3CA36C4282E"),
+ Package() {
+ Package(5) {0,1,0,0x01,0x0D}, // Portable Device Control Application Collection
+ Package(5) {1,0,1,0x01,0x81}, // Sleep
+ Package(5) {1,1,1,0x0C,0xE9}, // Volume Increment
+ Package(5) {1,2,1,0x0C,0xEA}, // Volume Decrement
+ // Package(5) {1,3,1,0x90,0x20}, // Camera Auto Focus
+ // Package(5) {1,4,1,0x90,0x21}, // Camera Shutter
+ },
+ })
+}
--- /dev/null
+//==============================================================================
+// <cust_camera.asl>
+// DESCRIPTION
+// This file contains resources (such as memory address, GPIOs, etc.) and
+// methods needed by camera drivers.
+//
+//==============================================================================
+
+Include("cust_camera_exasoc.asl")
+
+//
+// CAMERA MIPI CSI (based on Titan 170 v1 hardware)
+//
+Device (MPCS)
+{
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.CAMP
+ })
+
+ Name (_HID, "QCOM02E8")
+ Name (_UID, 24)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0AC65000, 0x00000900) // PHY 0 memory
+ Memory32Fixed (ReadWrite, 0x0AC66000, 0x00000900) // PHY 1 memory
+ Memory32Fixed (ReadWrite, 0x0AC67000, 0x00000900) // PHY 2 memory
+
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {509} // PHY 0 interrupt, csiphy_0_irq
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {510} // PHY 1 interrupt, csiphy_1_irq
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {511} // PHY 2 interrupt, csiphy_2_irq
+ })
+
+ Return (RBUF)
+ }
+
+ // PERF, EBUF left blank intentionally as only F state support required at this point.
+ // PEP Proxy is not needed as it is there for D state support.
+}
+
+//
+// JPEG ENCODER (JPGE)
+// JPEG 0: a dedicated JPEG encode instance;
+// JPEG 3: a DMA instance (for downscaling only, not for encoding).
+// Each JPEG instance is controlled indpendently; having its own set of
+// registers for control and hardware operation, and its own core clock.
+//
+Device (JPGE)
+{
+ Name (_DEP, Package(0x2)
+ {
+ \_SB_.CAMP,
+ \_SB_.MMU0
+ })
+
+ Name (_HID, "QCOM0276")
+ Name (_UID, 23)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // TITAN_A_JPEG_0
+ Memory32Fixed ( ReadWrite, 0x0AC4E000, 0x0340 )
+
+ // TITAN_A_JPEG_3
+ Memory32Fixed ( ReadWrite, 0x0AC52000, 0x01B4 )
+
+ // titan_jpeg_0_irq (Destination Subsystem: Application Processor)
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) { 506 }
+
+ // titan_jpeg_3_irq (Destination Subsystem: Application Processor)
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) { 507 }
+ })
+
+ Return (RBUF)
+ }
+
+ Method (PERF)
+ {
+ Name (EBUF, Package()
+ {
+ Package() // JPEG instance 0 PSET_0
+ {
+ "COMPONENT",
+ 0, // Component ID: JPEG_0 = 0, JPEG_3/DMA = 1
+
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // P_Set Index
+ 0, // CLK = 0, BW = 1
+ "JPEG0_CLK",
+
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ 600000000, // cam_cc_jpeg_clk supported configurations (TURBO = NOM / SVS / Low SVS)
+ 600000000,
+ 404000000,
+ 200000000,
+ },
+ },
+ },
+
+ Package() // JPEG instance 3 PSET_0
+ {
+ "COMPONENT",
+ 1,
+
+ Package() { "PSTATE_SET", 0, 0, "DMA_CLK", Package() { "PSTATE", 0, 600000000, 600000000, 200000000, }, }, // cam_cc_jpeg_clk: Turbo / Nominal / LowSVS
+ },
+ })
+
+ Return (EBUF)
+ }
+}
+
+//
+// VFE
+//
+Device (VFE0)
+{
+ Name (_DEP, Package(0x3)
+ {
+ \_SB_.MMU0,
+ \_SB_.PEP0,
+ \_SB_.CAMP
+ })
+
+ Name (_HID, "QCOM0243")
+ Name (_UID, 22)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // ICP
+ Memory32Fixed (ReadWrite, 0xAC00000, 0x20000)
+
+ //CPASS_CDM
+ Memory32Fixed (ReadWrite, 0xAC48000, 0x1000)
+
+ //FD_WRAPPER
+ Memory32Fixed (ReadWrite, 0xAC5A000, 0x4000)
+
+ // LRME
+ Memory32Fixed (ReadWrite, 0xAC6B000, 0x1000)
+
+ //BPS
+ Memory32Fixed (ReadOnly, 0xAC6F000, 0x8000)
+
+ // IPE0
+ Memory32Fixed (ReadOnly, 0xAC87000, 0xA000)
+
+ // IPE1
+ Memory32Fixed (ReadOnly, 0xAC91000, 0xA000)
+
+ // IFE0
+ Memory32Fixed (ReadWrite, 0xACAF000, 0x5000)
+
+ //IFE1
+ Memory32Fixed (ReadWrite, 0xACB6000, 0x5000)
+
+ //IFE_LITE
+ Memory32Fixed (ReadWrite, 0xACC4000, 0x5000)
+
+ //ICP FW
+ Memory32Fixed (ReadWrite, 0x8BF00000, 0x500000)
+
+
+ // CDM interrupt
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {493}
+
+ // ICP interrupt
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {495}
+
+
+ // IFE0 interrupt
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {497}
+
+ // IFE1 interrupt
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {499}
+
+ // IFE LITE interrupt
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {501}
+
+ // FD interrupt
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {494}
+
+ // IFE0 CSID interrupt
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {496}
+
+ // IFE1 CSID interrupt
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {498}
+
+ // IFE LITE CSDI interrupt
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {500}
+
+
+ })
+ Return (RBUF)
+ }
+ Method (PERF)
+ {
+ Name (EBUF, Package()
+ {
+ //------------------------------------------------------------------------------
+ // VFE and CPP P-state values listed here specific to Platform
+ // These packages enumerates all of the expected P-state values that should be used
+ // for the P-state transitions decision by VFE/CPP cores
+ // Package format is mentioned below.
+ //------------------------------------------------------------------------------
+
+ // Package()
+ // {
+ // "COMPONENT"
+ // INTEGER, VFE0/JPEG = 0,VFE1 = 1,CPP = 2
+ // Package()
+ // {
+ // "PSTATE_SET",
+ // PSTATE_INDEX_INTEGER, PStateIndex to access clocktable by index that contains Clock
+ // having PState.
+ // PSTATESET_TYPE_INTEGER, CLK = 0 , BW = 1
+ // STRING, ResourceName
+ // Package()
+ // {
+ // "PSTATE" , Package type mentioned in ACPIPackageNames
+ // INTEGER, Chipversion list availabiliy
+ //
+ // Clock values , Chipversion supported,
+ // Clock values , Chipversion supported,
+ // Clock values , Chipversion supported,
+ // },
+ // },
+ // },
+
+ Package()
+ {
+ "COMPONENT",
+ 0, // IFE0
+ // Clk Freq
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // PStateSet Index
+ 0, // CLK = 0 , BW = 1
+ "IFE0_CLK",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ // Clock value Chipversion supported
+ 600000000,
+ 480000000,
+ 404000000,
+ 0,
+ },
+ },
+
+ // BW: TODO
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // PStateSet Index
+ 1, // CLK =0 , BW =1
+ "HF0_UNCOMP_BANDWIDTH",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ 38000000000,
+ 35000000000,
+ 28000000000,
+ 23000000000,
+ 20000000000,
+ 16000000000,
+ 14000000000,
+ 12000000000,
+ 4000000000,
+ 3500000000,
+ 3300000000,
+ 3100000000,
+ 2900000000,
+ 2700000000,
+ 2500000000,
+ 2300000000,
+ 2100000000,
+ 1900000000,
+ 1700000000,
+ 1500000000,
+ 1300000000,
+ 1100000000,
+ 900000000,
+ 700000000,
+ 500000000,
+ 400000000,
+ 300000000,
+ 200000000,
+ 100000000,
+ 0,
+ },
+ },
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // PStateSet Index
+ 1, // CLK =0 , BW =1
+ "HF0_BANDWIDTH",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ 38000000000,
+ 35000000000,
+ 28000000000,
+ 23000000000,
+ 20000000000,
+ 16000000000,
+ 14000000000,
+ 12000000000,
+ 4000000000,
+ 3500000000,
+ 3300000000,
+ 3100000000,
+ 2900000000,
+ 2700000000,
+ 2500000000,
+ 2300000000,
+ 2100000000,
+ 1900000000,
+ 1700000000,
+ 1500000000,
+ 1300000000,
+ 1100000000,
+ 900000000,
+ 700000000,
+ 500000000,
+ 400000000,
+ 300000000,
+ 200000000,
+ 100000000,
+ 0,
+ },
+ },
+
+ // CSID Clk Freq: TODO
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 1, // IFE1
+ // Clk Freq
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // PStateSet Index
+ 0, // CLK = 0 , BW = 1
+ "IFE1_CLK",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ // Clock value Chipversion supported
+ 600000000,
+ 480000000,
+ 404000000,
+ 0,
+ },
+ },
+
+ // BW: TODO
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // PStateSet Index
+ 1, // CLK =0 , BW =1
+ "HF1_UNCOMP_BANDWIDTH",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ 38000000000,
+ 35000000000,
+ 28000000000,
+ 23000000000,
+ 20000000000,
+ 16000000000,
+ 14000000000,
+ 12000000000,
+ 4000000000,
+ 3500000000,
+ 3300000000,
+ 3100000000,
+ 2900000000,
+ 2700000000,
+ 2500000000,
+ 2300000000,
+ 2100000000,
+ 1900000000,
+ 1700000000,
+ 1500000000,
+ 1300000000,
+ 1100000000,
+ 900000000,
+ 700000000,
+ 500000000,
+ 400000000,
+ 300000000,
+ 200000000,
+ 100000000,
+ 0,
+ },
+ },
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // PStateSet Index
+ 1, // CLK =0 , BW =1
+ "HF1_BANDWIDTH",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ 38000000000,
+ 35000000000,
+ 28000000000,
+ 23000000000,
+ 20000000000,
+ 16000000000,
+ 14000000000,
+ 12000000000,
+ 4000000000,
+ 3500000000,
+ 3300000000,
+ 3100000000,
+ 2900000000,
+ 2700000000,
+ 2500000000,
+ 2300000000,
+ 2100000000,
+ 1900000000,
+ 1700000000,
+ 1500000000,
+ 1300000000,
+ 1100000000,
+ 900000000,
+ 700000000,
+ 500000000,
+ 400000000,
+ 300000000,
+ 200000000,
+ 100000000,
+ 0,
+ },
+ },
+
+ // CSID Clk Freq: TODO
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 2, // IFE_LITE
+ // Clk Freq
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // PStateSet Index
+ 0, // CLK = 0 , BW = 1
+ "IFE_LITE_CLK",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ // Clock value Chipversion supported
+ 600000000,
+ 480000000,
+ 404000000,
+ 0,
+ },
+ },
+
+ // BW: ICBID_MASTER_CAMNOC_HF1_UNCOMP is used for both ife1 & ife_lite
+
+ // CSID Clk Freq: TODO
+
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 3, // ICP
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // PStateSet Index
+ 0, // CLK =0 , BW =1
+ "ICP_CLK",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ // Clock value Chipversion supported
+ 600000000,
+ 400000000,
+ 0,
+ },
+ },
+
+ // AHB Clk: TODO
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 4, // IPE
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // PStateSet Index
+ 0, // CLK =0 , BW =1
+ "IPE0_CLK",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ // Clock value Chipversion supported
+ 600000000,
+ 480000000,
+ 404000000,
+ 0,
+ },
+ },
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // PStateSet Index
+ 0, // CLK =0 , BW =1
+ "IPE1_CLK",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ // Clock value Chipversion supported
+ 600000000,
+ 480000000,
+ 404000000,
+ 0,
+ },
+ },
+
+ // BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme
+
+ // AHB Clk : TODO
+
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 5, // BPS
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // PStateSet Index
+ 0, // CLK =0 , BW =1
+ "BPS_CLK",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ // Clock value Chipversion supported
+ 600000000,
+ 480000000,
+ 404000000,
+ 0,
+ },
+ },
+
+ // BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme
+
+ // AHB Clk : TODO
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 6, // LRME
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // PStateSet Index
+ 0, // CLK =0 , BW =1
+ "LRME_CLK",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ // Clock value Chipversion supported
+ 400000000,
+ 320000000,
+ 269000000,
+ 0,
+ },
+ },
+
+ // BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme
+
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 7, // FD
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // PStateSet Index
+ 0, // CLK =0 , BW =1
+ "FD_CLK",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ // Clock value Chipversion supported
+ 600000000,
+ 538000000,
+ 400000000,
+ 0,
+ },
+ },
+
+ // BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme
+
+ },
+
+ })
+
+ Return (EBUF)
+ }
+}
--- /dev/null
+//==============================================================================
+// <cust_camera_exasoc.asl>
+// DESCRIPTION
+// This file contains resources (such as memory address, GPIOs, etc.) and
+// methods needed by camera drivers for external components like sensors,flash etc.
+// Customers can update these files for different external components
+//
+//==============================================================================
+
+//
+// CAMERA PLATFORM
+//
+Device (CAMP)
+{
+ Name (_DEP, Package(0x3)
+ {
+ \_SB_.PEP0,
+ \_SB_.PMIC,
+ \_SB_.PMAP
+ })
+
+ Name (_HID, "QCOM026F")
+ Name (_UID, 27)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // TITAN_A_CPAS_0_CPAS_TOP_0
+ Memory32Fixed ( ReadWrite, 0x0AC40000, 0x0000006C )
+
+ // TITAN_A_CAMNOC
+ Memory32Fixed ( ReadWrite, 0x0AC42000, 0x00004E8C )
+
+ // TITAN_A_CCI
+ Memory32Fixed ( ReadWrite, 0x0AC4A000, 0x00000C1C )
+
+ // titan_cci_irq (Destination Subsystem: Application Processor)
+ Interrupt( ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) { 492 }
+ })
+
+ Return (RBUF)
+ }
+
+ //
+ // PLATFROM CONFIGURATION (PCFG) METHOD
+ //
+ // [1] SENSOR PRESENCE
+ // -----------------------|-----------/-----------|-----------/-----------|-----------/------------
+ // 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 | << BIT INDEX
+ // -----------------------|-----------/-----------|-----------/-----------|-----------/------------
+ // | SENSOR PRESENCE [0/1] | << FIELD MEANING
+ // RESERVED | 7 6 5 4 3 2 1 0 | << SENSOR INDEX
+ // -----------------------|-----------------------|-----------------------|-------------------------
+ // 0b | 0 0 0 0 0 1 1 1 | << 0x07
+ // -----------------------|-----------/-----------|-----------/-----------|-----------/------------
+ // SENSOR INDEX: 0(RFC), 1(FFC), 2(AUX), etc.
+ // SENSOR PRESENCE: 0 (ABSENT) / 1(PRESENTED)
+
+ // [2-9] SENSOR CONNECTION CONFIGURATION (here we only utilize three entires)
+ // -----------------------|-----------/-----------|-----------/-----------|-----------/------------
+ // 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 | << BIT INDEX
+ // -----------------------|-----------/-----------|-----------/-----------|-----------/------------
+ // RESERVED | CSI_PHY | I2C_BUS | RESERVED | FL_INX |FP| DIR | ORI | << FIELD MEANING
+ // ------------------- --|-----------------------|-----------|--------|--|-----------|------------
+ // 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 << 0x00000100 (RFC)
+ // 0b 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 << 0x00210010 (FFC)
+ // 0b 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 << 0x00110300 (AUX/IRIS); REVISIT AND DOUBLE CHECK FLASH_INDEX !!!
+ // -----------------------|-----------/-----------|-----------/-----------|-----------/------------
+ // CSIPHY INDEX: 4-bit field, valid values 0/1/2, respectively CSIPHY_0/1/2 LD20-NE182-9
+ // I2C_BUS INDEX: 4-bit field, valid values 0/1, respectively CCI_I2C_SDA/SCL0/1 LD20-NE182-7/42
+ // FLASH_INDEX: 3-bit field, valid values 0/1/2, respectively FLASH_LED0/1/2 LD20-NE182-19/45
+ // FLASH_PRESENCE: 1-bit field, valid values 0/1, respectively ABSENT/PRESENTED
+ // SENSOR_DIRECTION: 4-bit field, valid values 0/1, respectively Rear/Front
+ // SENSOR_ORIENTATION: 4-bit field, valid values 0/1/2/3 respectively 0/90/180/270 degrees
+
+ Method (PCFG, 0x0, Serialized)
+ {
+ Return
+ (
+ Package()
+ {
+ Package ()
+ {
+ 0x00000001, // [1] SENSOR PRESENCE
+ 0x00000100, // [2] SENSOR_0/RFC CONNECTION
+ 0x00000000, // [3] SENSOR_1/FFC CONNECTION
+ 0x00000000, // [4] SENSOR_2/AUX/IRIS CONNECTION
+ 0x00000000, // [5] SENSOR_3 CONNECTION; RESERVED
+ 0x00000000, // [6] SENSOR_4 CONNECTION; RESERVED
+ 0x00000000, // [7] SENSOR_5 CONNECTION; RESERVED
+ 0x00000000, // [8] SENSOR_6 CONNECTION; RESERVED
+ 0x00000000 // [9] SENSOR_7 CONNECTION; RESERVED
+ }
+ }
+ )
+ }
+
+ // The method contains P state power setting used by the camera driver. The clock presented
+ // here MUST be consistent with the PSTATE_SET values under the CAMP section in the file of
+ // cust_camera_exasoc_resources.asl.
+ Method (PERF)
+ {
+ Name (EBUF, Package()
+ {
+ Package()
+ {
+ "COMPONENT",
+ 0, // Platform = 0
+
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // PStateSet Index
+ 0, // CLK = 0, BW = 1
+ "CAMP_CLK",
+
+ Package() // The indexes and frequencies be consistent
+ { // with CCICLKFrqIdx in CCIResourceType.h and
+ "PSTATE", // cam_cc_cci_clk in cust_camera_exasoc_resources.asl
+ 0, // Chipversion list availabiliy
+ 37500000, // Index 0 clock
+ 19200000, // Index 1 clock
+ },
+ },
+
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // PStateSet Index
+ 1, // CLK =0 , BW =1
+ "NRT_UNCOMP_BANDWIDTH",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ 12000000000,
+ 11500000000,
+ 11000000000,
+ 10500000000,
+ 10000000000,
+ 9500000000,
+ 9000000000,
+ 8500000000,
+ 8000000000,
+ 7500000000,
+ 7000000000,
+ 6500000000,
+ 6000000000,
+ 5500000000,
+ 5000000000,
+ 4500000000,
+ 4000000000,
+ 3500000000,
+ 3300000000,
+ 3100000000,
+ 2900000000,
+ 2700000000,
+ 2500000000,
+ 2300000000,
+ 2100000000,
+ 1900000000,
+ 1700000000,
+ 1500000000,
+ 1300000000,
+ 1100000000,
+ 900000000,
+ 700000000,
+ 500000000,
+ 400000000,
+ 300000000,
+ 200000000,
+ 100000000,
+ 0,
+ },
+ },
+
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // PStateSet Index
+ 1, // CLK =0 , BW =1
+ "NRT_BANDWIDTH",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ 12000000000,
+ 11500000000,
+ 11000000000,
+ 10500000000,
+ 10000000000,
+ 9500000000,
+ 9000000000,
+ 8500000000,
+ 8000000000,
+ 7500000000,
+ 7000000000,
+ 6500000000,
+ 6000000000,
+ 5500000000,
+ 5000000000,
+ 4500000000,
+ 4000000000,
+ 3500000000,
+ 3300000000,
+ 3100000000,
+ 2900000000,
+ 2700000000,
+ 2500000000,
+ 2300000000,
+ 2100000000,
+ 1900000000,
+ 1700000000,
+ 1500000000,
+ 1300000000,
+ 1100000000,
+ 900000000,
+ 700000000,
+ 500000000,
+ 400000000,
+ 300000000,
+ 200000000,
+ 100000000,
+ 0,
+ },
+ },
+ },
+ Package()
+ {
+ "COMPONENT",
+ 1, // Platform = 0
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // PStateSet Index
+ 1, // CLK =0 , BW =1
+ "HF0_UNCOMP_BANDWIDTH",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ 1100000000,
+ 400000000,
+ 300000000,
+ 200000000,
+ 100000000,
+ 0,
+ },
+ },
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // PStateSet Index
+ 1, // CLK =0 , BW =1
+ "HF0_BANDWIDTH",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ 1100000000,
+ 400000000,
+ 300000000,
+ 200000000,
+ 100000000,
+ 0,
+ },
+ },
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // PStateSet Index
+ 1, // CLK =0 , BW =1
+ "NRT_UNCOMP_BANDWIDTH",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ 1100000000,
+ 400000000,
+ 300000000,
+ 200000000,
+ 100000000,
+ 0,
+ },
+ },
+ Package()
+ {
+ "PSTATE_SET",
+ 3, // PStateSet Index
+ 1, // CLK =0 , BW =1
+ "NRT_BANDWIDTH",
+ Package()
+ {
+ "PSTATE",
+ 0, // Chipversion list availabiliy
+ 1100000000,
+ 400000000,
+ 300000000,
+ 200000000,
+ 100000000,
+ 0,
+ },
+ },
+ },
+ })
+
+ Return (EBUF)
+ }
+}
+
+//
+// Primary Rear Camera (IMX363)
+//
+Device (CAMS)
+{
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.MPCS // MPCS has dependency on CAMP, which eventually ends up with PEP0 and PMIC
+ })
+
+ Name (_HID, "QCOM0245")
+ Name (_UID, 21)
+
+ // Return 0x0 to disable CAMS sensor
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+
+ //
+ // SENSOR CONFIGURATION (SCFG) METHOD
+ //
+ // [1/2] Driver/Tuning binary file name (no more than 50 characters)
+ //
+ // [3] I2C Slave Information for Sensor Probing
+ //------------------------|-----------/-----------|-----------------------|------------------------
+ // 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 | << BIT INDEX
+ // RESERVED | DTT | ADT | FRQ | SLAVE ADDRESS | << MEANING
+ // -----------------------------|-----|-----|-----|------------------------------------------------
+ // 0b 0 0 0 1 0 1 FROM IMX318 REG MAP | << 0x50034
+ // -----------------------|-----------/-----------|-----------------------|-----------/------------
+ // Register Data Type (DTT): 0b00 -- CAMERA_I2C_BYTE_DATA, 0b01 -- WORD, 0b10 -- DWORD
+ // Register Address Type (ADT): 0b00 -- CAMERA_I2C_BYTE_ADDR, 0b01 -- WORD, 0b10 -- 3B
+ // I2C Frequency mode: 0b00 -- 100 KHz (standard), 0b01 -- 400 KHz (fast), 0b10 -- 1 MHz (fast_plus).
+ //
+ // [4] Slave Data Part 1 for and from Probing
+ // Expected Reading (16 bits; 0x363) + Register Address (16 bits; 0x16)
+ //
+ // [5] Slave Data Part 2 for and from Probing
+ // Same format as above; Reserved for Revision # (if applied)
+
+ Method (SCFG, 0x0, Serialized)
+ {
+ Return
+ (
+ Package()
+ {
+ Package ()
+ {
+ "com.qti.sensormodule.imx363.bin", // [1] Driver binary file name
+ "com.qti.tuned.semco_imx363.bin", // [2] Tuning binary file name
+ 0x00050034, // [3] I2C Slave Information for Sensor Probing
+ 0x03630016, // [4] Slave Data Part 1 for and from Probing
+ 0x00000000 // [5] Slave Data Part 2 for and from Probing; Reserved
+ }
+ }
+ )
+ }
+
+ // PEP Proxy Support
+ Name(PGID, Buffer(10) {"\\_SB.CAMS"}) // Device ID buffer - PGID (Pep given ID)
+
+ Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID (Pep given ID)
+ CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE
+ // HIDDEN 1 BYTE (SIZE)
+ CreateByteField(DBUF, 2, DVAL) // Packet value, 1 BYTES Device Status
+ CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES (160 Bits)
+
+ Method (_S1D, 0) { Return (3) } // S1 => D3
+ Method (_S2D, 0) { Return (3) } // S2 => D3
+ Method (_S3D, 0) { Return (3) } // S3 => D3
+
+ Method(_PS0, 0x0, NotSerialized)
+ {
+ Store(Buffer(ESNL){}, DEID)
+ Store(0, DVAL)
+ Store(PGID, DEID)
+ If(\_SB.ABD.AVBL)
+ {
+ Store(DBUF, \_SB.PEP0.FLD0)
+ }
+ }
+
+ Method(_PS3, 0x0, NotSerialized)
+ {
+ Store(Buffer(ESNL){}, DEID)
+ Store(3, DVAL)
+ Store(PGID, DEID)
+ If(\_SB.ABD.AVBL)
+ {
+ Store(DBUF, \_SB.PEP0.FLD0)
+ }
+ }
+}
+
+//
+// Primary Front Camera (IMX258)
+//
+Device (CAMF)
+{
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.MPCS
+ })
+
+ Name (_HID, "QCOM024A")
+ Name (_UID, 26)
+
+ // Return 0x0 to disable CAMF sensor
+ Method (_STA)
+ {
+ Return (0x0)
+ }
+
+ Method (SCFG, 0x0, Serialized)
+ {
+ Return
+ (
+ Package()
+ {
+ Package ()
+ {
+ "com.qti.sensormodule.semco_imx258.bin",
+ "com.qti.tuned.semco_imx258.bin",
+ 0x00150034, // I2C Slave Info for Probing, primary address 0x34, secondary 0x20
+ 0x02580016,
+ 0x00000000
+ }
+ }
+ )
+ }
+
+ // PEP Proxy Support
+ Name(PGID, Buffer(10) {"\\_SB.CAMF"}) // Device ID buffer - PGID (Pep given ID)
+
+ Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID (Pep given ID)
+ CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE
+ // HIDDEN 1 BYTE (SIZE)
+ CreateByteField(DBUF, 2, DVAL) // Packet value, 1 BYTES Device Status
+ CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES (160 Bits)
+
+ Method (_S1D, 0) { Return (3) } // S1 => D3
+ Method (_S2D, 0) { Return (3) } // S2 => D3
+ Method (_S3D, 0) { Return (3) } // S3 => D3
+
+ Method(_PS0, 0x0, NotSerialized)
+ {
+ Store(Buffer(ESNL){}, DEID)
+ Store(0, DVAL)
+ Store(PGID, DEID)
+ If(\_SB.ABD.AVBL)
+ {
+ Store(DBUF, \_SB.PEP0.FLD0)
+ }
+ }
+
+ Method(_PS3, 0x0, NotSerialized)
+ {
+ Store(Buffer(ESNL){}, DEID)
+ Store(3, DVAL)
+ Store(PGID, DEID)
+ If(\_SB.ABD.AVBL)
+ {
+ Store(DBUF, \_SB.PEP0.FLD0)
+ }
+ }
+}
+
+//
+// Auxiliary sensor (OV2281, IRIS)
+//
+Device (CAMI)
+{
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.MPCS
+ })
+
+ Name (_HID, "QCOM0247")
+ Name (_UID, 28)
+
+ // Return 0x0 to disable CAMI sensor
+ Method (_STA)
+ {
+ Return (0x0)
+ }
+
+ Method (SCFG, 0x0, Serialized)
+ {
+ Return
+ (
+ Package()
+ {
+ Package ()
+ {
+ "com.qti.sensormodule.sunny_ov2281.bin",
+ "UPDATEME.bin", // NEED UPDATE!!!
+ 0x00150020,
+ 0x0056300A,
+ 0x00000000
+ }
+ }
+ )
+ }
+
+ // PEP Proxy Support
+ Name(PGID, Buffer(10) {"\\_SB.CAMI"}) // Device ID buffer - PGID (Pep given ID)
+
+ Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID (Pep given ID)
+ CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE
+ // HIDDEN 1 BYTE (SIZE)
+ CreateByteField(DBUF, 2, DVAL) // Packet value, 1 BYTES Device Status
+ CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES (160 Bits)
+
+ Method (_S1D, 0) { Return (3) } // S1 => D3
+ Method (_S2D, 0) { Return (3) } // S2 => D3
+ Method (_S3D, 0) { Return (3) } // S3 => D3
+
+ Method(_PS0, 0x0, NotSerialized)
+ {
+ Store(Buffer(ESNL){}, DEID)
+ Store(0, DVAL)
+ Store(PGID, DEID)
+ If(\_SB.ABD.AVBL)
+ {
+ Store(DBUF, \_SB.PEP0.FLD0)
+ }
+ }
+
+ Method(_PS3, 0x0, NotSerialized)
+ {
+ Store(Buffer(ESNL){}, DEID)
+ Store(3, DVAL)
+ Store(PGID, DEID)
+ If(\_SB.ABD.AVBL)
+ {
+ Store(DBUF, \_SB.PEP0.FLD0)
+ }
+ }
+}
+
+//
+// CAMERA WHITE LED FLASH
+//
+Device (FLSH)
+{
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.CAMP
+ })
+
+ Name (_HID, "QCOM025C")
+ Name (_UID, 25)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // "GPIO Interrupt Connection Resource Descriptor Macro" Format (ACPI $19.5.53):
+ // GpioInt (EdgeLevel, ActiveLevel, Shared, PinConfig, DebounceTimeout, ResourceSource,
+ // ResourceSourceIndex, ResourceUsage, DescriptorName, VendorData) {PinList}
+ })
+
+ Return (RBUF)
+ }
+}
--- /dev/null
+//===========================================================================
+// <cust_camera_exasoc_resources.asl>
+// DESCRIPTION
+// This file contains the resources needed by camera drivers for external components like sensors,flash etc.
+// Customers can update these files for different external components.
+//
+// [1] Refer Table 3-10 "Titan 170 Power Use Cases" in "Titan Camera
+// Hardware Architecture Specification" for the detailed information on
+// the operating points under different use case scenarios. Based on
+// the information in the table, this ACPI planned to support SVS and
+// NOM frequencies.
+//
+// [2] Refer Chapter 2 "Defintions of Terms" in the ACPI Specification for
+// the definitions of D, F, and P states. Refer the manual of PEP
+// driver for the syntax of defining the power and clock resources.
+//
+// [3] ACPI keeps 2 mA for most GPIO pins by setting the field of
+// "PullDriveStrength" to 0 on TLMMGPIO. For high frequency clock pins
+// (such as cam_mclk0/1/2/3 running at 24 MHz), the strength shall be
+// set to 6 mA to meet the timing requirement.
+//
+//===========================================================================
+
+Scope(\_SB_.PEP0)
+{
+ // Exa-SoC Devices
+ Method(CPMX)
+ {
+ Return (CPXC)
+ }
+
+ Name(CPXC,
+ Package ()
+ {
+ // Flash device (ISRC_R/G/B_LED, ISRC_FLASH_1/2/3)
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.FLSH",
+
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component ID
+ Package() { "FSTATE", 0x0, }, // Dummy F0
+ Package() { "FSTATE", 0x1, }, // Dummy F1
+ },
+ },
+
+ // Device CAMP Data
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.CAMP",
+
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0
+
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 state (fully on)
+
+ // FORMAT: FOOTSWITCH NAME; ACTION: 1 == ENABLE, 2 == DISABLE, 3 == HW_CONTROL_ENABLE, 4 == HW_CONTROL_
+ // DISABLE. When the ACTION field is set to 1, the CLOCK driver shall set SW_COLLAPSE bit to 1 (which
+ // means DISABLING/NO SW_COLLAPSE) and poll PWR_ON bit on TITAN_CAM_CC_TITAN_TOP_GDSCR register (as
+ // inidicated in "$2.3.1.4 Core Power On Sequence" of Titan HPG). The CLOCK driver MUST ensure that
+ // the power domain has been enabled before returning. It shall be a blocking operation. If a HW block
+ // (e.g., IPE) is involved, use 3/4 to enable/disable it. HW ENABLING always overrides other settings.
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+
+ Package() { "PSTATE_ADJUST", Package() { 1, 35 } }, // Set to 2nd lowest BW, need revisit
+ Package() { "PSTATE_ADJUST", Package() { 2, 35 } }, // Set to 2nd lowest BW, need revisit
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ // Action: 1 == ENABLE, 2 == DISABLE, 3 == SET_FREQ, 8 == ENABLE_SET_FREQ, 9 == CONFIGURE,
+ // 12 == Disable and Set Frequency (combines actions 2 & 3)(must pair with 8)
+ // Match_Type: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST, 3 == CLOCK_FREQUENCY_HZ_CLOSEST
+ // -----------------------------------------------------------------------------------------------------
+ // CLOCK Clock Name Action Freq (Hz) MatchType
+ // -----------------------------------------------------------------------------------------------------
+ package() { "CLOCK", package() { "cam_cc_cci_clk", 1} }, // Func: CCI. For CCI operations.
+
+ // Valid only in F-State; Used to adjust one or more current P-State within their respective P-State
+ // Sets. In this case, it will adjust to P state 0 in PSET 0 (to set cam_cc_cci_clk to 37.5 MHz).
+ Package() { "PSTATE_ADJUST", Package() { 0, 0 } },
+
+ // -----------------------------------------------------------------------------------------------------
+ // GPIO PIN (Refer CAMS TLMMGPIO) Pin|State|FuncSel|Dirc|PullType|DriveStrength
+ // -----------------------------------------------------------------------------------------------------
+ // Camera CCI 0/1
+ package() { "TLMMGPIO", package() { 17, 1, 1, 1, 3, 0, }, }, // cci_i2c_sda0
+ package() { "TLMMGPIO", package() { 18, 1, 1, 1, 3, 0, }, }, // cci_i2c_scl0
+ package() { "TLMMGPIO", package() { 19, 1, 1, 1, 3, 0, }, }, // cci_i2c_sda1
+ package() { "TLMMGPIO", package() { 20, 1, 1, 1, 3, 0, }, }, // cci_i2c_scl1
+
+ // Camera MCLK
+ package() { "TLMMGPIO", package() { 13, 1, 1, 1, 0, 2, }, }, // cam_mclk0, for CAM0/RFC/IMX318
+ package() { "TLMMGPIO", package() { 14, 1, 1, 1, 0, 2, }, }, // cam_mclk1, for CAM1/FFC/IMX258
+ package() { "TLMMGPIO", package() { 15, 1, 1, 1, 0, 2, }, }, // cam_mclk2, unused
+ package() { "TLMMGPIO", package() { 16, 1, 1, 1, 0, 2, }, }, // cam_mclk3, for CAM2/IRIS/OV2281
+ },
+
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 state (OFF)
+
+ package() { "TLMMGPIO", package() { 16, 0, 0, 0, 1, 2, }, },
+ package() { "TLMMGPIO", package() { 15, 0, 0, 0, 1, 2, }, },
+ package() { "TLMMGPIO", package() { 14, 0, 0, 0, 1, 2, }, },
+ package() { "TLMMGPIO", package() { 13, 0, 0, 0, 1, 2, }, },
+
+ package() { "TLMMGPIO", package() { 20, 0, 0, 0, 1, 0, }, },
+ package() { "TLMMGPIO", package() { 19, 0, 0, 0, 1, 0, }, },
+ package() { "TLMMGPIO", package() { 18, 0, 0, 0, 1, 0, }, },
+ package() { "TLMMGPIO", package() { 17, 0, 0, 0, 1, 0, }, },
+
+ package() { "CLOCK", package() { "cam_cc_cci_clk", 2 } },
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "PSTATE_ADJUST", Package() { 2, 37 } },
+ Package() { "PSTATE_ADJUST", Package() { 1, 37 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+
+ // This packet contains P state power setting used by the PEP driver. The clock presented here
+ // MUST be consistent with the clock values under the PERF method in the file of cust_camera_exasoc.asl.
+ Package()
+ {
+ "PSTATE_SET",
+ 0,
+
+ // Format: name / action / freq / match_type. The driver shall select the lowest frequency required to perform the task at the acceptable performance
+ // point. HPG recommends to limit the freq under 50 MHz. It is allowed to have multiple clock resources in one PSTATE package. The indexes and
+ // frequencies MUST be consistent with CCICLKFrqIdx in CCIResourceType.h and CAMP_CLK in cust_camera_exasoc.asl.
+ Package() { "PSTATE", 0, package() { "CLOCK", package() { "cam_cc_cci_clk", 3, 37500000, 3, } }, }, // LowSVS for all speeds from 100 KHz to 1 MHz.
+ Package() { "PSTATE", 1, package() { "CLOCK", package() { "cam_cc_cci_clk", 3, 19200000, 3, } }, }, // MinSVS, not used.
+ },
+
+ Package()
+ {
+ "PSTATE_SET", // PSET 1: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth); Driver limits the MaxComponentNameLen number as 40.
+ 1,
+
+ // Format: Type-3 Bus Arbiter Req | Master Name | Slave Name | IB in bytes/sec | AB
+ Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 12000000000, 12000000000 } }, },
+ Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 11500000000, 11500000000 } }, },
+ Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 11000000000, 11000000000 } }, },
+ Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 10500000000, 10500000000 } }, },
+ Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 10000000000, 10000000000 } }, },
+ Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 9500000000, 9500000000 } }, },
+ Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 9000000000, 9000000000 } }, },
+ Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 8500000000, 8500000000 } }, },
+ Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 8000000000, 8000000000 } }, },
+ Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 7500000000, 7500000000 } }, },
+ Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 7000000000, 7000000000 } }, },
+ Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 6500000000, 6500000000 } }, },
+ Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 6000000000, 6000000000 } }, },
+ Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 5500000000, 5500000000 } }, },
+ Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 5000000000, 5000000000 } }, },
+ Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 4500000000, 4500000000 } }, },
+ Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 4000000000, 4000000000 } }, },
+ Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3500000000, 3500000000 } }, },
+ Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3300000000, 3300000000 } }, },
+ Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3100000000, 3100000000 } }, },
+ Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2900000000, 2900000000 } }, },
+ Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2700000000, 2700000000 } }, },
+ Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2500000000, 2500000000 } }, },
+ Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2300000000, 2300000000 } }, },
+ Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2100000000, 2100000000 } }, },
+ Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1900000000, 1900000000 } }, },
+ Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1700000000, 1700000000 } }, },
+ Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1500000000, 1500000000 } }, },
+ Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1300000000, 1300000000 } }, },
+ Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } }, },
+ Package() { "PSTATE", 30, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 900000000, 900000000 } }, },
+ Package() { "PSTATE", 31, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 700000000, 700000000 } }, },
+ Package() { "PSTATE", 32, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 500000000, 500000000 } }, },
+ Package() { "PSTATE", 33, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } }, },
+ Package() { "PSTATE", 34, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } }, },
+ Package() { "PSTATE", 35, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } }, },
+ Package() { "PSTATE", 36, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } }, },
+ Package() { "PSTATE", 37, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } }, },
+ },
+
+ Package()
+ {
+ "PSTATE_SET", // PSET 2: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth)
+ 2,
+
+ // Format: Type-3 Bus Arbiter Req | Master Name | Slave Name | IB in bytes/sec | AB
+ Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 12000000000, 12000000000 } }, },
+ Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 11500000000, 11500000000 } }, },
+ Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 11000000000, 11000000000 } }, },
+ Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 10500000000, 10500000000 } }, },
+ Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 10000000000, 10000000000 } }, },
+ Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 9500000000, 9500000000 } }, },
+ Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 9000000000, 9000000000 } }, },
+ Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 8500000000, 8500000000 } }, },
+ Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 8000000000, 8000000000 } }, },
+ Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 7500000000, 7500000000 } }, },
+ Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 7000000000, 7000000000 } }, },
+ Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 6500000000, 6500000000 } }, },
+ Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 6000000000, 6000000000 } }, },
+ Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 5500000000, 5500000000 } }, },
+ Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 5000000000, 5000000000 } }, },
+ Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 4500000000, 4500000000 } }, },
+ Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 4000000000, 4000000000 } }, },
+ Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 3500000000, 3500000000 } }, },
+ Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 3300000000, 3300000000 } }, },
+ Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 3100000000, 3100000000 } }, },
+ Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2900000000, 2900000000 } }, },
+ Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2700000000, 2700000000 } }, },
+ Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2500000000, 2500000000 } }, },
+ Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2300000000, 2300000000 } }, },
+ Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2100000000, 2100000000 } }, },
+ Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1900000000, 1900000000 } }, },
+ Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1700000000, 1700000000 } }, },
+ Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1500000000, 1500000000 } }, },
+ Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1300000000, 1300000000 } }, },
+ Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } }, },
+ Package() { "PSTATE", 30, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 900000000, 900000000 } }, },
+ Package() { "PSTATE", 31, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 700000000, 700000000 } }, },
+ Package() { "PSTATE", 32, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 500000000, 500000000 } }, },
+ Package() { "PSTATE", 33, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 400000000, 400000000 } }, },
+ Package() { "PSTATE", 34, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 300000000, 300000000 } }, },
+ Package() { "PSTATE", 35, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 200000000, 200000000 } }, },
+ Package() { "PSTATE", 36, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 100000000, 100000000 } }, },
+ Package() { "PSTATE", 37, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 0, 0 } }, },
+ },
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 0x1, // Component 1
+
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 state (fully on)
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+
+ Package() { "PSTATE_ADJUST", Package() { 3, 4 } },
+ Package() { "PSTATE_ADJUST", Package() { 2, 4 } },
+ Package() { "PSTATE_ADJUST", Package() { 1, 4 } },
+ Package() { "PSTATE_ADJUST", Package() { 0, 4 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+ package() { "CLOCK", package() { "cam_cc_cci_clk", 1} }, // Func: CCI. For CCI operations.
+ },
+
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 state (OFF)
+
+ package() { "CLOCK", package() { "cam_cc_cci_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+
+ Package() { "PSTATE_ADJUST", Package() { 0, 5 } },
+ Package() { "PSTATE_ADJUST", Package() { 1, 5 } },
+ Package() { "PSTATE_ADJUST", Package() { 2, 5 } },
+ Package() { "PSTATE_ADJUST", Package() { 3, 5 } },
+
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2} },
+ },
+ Package()
+ {
+ "PSTATE_SET",
+ 0,
+ Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } } },
+ Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } } },
+ Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } } },
+ Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } } },
+ Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } } },
+ Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } } },
+ },
+ // BW - compressed
+ Package()
+ {
+ "PSTATE_SET",
+ 1,
+ Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } } },
+ Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 400000000, 400000000 } } },
+ Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 300000000, 300000000 } } },
+ Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 200000000, 200000000 } } },
+ Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 100000000, 100000000 } } },
+ Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 0, 0 } } },
+ },
+
+ // Moved BW from CAMP to here. this is temporary.
+ Package()
+ {
+ "PSTATE_SET", // PSET 3: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth)
+ 2,
+ Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } }, },
+ Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } }, },
+ Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } }, },
+ Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } }, },
+ Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } }, },
+ Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } }, },
+ },
+
+ // Moved BW from CAMP to here. this is temporary.
+ Package()
+ {
+ "PSTATE_SET", // PSET 3: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth)
+ 3,
+ Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } }, },
+ Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 400000000, 400000000 } }, },
+ Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 300000000, 300000000 } }, },
+ Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 200000000, 200000000 } }, },
+ Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 100000000, 100000000 } }, },
+ Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 0, 0 } }, },
+ },
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 0x2, // Component 2 (SHARED_RES: AFVDD)
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 state (fully on)
+
+ // CAM1_STBY_N / CAM_ELDO3_EN (AF_VDD LDO Enable All Cameras)
+ // VIN_PM8998 - VIN_PMI8998 - BOB - ELDO3 - AF_VDD; LD20-NE182-7-C6;
+ // Format: Pin|State|FuncSel|Dirc|PullType|DriveStrength
+ package() { "TLMMGPIO", package() { 27, 1, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+ },
+
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 state (OFF)
+
+ // AF_VDD OFF
+ package() { "TLMMGPIO", package() { 27, 0, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+ },
+ },
+ },
+
+ // Primary RFC (IMX318) Power Setting Array from imx318_lib.h (sensor vendor supplied). Mapping
+ // between lib and IP_CAT: VDIG (DVDD), VIO (DOVDD), VANA (AVDD), VAF (AF_VDD). Sony IMX318
+ // Application Note (AN): During power on, VANA, VDIG, and VIF may rise in any order. The XCLR
+ // pin needs to be LOW until all power supplies complete power-on. During power off, VANA, VDIG,
+ // and VIF may fall in any order. For delays, refer AN "Startup sequence timing constraints"
+ // and "Power down sequence timing constraints".
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.CAMS",
+
+ Package()
+ {
+ "DSTATE",
+ 0x0, // D0 state (ON)
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ // [1] TLMM_GPIO: set CAM0_RST_N to LOW; LD20-NE182-8-C5
+ package()
+ {
+ "TLMMGPIO", // Identifier: PMIC GPIO. Top Level Mode Mux (TLMM)
+ package()
+ {
+ 80, // Pin Number: CAM0_RST_N (Primary RFC)
+ 0, // State / OutVal: 0 == Low, 1 == High
+ 0, // Function Select: 0 == Generic I/O Pin, non-zero == Alternate Function
+ 1, // Direction: 0 == Input, 1 == Output
+ 0, // Pull Type: 0 == No Pull, 1 == Pull Down, 2 == Keeper, 3 == Pull Up
+ 0, // Strength: 0 == 2 mA, 1 == 4 mA, 2 == 6 mA, 3 == 8 mA, 4 == 10 mA, 5 == 12 mA, 4 == 14 mA, 7 == 16 mA
+ },
+ },
+ package() { "DELAY", package() { 1, }, }, // 1 ms(millisecond) delay
+
+ // [2] TLMM_GPIO: VIN_PM8998 - VIN_PMI8998 - BOB - ELDO9 - AVDD (VANA); CAM0_STBY_N / CAM_ELDO9_EN;
+ // Primary Rear Camera AVDD LDO Enable. LD20-NE182-8-C5. L22A, IMX318_AVDD_ALT is not used.
+ package() { "TLMMGPIO", package() { 79, 1, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [3] PMIC_GPIO: VIN_PM8998 - S3A - ELDO1 - DVDD; LD20-NE182-27-A6/41-D7
+ package()
+ {
+ "PMICGPIO",
+ package()
+ {
+ "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT",
+ 0, // PMIC Number: 0 == PM8998, 1 == PMI8998, 2 == PM8005
+ 11, // GPIO Number: PM_GPIO_12 / CAM_ELDO1_EN
+ 0, // Out Buffer Config: 0 == PM_GPIO_OUT_BUFFER_CONFIG_CMOS, 1 == NMOS, 2 == CMOS
+ 1, // VIN: 0 == PM_GPIO_VIN0, 1 == VIN1
+ 1, // Source: 0 == PM_GPIO_SOURCE_LOW, 1 == HIGH, 2 == PAIRED_GPIO, 3-4 == SPECIAL_FUNCTION1-2, 5-8 == DTEST1-4
+ 3, // Out Buffer Strength: 0 == PM_GPIO_OUT_BUFFER_RESERVED, 1 == LOW, 2 == MEDIUM, 3 == HIGH
+ 0, // I Source Pull: 0 == PM_GPIO_I_SOURCE_PULL_UP_30uA, 1 == UP_1_5uA, 2 == UP_31_5uA, 3 == UP_1_5uA_PLUS_30uA_BOOST, 4 == DOWN_10uA, 5 == NO_PULL
+ },
+ },
+ package() { "DELAY", package() { 1, }, },
+
+ // [4] PMIC_VREG_VOTE: VIN_PM8998 - S4A - VIN_LVS1_LVS2 - LVS1A - DOVDD. LD20-NE182-41-B4.
+ // Regulator name from //deploy/qcom/qct/platform/wpci/prod/woa/QCDK/main/latest/inc/pmic/PmicIVreg.h
+ package()
+ {
+ "PMICVREGVOTE", // Identifier: PMIC VREG Resource
+ package()
+ {
+ "PPP_RESOURCE_ID_LVS1_A", // Voltage Regulator ID (Type VS)
+ 4, // TYPE of VREG: 4 == LVS (Low Voltage Switch), 5 == MVS (Medium Voltage Switch)
+ 1800000, // Voltage: 1.8 V
+ 1, // Software Enable: 0 == Disable, 1 == Enable (Recommended)
+ // "HLOS_DRV", // Optional: DRV ID (Default: HLOS_DRV; Valid: HLOS_DRV / DISPLAY_DRV)
+ // "REQUIRED", // Optional: Suppressible Type (Default: REQUIRED; Valid: REQUIRED / SUPPRESSIBLE)
+ },
+ },
+
+ // [5] CLOCK; LD20-NE182-45-D4
+ package() { "CLOCK", package() { "cam_cc_mclk0_clk", 8, 24000000, 3, } }, // Frequency from imx318_lib.h
+ package() { "DELAY", package() { 1, }, },
+
+ // [6] TLMM_GPIO: set CAM0_RST_N to HIGH
+ package() { "TLMMGPIO", package() { 80, 1, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 18, }, }, // 18 ms wait time between XCLR rising and sending streaming command
+ },
+
+ Package()
+ {
+ "DSTATE",
+ 0x3, // D3 state (OFF)
+
+ // [1] CLOCK OFF
+ package() { "CLOCK", package() { "cam_cc_mclk0_clk", 2} },
+ package() { "DELAY", package() { 1, }, },
+
+ // [2] CAM0_RST_N LOW
+ package() { "TLMMGPIO", package() { 80, 0, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [3] DOVDD OFF
+ package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 0, 0, }, },
+
+ // [4] DVDD OFF
+ package() { "PMICGPIO", package() { "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", 0, 11, 0, 1, 0, 3, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [5] AVDD (VANA) OFF
+ package() { "TLMMGPIO", package() { 79, 0, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+ },
+
+ // Primary FFC (IMX258) Power Setting Array from imx258_lib.h. Sony IMX258 Application Note: During
+ // power on, VANA, VDIG, and VIF may rise in any order. The XCLR pin is set to "LOW" and the power
+ // suppliers are brought up. Then the XCLR pin should be set to "HIGH" after INCK supplied. During
+ // power off, VANA, VDIG, and VIF may fall in any order. For delays, refer AN "Startup sequence
+ // timing constraints" and "Power down sequence timing constraints".
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.CAMF",
+
+ Package()
+ {
+ "DSTATE",
+ 0x0,
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ // [1] TLMM_GPIO: set CAM1_RST_N to LOW; LD20-NE182-7-C6
+ package() { "TLMMGPIO", package() { 28, 0, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [2] TLMM_GPIO: VIN_PM8998 - VIN_PMI8998 - BOB - ELDO2 (GPIO_8 / CAM_ELDO2_EN / Front Camera AVDD LDO Enable) - AVDD (VANA); LD20-NE182-41-C7
+ package() { "TLMMGPIO", package() { 8, 1, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [3] PM_IC_GPIO: VIN_PM8998 - S3A - ELDO4 ( PM_GPIO_09 / CAM_ELDO4_EN / Camera Front DVDD LDO Enable) - DVDD; LD20-NE182-41-B6
+ package() { "PMICGPIO", package() { "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", 0, 8, 0, 1, 1, 3, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [4] PM_IC_VREG_VOTE: VIN_PM8998 - S4A - VIN_LVS1_LVS2 - LVS1A - DOVDD; LD20-NE182-41-B4
+ package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 1800000, 1, }, },
+
+ // [5] CLOCK; LD20-NE182-43-C2
+ package() { "CLOCK", package() { "cam_cc_mclk1_clk", 8, 24000000, 3, } },
+ package() { "DELAY", package() { 1, }, },
+
+ // [6] TLMM_GPIO: set CAM1_RST_N to HIGH; LD20-NE182-7-C6
+ package() { "TLMMGPIO", package() { 28, 1, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 12, }, }, // Delay between INCK-start-and-XCLR-rising and Sending-streaming-command
+ },
+
+ Package()
+ {
+ "DSTATE",
+ 0x3,
+
+ // [1] CAM1_RST_N LOW
+ package() { "TLMMGPIO", package() { 28, 0, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [2] CLOCK OFF
+ package(){ "CLOCK", package(){ "cam_cc_mclk1_clk", 2} },
+ package() { "DELAY", package() { 1, }, },
+
+ // [3] DOVDD OFF
+ package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 0, 0, }, },
+
+ // [4] DVDD OFF
+ package() { "PMICGPIO", package() { "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", 0, 8, 0, 1, 0, 3, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [5] AVDD (VANA) OFF
+ package() { "TLMMGPIO", package() { 8, 0, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+ },
+
+ // FFC Auxiliary (OV2281) Power Setting Array from ov2281_lib.h. Refer OV2281 datasheet
+ // "power up sequence", figure 2-3, "power down sequence", and figure 2-6 for more
+ // information.
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.CAMI",
+
+ Package()
+ {
+ "DSTATE",
+ 0x0,
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ // [1] VIO / DOVDD - VREG_LVS1A_1P8 (All camera 1.8 V IO); PM_IC_VREG_VOTE; LD20-NE182-41-B4, 42-D6
+ package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 1800000, 1, }, },
+
+ // [2] AVDD 2.8 V - P2V85_AVDD_CAM1_2; LD20-NE182-41-C5, 42-D6; TLMM_GPIO: ELDO2 (GPIO_8 / CAM_ELDO2_EN / Front Camera AVDD LDO Enable / CAM2_STBY_N)
+ package() { "TLMMGPIO", package() { 8, 1, 0, 1, 0, 0, }, },
+
+ // [3] VDD 1.2 V - P1V2_DVDD_CAM1_2; PM_IC_GPIO: ELDO4 ( PM_GPIO_09 / CAM_ELDO4_EN / Camera Front DVDD LDO Enable) - DVDD; LD20-NE182-41-B6
+ package() { "PMICGPIO", package() { "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", 0, 8, 0, 1, 1, 3, 0, }, },
+
+ // [4] CAM2_RST_N LOW (AUX1, 3rd camera in system); LD20-NE182-7-D6
+ package() { "TLMMGPIO", package() { 9, 0, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [5] CAM2_RST_N HIGH
+ package() { "TLMMGPIO", package() { 9, 1, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [6] CLOCK; LD20-NE182-42-C6
+ package() { "CLOCK", package() { "cam_cc_mclk3_clk", 8, 24000000, 3, } },
+ package() { "DELAY", package() { 1, }, },
+ },
+
+ Package()
+ {
+ "DSTATE",
+ 0x3,
+
+ // [1] CLOCK OFF
+ package(){ "CLOCK", package(){ "cam_cc_mclk3_clk", 2} },
+ package() { "DELAY", package() { 1, }, },
+
+ // [2] CAM2_RST_N HIGH
+ package() { "TLMMGPIO", package() { 9, 1, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [3] CAM2_RST_N LOW
+ package() { "TLMMGPIO", package() { 9, 0, 0, 1, 0, 0, }, },
+ package() { "DELAY", package() { 1, }, },
+
+ // [4] VDD OFF
+ package() { "PMICGPIO", package() { "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", 0, 8, 0, 1, 0, 3, 0, }, },
+
+ // [5] AVDD OFF
+ package() { "TLMMGPIO", package() { 8, 0, 0, 1, 0, 0, }, },
+
+ // [6] DOVDD OFF
+ package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 0, 0, }, },
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+ }
+ })
+}
--- /dev/null
+//===========================================================================
+// <cust_camera_resources.asl>
+// DESCRIPTION
+// This file contains the resources needed by camera drivers.
+//
+// [1] Refer Table 3-10 "Titan 170 Power Use Cases" in "Titan Camera
+// Hardware Architecture Specification" for the detailed information on
+// the operating points under different use case scenarios. Based on
+// the information in the table, this ACPI planned to support SVS and
+// NOM frequencies.
+//
+// [2] Refer Chapter 2 "Defintions of Terms" in the ACPI Specification for
+// the definitions of D, F, and P states. Refer the manual of PEP
+// driver for the syntax of defining the power and clock resources.
+//
+// [3] ACPI keeps 2 mA for most GPIO pins by setting the field of
+// "PullDriveStrength" to 0 on TLMMGPIO. For high frequency clock pins
+// (such as cam_mclk0/1/2/3 running at 24 MHz), the strength shall be
+// set to 6 mA to meet the timing requirement.
+//
+//===========================================================================
+
+Include("cust_camera_exasoc_resources.asl")
+
+Scope(\_SB_.PEP0)
+{
+ // CAMERA
+ Method(CPMD)
+ {
+ Return(CPCC)
+ }
+
+ Name(CPCC, Package()
+ {
+ // JPEG ENCODER (JPGE)
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.JPGE",
+
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0; JPEG 0 Encoder
+
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 State
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ package() { "CLOCK", package() { "cam_cc_jpeg_clk", 1} }, // For core processing on JPEG instance 0 and 3; SVS
+
+ package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS
+ },
+
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 State
+
+ package() { "CLOCK", package() { "cam_cc_jpeg_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+
+ Package()
+ {
+ "PSTATE_SET", // PSET 0: Clock frequency adjustments
+ 0,
+
+ Package() { "PSTATE", 0, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 600000000, 3, } }, }, // TURBO for driver turbo
+ Package() { "PSTATE", 1, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 600000000, 3, } }, }, // NOMINAL for driver nominal
+ Package() { "PSTATE", 2, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 404000000, 3, } }, }, // SVS only used in driver (revisit)
+ Package() { "PSTATE", 3, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 200000000, 3, } }, }, // LowSVS for driver Standby
+ },
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 0x1, // Component 2; JPEG_3/DMA. Note that this is normally indexed as JPEG core "3" in diagrams, but the ACPI entry index is 2 here
+
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 State
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ package() { "CLOCK", package() { "cam_cc_jpeg_clk", 1} }, // LowSVS for standby (JPEG3 ONLY)
+
+ package() { "PSTATE_ADJUST", Package() { 0, 2 }},
+ },
+
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 State
+
+ package() { "CLOCK", package() { "cam_cc_jpeg_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+
+ Package()
+ {
+ "PSTATE_SET",
+ 0,
+
+ Package() { "PSTATE", 0, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 600000000, 3, } }, }, // Turbo
+ Package() { "PSTATE", 1, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 600000000, 3, } }, }, // Nominal
+ Package() { "PSTATE", 2, Package() { "CLOCK", Package() { "cam_cc_jpeg_clk", 3, 200000000, 3, } }, }, // LowSVS for Standby
+ },
+ },
+ },
+
+
+ // Device MPCS Data (DEVICE/COMPONENT/STATE)
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.MPCS",
+
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0 (CSIPHY_0)
+
+ Package()
+ {
+ "FSTATE",
+ 0x0,
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ Package() { "CLOCK", Package() { "phy_refgen_south", 1} }, //To enable REFGEN SOUTH
+
+ package() { "CLOCK", package() { "cam_cc_csi0phytimer_clk", 8, 269330000, 3, }}, // SVS = NOM = TURBO
+ package() { "CLOCK", package() { "cam_cc_csiphy0_clk", 8, 384000000, 3, }}, // SVS = NOM = TURBO
+ },
+
+ Package()
+ {
+ "FSTATE",
+ 0x1,
+
+ package() { "CLOCK", package() { "cam_cc_csiphy0_clk", 2}},
+ package() { "CLOCK", package() { "cam_cc_csi0phytimer_clk", 2}},
+
+ Package() { "CLOCK", Package() { "phy_refgen_south", 2 }}, //To disable REFGEN SOUTH
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 0x1, // Component 1 (CSIPHY_1)
+
+ Package()
+ {
+ "FSTATE",
+ 0x0,
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ Package() { "CLOCK", Package() { "phy_refgen_south", 1} }, //To enable REFGEN SOUTH
+
+ package() { "CLOCK", package() { "cam_cc_csi1phytimer_clk", 8, 269330000, 3, }},
+ package() { "CLOCK", package() { "cam_cc_csiphy1_clk", 8, 384000000, 3, }},
+ },
+
+ Package()
+ {
+ "FSTATE",
+ 0x1,
+
+ package() { "CLOCK", package() { "cam_cc_csiphy1_clk", 2}},
+ package() { "CLOCK", package() { "cam_cc_csi1phytimer_clk", 2}},
+
+ Package() { "CLOCK", Package() { "phy_refgen_south", 2 }}, //To disable REFGEN SOUTH
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 0x2, // Component 2 (CSIPHY_2)
+
+ Package()
+ {
+ "FSTATE",
+ 0x0,
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ Package() { "CLOCK", Package() { "phy_refgen_south", 1} }, //To enable REFGEN SOUTH
+
+ package() { "CLOCK", package() { "cam_cc_csi2phytimer_clk", 8, 269330000, 3, }},
+ package() { "CLOCK", package() { "cam_cc_csiphy2_clk", 8, 384000000, 3, }},
+ },
+
+ Package()
+ {
+ "FSTATE",
+ 0x1,
+
+ package() { "CLOCK", package() { "cam_cc_csiphy2_clk", 2}},
+ package() { "CLOCK", package() { "cam_cc_csi2phytimer_clk", 2}},
+
+
+ Package() { "CLOCK", Package() { "phy_refgen_south", 2 }}, //To disable REFGEN SOUTH
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+ },
+ },
+
+ //Device VFE0 Data
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.VFE0",
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0. //IFE0 component
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 state
+
+ // Footswitch Name; Action (1 == Enable; 2 == Disable; 3 = HW_CONTROL enable, 4 = HW_CONTROL disable)
+
+ // Action: 1 == ENABLE 2 == DISABLE 3 == SET_FREQ 8 == EN_SETFREQ
+ // MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST 3 == CLOCK_FREQUENCY_HZ_CLOSEST
+
+ // Clock Name Action Frequency MatchType
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ Package(){"PSTATE_ADJUST", Package () { 1, 10 }}, // bw voting
+ Package(){"PSTATE_ADJUST", Package () { 2, 10 }}, // bw voting
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ Package() { "FOOTSWITCH", Package() { "ife_0_gdsc", 1 } },
+
+ //IFE0 Clocks
+ package() { "PSTATE_ADJUST", Package() { 0, 1 } }, // Pstate adjustment for clock frequencies. Set to SVS
+ package(){ "CLOCK", package(){ "cam_cc_ife_0_clk", 1 } },
+ package(){ "CLOCK", package(){ "cam_cc_ife_0_cphy_rx_clk", 8, 384000000, 3, } }, // SVS
+ package(){ "CLOCK", package(){ "cam_cc_ife_0_csid_clk", 8, 384000000, 3, } }, // SVS
+ package(){ "CLOCK", package(){ "cam_cc_ife_0_dsp_clk", 1} },
+
+ package(){ "CLOCK", package(){ "cam_cc_ife_0_axi_clk", 1} },
+
+ },
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 state
+
+ package(){ "CLOCK", package(){ "cam_cc_ife_0_axi_clk", 2}},
+
+ package(){ "CLOCK", package(){ "cam_cc_ife_0_dsp_clk", 2}},
+ package(){ "CLOCK", package(){ "cam_cc_ife_0_csid_clk", 2}},
+ package(){ "CLOCK", package(){ "cam_cc_ife_0_cphy_rx_clk", 2}},
+ //package() { "PSTATE_ADJUST", Package() { 0, 4 } },
+
+ package(){ "CLOCK", package(){ "cam_cc_ife_0_clk", 2}},
+
+ Package() { "FOOTSWITCH", Package() { "ife_0_gdsc", 2 } },
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package(){"PSTATE_ADJUST", Package () { 2, 29 }}, // bw voting
+ Package(){"PSTATE_ADJUST", Package () { 1, 29 }}, // bw voting
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+
+ },
+
+ // Clk Freq
+ Package()
+ {
+ "PSTATE_SET",
+ 0,
+ // TURBO, NOM
+ Package()
+ {
+ "PSTATE",
+ 0,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_0_clk", 3, 600000000, 3, }},
+ },
+ // SVS_L1
+ Package()
+ {
+ "PSTATE",
+ 1,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_0_clk", 3, 480000000, 3, }},
+ },
+ // SVS
+ Package()
+ {
+ "PSTATE",
+ 2,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_0_clk", 3, 404000000, 3, }},
+ },
+ // Off
+ Package()
+ {
+ "PSTATE",
+ 3,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_0_clk", 3, 0, 3, }},
+ },
+ },
+
+
+ // BW - Uncompressed
+ Package()
+ {
+ "PSTATE_SET",
+ 1,
+
+ // Req IB AB
+ // Type Master Slave Bytes/Sec Bytes/Sec
+ // ---- ----------------------- ---------------------- ---------- ----------
+ Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 38000000000, 38000000000 } } },
+ Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 35000000000, 35000000000 } } },
+ Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 28000000000, 28000000000 } } },
+ Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 23000000000, 23000000000 } } },
+ Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 20000000000, 20000000000 } } },
+ Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 16000000000, 16000000000 } } },
+ Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 14000000000, 14000000000 } } },
+ Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 12000000000, 12000000000 } } },
+ Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 4000000000, 4000000000 } } },
+ Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3500000000, 3500000000 } } },
+ Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3300000000, 3300000000 } } },
+ Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3100000000, 3100000000 } } },
+ Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2900000000, 2900000000 } } },
+ Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2700000000, 2700000000 } } },
+ Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2500000000, 2500000000 } } },
+ Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2300000000, 2300000000 } } },
+ Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2100000000, 2100000000 } } },
+ Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1900000000, 1900000000 } } },
+ Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1700000000, 1700000000 } } },
+ Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1500000000, 1500000000 } } },
+ Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1300000000, 1300000000 } } },
+ Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } } },
+ Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 900000000, 900000000 } } },
+ Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 700000000, 700000000 } } },
+ Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 500000000, 500000000 } } },
+ Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } } },
+ Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } } },
+ Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } } },
+ Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } } },
+ Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } } },
+ },
+ // BW - compressed
+ Package()
+ {
+ "PSTATE_SET",
+ 2,
+
+ // Req IB AB
+ // Type Master Slave Bytes/Sec Bytes/Sec
+ // ---- ----------------------- ---------------------- ---------- ----------
+ Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 38000000000, 38000000000 } } },
+ Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 35000000000, 35000000000 } } },
+ Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 28000000000, 28000000000 } } },
+ Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 23000000000, 23000000000 } } },
+ Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 20000000000, 20000000000 } } },
+ Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 16000000000, 16000000000 } } },
+ Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 14000000000, 14000000000 } } },
+ Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 12000000000, 12000000000 } } },
+ Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 4000000000, 4000000000 } } },
+ Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 3500000000, 3500000000 } } },
+ Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 3300000000, 3300000000 } } },
+ Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 3100000000, 3100000000 } } },
+ Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 2900000000, 2900000000 } } },
+ Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 2700000000, 2700000000 } } },
+ Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 2500000000, 2500000000 } } },
+ Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 2300000000, 2300000000 } } },
+ Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 2100000000, 2100000000 } } },
+ Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1900000000, 1900000000 } } },
+ Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1700000000, 1700000000 } } },
+ Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1500000000, 1500000000 } } },
+ Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1300000000, 1300000000 } } },
+ Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } } },
+ Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 900000000, 900000000 } } },
+ Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 700000000, 700000000 } } },
+ Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 500000000, 500000000 } } },
+ Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 400000000, 400000000 } } },
+ Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 300000000, 300000000 } } },
+ Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 200000000, 200000000 } } },
+ Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 100000000, 100000000 } } },
+ Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 0, 0 } } },
+ },
+
+ // CSID Clk Freq: TODO
+
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 0x1, // Component 1. //IFE1 component
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 state
+
+ // Footswitch Name; Action (1 == Enable; 2 == Disable; 3 = HW_CONTROL enable, 4 = HW_CONTROL disable)
+ // Action: 1 == ENABLE 2 == DISABLE 3 == SET_FREQ 8 == EN_SETFREQ
+ // MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST 3 == CLOCK_FREQUENCY_HZ_CLOSEST
+
+ // Clock Name Action Frequency MatchType
+ Package(){"PSTATE_ADJUST", Package () { 1, 10 }}, // bw voting
+ Package(){"PSTATE_ADJUST", Package () { 2, 10 }}, // bw voting
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ Package() { "FOOTSWITCH", Package() { "ife_1_gdsc", 1 } },
+
+ //IFE1 Clocks
+ package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS
+ package() { "CLOCK", package(){ "cam_cc_ife_1_clk", 1} },
+
+ package() { "CLOCK", package(){ "cam_cc_ife_1_cphy_rx_clk", 8, 384000000, 3, } }, // SVS
+ package() { "CLOCK", package(){ "cam_cc_ife_1_csid_clk", 8, 384000000, 3, } }, // SVS
+ package() { "CLOCK", package(){ "cam_cc_ife_1_dsp_clk", 1} },
+
+ package() { "CLOCK", package(){ "cam_cc_ife_1_axi_clk", 1} },
+
+ },
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 state
+
+ package(){ "CLOCK", package(){ "cam_cc_ife_1_axi_clk", 2} },
+
+ package(){ "CLOCK", package(){ "cam_cc_ife_1_dsp_clk", 2} },
+ package(){ "CLOCK", package(){ "cam_cc_ife_1_csid_clk", 2} },
+ package(){ "CLOCK", package(){ "cam_cc_ife_1_cphy_rx_clk", 2} },
+
+ //package() { "PSTATE_ADJUST", Package() { 0, 4 } },
+ package(){ "CLOCK", package(){ "cam_cc_ife_1_clk", 2} },
+
+ Package(){ "FOOTSWITCH", Package(){ "ife_1_gdsc", 2 } },
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+
+ Package(){"PSTATE_ADJUST", Package () { 2, 29 }}, // bw voting
+ Package(){"PSTATE_ADJUST", Package () { 1, 29 }}, // bw voting
+
+ },
+
+ // Clk Freq
+ Package()
+ {
+ "PSTATE_SET",
+ 0,
+ // TURBO, NOM
+ Package()
+ {
+ "PSTATE",
+ 0,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_1_clk", 3, 600000000, 3, }},
+ },
+ // SVS_L1
+ Package()
+ {
+ "PSTATE",
+ 1,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_1_clk", 3, 480000000, 3, }},
+ },
+ // SVS
+ Package()
+ {
+ "PSTATE",
+ 2,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_1_clk", 3, 404000000, 3, }},
+ },
+ // Off
+ Package()
+ {
+ "PSTATE",
+ 3,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_1_clk", 3, 0, 3, }},
+ },
+ },
+
+ // BW - Uncompressed
+ Package()
+ {
+ "PSTATE_SET",
+ 1,
+
+ // Req IB AB
+ // Type Master Slave Bytes/Sec Bytes/Sec
+ // ---- ----------------------- ---------------------- ---------- ----------
+ Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 38000000000, 38000000000 } } },
+ Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 35000000000, 35000000000 } } },
+ Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 28000000000, 28000000000 } } },
+ Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 23000000000, 23000000000 } } },
+ Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 20000000000, 20000000000 } } },
+ Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 16000000000, 16000000000 } } },
+ Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 14000000000, 14000000000 } } },
+ Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 12000000000, 12000000000 } } },
+ Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 4000000000, 4000000000 } } },
+ Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3500000000, 3500000000 } } },
+ Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3300000000, 3300000000 } } },
+ Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3100000000, 3100000000 } } },
+ Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2900000000, 2900000000 } } },
+ Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2700000000, 2700000000 } } },
+ Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2500000000, 2500000000 } } },
+ Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2300000000, 2300000000 } } },
+ Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2100000000, 2100000000 } } },
+ Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1900000000, 1900000000 } } },
+ Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1700000000, 1700000000 } } },
+ Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1500000000, 1500000000 } } },
+ Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1300000000, 1300000000 } } },
+ Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } } },
+ Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 900000000, 900000000 } } },
+ Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 700000000, 700000000 } } },
+ Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 500000000, 500000000 } } },
+ Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } } },
+ Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } } },
+ Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } } },
+ Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } } },
+ Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } } },
+ },
+ // BW - compressed
+ Package()
+ {
+ "PSTATE_SET",
+ 2,
+
+ // Req IB AB
+ // Type Master Slave Bytes/Sec Bytes/Sec
+ // ---- ----------------------- ---------------------- ---------- ----------
+ Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 38000000000, 38000000000 } } },
+ Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 35000000000, 35000000000 } } },
+ Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 28000000000, 28000000000 } } },
+ Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 23000000000, 23000000000 } } },
+ Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 20000000000, 20000000000 } } },
+ Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 16000000000, 16000000000 } } },
+ Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 14000000000, 14000000000 } } },
+ Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 12000000000, 12000000000 } } },
+ Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 4000000000, 4000000000 } } },
+ Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 3500000000, 3500000000 } } },
+ Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 3300000000, 3300000000 } } },
+ Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 3100000000, 3100000000 } } },
+ Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 2900000000, 2900000000 } } },
+ Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 2700000000, 2700000000 } } },
+ Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 2500000000, 2500000000 } } },
+ Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 2300000000, 2300000000 } } },
+ Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 2100000000, 2100000000 } } },
+ Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 1900000000, 1900000000 } } },
+ Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 1700000000, 1700000000 } } },
+ Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 1500000000, 1500000000 } } },
+ Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 1300000000, 1300000000 } } },
+ Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } } },
+ Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 900000000, 900000000 } } },
+ Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 700000000, 700000000 } } },
+ Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 500000000, 500000000 } } },
+ Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 400000000, 400000000 } } },
+ Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 300000000, 300000000 } } },
+ Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 200000000, 200000000 } } },
+ Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 100000000, 100000000 } } },
+ Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF1", "ICBID_SLAVE_EBI1", 0, 0 } } },
+ },
+
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 0x2, // Component 2. //IFE LITE component
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 state
+
+ // Footswitch Name; Action (1 == Enable; 2 == Disable; 3 = HW_CONTROL enable, 4 = HW_CONTROL disable)
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ //IFE Lite Clocks
+ package(){ "CLOCK", package(){ "cam_cc_ife_lite_clk", 1 } },
+ package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS
+
+ package(){ "CLOCK", package(){ "cam_cc_ife_lite_cphy_rx_clk", 8, 384000000, 3, } }, // SVS
+ package(){ "CLOCK", package(){ "cam_cc_ife_lite_csid_clk", 8, 384000000, 3, } }, // SVS
+
+ },
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 state
+
+ package(){ "CLOCK", package(){ "cam_cc_ife_lite_csid_clk", 2 } },
+ package(){ "CLOCK", package(){ "cam_cc_ife_lite_cphy_rx_clk", 2 } },
+
+ package() { "PSTATE_ADJUST", Package() { 0, 4 } },
+ package(){ "CLOCK", package(){ "cam_cc_ife_lite_clk", 2 } },
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+
+ // Clk Freq
+ Package()
+ {
+ "PSTATE_SET",
+ 0,
+ // TURBO, NOM
+ Package()
+ {
+ "PSTATE",
+ 0,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_lite_clk", 3, 600000000, 3, }},
+ },
+ // SVS_L1
+ Package()
+ {
+ "PSTATE",
+ 1,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_lite_clk", 3, 480000000, 3, }},
+ },
+ // SVS
+ Package()
+ {
+ "PSTATE",
+ 2,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_lite_clk", 3, 404000000, 3, }},
+ },
+ // Off
+ Package()
+ {
+ "PSTATE",
+ 3,
+ Package(){ "CLOCK", Package(){ "cam_cc_ife_lite_clk", 3, 0, 3, }},
+ },
+ },
+
+ // BW: ICBID_MASTER_CAMNOC_HF1_UNCOMP is used for both ife1 & ife_lite
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 0x3, // Component 3. //ICP component
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 state
+
+ // Vote for QDSS to enable the following AOP clocks:
+ // cam_cc_icp_apb_clk : gcc_mmss_icp_apb_clk : gcc_apb_clk
+ // cam_cc_icp_atb_clk : gcc_mmss_icp_atb_clk : gcc_mmss_at_clk
+ // cam_cc_icp_cti_clk : gcc_mmss_icp_cti_clk : gcc_mmss_trig_clk
+ // cam_cc_icp_ts_clk : gcc_mmss_icp_ts_clk : gcc_qdss_tsctr_clk
+ //
+ package() {"NPARESOURCE", package() {1, "/clk/qdss", 1},},
+
+ // Footswitch Name; Action (1 == Enable; 2 == Disable)
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ package() { "CLOCK", package() { "cam_cc_icp_apb_clk", 1 } },
+
+ package() { "CLOCK", package() { "cam_cc_icp_clk", 1 } }, // SVS. DCVS recommendation
+ package() { "PSTATE_ADJUST", Package() { 0, 1 } }, // Pstate adjustment for clock frequencies. Set to SVS
+
+ package() { "CLOCK", package() { "cam_cc_icp_atb_clk", 1 } },
+ package() { "CLOCK", package() { "cam_cc_icp_cti_clk", 1 } },
+ package() { "CLOCK", package() { "cam_cc_icp_ts_clk", 1 } },
+ },
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 state
+ package(){ "CLOCK", package(){ "cam_cc_icp_ts_clk", 2 } },
+ package(){ "CLOCK", package(){ "cam_cc_icp_cti_clk", 2 } },
+ package(){ "CLOCK", package(){ "cam_cc_icp_atb_clk", 2 } },
+
+ package() { "PSTATE_ADJUST", Package() { 0, 2 } },
+ package(){ "CLOCK", package(){ "cam_cc_icp_clk", 2 } },
+ package(){ "CLOCK", package(){ "cam_cc_icp_apb_clk", 2 } },
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+
+ // Remove the QDSS vote to disable the following AOP clocks:
+ // cam_cc_icp_apb_clk : gcc_mmss_icp_apb_clk : gcc_apb_clk
+ // cam_cc_icp_atb_clk : gcc_mmss_icp_atb_clk : gcc_mmss_at_clk
+ // cam_cc_icp_cti_clk : gcc_mmss_icp_cti_clk : gcc_mmss_trig_clk
+ // cam_cc_icp_ts_clk : gcc_mmss_icp_ts_clk : gcc_qdss_tsctr_clk
+ //
+ package() {"NPARESOURCE", package() {1, "/clk/qdss", 0},},
+ },
+
+ Package()
+ {
+ "PSTATE_SET",
+ 0,
+
+ // NOM
+ Package()
+ {
+ "PSTATE",
+ 0,
+ package() { "CLOCK", package() { "cam_cc_icp_clk", 3, 600000000, 3, } },
+
+ },
+
+ // SVS
+ Package()
+ {
+ "PSTATE",
+ 1,
+ package() { "CLOCK", package() { "cam_cc_icp_clk", 3, 400000000, 3, } },
+
+ },
+
+ // Off
+ Package()
+ {
+ "PSTATE",
+ 2,
+ package() { "CLOCK", package() { "cam_cc_icp_clk", 3, 0, 3, } },
+
+ },
+ },
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 0x4, // Component 4. //IPE0/1 component
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 state
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ // IPE0 clocks
+ Package() { "FOOTSWITCH", Package() { "ipe_0_gdsc", 1 } },
+
+ package() { "CLOCK", package() { "cam_cc_ipe_0_ahb_clk", 1 } },
+
+ package() { "CLOCK", package() { "cam_cc_ipe_0_clk", 1 } },
+ package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS
+
+ package() { "CLOCK", package() { "cam_cc_ipe_0_areg_clk", 1 } },
+ package() { "CLOCK", package() { "cam_cc_ipe_0_axi_clk", 1 } },
+
+ Package() { "FOOTSWITCH", Package() { "ipe_0_gdsc", 3 } }, // HW control (TODO: need to enable by ES)
+
+
+ // IPE1 clocks
+ Package() { "FOOTSWITCH", Package() { "ipe_1_gdsc", 1 } },
+
+ package() { "CLOCK", package() { "cam_cc_ipe_1_ahb_clk", 1 } },
+
+ package() { "CLOCK", package() { "cam_cc_ipe_1_clk", 1 } },
+ package() { "PSTATE_ADJUST", Package() { 1, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS
+
+ package() { "CLOCK", package() { "cam_cc_ipe_1_areg_clk", 1 } },
+ package() { "CLOCK", package() { "cam_cc_ipe_1_axi_clk", 1 } },
+
+ Package() { "FOOTSWITCH", Package() { "ipe_1_gdsc", 3 } }, // HW control (TODO: need to enable by ES)
+
+ },
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 state
+
+
+ Package() { "FOOTSWITCH", Package() { "ipe_1_gdsc", 4 } }, // HW control (TODO: need to enable by ES)
+
+ package() { "CLOCK", package() { "cam_cc_ipe_1_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_ipe_1_areg_clk", 2 } },
+
+ package() { "PSTATE_ADJUST", Package() { 1, 4 } },
+ package() { "CLOCK", package() { "cam_cc_ipe_1_clk", 2 } },
+
+ package() { "CLOCK", package() { "cam_cc_ipe_1_ahb_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "ipe_1_gdsc", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "ipe_0_gdsc", 4 } }, // HW control (TODO: need to enable by ES)
+
+ package() { "CLOCK", package() { "cam_cc_ipe_0_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_ipe_0_areg_clk", 2 } },
+
+ package() { "PSTATE_ADJUST", Package() { 0, 4 } },
+ package() { "CLOCK", package() { "cam_cc_ipe_0_clk", 2 } },
+
+ package() { "CLOCK", package() { "cam_cc_ipe_0_ahb_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "ipe_0_gdsc", 2 } },
+
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+
+ // Clk Freq
+ Package()
+ {
+ "PSTATE_SET",
+ 0,
+ Package() // Turbo
+ {
+ "PSTATE",
+ 0,
+ Package(){ "CLOCK", Package(){ "cam_cc_ipe_0_clk", 3, 600000000, 3, }},
+ },
+ Package() // SVS_L1
+ {
+ "PSTATE",
+ 1,
+ Package(){ "CLOCK", Package(){ "cam_cc_ipe_0_clk", 3, 480000000, 3, }},
+ },
+ Package() // SVS
+ {
+ "PSTATE",
+ 2,
+ Package(){ "CLOCK", Package(){ "cam_cc_ipe_0_clk", 3, 404000000, 3, }},
+ },
+ Package() // Off
+ {
+ "PSTATE",
+ 3,
+ Package(){ "CLOCK", Package(){ "cam_cc_ipe_0_clk", 3, 0, 3, }},
+ },
+ },
+
+ // Clk Freq
+ Package()
+ {
+ "PSTATE_SET",
+ 1,
+ Package() // Turbo
+ {
+ "PSTATE",
+ 0,
+ Package(){ "CLOCK", Package(){ "cam_cc_ipe_1_clk", 3, 600000000, 3, }},
+ },
+ Package() // SVS_L1
+ {
+ "PSTATE",
+ 1,
+ Package(){ "CLOCK", Package(){ "cam_cc_ipe_1_clk", 3, 480000000, 3, }},
+ },
+ Package() // SVS
+ {
+ "PSTATE",
+ 2,
+ Package(){ "CLOCK", Package(){ "cam_cc_ipe_1_clk", 3, 404000000, 3, }},
+ },
+ Package() // Off
+ {
+ "PSTATE",
+ 3,
+ Package(){ "CLOCK", Package(){ "cam_cc_ipe_1_clk", 3, 0, 3, }},
+ },
+ },
+
+ // IPE0/1 AHB & AREG Freq: TODO
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 0x5, // Component 5. //BPS component
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 state
+ // Footswitch Name; Action (1 == Enable; 2 == Disable; 3 = HW_CONTROL enable, 4 = HW_CONTROL disable)
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ // BPS clocks
+ Package() { "FOOTSWITCH", Package() { "bps_gdsc", 1 } },
+
+ package() { "CLOCK", package() { "cam_cc_bps_ahb_clk", 1 } }, // SVS
+
+ package() { "CLOCK", package() { "cam_cc_bps_clk", 1 } },
+ package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS
+
+ package() { "CLOCK", package() { "cam_cc_bps_areg_clk", 1 } }, // SVS
+ package() { "CLOCK", package() { "cam_cc_bps_axi_clk", 1 } },
+
+ Package() { "FOOTSWITCH", Package() { "bps_gdsc", 3 } }, // HW control (TODO: need to enable by ES)
+
+
+ },
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 state
+
+ Package() { "FOOTSWITCH", Package() { "bps_gdsc", 4 } }, // HW control (TODO: need to enable by ES)
+
+ package() { "CLOCK", package() { "cam_cc_bps_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_bps_areg_clk", 2 } },
+
+ package() { "PSTATE_ADJUST", Package() { 0, 4 } },
+ package() { "CLOCK", package() { "cam_cc_bps_clk", 2 } },
+
+ package() { "CLOCK", package() { "cam_cc_bps_ahb_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "bps_gdsc", 2 } },
+
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+
+ // Clk Freq
+ Package()
+ {
+ "PSTATE_SET",
+ 0,
+ Package() // Turbo
+ {
+ "PSTATE",
+ 0,
+ Package(){ "CLOCK", Package(){ "cam_cc_bps_clk", 3, 600000000, 3, }},
+ },
+ Package() // SVS_L1
+ {
+ "PSTATE",
+ 1,
+ Package(){ "CLOCK", Package(){ "cam_cc_bps_clk", 3, 480000000, 3, }},
+ },
+ Package() // SVS
+ {
+ "PSTATE",
+ 2,
+ Package(){ "CLOCK", Package(){ "cam_cc_bps_clk", 3, 404000000, 3, }},
+ },
+ Package() // Off
+ {
+ "PSTATE",
+ 3,
+ Package(){ "CLOCK", Package(){ "cam_cc_bps_clk", 3, 0, 3, }},
+ },
+ },
+ // BPS AHB & AREG Freq: TODO
+ },
+
+ Package()
+ {
+ "COMPONENT",
+ 0x6, // Component 6. //LRME component
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 state
+
+ // Footswitch Name; Action (1 == Enable; 2 == Disable; )
+
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ // LRME clocks
+ package() { "CLOCK", package() { "cam_cc_lrme_clk", 1 } },
+ package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS
+ },
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 state
+
+ package() { "PSTATE_ADJUST", Package() { 0, 4 } },
+ package() { "CLOCK", package() { "cam_cc_lrme_clk", 2 } },
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+
+ // Clk Freq
+ Package()
+ {
+ "PSTATE_SET",
+ 0,
+ Package() // Turbo, NOM
+ {
+ "PSTATE",
+ 0,
+ Package(){ "CLOCK", Package(){ "cam_cc_lrme_clk", 3, 400000000, 3, }},
+ },
+ Package() // SVS_L1
+ {
+ "PSTATE",
+ 1,
+ Package(){ "CLOCK", Package(){ "cam_cc_lrme_clk", 3, 320000000, 3, }},
+ },
+ Package() // SVS
+ {
+ "PSTATE",
+ 2,
+ Package(){ "CLOCK", Package(){ "cam_cc_lrme_clk", 3, 269000000, 3, }},
+ },
+ Package() // Off
+ {
+ "PSTATE",
+ 3,
+ Package(){ "CLOCK", Package(){ "cam_cc_lrme_clk", 3, 0, 3, }},
+ },
+ },
+ },
+
+
+ Package()
+ {
+ "COMPONENT",
+ 0x7, // Component 7. //FD component
+ Package()
+ {
+ "FSTATE",
+ 0x0, // F0 state
+
+ // Footswitch Name; Action (1 == Enable; 2 == Disable; )
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
+
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
+
+ // FD clocks
+ Package() { "CLOCK", Package(){ "cam_cc_fd_core_clk", 1 }}, // SVS. DCVS recommendation
+ package() { "PSTATE_ADJUST", Package() { 0, 2 } }, // Pstate adjustment for clock frequencies. Set to SVS
+
+ },
+ Package()
+ {
+ "FSTATE",
+ 0x1, // F1 state
+
+ package() { "PSTATE_ADJUST", Package() { 0, 4 } },
+ package() { "CLOCK", package() { "cam_cc_fd_core_clk", 2 } },
+
+ package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
+
+ Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
+ package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
+ },
+
+ // Clk Freq
+ Package()
+ {
+ "PSTATE_SET",
+ 0,
+ Package() // Turbo, NOM
+ {
+ "PSTATE",
+ 0,
+ Package(){ "CLOCK", Package(){ "cam_cc_fd_core_clk", 3, 600000000, 3, }},
+ },
+ Package() // SVS_L1
+ {
+ "PSTATE",
+ 1,
+ Package(){ "CLOCK", Package(){ "cam_cc_fd_core_clk", 3, 538000000, 3, }},
+ },
+ Package() // SVS
+ {
+ "PSTATE",
+ 2,
+ Package(){ "CLOCK", Package(){ "cam_cc_fd_core_clk", 3, 400000000, 3, }},
+ },
+ Package() // Off
+ {
+ "PSTATE",
+ 3,
+ Package(){ "CLOCK", Package(){ "cam_cc_fd_core_clk", 3, 0, 3, }},
+ },
+ },
+ },
+ },
+ })
+}
--- /dev/null
+//
+// Camera Platform, Camera Sensors, White LED Flash, JPEG HW, VFE Moved to a dedicated asl
+// This is done to support Multiple platforms and Multiple OEM Projects in CRM Builds
+//
+Include("cust_camera.asl")
+Include("cust_sensors.asl")
+
+// GPIO_11
+
+Method (ADDR)
+{
+ If(Lequal(\_SB_.SVMJ, 1))
+ {
+ return(0x390B000)
+ }
+ ElseIf(Lequal(\_SB_.SVMJ, 2))
+ {
+ return(0x350B000)
+ }
+}
+
+OperationRegion(NM11, SystemMemory, ADDR, 0x14)
+Field(NM11, DWordAcc, NoLock, Preserve){
+ PI1C, 32,
+ PIN1, 32,
+ PI1N, 32,
+ PI1S, 32,
+ PI1L, 32,
+}
+
+// BOARD VERSION (NBID)
+// NBID == 0x0 i.e. FULL MODEM BUILD
+// NBID == 0x1 i.e. NO MODEM BUILD
+
+Method (_MID, 0, Serialized) {
+ Name(NMID, Zero)
+ Store(PIN1, NMID)
+ Return (NMID)
+}
--- /dev/null
+Name(HWNH, 0)
+Name(HWNL, 0)
+
+//
+// HWN Haptics
+//
+Device (HWN1)
+{
+ Name (_HID, "QCOM02A9")
+ Alias(\_SB.PSUB, _SUB)
+
+ Method (_STA)
+ {
+ if(LEqual(\_SB_.HWNH, 0)) {
+ Return (0)
+ }
+ else {
+ Return (0x0F)
+ }
+ }
+
+ Name (_DEP,
+ Package(0x1)
+ {
+ \_SB_.PMIC
+ }
+ )
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF,
+ ResourceTemplate ()
+ {
+ // Short Circuit IRQ
+ GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.PM01", , , , ) {400} // 0xE00 - PM_INT__HAPTICS__SC_INT
+
+ // Play IRQ
+ // GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.PM01", , , , ) {401} // 0xE01 - PM_INT__HAPTICS__PLAY_INT
+ }
+ )
+ Return(RBUF)
+ }
+
+ /* ACPI methods for HAPI - Haptics Device info */
+ Method(HAPI, 0x0, NotSerialized)
+ {
+ Name (CFG0,
+ Package()
+ {
+ 1, // TotalHwnVib - Total HWN Vibs
+ 1, // PmicNumber - PMIC Number for HWN Vibs
+ 1, // HapticsConfigInputSource - Read configuration from 0: Registry, 1: ACPI (HAPC method)
+ }
+ )
+ Return (CFG0)
+ }
+
+ /* ACPI methods for HAPC - Haptics configuration method */
+ Method(HAPC, 0x0, NotSerialized)
+ {
+ Name (CFG0,
+ Package()
+ {
+ //------------------------ Actuator Config -----------------------------------------------------
+ 0, // VibType - 0: LRA, 1: ERM
+ 2436, // VibVmaxCfg - 2436 mV
+ 0, // PeakCurrentLimit - 0: 400ma, 1: 800ma
+ 1, // ShortCircuitDebounce - 0: No Deb, 1: 8 clk cycles, 2: 16 clk cycles, 3: 32 clk cycles
+ 1, // InternalPWMFreq - 0: 253KHz, 1: 505KHz, 2: 739KHz, 3: 1076KHz
+ 1, // PWMCapacitance - 0: 26PF, 1: 13PF, 2: 8p7PF, 3: 6p5PF
+ 1, // SlewRate - 0: 6ns, 1: 16ns
+ 0, // LRASignalType - 0: Sinusoidal, 1: Square
+ //----------------------------------------------------------------------------------------------
+
+ //------------------------ LRA Auto Resonance Config -------------------------------------------
+ 4, // LRAAutoResMode - 0: No auto resonance, 1: ZXD, 2: QWD, 3: MAX QWD, 4: ZXD with EOP
+
+ 1, // LRAAutoResHighZDuration - 0: No HighZ,
+ // 1: [2 LRA period (ZXD), 1/8 LRA period (QWD)],
+ // 2: [3 LRA period (ZXD), 1/4 LRA period (QWD)],
+ // 3: [4 LRA period (ZXD), 1/2 LRA period (QWD)]
+
+ 3, // LRAAutoResCalibFreqZXD - 0: 4 LRA periods, 1: 8 LRA periods,
+ // 2: 16 LRA periods, 3: 32 LRA periods
+
+ 20, // InitialAutoResDelayQWD - Delay(in ms) used for QWD mode before enabling auto-resonance
+ // Typical value is 5-20ms. This is to ensure there is enough
+ // back emf for Auto Resonance to work fine.
+ // - This is a don't care in ZXD mode
+ //----------------------------------------------------------------------------------------------
+
+ //------------------------ Braking Config ------------------------------------------------------
+ 1, // AutoBrakingEnable - 0: Disable, 1: Enable
+ 0x03, // BrakePattern - brake pattern of [0,0,0,VMAX] = [ 00 00 00 11] = 0x03
+ 0, // BrakeWithMaxVoltageEnable - 0: Disable, 1: Enable - Brake pattern applied with max voltage
+ // that can be supplied by PMIC Haptics module
+ //----------------------------------------------------------------------------------------------
+
+ //------------------------ Acceleration Config -------------------------------------------------
+ 0, // DirectModeAccelerationEnable - 0: Disable, 1: Enable
+ 6, // DirectModeAccelerationDuration - in milli seconds
+ //----------------------------------------------------------------------------------------------
+
+ 0, // HapticsSource - 0: VMAX, 1: BUFFER, 2: AUDIO, 3: EXT PWM
+ 0, // HapticsTrigger - 0: Play, 1: Line In
+ 1333, // PlayRateCode - LRA Freq 150Hz, PlayRateCode = (200 * 1000) / LRA_Freq
+
+ 3, // MaxSCIntrRetries - Max SC Interrupt retries before crashing the device
+
+ 1, // HapticsAutoResErrorRecover - Enable Auto Resonance Error recovery support
+ }
+ )
+ Return (CFG0)
+ }
+}
+
+
+//
+// HWN LED
+//
+Device (HWN0)
+{
+ Name (_HID, "QCOM02A8")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 0)
+
+ Method (_STA)
+ {
+ if(LEqual(\_SB_.HWNL, 0)) {
+ Return (0)
+ }
+ else {
+ Return (0x0F)
+ }
+ }
+
+ // ACPI method for LED Configs
+ Method(HWNL, 0x0, NotSerialized)
+ {
+ Name (CFG0,
+ Package()
+ {
+ 1, // PMIC number PMI8994
+ 3, // Total HWN LEDs
+
+ //RGB LEDs
+ 411, // Fade interval in ms (0-511 ms)
+ 20, // Fade Steps i.e 5, 10, 15, 20(max)
+
+ 0x20, // LED0 Id (BLUE)
+ 0x02, // LED0 bank on PMI8998 (LPG_CHAN3)
+
+ 0x40, // LED1 Id (GREEN)
+ 0x03, // LED1 bank on PMI8998 (LPG_CHAN4)
+
+ 0x80, // LED2 Id (RED)
+ 0x04, // LED2 bank on PMI8998 (LPG_CHAN5)
+
+ //RGB PWM Config
+ 1, //PWM bit Resoultion
+ //Valid Inputs ( 0 - 6 bit mode, 1 - 9 bit mode)
+ 1, //PWM_EN_HI
+ 1, //PWM_EN_LO
+ 3, //PWM_MASTER_CLK_FREQ
+ //Valid Inputs(0- No Clk, 1 - 1.024 KHz, 2 - 32.764 KHz, 3 - 19.2 MHz)
+ 1, //Clock Pre Divide (Values can be 1, 3, 5, 6)
+ 1, //Exponent (Values range 0 - 7)
+ })
+ Return (CFG0)
+ }
+}
--- /dev/null
+// This file contains the Power Management IC (PMIC)
+// customer-modifiable ACPI configurations.
+//
+
+//******************************************
+//Configs for Battery Manager Device: PMBT
+//******************************************
+//--------------------
+//PMBT: Method(BBAT)
+//--------------------
+Name(BFCC, 13100) //* (mWh), Full Charge Capacity
+Name(PCT1, 5) //* (% of FCC), Default Alert 1
+Name(PCT2, 9) //* (% of FCC), Default Alert 2
+
+//--------------------
+//PMBT: Method(BMNR)
+//--------------------
+Name(CUST, "850_MTP") //* cust file identifier
+
+//--------------------
+//PMBT: Method(BPLT)
+//--------------------
+Name(VNOM, 3800) //* (mV), Nominal Battery Voltage
+Name(VLOW, 3300) //* (mV), Low Battery Voltage
+Name(EMPT, 3200) //* (mV), VCutOff
+Name(DCMA, 900) //* (mA), DC Current
+Name(BOCP, 4500) //* (mA), OCP current used in BCL
+Name(BVLO, 3000) //* (mV), BCL low Vbatt
+Name(BLOP, 20) //* (%), BCL Low batt percent notification
+Name(BNOP, 22) //* (%), BCL normal batt percent notification
+Name(IFGD, 50) //* (mA), FG Iterm delta; (iterm + this value) determines when FG report 100%
+Name(VFGD, 50) //* (mV), CC to CV Vdelta; (Vfloat - this value) determine when FG report 100%
+
+//--------------------------------
+//PMBT: Method(BJTA)/Method(BAT1)
+//--------------------------------
+Name(VDD1, 4350) //* (mV), Battery-1: Float Voltage (Standard Zone)
+Name(FCC1, 2100) //* (mA), Battery-1: Full Charge Current (Standard Zone)
+Name(HCLI, 0) //* (degree C), hard-cold temperature limit
+Name(SCLI, 10) //* (degree C), soft-cold temperature limit
+Name(SHLI, 45) //* (degree C), soft-hot temperature limit
+Name(HHLI, 55) //* (degree C), hard-hot temperature limit
+Name(FVC1, 105) //* (mV), Float voltage compensation, when battery in JEITA soft-limit
+Name(CCC1, 1000) //* (mA), Charge current compensation, when battery in JEITA soft-limit
+
+//--------------------
+//PMBT: Method(CTMC)
+//--------------------
+Name(RID2, 15000) //* (Ohm), min RID for NORMAL category: 15K
+Name(RID3, 140000) //* (Ohm), max RID for NORMAL category: 140K
--- /dev/null
+// This file contains the sensor ACPI device definitions.
+//
+
+
+// Qualcomm Sensor Collection
+Device (SEN2)
+{
+ Name (_DEP, Package(0x3)
+ {
+ \_SB_.IPC0, //IPC Router used by QMI
+ \_SB_.SCSS, //SCSS loads the sensors image
+ \_SB_.ARPC //Dependency on FastRPC
+ })
+ Name (_HID, "QCOM0308")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_CID, "QCOM02A2")
+
+ // Methods used for parsing the sensors configuration (.conf) file.
+ // HARD corresponds to ":hardware"
+ // PLAT corresponds to ":platform"
+ Method(HARD, 0x0, NotSerialized) {
+ Return("845")
+ }
+ Method(PLAT, 0x0, NotSerialized) {
+ Return("MTP")
+ }
+ Method(_STA, 0)
+ {
+ Return (0x0)
+ }
+}
--- /dev/null
+ //CPU Aggregator Device -- Required for Thermal Parking
+ Device(AGR0)
+ {
+ Name(_HID, "ACPI000C")
+ Name(_PUR, Package() {1, 0})
+ Method(_OST, 0x3, NotSerialized)
+ {
+ Store(Arg2, \_SB_.PEP0.ROST)
+ }
+ }
+
+ //---------------------------------------------------------------------
+ //
+ // Thermal Zones for QC reference hardware
+ //
+ //TZ0 - TZ39 are thermal zones developed by QC for reference hardware
+ //and can be modified by the OEMs.
+ //---------------------------------------------------------------------
+
+ //---------------------------------------------------------------------
+ // Thermal Zones(0-19) for CPU sensors
+ //24AD - Little CPU virtual sensor
+ //24AE - Big CPU virtual sensor
+ // This thermal zone is only used for temperature logging for little CPUs
+ // as you may notice that _PSV, _TC1, _TC2, _TSP params are removed.
+ // This is the passive cooling mechanism by dialing down frequency is now
+ // done actively by hardware.
+ //---------------------------------------------------------------------
+ ThermalZone (TZ0) {
+ Name (_HID, "QCOM02B0")
+ Name (_UID, 0)
+ Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3})
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ } // end of TZ0
+
+ //Regular Thermal Zone for Little CPU TSENS to Park cores at 110C
+ ThermalZone (TZ1) {
+ Name (_HID, "QCOM02B0")
+ Name (_UID, 1)
+ Name(_TZD, Package (){\_SB.PEP0})
+ Name(TPSV, 3830)
+ Method(_PSV) { Return (\_SB.TZ1.TPSV) }
+ Name(_MTL, 20) // minimum throttle limit
+ //Control how aggressively the thermal manager applies thermal
+ //throttling performance against temperature change.
+ Name(TTC1, 0)
+ Method(_TC1) { Return (\_SB.TZ1.TTC1) }
+
+ // _TC2 Controls how aggressively the thermal manager applies thermal
+ // throttling performance against temperature delta between the
+ // current temperature and _PSV.
+ // once the temp goes above _PSV, we like to have aggressive
+ // throttling based on how far above the temp is above the threshold.
+ // Since that is controlled via _TC2, we like it to be high.
+ // please refer to the ACPI spec 6.0 to understand the significance of
+ // _TC2 or take a look at the explanation at the top of this file.
+ Name(TTC2, 1)
+ Method(_TC2) { Return (\_SB.TZ1.TTC2) }
+
+ // Appropriate temperature sampling interval for the zone in tenths
+ // of a second. The thermal manager uses this interval to determine
+ // how often it should evaluate the thermal throttling performance.
+ // Must be greater than zero. For more information, see Thermal
+ // throttling algorithm on msdn page
+ // https://msdn.microsoft.com/en-us/library/windows/hardware/mt643928(v=vs.85).aspx
+ Name(TTSP, 50)
+ Method(_TSP) { Return (\_SB.TZ1.TTSP) }
+
+ // This optional object evaluates to a recommended polling frequency
+ // (in tenths of seconds) for this thermal zone. A value of zero indicates
+ // that OSPM does not need to poll the temperature of this thermal zone in
+ // order to detect temperature changes (the hardware is capable of
+ // generating asynchronous notifications).
+ // TZP should be marked 0 for all thermal zones as our TSENS sensors
+ // generate interrupts to complete thermal IOCTL read call.
+ Name(_TZP, 0)
+
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ } // end of TZ1
+
+ // This thermal zone is only used for temperature logging for Big CPUs
+ // as you may notice that _PSV, _TC1, _TC2, _TSP params are removed.
+ // This is the passive cooling mechanism by dialing down frequency is now
+ // done actively by hardware.
+ ThermalZone (TZ2) {
+ Name (_HID, "QCOM02B1")
+ Name (_UID, 0)
+ Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5, \_SB.SYSM.CLUS.CPU6, \_SB.SYSM.CLUS.CPU7})
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ } // end of TZ2
+
+ //Regular Thermal Zone for BigCPU TSENS to Park cores at 110C
+ ThermalZone (TZ3) {
+ Name (_HID, "QCOM02B1")
+ Name (_UID, 1)
+ Name(_TZD, Package (){\_SB.PEP0})
+
+ Name(TPSV, 3830)
+ Method(_PSV) { Return (\_SB.TZ3.TPSV) }
+ Name(TTC1, 0)
+ Method(_TC1) { Return (\_SB.TZ3.TTC1) }
+ Name(TTC2, 1)
+ Method(_TC2) { Return (\_SB.TZ3.TTC2) }
+ Name(TTSP, 1)
+ Method(_TSP) { Return (\_SB.TZ3.TTSP) }
+ Name(_MTL, 20) // minimum throttle limit
+ Name(_TZP, 0)
+
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ } // end of TZ3
+
+ //---------------------------------------------------------------------
+ // Thermal Zones(20-21) for GPU TSENS
+ //
+ // \_SB.GPU0 should be used for GPU thermal mitigation, and
+ // \_SB.GPU0.AVS0 should be used for MDSS/Video thermal mitigation.
+ // Currently there is no handling for Video thermal mitigation.
+ // When needed, Video will be added to GPU0.AVS0 interface.
+ //---------------------------------------------------------------------
+ //Thermal zone for TSENS11 dial back GPUs at 95C
+ ThermalZone (TZ20) {
+ Name (_HID, "QCOM02AB")
+ Name (_UID, 0)
+ Name(_TZD, Package (){\_SB.GPU0})
+ Name(TPSV, 3680)
+ Method(_PSV) { Return (\_SB.TZ20.TPSV) }
+ Name(TTC1, 1)
+ Method(_TC1) { Return (\_SB.TZ20.TTC1) }
+ // For non-cpu devices, tc2 should be atleast 5, please refer to the
+ // explanation at the top of the file or msdn link for thermal guide.
+ Name(TTC2, 2)
+ Method(_TC2) { Return (\_SB.TZ20.TTC2) }
+ // For non-cpu devices, _tsp should be 20 or 30
+ Name(TTSP, 2)
+ Method(_TSP) { Return (\_SB.TZ20.TTSP) }
+ Name(_TZP, 0)
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ } // end of TZ20
+
+ //Thermal zone for TSENS12 to dial back GPUs at 95C
+ ThermalZone (TZ21) {
+ Name (_HID, "QCOM02AC")
+ Name (_UID, 0)
+ Name(_TZD, Package (){\_SB.GPU0})
+ Name(TPSV, 3680)
+ Method(_PSV) { Return (\_SB.TZ21.TPSV) }
+ Name(TTC1, 1)
+ Method(_TC1) { Return (\_SB.TZ21.TTC1) }
+ Name(TTC2, 2)
+ Method(_TC2) { Return (\_SB.TZ21.TTC2) }
+ Name(TTSP, 2)
+ Method(_TSP) { Return (\_SB.TZ21.TTSP) }
+ Name(_TZP, 0)
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ } // end of TZ21
+
+ //---------------------------------------------------------------------
+ // Thermal Zones for QDSP TSENS
+ //4/16/15: TODO waiting to get a new HID assigned for TSENS17
+ //---------------------------------------------------------------------
+ //Thermall zone for TSENS14 dial back MSM at 95C
+ //ThermalZone (TZ31) {
+ //Name (_HID, "QCOM02AE")
+ //Name (_UID, 0)
+ //Name(_TZD, Package (){
+ //\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
+ //\_SB.PEP0, \_SB.GPU0.MON0, \_SB.GPU0})
+ //Method(_PSV) { Return (3680) }
+ //Name(_TC1, 1)
+ //Name(_TC2, 2)
+ //Name(_TSP, 10)
+ //Name(_TZP, 0)
+ //Method(_DEP) {
+ // Return (Package() {\_SB.PEP0})
+ //}
+ //} // end of TZ31
+
+ //---------------------------------------------------------------------
+ // Thermal Zones for Camera TSENS
+ //---------------------------------------------------------------------
+ //Thermal zone for TSENS17 to dial back MSM at 95C
+ ThermalZone (TZ32) {
+ Name (_HID, "QCOM02C9")
+ Name (_UID, 0)
+ Name(_TZD, Package (){\_SB.GPU0.AVS0})
+ Name(TPSV, 3680)
+ Method(_PSV) { Return (\_SB.TZ32.TPSV) }
+ Name(TTC1, 1)
+ Method(_TC1) { Return (\_SB.TZ32.TTC1) }
+ // For non-cpu devices, tc2 should be atleast 5, please refer to the
+ // explanation at the top of the file or msdn link for thermal guide.
+ Name(TTC2, 2)
+ Method(_TC2) { Return (\_SB.TZ32.TTC2) }
+ // For non-cpu devices, _tsp should be 20 or 30
+ Name(TTSP, 10)
+ Method(_TSP) { Return (\_SB.TZ32.TTSP) }
+ Name(_TZP, 0)
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ } // end of TZ32
+
+ ThermalZone (TZ33) {
+ Name (_HID, "QCOM02CB")
+ Name (_UID, 1)
+ Name(_TZD, Package (){\_SB.AMSS})
+
+ Name(TPSV, 3680)
+ Method(_PSV) { Return (\_SB.TZ33.TPSV) }
+
+ Name(TTC1, 1)
+ Method(_TC1) { Return (\_SB.TZ33.TTC1) }
+
+ Name(TTC2, 2)
+ Method(_TC2) { Return (\_SB.TZ33.TTC2) }
+
+ Name(TTSP, 10)
+ Method(_TSP) { Return (\_SB.TZ33.TTSP) }
+
+ Name(_TZP, 0)
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ }
+
+ //---------------------------------------------------------------------
+ // Thermal Zones for MDSS TENS (Display Subsystem)
+ // Only the MDP Blt engine and Rotator engines on the MDSS are cooled
+ // using this interface. Display cooling is not supported currently.
+ //---------------------------------------------------------------------
+ //Thermal zone for TSENS18 to dial back MSM at 95C
+ //ThermalZone (TZ34) {
+ //Name (_HID, "QCOM02CA")
+ //Name (_UID, 0)
+ //Name(_TZD, Package (){\_SB.GPU0.AVS0})
+ //Method(_PSV) { Return (3680) }
+ //Name(_TC1, 1)
+ //Name(_TC2, 2)
+ //Name(_TSP, 10)
+ //Name(_TZP, 0)
+ //Method(_DEP) {
+ // Return (Package() {\_SB.PEP0})
+ //}
+ //} // end of TZ34
+
+ //---------------------------------------------------------------------
+ // Thermal Zones for ADC Channels
+ //---------------------------------------------------------------------
+ //Thermal zone for PMIC_THERM
+ ThermalZone (TZ36) {
+ Name (_HID, "QCOM029E")
+ Name (_UID, 0)
+ Name(_TZD, Package (){
+ \_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
+ \_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5, \_SB.SYSM.CLUS.CPU6, \_SB.SYSM.CLUS.CPU7,
+ \_SB.PMBM})
+
+ Name(TPSV, 3780)
+ Method(_PSV) { Return (\_SB.TZ36.TPSV) }
+
+ Name(TTC1, 4)
+ Method(_TC1) { Return (\_SB.TZ36.TTC1) }
+
+ Name(TTC2, 3)
+ Method(_TC2) { Return (\_SB.TZ36.TTC2) }
+
+ Name(TTSP, 50)
+ Method(_TSP) { Return (\_SB.TZ36.TTSP) }
+
+ Name(_TZP, 0)
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0, \_SB.ADC1})
+ }
+ } // end of TZ36
+
+ //Thermal zone for PMIC_THERM
+ ThermalZone (TZ37) {
+ Name (_HID, "QCOM029E")
+ Name (_UID, 1)
+ Name(_TZD, Package (){
+ \_SB.PEP0, \_SB.PMBM})
+ Name(TPSV, 3980)
+ Method(_PSV) { Return (\_SB.TZ37.TPSV) }
+ Name(TCRT, 4180)
+ Method(_CRT) { Return (\_SB.TZ37.TCRT) }
+ Name(TTC1, 4)
+ Method(_TC1) { Return (\_SB.TZ37.TTC1) }
+ Name(TTC2, 3)
+ Method(_TC2) { Return (\_SB.TZ37.TTC2) }
+ Name(TTSP, 50)
+ Method(_TSP) { Return (\_SB.TZ37.TTSP) }
+
+ Name(_TZP, 0)
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0, \_SB.ADC1})
+ }
+ } // end of TZ37
+
+ //Example: Inverse Thermal zone for PMIC_THERM
+ ThermalZone (TZ38) {
+ Name (_HID, "QCOM029E")
+ Name (_UID, 2) //Update UID on addition of new thermal zone with same HID
+ Name(_TZD, Package (){
+ \_SB.PEP0})
+ Method(INVT) { Return (1) }
+ Method(_MTL) { Return (60) }
+ Name(TPSV, 2830)
+ Method(_PSV) { Return (\_SB.TZ38.TPSV) }
+ Name(TTC1, 4)
+ Method(_TC1) { Return (\_SB.TZ38.TTC1) }
+ Name(TTC2, 3)
+ Method(_TC2) { Return (\_SB.TZ38.TTC2) }
+ Name(TTSP, 10)
+ Method(_TSP) { Return (\_SB.TZ38.TTSP) }
+ Name(_TZP, 0)
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0, \_SB.ADC1})
+ }
+ } // end of TZ38
+
+ //------------------------------------------------------------------------
+ // Thermal Zones for Wlan
+ //------------------------------------------------------------------------
+ //Thermal zone for iHelium, Wlan MAC&PHY on SOC
+ ThermalZone (TZ40) {
+ Name (_HID, "QCOM02AF")
+ Name (_UID, 0)
+ Name(_TZD, Package (){\_SB.COEX})
+
+ Name(TPSV, 3580)
+ Method(_PSV) { Return (\_SB.TZ40.TPSV) }
+ Name(TTC1, 1)
+ Method(_TC1) { Return (\_SB.TZ40.TTC1) }
+ Name(TTC2, 5) // For non-cpu devices, tc2 should be atleast 5
+ Method(_TC2) { Return (\_SB.TZ40.TTC2) }
+ Name(TTSP, 30) // For non-cpu devices, _tsp should be 20 or 30
+ Method(_TSP) { Return (\_SB.TZ40.TTSP) }
+
+ Name(_TZP, 0)
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ } // end of TZ40
+ //Thermal zone for Cherokee, Wlan radio on WCN3990
+ ThermalZone (TZ41) {
+ Name (_HID, "QCOM0295")//virtual sensor by wlan WMI thermal interface
+ Name (_UID, 1)
+ //Name(_TZD, Package (){\_SB.COEX}) // Temperature report only
+ //Method(_PSV) { Return (4030) }
+ //Name(_TC1, 4)
+ //Name(_TC2, 3)
+ Name(_TSP, 50)
+ Name(_TZP, 0)
+ } // end of TZ41
+
+ //------------------------------------------------------------------------
+ // Thermal Zones for DDR/POP
+ //------------------------------------------------------------------------
+ //Thermal zone for DDR
+ //Thermal zone for TSENS20 to dial back Big CPU's at 95C
+
+ ThermalZone (TZ44) {
+ Name (_HID, "QCOM02CC")
+ Name (_UID, 0)
+ Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5, \_SB.SYSM.CLUS.CPU6, \_SB.SYSM.CLUS.CPU7})
+ Name(TPSV, 3680)
+ Method(_PSV) { Return (\_SB.TZ44.TPSV) }
+ Name(TTC1, 0)
+ Method(_TC1) { Return (\_SB.TZ44.TTC1) }
+ Name(TTC2, 1)
+ Method(_TC2) { Return (\_SB.TZ44.TTC2) }
+ Name(TTSP, 1)
+ Method(_TSP) { Return (\_SB.TZ44.TTSP) }
+ Name(_TZP, 0)
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ } // end of TZ44
+
+ //---------------------------------------------------------------------
+ //
+ // QC Recommended thermal limits starts
+ //
+ //TZ80 - TZ98 represent the thermal zones corresponding to QC
+ //recommended thermal limits. These thermal zones must not be removed
+ //or tampered with.
+ //---------------------------------------------------------------------
+ //Thermal zone for TSENS2 at 70C to match the LA thermal limits
+ //ThermalZone (TZ80) {
+ //Name (_HID, "QCOM2472")
+ //Name (_UID, 0)
+ //Name(_TZD, Package (){
+ // \_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
+ //Method(_PSV) { Return (3430) }
+ //Name(_TC1, 1)
+ //Name(_TC2, 2)
+ //Name(_TSP, 10)
+ //Name(_TZP, 0)
+ //Method(_DEP) {
+ // Return (Package() {\_SB.PEP0})
+ //}
+ //} // end of TZ80
+
+ //Thermal zone near for TSENS2 to shutdown the system at 85C to match LA
+ //thermal limits
+ //ThermalZone (TZ81) {
+ //Name (_HID, "QCOM2472")
+ //Name (_UID, 1)
+ //Name(_TZD, Package (){
+ // \_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
+ // \_SB.PEP0})
+ //Method(_PSV) { Return (3530) }
+ //Method(_CRT) { Return (3580) }
+ //Name(_TC1, 1)
+ //Name(_TC2, 2)
+ //Name(_TSP, 10)
+ //Name(_TZP, 0)
+ //Method(_DEP) {
+ // Return (Package() {\_SB.PEP0})
+ //}
+ //} // end of TZ81
+
+ //Entry for BCL thermal zone
+ ThermalZone (TZ98) {
+ Name (_HID, "QCOM0294")
+ Name (_UID, 0)
+ Name(_TZD, Package (){
+ \_SB.GPU0.MON0, \_SB.GPU0})
+
+ Name(TPSV, 3630)
+ Method(_PSV) { Return (\_SB.TZ98.TPSV) }
+ Name(TTC1, 1)
+ Method(_TC1) { Return (\_SB.TZ98.TTC1) }
+ //Method(_CRT) { Return (5630) }
+ Name(TTC2, 5)
+ Method(_TC2) { Return (\_SB.TZ98.TTC2) }
+ Name(TTSP, 20)
+ Method(_TSP) { Return (\_SB.TZ98.TTSP) }
+
+ Name(_TZP, 0)
+ Method(_DEP) {
+ Return (Package(0x2) {\_SB.PEP0,\_SB_.BCL1})
+ }
+ } // end of TZ98
+
+ //---------------------------------------------------------------------
+ // Critical Thermal Zones for ALL TSENS
+ //This sensor aggregates all the on chip TSENS into a single sensor
+ //for ACPI thermal manager. By having a critical thermal zone on this
+ //"virtual sensor" we don't have to add a critical thermal zone on every
+ //sensor and hence reduce the number of thermal zones.
+ //---------------------------------------------------------------------
+ //Critical Thermal zone on MSM virtual sensor to shutdown entire system
+ //at 110C.
+ ThermalZone (TZ99) {
+ Name (_HID, "QCOM02B2")
+ Name (_UID, 100)
+
+ Name(TCRT, 3830)
+ Method(_CRT) { Return (\_SB.TZ99.TCRT) }
+ Name(TTC1, 4)
+ Method(_TC1) { Return (\_SB.TZ99.TTC1) }
+ Name(TTC2, 3)
+ Method(_TC2) { Return (\_SB.TZ99.TTC2) }
+ Name(TTSP, 10)
+ Method(_TSP) { Return (\_SB.TZ99.TTSP) }
+ Name(_TZP, 0)
+
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ } // end of TZ99
+
+ //---------------------------------------------------------------------
+ // QC Recommended thermal limits ends
+ //---------------------------------------------------------------------
+
+ //---------------------------------------------------------------------
+ //
+ // Sample Thermal Zones for OEMs TZ40 - TZ79
+ //
+ //Sample TSENS thermal zone that can be added on any TSENS
+ //---------------------------------------------------------------------
+ //ThermalZone (TZ40) {
+ //Name (_HID, "QCOM2470")
+ //Name (_UID, 0)
+ //Name(_TZD, Package (){
+ //\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5,
+ //\_SB.PEP0, <Your cooling device>})
+ //Method(_PSV) { Return (3730) }
+ //Method(_CRT) { Return (3780) }
+ //Name(_TC1, 1)
+ //Name(_TC2, 2)
+ //Name(_TSP, 10) //Sampling rate of 1sec
+ //Name(_TZP, 0)
+ //Method(_DEP) {
+ // Return (Package() {\_SB.PEP0})
+ //}
+ //} // end of TZ40
+
+ //ThermalZone (TZ41) {
+ //Name (_HID, "QCOM2470")
+ //Name (_UID, 0)
+ //Name(_TZD, Package (){
+ //\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5,
+ //\_SB.PEP0, <Your cooling device>})
+ //Method(_PSV) { Return (3730) }
+ //Method(_CRT) { Return (3780) }
+ //Name(_TC1, 1)
+ //Name(_TC2, 2)
+ //Name(_TSP, 50) //Sampling rate of 5sec
+ //Name(_TZP, 0)
+ //Method(_DEP) {
+ // Return (Package() {\_SB.PEP0})
+ //}
+ //} // end of TZ41
+
+
+ //--------------------------------------------------------------------------//
+ //
+ // Sample VADC Thermal zones for OEMs
+ //
+ //Following are sample thermal zones that use the off chip ADC thermistors
+ //they are all currently using CPUs as a cooling device for a lack of better
+ //option. The OEMs should change this.
+ //--------------------------------------------------------------------------//
+
+ //Thermal zone for SYS_THERM2
+ // ThermalZone (TZ51) {
+ // Name (_HID, "QCOM248D")
+ // Name (_UID, 0)
+ // Name(_TZD, Package (){
+ //\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5,})
+ // Method(_PSV) { Return (3830) }
+ //Name(_TC1, 4)
+ //Name(_TC2, 3)
+ // Name(_TSP, 50)
+ //Name(_TZP, 0)
+ //Method(_DEP) {
+ // Return (Package() {\_SB.PEP0})
+ //}
+ // } // end of TZ51
+
+ //Thermal zone for PA_THERM1
+ // ThermalZone (TZ52) {
+ // Name (_HID, "QCOM248E")
+ // Name (_UID, 0)
+ // Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3})
+ // Method(_PSV) { Return (3430) }
+ // Name(_TC1, 4)
+ // Name(_TC2, 3)
+ // Name(_TSP, 50)
+ // Name(_TZP, 0)
+ //Method(_DEP) {
+ // Return (Package() {\_SB.PEP0})
+ //}
+ // } // end of TZ52
--- /dev/null
+//
+// This file contains the touch ACPI device definitions.
+//
+
+Device (TSC1)
+{
+ Name (_HID, "STFT0521") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_DEP, Package (0x03) // _DEP: Dependencies
+ {
+ \_SB.GIO0,
+ \_SB.IC15,
+ \_SB.PEP0
+ })
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ I2cSerialBusV2 (0x0049, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.IC15",
+ 0x00, ResourceConsumer, , Exclusive,
+ )
+ GpioInt (Level, ActiveLow, Exclusive, PullUp, 0x0000,
+ "\\_SB.GIO0", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x001F
+ }
+ })
+ Return (RBUF) /* \_SB_.TSC1._CRS.RBUF */
+ }
+ Name (PGID, Buffer (0x0A)
+ {
+ "\\_SB.TSC1"
+ })
+ Name (DBUF, Buffer (DBFL){})
+ CreateByteField (DBUF, Zero, STAT)
+ CreateByteField (DBUF, 0x02, DVAL)
+ CreateField (DBUF, 0x18, 0xA0, DEID)
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (0x03)
+ }
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (0x03)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (0x03)
+ }
+
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ DEID = Buffer (ESNL){}
+ DVAL = Zero
+ DEID = PGID /* \_SB_.TSC1.PGID */
+ If (\_SB.ABD.AVBL)
+ {
+ \_SB.PEP0.FLD0 = DBUF /* \_SB_.TSC1.DBUF */
+ }
+ }
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ DEID = Buffer (ESNL){}
+ DVAL = 0x03
+ DEID = PGID /* \_SB_.TSC1.PGID */
+ If (\_SB.ABD.AVBL)
+ {
+ \_SB.PEP0.FLD0 = DBUF /* \_SB_.TSC1.DBUF */
+ }
+ }
+}
--- /dev/null
+//===========================================================================
+// <cust_touch_resources.asl>
+// DESCRIPTION
+// This file contains the resources needed by touch driver.
+//
+//===========================================================================
+Scope(\_SB_.PEP0)
+{
+
+ Method(LPMX)
+ {
+ Return(LPXC)
+ }
+
+ Name(LPXC,
+ Package(){
+ Package ()
+ {
+ "DEVICE",
+ "\\_SB.TSC1",
+ Package ()
+ {
+ "DSTATE",
+ Zero,
+ Package ()
+ {
+ "PMICVREGVOTE",
+ Package ()
+ {
+ "PPP_RESOURCE_ID_LDO6_A",
+ One,
+ 0x001C5200,
+ One,
+ 0x07,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "PMICVREGVOTE",
+ Package ()
+ {
+ "PPP_RESOURCE_ID_LDO28_A",
+ One,
+ 0x002DE600,
+ One,
+ 0x07,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 23,
+ One,
+ Zero,
+ One,
+ 0x03,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 125,
+ Zero,
+ Zero,
+ Zero,
+ 0x03,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 32,
+ Zero,
+ Zero,
+ One,
+ Zero,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "DELAY",
+ Package ()
+ {
+ 0x02
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 32,
+ One,
+ Zero,
+ One,
+ Zero,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "DELAY",
+ Package ()
+ {
+ 0xC8
+ }
+ }
+ },
+
+ Package ()
+ {
+ "DSTATE",
+ 0x03,
+ Package ()
+ {
+ "PMICVREGVOTE",
+ Package ()
+ {
+ "PPP_RESOURCE_ID_LDO6_A",
+ One,
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "PMICVREGVOTE",
+ Package ()
+ {
+ "PPP_RESOURCE_ID_LDO28_A",
+ One,
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 23,
+ Zero,
+ Zero,
+ One,
+ One,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 32,
+ Zero,
+ Zero,
+ Zero,
+ One,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 125,
+ Zero,
+ Zero,
+ Zero,
+ One,
+ Zero
+ }
+ }
+ }
+ }
+ })
+}
--- /dev/null
+//
+// MPROC Drivers (PIL Driver and Subsystem Drivers)
+//
+
+Scope(\_SB.ADSP)
+{
+
+}
+
+Scope(\_SB.AMSS)
+{
+
+}
+
+Scope(\_SB.SCSS)
+{
+
+}
+
+Scope(\_SB.PILC)
+{
+
+}
+
+Scope(\_SB.CDI)
+{
+
+}
+
+Scope(\_SB.RPEN)
+{
+
+}
--- /dev/null
+//
+// This file contains the ACPI Extensions for Display Adapters
+//
+///
+// _ROM Method - Used to retrieve proprietary ROM data for primary panel
+//
+Method (_ROM, 3, NotSerialized) {
+
+ // Include primary panel specific ROM data
+ Include("panelcfg.asl")
+
+ //======================================================================================
+ // Based on the panel Id(Arg2), store the buffer object into Local2
+ //
+ // IMPORTANT:
+ // PCFG is buffer name for all default panel configurations
+ // All other dynamically detected panel configurations must not use this name
+ //======================================================================================
+
+ Local2 = PCFG
+
+ // Ensure offset does not exceed the buffer size
+ // otherwise return a Null terminated buffer
+ If (LGreaterEqual(Arg0, Sizeof(Local2)))
+ {
+ Return( Buffer(){0x0} )
+ }
+ Else
+ {
+ // Make a local copy of the offset
+ Store(Arg0, Local0)
+ }
+
+ // Ensure the size requested is less than 4k
+ If (LGreater(Arg1, 0x1000))
+ {
+ Store(0x1000, Local1)
+ }
+ else
+ {
+ Store(Arg1, Local1)
+ }
+
+ // Finaly ensure the total size does not exceed the size of the buffer
+ if (LGreater(Add(Local0, Local1), Sizeof(Local2)))
+ {
+ // Calculate the maximum size we can return
+ Subtract(Sizeof(Local2), Local0, Local1);
+ }
+
+ // Multiply offset and size by 8 to convert to bytes and create the RBuf
+ CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
+
+ Return(RBUF)
+}
+
+//
+// IGC method - panel inverse gamma correction table.
+//
+// The buffer contains inverse gamma correction data for 3 color components, each with 256 16-bit integers.
+// The buffer size is 3*256*2 = 1536 bytes.
+// each table entry is represend by a 16-bit integer and data format in the buffer is described below:
+//
+// +--- 16 bits ---+--- 16 bits ---+--- 16 bits ---+---------+--- 16 bits ---+ 0
+// | Red[0] | Red[1] | Red[2] | ... | Red[255] |
+// +---------------+---------------+---------------+---------+---------------+ 512
+// | Green[0] | Green[1] | Green[2] | ... | Green[255] |
+// +---------------+---------------+---------------+---------+---------------+ 1024
+// | Blue[0] | Blue[1] | Blue[2] | ... | Blue[255] |
+// +---------------+---------------+---------------+---------+---------------+ 1536
+//
+Method (PIGC, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the IGC buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (RBUF, Buffer() {0x0} )
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+//
+// PCC method - panel color correction matrix
+//
+// Buffer format for HW which support 3X8 color correction matrix.
+//
+// The buffer contains color correction coefficients for 3 color components, each with 11 64-bit integers.
+// The buffer size is 3*11*8 = 264 bytes.
+// each coefficient in the matrix is represented by a long long integer (64-bit), and data format in the
+// buffer is described below:
+//
+// +--64 bits--+--64 bits--+--------+--64 bits--+--64 bits--+--64 bits--+--64 bits--+ 0
+// | Red[0] | Red[1] | ... | Red[7] | 0 | 0 | 0 |
+// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 88
+// | Green[0] | Green[1] | ... | Green[7] | 0 | 0 | 0 |
+// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 176
+// | Blue[0] | Blue[1] | ... | Blue[7] | 0 | 0 | 0 |
+// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 264
+//
+// Buffer format for HW which support 3X11 color correction matrix.
+//
+// The buffer contains color correction coefficients for 3 color components, each with 11 64-bit integers.
+// The buffer size is 3*11*8 = 264 bytes.
+// each coefficient in the matrix is represented by a long long integer (64-bit), and data format in the
+// buffer is described below:
+//
+// +--- 64 bits ---+--- 64 bits ---+--- 64 bits ---+-----------+--- 64 bits ---+ 0
+// | Red[0] | Red[1] | Red[2] | ... | Red[10] |
+// +---------------+---------------+---------------+-----------+---------------+ 88
+// | Green[0] | Green[1] | Green[2] | ... | Green[10] |
+// +---------------+---------------+---------------+-----------+---------------+ 176
+// | Blue[0] | Blue[1] | Blue[2] | ... | Blue[10] |
+// +---------------+---------------+---------------+-----------+---------------+ 264
+//
+Method (PPCC, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the PCC buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (RBUF, Buffer() {0x0} )
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+//
+// PGC method - panel segment gamma correction table
+//
+// there're thee components and each with 16 gamma correction segments. Each segment is defined
+// as below with parameters, and each parameter is represented by a 32-bit integer (DWORD):
+//
+// +--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--+
+// | enable | start | gain | offset | one gamma correction segment(16 bytes)
+// +-----------+-----------+-----------+-----------+
+//
+// +--- 16 bytes ---+--- 16 bytes ---+--- 16 bytes ---+-----------+--- 16 bytes ---+ 0
+// | red_seg[0] | red_seg[1] | red_seg[2] | ... | red_seg[15] |
+// +----------------+----------------+----------------+-----------+----------------+ 256
+// | green_seg[0] | green_seg[1] | green_seg[2] | ... | green_seg[15] |
+// +----------------+----------------+----------------+-----------+----------------+ 512
+// | blue_seg[0] | blue_seg[1] | blue_seg[2] | ... | blue_seg[15] |
+// +----------------+----------------+----------------+-----------+----------------+ 768
+//
+Method (PGCT, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the GCT buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (RBUF, Buffer() {0x0} )
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+//
+// PLGC method - panel linear gamma correction table
+//
+// There are three color components, each color component has 1024 entries. each entry is 2 bytes.
+//
+// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+ 0
+// | red[0] | red[1] | red[2] | ... | red[1023] |
+// +---------------+---------------+---------------+-----------+---------------+ 2048
+// | green[0] | green[1] | green[2] | ... | green[1023] |
+// +---------------+---------------+---------------+-----------+---------------+ 4096
+// | blue[0] | blue[1] | blue[2] | ... | blue[1023] |
+// +---------------+---------------+---------------+-----------+---------------+ 6144
+//
+Method (PLGC, 3, NotSerialized) {
+ // Arg0 - Panel ID
+ // Arg1 - Data offset
+ // Arg2 - Data size
+
+ // Based on the panel Id read the LGC buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (TBUF, Buffer() {0x0} )
+
+
+ // Ensure offset does not exceed the buffer size
+ // otherwise return a Null terminated buffer
+ If (LGreaterEqual(Arg1, Sizeof(TBUF)))
+ {
+ Return( Buffer(){0x0} )
+ }
+ Else
+ {
+ // Make a local copy of the offset
+ Store(Arg1, Local1)
+ }
+
+ // Arg2 - Data size
+ // Ensure the size requested is less than 4k
+ If (LGreater(Arg2, 0x1000))
+ {
+ Store(0x1000, Local2)
+ }
+ else
+ {
+ Store(Arg2, Local2)
+ }
+
+ // Finaly ensure the total size does not exceed the size of the buffer
+ if (LGreater(Add(Local1, Local2), Sizeof(TBUF)))
+ {
+ // Calculate the maximum size we can return
+ Subtract(Sizeof(TBUF), Local1, Local2);
+ }
+
+ // Multiply offset and size by 8 to convert to bytes and create the RBUF
+ CreateField(TBUF, Multiply(0x8, Local1), Multiply(0x8, Local2), RBUF)
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+//
+// HSIC method - HSIC settings
+//
+// Hue, Saturation, Intensity, Contrast levels, the first parameter enable/disable HSIC control,
+// followed by HSIC level values, each level ranges from -100 to 100, represented by a 32-bit integer:
+//
+// +--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--++
+// | Enable | Hue | Saturation| Intensity | Contrast |
+// +-----------+-----------+-----------+-----------+-----------++
+//
+//
+Method (HSIC, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the HSIC buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (RBUF, Buffer() {0x0} )
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+
+//
+// PGMT - panel gamut mapping table for HW which support 9x9x9 gamut mapping:
+//
+// This method returns the gamut mapping table for a panel.
+//
+// There are three components. Each component has 8 tables and a total of 729 entries.
+// Each value is represented by a 16-bit integer:
+//
+// Table ID Entries
+// 0 125
+// 1 100
+// 2 80
+// 3 100
+// 4 100
+// 5 80
+// 6 64
+// 7 80
+//
+// +----- 16 bits -----+----- 16 bits ------+----- 16 bits -----+-----------+----- 16 bits -------+
+// | red_comp[0][0] | red_comp[0][1] | red_comp[0][2] | ... | red_comp[7][79] |
+// +-------------------+--------------------+-------------------+---------------------------------+
+// | green_comp[0][0] | green_comp[0][1] | green_comp[0][2] | ... | green_comp[7][79] |
+// +-------------------+--------------------+-------------------+---------------------------------+
+// | blue_comp[0][0] | blue_comp[0][1] | blue_comp[0][2] | ... | blue_comp[7][79] |
+// +-------------------+--------------------+-------------------+---------------------------------+
+//
+Method (PGMT, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the GMT buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (TBUF, Buffer() {0x0} )
+
+
+ // Ensure offset does not exceed the buffer size
+ // otherwise return a Null terminated buffer
+ If (LGreaterEqual(Arg0, Sizeof(TBUF)))
+ {
+ Return( Buffer(){0x0} )
+ }
+ Else
+ {
+ // Make a local copy of the offset
+ Store(Arg0, Local0)
+ }
+
+ // Arg1 - Data size
+ // Ensure the size requested is less than 4k
+ If (LGreater(Arg1, 0x1000))
+ {
+ Store(0x1000, Local1)
+ }
+ else
+ {
+ Store(Arg1, Local1)
+ }
+
+ // Finaly ensure the total size does not exceed the size of the buffer
+ if (LGreater(Add(Local0, Local1), Sizeof(TBUF)))
+ {
+ // Calculate the maximum size we can return
+ Subtract(Sizeof(TBUF), Local0, Local1);
+ }
+
+ // Multiply offset and size by 8 to convert to bytes and create the RBUF
+ CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
+
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+
+//
+// PWGM - panel gamut mapping data for HW which support 17x17x17 gamut mapping
+//
+// This data's header which has two fields:
+// NumSamplesPerColorComponent: Number samples per color component in gamut mapping table.
+// NumSegmentsPerColor : Number of segments per color component.
+// NumSegmentsPerColor must equal 0 or NumSamplesPerColorComponent -1.
+//
+// This data also can have two tables, one is 3d table, one is segment table.
+// Segment table is only required if NumSegmentsPerColor != 0.
+//
+// 3d table: There are three components. If number samples per component is N = NumSamplesPerColorComponent,
+// total entries are NxNxN per component. Each value is represented by a 16-bit integer:
+// Segment table: There are three components, table entries are uNumSegmentsPerColor per component,
+// each entry is 32 bit value.
+//
+// Table data header:
+// +--------- 32 bits ----------+------- 32 bits -----+
+// | NumSamplesPerColorComponent| NumSegmentsPerColor |
+// +----------------------------+---------------------+ 8 bytes
+//
+// 3d table:
+// +---- 16 bits ----+---- 16 bits ----+---- 16 bits ----+-------------+------- 16 bits -----------+ 8
+// | red_comp[0] | red_comp[1] | red_comp[2] | ... | red_comp[N x N x N - 1 ] |
+// +-----------------+-----------------+-----------------+-------------+---------------------------+ NxNxNx2 + 8
+// | green_comp[0] | green_comp[1] | green_comp[2] | ... | green_comp[N x N x N - 1] |
+// +-----------------+-----------------+-----------------+-------------+---------------------------+ 2xNxNxNx2 + 8
+// | blue_comp[0] | blue_comp[1] | blue_comp[2] | ... | blue_comp[N x N x N - 1] |
+// +-----------------+-----------------+-----------------+-------------+---------------------------+ 3xNxNxNx2 + 8
+//
+// Segment table: ( if NumSegmentsPerColor = 0, there is no segment table).
+// +----- 32 bits ------+----- 32 bits ------+------ 32 bits -----+-------------+-------- 32 bits -------+ 3xNxNxNx2 + 8
+// | sg_red_comp[[0] | sg_red_comp[1] | sg_red_comp[2] | ... | sg_red_comp[N-2] |
+// +--------------------+--------------------+--------------------+-------------+------------------------+ (N-1)x4 + 3xNxNxNx2 + 8
+// | sg_green_comp[0] | sg_ green_comp[1] | sg_ green_comp[2] | ... | sg_green_comp[N-2] |
+// +--------------------+--------------------+--------------------+-------------+------------------------+ 2x(N-1)x4 + 3xNxNxNx2 + 8
+// | sg_ blue_comp[0] | sg_ blue_comp[1] | sg_ blue_comp[2] | ... | sg_ blue_comp[N-2] |
+// +--------------------+--------------------+------------------- +-------------+------------------------+ 3x(N-1)x4 + 3xNxNxNx2 + 8
+//
+// Maximum size = 3 x(17 - 1) x 4 + 3 x 17 x 17 x 17 x 2 + 8 = 29678 bytes.
+//
+Method (PWGM, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the WGM buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (TBUF, Buffer() {0x0} )
+
+
+ // Ensure offset does not exceed the buffer size
+ // otherwise return a Null terminated buffer
+ If (LGreaterEqual(Arg0, Sizeof(TBUF)))
+ {
+ Return( Buffer(){0x0} )
+ }
+ Else
+ {
+ // Make a local copy of the offset
+ Store(Arg0, Local0)
+ }
+
+ // Arg1 - Data size
+ // Ensure the size requested is less than 4k
+ If (LGreater(Arg1, 0x1000))
+ {
+ Store(0x1000, Local1)
+ }
+ else
+ {
+ Store(Arg1, Local1)
+ }
+
+ // Finaly ensure the total size does not exceed the size of the buffer
+ if (LGreater(Add(Local0, Local1), Sizeof(TBUF)))
+ {
+ // Calculate the maximum size we can return
+ Subtract(Sizeof(TBUF), Local0, Local1);
+ }
+
+ // Multiply offset and size by 8 to convert to bytes and create the RBUF
+ CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
+
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+
+//
+// PGRT - panel gamma response table
+//
+// This method returns the Gamma response table for a panel.
+// The table is given in 2 arrays, one representing the x axis or grayscale and other
+// representing the y axis or luminance.
+//
+// The table is given in a 256 entries array, where the first entry value represents
+// the luminance (Y) achieved when displaying black on the screen (shade value is 0
+// for all R, G and B) and the last entry represents the luminance (Y) achieved when
+// displaying white on the screen (shade value is 255 for all R, G and B).
+//
+// The array must be 256 entries.
+//
+// The range of each entry must be from 0 to 0xffff
+//
+// Values are least significant byte first. E.g. {0x01, 0x00} represents 0x1 and
+// {0x02, 0x01} represents 0x0102
+//
+// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+
+// | Y[0] | Y[1] | Y[2] | ... | Y[255] |
+// +---------------+---------------+---------------+-----------+---------------+
+Method (PGRT, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the GRT buffer and return the data
+
+ // If nothing specified return NULL
+
+ Name (RBUF, Buffer() {0x0})
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+//
+// PBRT - panel backlight response table
+//
+// This method returns the Backlight response table for a panel.
+// The table is given in a 256 entries array, where the first entry value represents
+// the backlight level (BL) to achieve 0 luminance and the last entry represents
+// the highest backlight level to achieve the maximum desired luminance.
+// In other words, this array serves as a map from luminance to backlight levels,
+// where the index is the desired luminance level and the value (or output) is
+// the backlight level to be sent to the hardware (backlight controller).
+//
+// The array must be 256 entries.
+//
+// The range of each entry must be from 0 to 0xffff
+//
+// Values are least significant byte first. E.g. {0x01, 0x00} represents 0x1 and
+// {0x02, 0x01} represents 0x0102
+//
+// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+
+// | BL[0] | BL[1] | BL[2] | ... | BL[255] |
+// +---------------+---------------+---------------+-----------+---------------+
+Method (PBRT, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the BRT buffer and return the data
+
+ // If nothing specified return NULL
+
+ Name (RBUF, Buffer(){0x0})
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+//
+// PBRC - panel backlight response curve for CABL
+//
+// This method returns the Backlight response curve for a panel used specifically for CABL algorithm.
+// The curve is represented in a maximum 1024 x 2 elements array, where the first entry in each row
+// will be backlight level and next entry will be correponding luminance value. In other words,
+// this array serves as a map from backlight to luminance levels.
+
+// First row will be number of control points in the backlight curve. Maximum number of points allowed is 1024.
+// Points on the backlight response curve has to be specified in increasing order i.e last control point will
+// correspond for maximum backlight value and first control point will correspond for minimum backlight value.
+
+// The buffer must be of 4*(2*x + 1) bytes. where x < 1024 is number of control points.
+//
+// The range of each backlight or luminance value must be from 0 to 0xffff. ( 2 bytes each )
+//
+// Values are least significant byte first. E.g. {0x01, 0x00} represents 0x1 and
+// {0x02, 0x01} represents 0x0102.
+
+// Below is an example of Backlight Response curve consisting of 5 control points.
+
+// +----- 2 bytes -----------+----- 2 bytes ------+
+// | table_length | |
+// +-------------------------+--------------------+
+// | BacklightLevel[0] | Luminance[0] |
+// +-------------------------+--------------------+
+// | BacklightLevel[1] | Luminance[1] |
+// +-------------------------+--------------------+
+// | BacklightLevel[2] | Luminance[2] |
+// +-------------------------+--------------------+
+// | BacklightLevel[3] | Luminance[3] |
+// +-------------------------+--------------------+
+// | BacklightLevel[4] | Luminance[4] |
+// +-------------------------+--------------------+
+Method (PBRC, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the BRC buffer and return the data
+
+ // If nothing specified return NULL
+
+ Name (RBUF, Buffer() {0x00,0x00})
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+//
+// DITH method - Dithering settings
+//
+// Dithering matrix could have following two formats:
+//
+// Format 1:
+// +--1 byte--------+--1 byte--------+--1 byte--------+--1 byte--------+
+// | Element[0,0] | Element[0,1] | Element[0,2] | Element[0,3] |
+// | Element[1,0] | Element[1,1] | Element[1,2] | Element[1,3] |
+// | Element[2,0] | Element[2,1] | Element[2,2] | Element[2,3] |
+// | Element[3,0] | Element[3,1] | Element[3,2] | Element[3,3] |
+// | Bit Depth C2 | Bit Depth C1 | Bit Depth C0 | Reserved(0x0) |
+// +----------------+----------------+----------------+----------------+
+// | Dithering mode (4 bytes) (0: not supported, 1:Spatial, 2:Temporal)|
+// +----------------+----------------+----------------+----------------+
+//
+// There is dithering mode in Format 1.
+//
+// Format 2:
+//
+// +--1 byte--------+--1 byte--------+--1 byte--------+--1 byte--------++
+// | Element[0,0] | Element[0,1] | Element[0,2] | Element[0,3] |
+// | Element[1,0] | Element[1,1] | Element[1,2] | Element[1,3] |
+// | Element[2,0] | Element[2,1] | Element[2,2] | Element[2,3] |
+// | Element[3,0] | Element[3,1] | Element[3,2] | Element[3,3] |
+// | Bit Depth C2 | Bit Depth C1 | Bit Depth C0 | Reserved(0x0) |
+// +----------------+----------------+----------------+----------------+
+//
+// There is no dithering mode in Format 2. Default dither mode: spatial.
+//
+Method (DITH, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the DITH buffer and return the data
+
+ // If nothing specified return NULL
+ // Create response buffer
+ Name (RBUF, Buffer() {0x0} )
+
+ // Return the packet data
+ Return(RBUF)
+}
+// Include primary panel specific configuration for backlight control packets
+//
+Include("backlightcfg.asl")
--- /dev/null
+//
+// This file contains the ACPI Extensions for Secondary Display Adapters
+//
+
+//
+// ROM2 Method - Used to retrieve proprietary ROM data for secondary panel
+//
+Method (ROM2, 3, NotSerialized) {
+
+ // Include secondary panel specific ROM data
+ Include("panelcfg2.asl")
+
+ //======================================================================================
+ // Based on the panel Id(Arg2), store the buffer object into Local2
+ //
+ // IMPORTANT:
+ // PCFG is buffer name for all default panel configurations
+ // All other dynamically detected panel configurations must not use this name
+ //======================================================================================
+ Switch ( ToInteger (Arg2) )
+ {
+ // Default case
+ Default {
+ Store (PCFG, Local2)
+ }
+ }
+
+ // Ensure offset does not exceed the buffer size
+ // otherwise return a Null terminated buffer
+ If (LGreaterEqual(Arg0, Sizeof(Local2)))
+ {
+ Return( Buffer(){0x0} )
+ }
+ Else
+ {
+ // Make a local copy of the offset
+ Store(Arg0, Local0)
+ }
+
+ // Ensure the size requested is less than 4k
+ If (LGreater(Arg1, 0x1000))
+ {
+ Store(0x1000, Local1)
+ }
+ else
+ {
+ Store(Arg1, Local1)
+ }
+
+ // Finaly ensure the total size does not exceed the size of the buffer
+ if (LGreater(Add(Local0, Local1), Sizeof(Local2)))
+ {
+ // Calculate the maximum size we can return
+ Subtract(Sizeof(Local2), Local0, Local1);
+ }
+
+ // Multiply offset and size by 8 to convert to bytes and create the RBuf
+ CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
+
+ Return(RBUF)
+}
+
+//
+// IGC2 method - panel inverse gamma correction table.
+//
+// Secondary panel IGC2 configuration, format is same as IGCT of primary
+// panel in display.asl
+//
+Method (IGC2, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the IGC buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (RBUF, Buffer() {0x0} )
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+//
+// PCC2 method - panel color correction matrix
+// Secondary panel PCC2 configuration, format is same as PPCC of primary
+// panel in display.asl
+//
+Method (PCC2, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the PCC buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (RBUF, Buffer() {0x0} )
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+//
+// GCT2 method - panel segment gamma correction table
+// Secondary panel GCT2 configuration, format is same as PGCT of primary
+// panel in display.asl
+//
+Method (GCT2, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the GCT buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (RBUF, Buffer() {0x0} )
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+//
+// LGC2 method - panel linear gamma correction table
+// Secondary panel LGC2 configuration, format is same as PLGC of primary
+// panel in display.asl
+//
+Method (LGC2, 3, NotSerialized) {
+
+ // Arg0 - Panel ID
+ // Arg1 - Data offset
+ // Arg2 - Data size
+
+ // Based on the panel Id read the LGC buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (TBUF, Buffer() {0x0} )
+
+
+ // Ensure offset does not exceed the buffer size
+ // otherwise return a Null terminated buffer
+ If (LGreaterEqual(Arg1, Sizeof(TBUF)))
+ {
+ Return( Buffer(){0x0} )
+ }
+ Else
+ {
+ // Make a local copy of the offset
+ Store(Arg1, Local1)
+ }
+
+ // Arg2 - Data size
+ // Ensure the size requested is less than 4k
+ If (LGreater(Arg2, 0x1000))
+ {
+ Store(0x1000, Local2)
+ }
+ else
+ {
+ Store(Arg2, Local2)
+ }
+
+ // Finaly ensure the total size does not exceed the size of the buffer
+ if (LGreater(Add(Local1, Local2), Sizeof(TBUF)))
+ {
+ // Calculate the maximum size we can return
+ Subtract(Sizeof(TBUF), Local1, Local2);
+ }
+
+ // Multiply offset and size by 8 to convert to bytes and create the RBUF
+ CreateField(TBUF, Multiply(0x8, Local1), Multiply(0x8, Local2), RBUF)
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+//
+// HSI2 method - HSIC settings
+// Secondary panel HSI2 configuration, format is same as HSIC of primary
+// panel in display.asl
+//
+Method (HSI2, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the HSIC buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (RBUF, Buffer() {0x0} )
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+
+//
+// GMT2 - panel gamut mapping table for HW which support 9x9x9 gamut mapping:
+// Secondary panel GMT2 configuration, format is same as PGMT of primary
+// panel in display.asl
+//
+Method (GMT2, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the GMT buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (TBUF, Buffer() {0x0} )
+
+
+ // Ensure offset does not exceed the buffer size
+ // otherwise return a Null terminated buffer
+ If (LGreaterEqual(Arg0, Sizeof(TBUF)))
+ {
+ Return( Buffer(){0x0} )
+ }
+ Else
+ {
+ // Make a local copy of the offset
+ Store(Arg0, Local0)
+ }
+
+ // Arg1 - Data size
+ // Ensure the size requested is less than 4k
+ If (LGreater(Arg1, 0x1000))
+ {
+ Store(0x1000, Local1)
+ }
+ else
+ {
+ Store(Arg1, Local1)
+ }
+
+ // Finaly ensure the total size does not exceed the size of the buffer
+ if (LGreater(Add(Local0, Local1), Sizeof(TBUF)))
+ {
+ // Calculate the maximum size we can return
+ Subtract(Sizeof(TBUF), Local0, Local1);
+ }
+
+ // Multiply offset and size by 8 to convert to bytes and create the RBUF
+ CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
+
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+
+//
+// WGM2 - panel gamut mapping data for HW which support 17x17x17 gamut mapping
+// Secondary panel WGM2 configuration, format is same as PWGM of primary
+// panel in display.asl
+//
+Method (WGM2, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the WGM buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (TBUF, Buffer() {0x0} )
+
+
+ // Ensure offset does not exceed the buffer size
+ // otherwise return a Null terminated buffer
+ If (LGreaterEqual(Arg0, Sizeof(TBUF)))
+ {
+ Return( Buffer(){0x0} )
+ }
+ Else
+ {
+ // Make a local copy of the offset
+ Store(Arg0, Local0)
+ }
+
+ // Arg1 - Data size
+ // Ensure the size requested is less than 4k
+ If (LGreater(Arg1, 0x1000))
+ {
+ Store(0x1000, Local1)
+ }
+ else
+ {
+ Store(Arg1, Local1)
+ }
+
+ // Finaly ensure the total size does not exceed the size of the buffer
+ if (LGreater(Add(Local0, Local1), Sizeof(TBUF)))
+ {
+ // Calculate the maximum size we can return
+ Subtract(Sizeof(TBUF), Local0, Local1);
+ }
+
+ // Multiply offset and size by 8 to convert to bytes and create the RBUF
+ CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
+
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+
+//
+// GRT2 - panel gamma response table
+// Secondary panel GRT2 configuration, format is same as PGRT of primary
+// panel in display.asl
+//
+Method (GRT2, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the GRT buffer and return the data
+
+ // If nothing specified return NULL
+
+ Name (RBUF, Buffer() {0x0})
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+//
+// BRT2 - panel backlight response table
+// Secondary panel BRT2 configuration, format is same as PBRT of primary
+// panel in display.asl
+//
+Method (BRT2, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the BRT buffer and return the data
+
+ // If nothing specified return NULL
+
+ Name (RBUF, Buffer() {0x0})
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+//
+// DIT2 method - Dithering settings
+// Secondary panel DIT2 configuration, format is same as DITH of primary
+// panel in display.asl
+//
+Method (DIT2, 2, NotSerialized) {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ // Based on the panel Id read the DITH buffer and return the data
+
+ // If nothing specified return NULL
+
+ // Create response buffer
+ Name (RBUF, Buffer() {0x0} )
+
+ // Return the packet data
+ Return(RBUF)
+}
+// Include secondary panel specific configuration for backlight control packets
+//
+Include("backlightcfg2.asl")
--- /dev/null
+//
+// This file contains the ACPI Extensions for External Display Adapters
+//
+
+//
+// ROE1 Method - Used to retrieve proprietary ROM data for External display
+//
+Method (ROE1, 3, NotSerialized) {
+
+ // Include external panel specific ROM data
+ Include("panelcfgext.asl")
+
+ // Store the panel configuration
+ Store (PCFG, Local2)
+
+ // Ensure offset does not exceed the buffer size
+ // otherwise return a Null terminated buffer
+ If (LGreaterEqual(Arg0, Sizeof(Local2)))
+ {
+ Return( Buffer(){0x0} )
+ }
+ Else
+ {
+ // Make a local copy of the offset
+ Store(Arg0, Local0)
+ }
+
+ // Ensure the size requested is less than 4k
+ If (LGreater(Arg1, 0x1000))
+ {
+ Store(0x1000, Local1)
+ }
+ else
+ {
+ Store(Arg1, Local1)
+ }
+
+ // Finaly ensure the total size does not exceed the size of the buffer
+ if (LGreater(Add(Local0, Local1), Sizeof(Local2)))
+ {
+ // Calculate the maximum size we can return
+ Subtract(Sizeof(Local2), Local0, Local1);
+ }
+
+ // Multiply offset and size by 8 to convert to bytes and create the RBuf
+ CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
+
+ Return(RBUF)
+}
--- /dev/null
+// To enable SOC revision based run time differentiation, uncomment following line
+// and uncomment SSID method in ABD device. The original string is artificailly set as
+// 16 characters, so there is enough room to hold SOC revision string.
+// To adjust the number, the MAX_SOCID_LEN macro as defined in ABD device.h should be
+// adjusted at the same time.
+
+Name (SOID, 0x0141) // Holds the Chip Id
+Name (SIDS, "SDM845") // Holds the Chip ID translated to a string
+Name (SIDV, 0x00020001) // Holds the Chip Version as (major<<16)|(minor&0xffff)
+Name (SVMJ, 0x02) // Holds the major Chip Version
+Name (SVMI, One) // Holds the minor Chip Version
+Name (SDFE, 0x4F) // Holds the Chip Family enum
+Name (SFES, "899800000000000") // Holds the Chip Family translated to a string
+Name (SIDM, 0x0000000FFFFF00FF) // Holds the Modem Support bit field
+Name (SOSN, 0x000003F48D126594)
+Name (RMTB, 0x85D00000)
+Name (RMTX, 0x00200000)
+Name (RFMB, Zero)
+Name (RFMS, Zero)
+Name (RFAB, Zero)
+Name (RFAS, Zero)
+Name (TPMA, 0x11111111) // Holds whether TPM is seperate app or combined with Winsecapp
+Name (TDTV, 0x6654504D) // Holds TPM type, by default it set to fTPM type
+Name (TCMA, 0x8AB00000) // Holds TrEE Carveout Memory Address
+Name (TCML, 0x01400000) // Holds TrEE Carveout Memory Length
+// Name (SOSI, 0xdeadbeefffffffff) // Holds the base address of the SoCInfo shared memory region used by ChipInfoLib
+
+//Audio Drivers
+Include("audio.asl")
+
+ //
+ // Storage - UFS/SD
+ //
+ Include("../Common/ufs.asl")
+ // Include("../Common/sdc.asl") // No SD support on polaris
+
+ //
+ // ASL Bridge Device
+ //
+ Include("../Common/abd.asl")
+
+ Name (ESNL, 20) // Exsoc name limit 20 characters
+ Name (DBFL, 23) // buffer Length, should be ESNL+3
+
+//
+// PMIC driver
+//
+Include("../Common/pmic_core.asl")
+
+//
+// PMICTCC driver
+//
+Include("pmic_batt.asl")
+
+ Include("pep.asl")
+ Include("../Common/bam.asl")
+ Include("buses.asl")
+ // MPROC Drivers (PIL Driver and Subsystem Drivers)
+ Include("../Common/win_mproc.asl")
+ Include("../Common/syscache.asl")
+ Include("../Common/HoyaSmmu.asl")
+ Include("graphics.asl")
+
+ Include("../Common/SCM.asl");
+
+ //
+ // SPMI driver
+ //
+ Include("../Common/spmi.asl")
+
+ //
+ // TLMM controller.
+ //
+ Include("qcgpio.asl")
+
+ Include("../Common/pcie.asl")
+
+ Include("../Common/cbsp_mproc.asl")
+
+ Include("../Common/adsprpc.asl")
+
+ //
+ // RemoteFS
+ //
+ Include("../Common/rfs.asl")
+
+
+ // Test Drivers
+ Include("testdev.asl")
+ //
+
+ //
+ // Qualcomm IPA
+ Include("../Common/ipa.asl")
+
+ Include("../Common/gsi.asl")
+
+ //
+ //Qualcomm DIAG Service
+ //
+ Device (QDIG)
+ {
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.GLNK
+ })
+ Name (_HID, "QCOM0225")
+ Alias(\_SB.PSUB, _SUB)
+ }
+ Include("../Common/qcdb.asl")
+ Include("../Common/pep_lpi.asl")
+
+ //
+ // QcRNG Driver (qcsecuremsm)
+ //
+ Device (QRNG)
+ {
+ Name (_DEP, Package(0x1) {
+ \_SB_.PEP0,
+ })
+ Name (_HID, "QCOM02FE")
+ Name (_UID, 0)
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // PRNG_CFG_EE2_EE2_PRNG_SUB register address space
+ Memory32Fixed (ReadWrite, 0x00793000, 0x00001000)
+ })
+ Return (RBUF)
+ }
+ }
+
+ //
+ // QCOM GPS
+ //
+ Include("../Common/gps.asl")
+
+ // QDSS driver
+ Include("../Common/Qdss.asl")
+
+// QUPV3 GPI device node and resources
+//
+Include("../Common/qgpi.asl")
+
+Include("nfc.asl")
+
+Include("../Common/sar_manager.asl")
--- /dev/null
+//--------------------------------------------------------------------------------------------------
+// GfxXMLToACPI Version 2.3.
+//--------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------
+// This file contains all graphics ACPI Device Configuration Information and Methods
+//
+// !!WARNING: This is an auto-generated file and should NOT be edited by hand!!
+// This file contains several interdependent ACPI methods that are all generated from
+// a single XML source. Items in this file should not be updated manually, as they
+// will be overwritten by the auto-generated output. Instead, modifications should be
+// made to the XML source, such that they are applied across all relevant tables.
+//--------------------------------------------------------------------------------------------------
+
+Device (GPU0)
+{
+ Name (_HID, "QCOM027E")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_CID, "ACPI\QCOM027E")
+ Name (_UID, 0)
+ Name (_HRV, 0x07C)
+
+ // Expose the internal monitor device to allow it to be used in a thermal zone
+ // for thermal mitigation.
+ //
+ Device (MON0)
+ {
+ Method(_ADR)
+ {
+ // 0 is always the address assigned for the internal monitor.
+ //
+ Return(0)
+ }
+ }
+
+ Name (_DEP, Package()
+ {
+ \_SB_.MMU0,
+ \_SB_.MMU1,
+ \_SB_.IMM0,
+ \_SB_.IMM1,
+ \_SB_.PEP0,
+ \_SB_.PMIC,
+ \_SB_.PILC,
+ \_SB_.RPEN,
+ \_SB_.TREE,
+ \_SB_.SCM0,
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // MDP register/memory space (IPCAT->SoC->Memory Maps->Config NOC->MMSS->MMSS_MDSS). Address range includes RSCC
+ //
+ Memory32Fixed(ReadWrite, 0x0AE00000, 0x00140000)
+
+ // DP PHY register/memory space (IPCAT->SoC->Memory Maps->Config NOC->PERIPH_SS_AHB2PHY_NORTH)
+ //
+ Memory32Fixed(ReadWrite, 0x088E0000, 0x000F4000)
+
+ // MDP Interrupt, vsync (IPCAT->SoC->Interrupts->SDM850->mdp_irq)
+ //
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {115}
+
+ // GPU register space (IPCAT->SoC->Memory Maps->Config NOC->A6X) from SWI Browser
+ //
+ Memory32Fixed(ReadWrite, 0x05000000, 0x0003F010)
+
+ // GPU register space (IPCAT->SoC->Memory Maps->Config NOC->A6X) from SWI Browser
+ //
+ Memory32Fixed(ReadWrite, 0x05060000, 0x0003F000)
+
+ // GPU Interrupt (IPCAT->SoC->Interrupts->SDM850->gc_sys_irq[0]) (Source Subsystem = GPU Subsystem, Subsystem Port = gc_sys_irq[0])
+ //
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {332}
+
+ // GPU register space (IPCAT->SoC->Memory Maps->Config NOC->A6X) from SWI Browser
+ //
+ Memory32Fixed(ReadWrite, 0x0B280000, 0x0000FFFF)
+
+ // GPU register space (IPCAT->SoC->Memory Maps->Config NOC->A6X) from SWI Browser
+ //
+ Memory32Fixed(ReadWrite, 0x0B480000, 0x00010000)
+
+ // GPU register space (IPCAT->SoC->Memory Maps->Config NOC->A6X) from SWI Browser
+ //
+ Memory32Fixed(ReadWrite, 0x05090000, 0x00009000)
+
+ // GPU RPMh CPRF register range
+ //
+ Memory32Fixed(ReadWrite, 0x0C200000, 0x0000FFFF)
+
+ // VIDC register address space (IPCAT->SoC->Memory Maps->Config NOC->Video_SS_Wrapper)
+ //
+ Memory32Fixed(ReadWrite, 0x0AA00000, 0x00200000)
+
+ // VIDC Interrupt (IPCAT->SoC->Interrupts->SDM850->VENUS_IRQ)
+ //
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {206}
+
+ // VIDC Interrupt (IPCAT->SoC->Interrupts->SDM850->VENUS_WD_IRQ)
+ //
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {207}
+
+ // TLMM GPIO used to reset the DSI panel
+ //
+ GpioIo(Exclusive, PullUp, 0, 0, , "\\_SB.GIO0", ,) {96}
+
+ // TLMM GPIO used to select DSI panel mode
+ //
+ // GpioIo(Exclusive, PullUp, 0, 0, , "\\_SB.GIO0", ,) {52}
+
+ // TLMM GPIO used to DP AUX polarity select
+ //
+ // GpioIo(Shared, PullUp, 0, 0, , "\\_SB.GIO0", ,) {51}
+ })
+ Return (RBUF)
+ }
+
+ //------------------------------------------------------------------------------
+ // Resource Auxiliary Info
+ // This method is a companion method to the main _CRS resource method. It
+ // includes information for each resource, such as the owning component, a
+ // string identifier, etc.
+ //------------------------------------------------------------------------------
+ //
+ Method (RESI, 0x0, NotSerialized)
+ {
+ Name (RINF, Package()
+ {
+ 3, // Table Format Major Version
+ 0, // Table Format Minor Version
+
+ // MDP register/memory space (IPCAT->SoC->Memory Maps->Config NOC->MMSS->MMSS_MDSS). Address range includes RSCC
+ //
+ Package()
+ {
+ "RESOURCE",
+ "MDP_REGS", // Resource Name
+ "DISPLAY", // Owning Component
+ },
+
+ // DP PHY register/memory space (IPCAT->SoC->Memory Maps->Config NOC->PERIPH_SS_AHB2PHY_NORTH)
+ //
+ Package()
+ {
+ "RESOURCE",
+ "DP_PHY_REGS", // Resource Name
+ "DISPLAY", // Owning Component
+ },
+
+ // MDP Interrupt, vsync (IPCAT->SoC->Interrupts->SDM850->mdp_irq)
+ //
+ Package()
+ {
+ "RESOURCE",
+ "VSYNC_INTERRUPT", // Resource Name
+ "DISPLAY", // Owning Component
+ },
+
+ // GPU register space (IPCAT->SoC->Memory Maps->Config NOC->A6X) from SWI Browser
+ //
+ Package()
+ {
+ "RESOURCE",
+ "GFX_REGS", // Resource Name
+ "GRAPHICS", // Owning Component
+ },
+
+ // GPU register space (IPCAT->SoC->Memory Maps->Config NOC->A6X) from SWI Browser
+ //
+ Package()
+ {
+ "RESOURCE",
+ "GFX_REG_CONT", // Resource Name
+ "GRAPHICS", // Owning Component
+ },
+
+ // GPU Interrupt (IPCAT->SoC->Interrupts->SDM850->gc_sys_irq[0]) (Source Subsystem = GPU Subsystem, Subsystem Port = gc_sys_irq[0])
+ //
+ Package()
+ {
+ "RESOURCE",
+ "GFX_INTERRUPT", // Resource Name
+ "GRAPHICS", // Owning Component
+ },
+
+ // GPU register space (IPCAT->SoC->Memory Maps->Config NOC->A6X) from SWI Browser
+ //
+ Package()
+ {
+ "RESOURCE",
+ "GPU_PDC_SEQ_MEM", // Resource Name
+ "GRAPHICS", // Owning Component
+ },
+
+ // GPU register space (IPCAT->SoC->Memory Maps->Config NOC->A6X) from SWI Browser
+ //
+ Package()
+ {
+ "RESOURCE",
+ "GPU_PDC_REGS", // Resource Name
+ "GRAPHICS", // Owning Component
+ },
+
+ // GPU register space (IPCAT->SoC->Memory Maps->Config NOC->A6X) from SWI Browser
+ //
+ Package()
+ {
+ "RESOURCE",
+ "GPU_CC", // Resource Name
+ "GRAPHICS", // Owning Component
+ },
+
+ // GPU RPMh CPRF register range
+ //
+ Package()
+ {
+ "RESOURCE",
+ "GPU_RPMH_CPRF", // Resource Name
+ "GRAPHICS", // Owning Component
+ },
+
+ // VIDC register address space (IPCAT->SoC->Memory Maps->Config NOC->Video_SS_Wrapper)
+ //
+ Package()
+ {
+ "RESOURCE",
+ "VIDEO_REGS", // Resource Name
+ "VIDEO", // Owning Component
+ },
+
+ // VIDC Interrupt (IPCAT->SoC->Interrupts->SDM850->VENUS_IRQ)
+ //
+ Package()
+ {
+ "RESOURCE",
+ "VIDC_INTERRUPT", // Resource Name
+ "VIDEO", // Owning Component
+ },
+
+ // VIDC Interrupt (IPCAT->SoC->Interrupts->SDM850->VENUS_WD_IRQ)
+ //
+ Package()
+ {
+ "RESOURCE",
+ "VIDC_WD_INTERRUPT", // Resource Name
+ "VIDEO", // Owning Component
+ },
+
+ // TLMM GPIO used to reset the DSI panel
+ //
+ Package()
+ {
+ "RESOURCE",
+ "DSI_PANEL_RESET", // Resource Name
+ "DISPLAY", // Owning Component
+ },
+
+ // TLMM GPIO used to select DSI panel mode
+ //
+ // Package()
+ // {
+ // "RESOURCE",
+ // "DSI_PANEL_MODE_SELECT", // Resource Name
+ // "DISPLAY", // Owning Component
+ // },
+
+ // TLMM GPIO used to DP AUX polarity select
+ //
+ // Package()
+ // {
+ // "RESOURCE",
+ // "DP_AUX", // Resource Name
+ // "DISPLAY", // Owning Component
+ // },
+ })
+
+ Return (RINF)
+ }
+
+ //------------------------------------------------------------------------------
+ // Graphics Engines and Display Config
+ // This method encapsulates all per-platform configuration data for engines and
+ // the display. This method consists of three sub-packages. The first package
+ // encapsulates all configuration information for the supported engines. The
+ // second package encapsulates all display configuration data. The third
+ // package is the list of all page tables used by the SMMUs in the engines and
+ // display.
+ //------------------------------------------------------------------------------
+ //
+ Method (ENGS)
+ {
+ Name (EBUF, Package()
+ {
+ 3, // Table Format Major Version
+ 2, // Table Format Minor Version
+ 0x00440029, // XML Common/Platform Source File Revision (16.16)
+
+ //------------------------------------------------------------------------------
+ // Graphics Engine List
+ // This package enumerates all of the expected engines that should be enumerated
+ // on this platform, as well as engine-specific configuration data. This
+ // includes resource assignments, power component assignments, MMU IDs,
+ // and even chip family information.
+ //------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "ENGINES",
+ 6, // Number of engines
+
+ Package()
+ {
+ "ENGINE",
+ "GRAPHICS", // Engine String Identifier
+ "Adreno6X", // Chip Family Identifier
+ 1, // Index of Primary Power Component
+ 2, // P-State Set Index of Footswitch override
+ 0, // P-State Set Index of Reset
+ Package()
+ {
+ "MMUINFO",
+ "Miniport", // SMMU managed by miniport or engine
+ "ArmSmmuV2", // SMMU Family
+ 2, // Number of SMMU stages
+ 49, // Address bits
+ "V8L", // Address format
+ "SMMUID", ToUUID("9833C712-3292-4FFB-B0F4-2BD20E1F7F66"),
+ "SMMUINTERFACEID", ToUUID("00000000-0000-0000-0000-000000000000"),
+ // If default the above would be:
+ // ToUUID("00000000-0000-0000-0000-000000000000")
+ Package()
+ {
+ "PAGETABLEUSAGE",
+ 4, // Number of page tables
+ "GraphicsGlobalPT", 0, 0x03030000 ,
+ "GraphicsPerProcessPT", 0, 0x03030000 ,
+ "GraphicsSecurePT", 1, 0x030A0000 ,
+ "GraphicsGmuPT", 3, 0x03030002 ,
+ },
+ },
+ Package()
+ {
+ "PERF_CONTROLS",
+ Package()
+ { // CX_HS_MGMT
+ 1, // State Set Index
+ },
+ Package()
+ { //
+ 3, // State Set Index
+ Package()
+ {
+ "LimitForPassiveCooling", // Property Name
+ 0x00000001, // Value
+ },
+ },
+ Package()
+ { // GRAPHICS_BW_CONTROL
+ 4, // State Set Index
+ Package()
+ {
+ "LimitForPassiveCooling", // Property Name
+ 0x00000001, // Value
+ },
+ },
+ },
+ Package()
+ {
+ "THERMAL_DOMAINS",
+ "GPU",
+ },
+ Package()
+ {
+ "PROPERTIES",
+ 3, // Number of properties
+ Package()
+ {
+ "GmemBaseAddr", // Property Name
+ 0x00000000, // Value
+ },
+ Package()
+ {
+ "GmemSize", // Property Name
+ 0x00100000, // Value
+ },
+ Package()
+ {
+ "SMMUCount", // Property Name
+ 0x00000001, // Value
+ },
+ },
+ },
+
+ Package()
+ {
+ "ENGINE",
+ "MDPBLT", // Engine String Identifier
+ "MDP5.x", // Chip Family Identifier
+ 2, // Index of Primary Power Component
+ 1, // P-State Set Index of Footswitch override
+ 0, // P-State Set Index of Reset
+ Package()
+ {
+ "SHAREDSMMU",
+ "ROTATOR", // Engine whose SMMU is shared
+ },
+ Package()
+ {
+ "PERF_CONTROLS",
+ Package()
+ { // MDPBLT_CORE_CLOCK_CONTROL
+ 2, // State Set Index
+ Package()
+ {
+ "LimitForPassiveCooling", // Property Name
+ 0x00000001, // Value
+ },
+ },
+ Package()
+ { // MDPBLT_AXI_BANDWIDTH_CONTROL
+ 3, // State Set Index
+ Package()
+ {
+ "LimitForPassiveCooling", // Property Name
+ 0x00000001, // Value
+ },
+ },
+ },
+ Package()
+ {
+ "THERMAL_DOMAINS",
+ "GPU",
+ },
+ },
+
+ Package()
+ {
+ "ENGINE",
+ "ROTATOR", // Engine String Identifier
+ "MDP5.x", // Chip Family Identifier
+ 3, // Index of Primary Power Component
+ 1, // P-State Set Index of Footswitch override
+ 0, // P-State Set Index of Reset
+ Package()
+ {
+ "MMUINFO",
+ "Miniport", // SMMU managed by miniport or engine
+ "ArmSmmuV2", // SMMU Family
+ 2, // Number of SMMU stages
+ 32, // Address bits
+ "V7S", // Address format
+ "SMMUID", ToUUID("36079AE4-78E8-452D-AF50-0CFF78B2F1CA"),
+ "SMMUINTERFACEID", ToUUID("00000000-0000-0000-0000-000000000000"),
+ // If default the above would be:
+ // ToUUID("00000000-0000-0000-0000-000000000000")
+ Package()
+ {
+ "PAGETABLEUSAGE",
+ 2, // Number of page tables
+ "MdpNonSecurePT",
+ "MdpSecurePT",
+ },
+ },
+ Package()
+ {
+ "PERF_CONTROLS",
+ Package()
+ { // ROTATOR_CORE_CLOCK_CONTROL
+ 2, // State Set Index
+ Package()
+ {
+ "LimitForPassiveCooling", // Property Name
+ 0x00000001, // Value
+ },
+ },
+ Package()
+ { // ROTATOR_AXI_BANDWIDTH_CONTROL
+ 3, // State Set Index
+ Package()
+ {
+ "LimitForPassiveCooling", // Property Name
+ 0x00000001, // Value
+ },
+ },
+ },
+ Package()
+ {
+ "THERMAL_DOMAINS",
+ "GPU",
+ },
+ },
+
+ Package()
+ {
+ "ENGINE",
+ "VIDEO", // Engine String Identifier
+ "Venus", // Chip Family Identifier
+ 4, // Index of Primary Power Component
+ 1, // P-State Set Index of Footswitch override
+ 0, // P-State Set Index of Reset
+ Package()
+ {
+ "MMUINFO",
+ "Engine", // SMMU managed by miniport or engine
+ "ArmSmmuV2", // SMMU Family
+ 2, // Number of SMMU stages
+ 32, // Address bits
+ "V7S", // Address format
+ "SMMUID", ToUUID("665E0F8E-ADD3-49D1-91BC-5540C5F57FBA"),
+ "SMMUINTERFACEID", ToUUID("1C3FC0E8-0B11-4EE0-BE89-3E21420A865F"),
+ // If default the above would be:
+ // ToUUID("00000000-0000-0000-0000-000000000000")
+ Package()
+ {
+ "PAGETABLEUSAGE",
+ 5, // Number of page tables
+ "VideoNonSecurePT",
+ "VideoSecurePT1",
+ "VideoSecurePT2",
+ "VideoSecurePT3",
+ "VideoSecurePT4",
+ },
+ },
+ Package()
+ {
+ "PERF_CONTROLS",
+ Package()
+ { // VIDEO_CORE_CLOCK_CONTROL
+ 2, // State Set Index
+ },
+ Package()
+ { // VIDEO_AXI_PORT_BW
+ 3, // State Set Index
+ },
+ },
+ Package()
+ {
+ "THERMAL_DOMAINS",
+ },
+ Package()
+ {
+ "PROPERTIES",
+ 1, // Number of properties
+ Package()
+ {
+ "DecMaxFps", // Property Name
+ 0x0000003C, // Value
+ },
+ },
+ },
+
+ Package()
+ {
+ "ENGINE",
+ "CRYPTO", // Engine String Identifier
+ "Crypto1.0", // Chip Family Identifier
+ 5, // Index of Primary Power Component
+ 1, // P-State Set Index of Footswitch override
+ 0, // P-State Set Index of Reset
+ Package()
+ {
+ "MMUINFO",
+ "Miniport", // SMMU managed by miniport or engine
+ "ArmSmmuV2", // SMMU Family
+ 2, // Number of SMMU stages
+ 32, // Address bits
+ "V7S", // Address format
+ "SMMUID", ToUUID("36079AE4-78E8-452D-AF50-0CFF78B2F1CA"),
+ "SMMUINTERFACEID", ToUUID("00000000-0000-0000-0000-000000000000"),
+ // If default the above would be:
+ // ToUUID("00000000-0000-0000-0000-000000000000")
+ Package()
+ {
+ "PAGETABLEUSAGE",
+ 2, // Number of page tables
+ "CryptoNonSecurePT",
+ "CryptoSecurePT",
+ },
+ },
+ Package()
+ {
+ "PERF_CONTROLS",
+ Package()
+ { // CRYPTO_CORE_CLOCK_CONTROL
+ 2, // State Set Index
+ },
+ },
+ Package()
+ {
+ "THERMAL_DOMAINS",
+ },
+ },
+
+ Package()
+ {
+ "ENGINE",
+ "VIDEO_ENCODER", // Engine String Identifier
+ "Venus", // Chip Family Identifier
+ 6, // Index of Primary Power Component
+ 1, // P-State Set Index of Footswitch override
+ 0, // P-State Set Index of Reset
+ Package()
+ {
+ "PERF_CONTROLS",
+ Package()
+ { // VIDEO_ENCODER_CORE_CLOCK_CONTROL
+ 2, // State Set Index
+ },
+ Package()
+ { // VIDEO_ENCODER_AXI_PORT_BW
+ 3, // State Set Index
+ },
+ },
+ Package()
+ {
+ "THERMAL_DOMAINS",
+ },
+ },
+ },
+
+ //------------------------------------------------------------------------------
+ // Display Info Package
+ // This package enumerates all resources assigned to the display. Additionally,
+ // this routine includes any display configuration data, such as hotplug
+ // support.
+ //------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "DISPLAYS",
+ "MDP5.x", // Chip Family Identifier
+ 3, // Number of displays
+
+ Package()
+ {
+ "DISPLAY",
+ "INTERNAL1", // Display Name
+
+ 0, // Index of Display Power Component
+ 1, // P-State Set Index of Footswitch override
+ 0, // P-State Set Index of reset
+
+ Package()
+ {
+ "PERF_CONTROLS",
+ Package()
+ { // INTERNAL1_SCAN_CONTROL
+ 2, // State Set Index
+ },
+ Package()
+ { // INTERNAL1_CORE_CLOCK_CONTROL
+ 3, // State Set Index
+ },
+ Package()
+ { // INTERNAL1_EBI_BANDWIDTH
+ 4, // State Set Index
+ },
+ },
+ Package()
+ {
+ "THERMAL_DOMAINS",
+ },
+ },
+ Package()
+ {
+ "DISPLAY",
+ "INTERNAL2", // Display Name
+
+ 7, // Index of Display Power Component
+ 1, // P-State Set Index of Footswitch override
+ 0, // P-State Set Index of reset
+
+ Package()
+ {
+ "PERF_CONTROLS",
+ Package()
+ { // INTERNAL2_SCAN_CONTROL
+ 2, // State Set Index
+ },
+ Package()
+ { // INTERNAL2_CORE_CLOCK_CONTROL
+ 3, // State Set Index
+ },
+ Package()
+ { // INTERNAL2_EBI_BANDWIDTH
+ 4, // State Set Index
+ },
+ },
+ Package()
+ {
+ "THERMAL_DOMAINS",
+ },
+ },
+ Package()
+ {
+ "DISPLAY",
+ "EXTERNAL1", // Display Name
+
+ 8, // Index of Display Power Component
+ 1, // P-State Set Index of Footswitch override
+ 0, // P-State Set Index of reset
+
+ Package()
+ {
+ "PERF_CONTROLS",
+ Package()
+ { // EXTERNAL1_CORE_CLOCK_CONTROL
+ 2, // State Set Index
+ },
+ Package()
+ { // EXTERNAL1_EBI_BANDWIDTH
+ 3, // State Set Index
+ },
+ },
+ Package()
+ {
+ "THERMAL_DOMAINS",
+ },
+ },
+
+ Package()
+ {
+ "RESOURCES",
+ Package()
+ {
+ "MMUINFO",
+ "Miniport", // SMMU managed by miniport or engine
+ "ArmSmmuV2", // SMMU Family
+ 2, // Number of SMMU stages
+ 32, // Address bits
+ "V7S", // Address format
+ "SMMUID", ToUUID("36079AE4-78E8-452D-AF50-0CFF78B2F1CA"),
+ "SMMUINTERFACEID", ToUUID("00000000-0000-0000-0000-000000000000"),
+ // If default the above would be:
+ // ToUUID("00000000-0000-0000-0000-000000000000")
+ Package()
+ {
+ "PAGETABLEUSAGE",
+ 2, // Number of page tables
+ "MdpNonSecurePT",
+ "MdpSecurePT",
+ },
+ },
+ },
+ Package()
+ {
+ "PRIMARY_SOURCE_MODES",
+ 32, // Number of Primary source modes
+ Package()
+ {
+ 640, // Width
+ 480, // Height
+ },
+ Package()
+ {
+ 640, // Width
+ 360, // Height
+ },
+ Package()
+ {
+ 800, // Width
+ 600, // Height
+ },
+ Package()
+ {
+ 960, // Width
+ 540, // Height
+ },
+ Package()
+ {
+ 1280, // Width
+ 720, // Height
+ },
+ Package()
+ {
+ 1280, // Width
+ 1080, // Height
+ },
+ Package()
+ {
+ 1024, // Width
+ 768, // Height
+ },
+ Package()
+ {
+ 1152, // Width
+ 768, // Height
+ },
+ Package()
+ {
+ 1280, // Width
+ 768, // Height
+ },
+ Package()
+ {
+ 1360, // Width
+ 768, // Height
+ },
+ Package()
+ {
+ 1366, // Width
+ 768, // Height
+ },
+ Package()
+ {
+ 1600, // Width
+ 900, // Height
+ },
+ Package()
+ {
+ 1280, // Width
+ 1024, // Height
+ },
+ Package()
+ {
+ 1920, // Width
+ 1080, // Height
+ },
+ Package()
+ {
+ 1920, // Width
+ 1200, // Height
+ },
+ Package()
+ {
+ 1920, // Width
+ 1280, // Height
+ },
+ Package()
+ {
+ 2048, // Width
+ 1080, // Height
+ },
+ Package()
+ {
+ 2048, // Width
+ 1152, // Height
+ },
+ Package()
+ {
+ 2048, // Width
+ 1536, // Height
+ },
+ Package()
+ {
+ 2560, // Width
+ 1080, // Height
+ },
+ Package()
+ {
+ 2560, // Width
+ 1600, // Height
+ },
+ Package()
+ {
+ 2560, // Width
+ 1440, // Height
+ },
+ Package()
+ {
+ 2560, // Width
+ 2048, // Height
+ },
+ Package()
+ {
+ 3200, // Width
+ 1800, // Height
+ },
+ Package()
+ {
+ 3200, // Width
+ 2400, // Height
+ },
+ Package()
+ {
+ 3200, // Width
+ 2048, // Height
+ },
+ Package()
+ {
+ 3440, // Width
+ 1440, // Height
+ },
+ Package()
+ {
+ 3840, // Width
+ 1080, // Height
+ },
+ Package()
+ {
+ 3840, // Width
+ 1600, // Height
+ },
+ Package()
+ {
+ 3840, // Width
+ 2400, // Height
+ },
+ Package()
+ {
+ 3840, // Width
+ 2160, // Height
+ },
+ Package()
+ {
+ 4096, // Width
+ 2160, // Height
+ },
+ },
+ },
+
+ //------------------------------------------------------------------------------
+ // Page Table List
+ // This package enumerates all of the page tables used by any of the displays
+ // and engines. Page tables defined here may be referenced by one or more engine
+ // or display.
+ //------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PAGETABLES",
+ 13, // Number of page tables
+ Package()
+ {
+ "GraphicsGlobalPT", // Name
+ 1, // Global
+ 0, // Secure
+ 1, // HighTTBR
+ 1, // HiddenFromOS
+ 0x8000000000, // VaStart
+ 0x800000000, // VaSizeBytes
+ },
+ Package()
+ {
+ "GraphicsPerProcessPT", // Name
+ 0, // Global
+ 0, // Secure
+ 0, // HighTTBR
+ 0, // HiddenFromOS
+ 0x00400000, // VaStart
+ 0x7FFFC00000, // VaSizeBytes
+ },
+ Package()
+ {
+ "GraphicsSecurePT", // Name
+ 0, // Global
+ 1, // Secure
+ 0, // HighTTBR
+ 1, // HiddenFromOS
+ 0x8800000000, // VaStart
+ 0xC0000000, // VaSizeBytes
+ },
+ Package()
+ {
+ "GraphicsGmuPT", // Name
+ 0, // Global
+ 0, // Secure
+ 0, // HighTTBR
+ 0, // HiddenFromOS
+ 0x60000000, // VaStart
+ 0x20000000, // VaSizeBytes
+ },
+ Package()
+ {
+ "MdpNonSecurePT", // Name
+ 0, // Global
+ 0, // Secure
+ 0, // HighTTBR
+ 0, // HiddenFromOS
+ 0x40100000, // VaStart
+ 0xBFF00000, // VaSizeBytes
+ },
+ Package()
+ {
+ "MdpSecurePT", // Name
+ 0, // Global
+ 1, // Secure
+ 0, // HighTTBR
+ 1, // HiddenFromOS
+ 0x80000000, // VaStart
+ 0x80000000, // VaSizeBytes
+ },
+ Package()
+ {
+ "VideoNonSecurePT", // Name
+ 0, // Global
+ 0, // Secure
+ 0, // HighTTBR
+ 1, // HiddenFromOS
+ 0x00100000, // VaStart
+ 0xBFF00000, // VaSizeBytes
+ 0x0000001B, // VideoBufferMask
+ 0, // VideoCBIndex
+ },
+ Package()
+ {
+ "VideoSecurePT1", // Name
+ 0, // Global
+ 1, // Secure
+ 0, // HighTTBR
+ 1, // HiddenFromOS
+ 0xC0000000, // VaStart
+ 0x10000000, // VaSizeBytes
+ 0x00000009, // VideoBufferMask
+ 1, // VideoCBIndex
+ },
+ Package()
+ {
+ "VideoSecurePT2", // Name
+ 0, // Global
+ 1, // Secure
+ 0, // HighTTBR
+ 1, // HiddenFromOS
+ 0xD0000000, // VaStart
+ 0x10000000, // VaSizeBytes
+ 0x00000007, // VideoBufferMask
+ 2, // VideoCBIndex
+ },
+ Package()
+ {
+ "VideoSecurePT3", // Name
+ 0, // Global
+ 1, // Secure
+ 0, // HighTTBR
+ 1, // HiddenFromOS
+ 0xE0000000, // VaStart
+ 0x10000000, // VaSizeBytes
+ 0x00000002, // VideoBufferMask
+ 3, // VideoCBIndex
+ },
+ Package()
+ {
+ "VideoSecurePT4", // Name
+ 0, // Global
+ 1, // Secure
+ 0, // HighTTBR
+ 1, // HiddenFromOS
+ 0xF0000000, // VaStart
+ 0x10000000, // VaSizeBytes
+ 0x0000002A, // VideoBufferMask
+ 4, // VideoCBIndex
+ },
+ Package()
+ {
+ "CryptoNonSecurePT", // Name
+ 0, // Global
+ 0, // Secure
+ 0, // HighTTBR
+ 0, // HiddenFromOS
+ 0x00100000, // VaStart
+ 0x7FF00000, // VaSizeBytes
+ },
+ Package()
+ {
+ "CryptoSecurePT", // Name
+ 0, // Global
+ 1, // Secure
+ 0, // HighTTBR
+ 1, // HiddenFromOS
+ 0x80000000, // VaStart
+ 0x80000000, // VaSizeBytes
+ },
+ },
+ })
+
+ Return (EBUF)
+ }
+
+ //------------------------------------------------------------------------------
+ // Graphics Thermal Management Details
+ //------------------------------------------------------------------------------
+ //
+ Method (TMDT)
+ {
+ Name (RBUF, Package()
+ {
+ 1, // Table Format Major Version
+ 0, // Table Format Minor Version
+
+ // Thermal Domain Definitions
+ //
+ Package()
+ {
+ "THERMAL_DOMAINS",
+ 1, // Num Thermal Domains
+
+ // Thermal Zone
+ // Domain Name Interface Name Endpoints
+ // ------------- -------------- -----------------------
+ Package() { "GPU", "GPU0", Package() { "GRAPHICS", "MDPBLT", "ROTATOR", } },
+ }
+ })
+
+ Return (RBUF)
+ }
+
+ //------------------------------------------------------------------------------
+ // Graphics PEP Component List
+ // This method is a companion method to the graphics entries inside PEP's DCFG
+ // method. It includes the same components, generated from a single XML source,
+ // with any additional information required to be passed to dxgkrnl.
+ //------------------------------------------------------------------------------
+ //
+ Method (PMCL)
+ {
+ Name (RBUF, Package()
+ {
+ 3, // Table Format Major Version
+ 1, // Table Format Minor Version
+ 10, // Number of power components
+
+ //----------------------------------------------------------------------------------
+ // C0 - Internal (Primary) Display Power States
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "COMPONENT",
+ 0, // Component Index
+ Buffer()
+ {
+ 0x91, 0x59, 0x13, 0x2C, 0x91, 0x43, 0x33, 0x46, // GUID: {2C135991-4391-4633-90B1-FA96F2E2CC04}
+ 0x90, 0xB1, 0xFA, 0x96, 0xF2, 0xE2, 0xCC, 0x04
+ },
+
+ "PRIMDISPLAY_POWER_STATES", // Common Name
+ "HW_BLOCK_MDP", // Hw Block associated with this component
+
+ Package()
+ {
+ "DISPLAY", // Dxgkrnl Component Type
+ "INTERNAL1",
+ },
+
+ 2, // Number of F-States
+ 5, // Number of P-State Sets
+
+ // Logical Transition Residency Nominal
+ // ID Power State Latency Requirement Power
+ // --- ----------- ---------- ----------- -------
+ Package() { "FSTATE", 0, "ALL_ON", 0, 0, 2 },
+ Package() { "FSTATE", 1, "PWR_OFF", 1, 1, 1 },
+
+ //----------------------------------------------------------------------------------
+ // C0.PS0 - Internal (Primary) Display: MDP Reset Control
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // P-State Set Index
+ "INTERNAL1_RESET",
+ "*", // HW Revisions
+ "RESET", // Resource Type
+ 2, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Do Nothing
+ Package() { "PSTATE", 1, 0, 2 }, // Reset Display Core
+ },
+
+ //----------------------------------------------------------------------------------
+ // C0.PS1 - Internal Display: MDP Footswitch override
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // P-State Set Index
+ "INTERNAL1_FOOTSWITCH_OVERRIDE",
+ "*", // HW Revisions
+ "FOOTSWITCH_OVERRIDE", // Resource Type
+ 2, // Num P-States in Set
+ 0xFFFFFFFF, // Initial P-State (i.e. none)
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Footswitch On
+ Package() { "PSTATE", 1, 0, 2 }, // Footswitch Off
+ },
+
+ //----------------------------------------------------------------------------------
+ // C0.PS2 - Internal (Primary) Display: Power states for MDP scan-out HW
+ //
+ // @Brief:
+ // - Used to dynamically control MDP related clocks within a PState
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // P-State Set Index
+ "INTERNAL1_SCAN_CONTROL",
+ "*", // HW Revisions
+ "DISPLAY_SOURCE_SCAN_CTRL", // Resource Type
+ 5, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 4, 2 }, // Vote for all scan-out resources
+ Package() { "PSTATE", 1, 3, 2 }, // Vote for only MDP, DSI 0 and DSI 1 scan-out resources
+ Package() { "PSTATE", 2, 2, 2 }, // Vote for only MDP and DSI 0 scan-out resources
+ Package() { "PSTATE", 3, 1, 2 }, // Vote for only MDP and DSI 1 scan-out resources
+ Package() { "PSTATE", 4, 0, 2 }, // Remove votes for all scan-out resources
+ },
+
+ //----------------------------------------------------------------------------------
+ // C0.PS3 - Internal (Primary) Display: MDP Core Clock Frequency
+ //
+ // @Brief:
+ // Notes:
+ // - This table reflects the frequency plan for the v1 part.
+ // - All core frequency votes are based on specific clock plan values and are cast
+ // 2 MHz below what we actually desire. This helps avoid potential issues with
+ // round-up when the actual clock frequency on real HW is slightly less than
+ // that which was advertized in the clock plan.
+ // - [NC] Temporarily moved all AHB bandwidth votes to F-states to help work around
+ // 64K size issue in the final AML.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 3, // P-State Set Index
+ "INTERNAL1_CORE_CLOCK_CONTROL",
+ "*", // HW Revisions
+ "CORE_CLOCK", // Resource Type
+ 13, // Num P-States in Set
+ 4, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 430000000, 1 },
+ Package() { "PSTATE", 1, 412500000, 1 },
+ Package() { "PSTATE", 2, 344000000, 2 },
+ Package() { "PSTATE", 3, 300000000, 2 },
+ Package() { "PSTATE", 4, 275000000, 2 },
+ Package() { "PSTATE", 5, 200000000, 2 },
+ Package() { "PSTATE", 6, 171428571, 3 },
+ Package() { "PSTATE", 7, 165000000, 3 },
+ Package() { "PSTATE", 8, 150000000, 3 },
+ Package() { "PSTATE", 9, 100000000, 3 },
+ Package() { "PSTATE", 10, 85710000, 3 },
+ Package() { "PSTATE", 11, 19200000, 3 },
+ Package() { "PSTATE", 12, 0, 3 },
+ },
+
+ //----------------------------------------------------------------------------------
+ // C0.PS4 - Internal (Primary) Display: Display Bandwidth to EBI
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 4, // P-State Set Index
+ "INTERNAL1_EBI_BANDWIDTH",
+ "*", // HW Revisions
+ "BANDWIDTH", // Resource Type
+ 43, // Num P-States in Set
+ 28, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 13326000000, 0 },
+ Package() { "PSTATE", 1, 12926000000, 0 },
+ Package() { "PSTATE", 2, 12526000000, 0 },
+ Package() { "PSTATE", 3, 12126000000, 0 },
+ Package() { "PSTATE", 4, 11726000000, 0 },
+ Package() { "PSTATE", 5, 11326000000, 0 },
+ Package() { "PSTATE", 6, 10926000000, 0 },
+ Package() { "PSTATE", 7, 10526000000, 0 },
+ Package() { "PSTATE", 8, 10126000000, 1 },
+ Package() { "PSTATE", 9, 9600000000, 1 },
+ Package() { "PSTATE", 10, 9200000000, 1 },
+ Package() { "PSTATE", 11, 8800000000, 1 },
+ Package() { "PSTATE", 12, 8400000000, 1 },
+ Package() { "PSTATE", 13, 8000000000, 1 },
+ Package() { "PSTATE", 14, 7600000000, 1 },
+ Package() { "PSTATE", 15, 7200000000, 1 },
+ Package() { "PSTATE", 16, 6800000000, 1 },
+ Package() { "PSTATE", 17, 6400000000, 1 },
+ Package() { "PSTATE", 18, 6000000000, 1 },
+ Package() { "PSTATE", 19, 5600000000, 1 },
+ Package() { "PSTATE", 20, 5200000000, 2 },
+ Package() { "PSTATE", 21, 4800000000, 2 },
+ Package() { "PSTATE", 22, 4400000000, 2 },
+ Package() { "PSTATE", 23, 4000000000, 2 },
+ Package() { "PSTATE", 24, 3600000000, 2 },
+ Package() { "PSTATE", 25, 3200000000, 2 },
+ Package() { "PSTATE", 26, 2800000000, 2 },
+ Package() { "PSTATE", 27, 2400000000, 2 },
+ Package() { "PSTATE", 28, 2000000000, 2 },
+ Package() { "PSTATE", 29, 1600000000, 2 },
+ Package() { "PSTATE", 30, 1500000000, 2 },
+ Package() { "PSTATE", 31, 1400000000, 2 },
+ Package() { "PSTATE", 32, 1300000000, 2 },
+ Package() { "PSTATE", 33, 1200000000, 2 },
+ Package() { "PSTATE", 34, 1100000000, 2 },
+ Package() { "PSTATE", 35, 1000000000, 2 },
+ Package() { "PSTATE", 36, 900000000, 2 },
+ Package() { "PSTATE", 37, 800000000, 2 },
+ Package() { "PSTATE", 38, 700000000, 2 },
+ Package() { "PSTATE", 39, 600000000, 2 },
+ Package() { "PSTATE", 40, 500000000, 2 },
+ Package() { "PSTATE", 41, 400000000, 2 },
+ Package() { "PSTATE", 42, 0, 2 },
+ },
+
+
+ },
+
+ //----------------------------------------------------------------------------------
+ // C1 - 3D Graphics Engine Power States
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "COMPONENT",
+ 1, // Component Index
+ Buffer()
+ {
+ 0xB5, 0xF1, 0xBD, 0x30, 0xF7, 0x28, 0x0C, 0x4C, // GUID: {30BDF1B5-28F7-4C0C-AC47-273DD1401E11}
+ 0xAC, 0x47, 0x27, 0x3D, 0xD1, 0x40, 0x1E, 0x11
+ },
+
+ "GRAPHICS_POWER_STATES", // Common Name
+ "HW_BLOCK_GRAPHICS", // Hw Block associated with this component
+
+ Package()
+ {
+ "ENGINE", // Dxgkrnl Component Type
+ "GRAPHICS",
+ },
+
+ 3, // Number of F-States
+ 5, // Number of P-State Sets
+
+ // Logical Transition Residency Nominal
+ // ID Power State Latency Requirement Power
+ // --- ----------- ---------- ----------- -------
+ Package() { "FSTATE", 0, "ALL_ON", 0, 0, 3 },
+ Package() { "FSTATE", 1, "PWR_OFF", 10000, 10, 2 },
+ Package() { "FSTATE", 2, "PWR_OFF", 10001, 10, 1 },
+
+ //----------------------------------------------------------------------------------
+ // C1.PS0 - 3D Graphics Core P-State Set: Reset
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // P-State Set Index
+ "GRAPHICS_RESET",
+ "*", // HW Revisions
+ "RESET", // Resource Type
+ 2, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Do Nothing
+ Package() { "PSTATE", 1, 0, 2 }, // Reset Graphics Core
+ },
+
+ //----------------------------------------------------------------------------------
+ // C1.PS1 - 3D Graphics Core P-State Set: CX Headswitch Management
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // P-State Set Index
+ "CX_HS_MGMT",
+ "*", // HW Revisions
+ "INTERNAL", // Resource Type
+ 3, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 2, 2 }, // Do Nothing
+ Package() { "PSTATE", 1, 1, 2 }, // CX Headswitch On
+ Package() { "PSTATE", 2, 0, 2 }, // CX Headswitch Off
+ },
+
+ //----------------------------------------------------------------------------------
+ // C1.PS2 - 3D Graphics Core P-State Set: Footswitch override
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // P-State Set Index
+ "GRAPHICS_FOOTSWITCH_OVERRIDE",
+ "*", // HW Revisions
+ "FOOTSWITCH_OVERRIDE", // Resource Type
+ 2, // Num P-States in Set
+ 1, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Footswitch On
+ Package() { "PSTATE", 1, 0, 2 }, // Footswitch Off
+ },
+
+
+ //----------------------------------------------------------------------------------
+ // C1.PS3
+ // << Placeholder for runtime patches: P001, P002 >>
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "ENGINE_PSTATE_SET",
+ 3,
+ },
+
+ //----------------------------------------------------------------------------------
+ // C1.PS4 - 3D Graphics Core P-State Set: Bus 850
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "ENGINE_PSTATE_SET",
+ 4,
+ "GRAPHICS_BW_CONTROL",
+ "BANDWIDTH", // Resource Type
+ 13, // Num P-States in Set
+ 0, // Num CustomData fields in Set
+ TRUE, // Has Thermal Thresholds
+ 4, // Initial P-State
+ 3, // Stable Power P-State
+
+ // Voltage
+ // ID Value Level Thermal Thresholds
+ // --- ---------- ----- --------------------
+ Package() { "PSTATE", 0, 7216000000, 384, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 1, 6220000000, 256, Package() { "GPU", 86, } },
+ Package() { "PSTATE", 2, 5184000000, 256, Package() { "GPU", 72, } },
+ Package() { "PSTATE", 3, 4068000000, 192, Package() { "GPU", 56, } },
+ Package() { "PSTATE", 4, 3072000000, 128, Package() { "GPU", 42, } },
+ Package() { "PSTATE", 5, 2724000000, 128, Package() { "GPU", 38, } },
+ Package() { "PSTATE", 6, 2188000000, 128, Package() { "GPU", 30, } },
+ Package() { "PSTATE", 7, 1648000000, 64, Package() { "GPU", 23, } },
+ Package() { "PSTATE", 8, 1200000000, 48, Package() { "GPU", 17, } },
+ Package() { "PSTATE", 9, 800000000, 48, Package() { "GPU", 11, } },
+ Package() { "PSTATE", 10, 600000000, 48, Package() { "GPU", 8, } },
+ Package() { "PSTATE", 11, 400000000, 48, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 12, 0, 0, Package() { "GPU", 0, } },
+ },
+
+ },
+
+ //----------------------------------------------------------------------------------
+ // C2 - MDP BLT Engine Power States
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "COMPONENT",
+ 2, // Component Index
+ Buffer()
+ {
+ 0xDD, 0x2A, 0xCA, 0x07, 0x87, 0xDF, 0xE1, 0x49, // GUID: {07CA2ADD-DF87-49E1-8583-08687DC81C8E}
+ 0x85, 0x83, 0x08, 0x68, 0x7D, 0xC8, 0x1C, 0x8E
+ },
+
+ "MDPBLT_POWER_STATES", // Common Name
+ "HW_BLOCK_MDP", // Hw Block associated with this component
+
+ Package()
+ {
+ "ENGINE", // Dxgkrnl Component Type
+ "MDPBLT",
+ },
+
+ 3, // Number of F-States
+ 4, // Number of P-State Sets
+
+ // Logical Transition Residency Nominal
+ // ID Power State Latency Requirement Power
+ // --- ----------- ---------- ----------- -------
+ Package() { "FSTATE", 0, "ALL_ON", 0, 0, 3 },
+ Package() { "FSTATE", 1, "CLK_OFF", 10000, 0, 2 },
+ Package() { "FSTATE", 2, "PWR_OFF", 100000, 0, 1 },
+
+ //----------------------------------------------------------------------------------
+ // C2.PS0 - MDP BLT Core P-State Set: Reset
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // P-State Set Index
+ "MDPBLT_RESET",
+ "*", // HW Revisions
+ "RESET", // Resource Type
+ 2, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Do Nothing
+ Package() { "PSTATE", 1, 0, 2 }, // Reset Display Core
+ },
+
+ //----------------------------------------------------------------------------------
+ // C2.PS1 - MDP BLT Core P-State Set: Footswitch override
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // P-State Set Index
+ "MDPBLT_FOOTSWITCH_OVERRIDE",
+ "*", // HW Revisions
+ "FOOTSWITCH_OVERRIDE", // Resource Type
+ 2, // Num P-States in Set
+ 0xFFFFFFFF, // Initial P-State (i.e. none)
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Footswitch On
+ Package() { "PSTATE", 1, 0, 2 }, // Footswitch Off
+ },
+
+ //----------------------------------------------------------------------------------
+ // C2.PS2 - MDP Core Performance: Core Clock Frequency
+ //
+ // @Brief:
+ // Notes:
+ // - All core frequency votes are based on specific clock plan values and are cast
+ // 2 MHz below what we actually desire. This helps avoid potential issues with
+ // round-up when the actual clock frequency on real HW is slightly less than
+ // that which was advertized in the clock plan.
+ // - [NC] Temporarily moved all AHB bandwidth votes to F-states to help work around
+ // 64K size issue in the final AML.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // P-State Set Index
+ "MDPBLT_CORE_CLOCK_CONTROL",
+ "*", // HW Revisions
+ "CORE_CLOCK", // Resource Type
+ 13, // Num P-States in Set
+ 8, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level Thermal Thresholds
+ // --- ---------- ----- --------------------
+ Package() { "PSTATE", 0, 430000000, 1, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 1, 412500000, 1, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 2, 344000000, 2, Package() { "GPU", 66, } },
+ Package() { "PSTATE", 3, 300000000, 2, Package() { "GPU", 66, } },
+ Package() { "PSTATE", 4, 275000000, 2, Package() { "GPU", 66, } },
+ Package() { "PSTATE", 5, 200000000, 2, Package() { "GPU", 66, } },
+ Package() { "PSTATE", 6, 171428571, 3, Package() { "GPU", 33, } },
+ Package() { "PSTATE", 7, 165000000, 3, Package() { "GPU", 33, } },
+ Package() { "PSTATE", 8, 150000000, 3, Package() { "GPU", 33, } },
+ Package() { "PSTATE", 9, 100000000, 3, Package() { "GPU", 33, } },
+ Package() { "PSTATE", 10, 85710000, 3, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 11, 19200000, 3, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 12, 0, 3, Package() { "GPU", 0, } },
+ },
+
+ //----------------------------------------------------------------------------------
+ // C2.PS3 - MDP Core Performance: MDPBLT Bandwidth to EBI
+ //
+ // @Brief:
+ // Note (TODO: Update this comment):
+ // - AXI port 1 is strictly used by the BLT engine. The BLT engine will have definite
+ // modes of operation based on surface sizes and refresh rates. Instead of bothering
+ // to identify all possible modes, however, we simply build a table based on the
+ // possible combination of frequency levels between the core and EBI. With
+ // arbitrated and instantaneous bandwidth requests, these frequency levels represent
+ // all of the possible system configurations that can result from any request.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 3, // P-State Set Index
+ "MDPBLT_AXI_BANDWIDTH_CONTROL",
+ "*", // HW Revisions
+ "BANDWIDTH", // Resource Type
+ 50, // Num P-States in Set
+ 0xFFFFFFFF, // Initial P-State (i.e. none)
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level Thermal Thresholds
+ // --- ---------- ----- --------------------
+ Package() { "PSTATE", 0, 13326000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 1, 12926000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 2, 12526000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 3, 12126000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 4, 11726000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 5, 11326000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 6, 10926000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 7, 10526000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 8, 10126000000, 1, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 9, 9726000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 10, 9326000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 11, 8926000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 12, 8526000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 13, 8126000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 14, 7726000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 15, 7326000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 16, 6926000000, 1, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 17, 6526000000, 1, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 18, 6126000000, 1, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 19, 5726000000, 1, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 20, 5326000000, 2, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 21, 4926000000, 2, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 22, 4526000000, 2, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 23, 4126000000, 2, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 24, 3726000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 25, 3326000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 26, 2926000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 27, 2526000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 28, 2400000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 29, 2300000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 30, 2200000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 31, 2100000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 32, 2000000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 33, 1900000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 34, 1800000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 35, 1700000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 36, 1600000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 37, 1500000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 38, 1400000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 39, 1300000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 40, 1200000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 41, 1100000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 42, 1000000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 43, 900000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 44, 800000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 45, 700000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 46, 600000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 47, 500000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 48, 400000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 49, 0, 2, Package() { "GPU", 0, } },
+ },
+
+
+ },
+
+ //----------------------------------------------------------------------------------
+ // C3 - Rotator Engine Power States
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "COMPONENT",
+ 3, // Component Index
+ Buffer()
+ {
+ 0xF5, 0xFB, 0x5F, 0x4D, 0x91, 0xD7, 0xCD, 0x41, // GUID: {4D5FFBF5-D791-41CD-89CB-0154129BA607}
+ 0x89, 0xCB, 0x01, 0x54, 0x12, 0x9B, 0xA6, 0x07
+ },
+
+ "ROTATOR_POWER_STATES", // Common Name
+ "HW_BLOCK_ROTATOR", // Hw Block associated with this component
+
+ Package()
+ {
+ "ENGINE", // Dxgkrnl Component Type
+ "ROTATOR",
+ },
+
+ 3, // Number of F-States
+ 4, // Number of P-State Sets
+
+ // Logical Transition Residency Nominal
+ // ID Power State Latency Requirement Power
+ // --- ----------- ---------- ----------- -------
+ Package() { "FSTATE", 0, "ALL_ON", 0, 0, 3 },
+ Package() { "FSTATE", 1, "CLK_OFF", 10000, 0, 2 },
+ Package() { "FSTATE", 2, "PWR_OFF", 100000, 0, 1 },
+
+ //----------------------------------------------------------------------------------
+ // C3.PS0 - Rotator Core P-State Set: Reset
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // P-State Set Index
+ "ROTATOR_RESET",
+ "*", // HW Revisions
+ "RESET", // Resource Type
+ 2, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Do Nothing
+ Package() { "PSTATE", 1, 0, 2 }, // Reset MDP Core
+ },
+
+ //----------------------------------------------------------------------------------
+ // C3.PS1 - Rotator Core P-State Set: Footswitch override
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // P-State Set Index
+ "ROTATOR_FOOTSWITCH_OVERRIDE",
+ "*", // HW Revisions
+ "FOOTSWITCH_OVERRIDE", // Resource Type
+ 2, // Num P-States in Set
+ 0xFFFFFFFF, // Initial P-State (i.e. none)
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Footswitch On
+ Package() { "PSTATE", 1, 0, 2 }, // Footswitch Off
+ },
+
+ //----------------------------------------------------------------------------------
+ // C3.PS2 - Rotator Core P-State Set: Rotator Core Clock Frequency
+ //
+ // @Brief:
+ // Notes:
+ // - All core frequency votes are based on specific clock plan values and are cast
+ // 2 MHz below what we actually desire. This helps avoid potential issues with
+ // round-up when the actual clock frequency on real HW is slightly less than
+ // that which was advertised in the clock plan.
+ // - This table reflects the frequency plans for the v1 and v2 parts.
+ // - [NC] Temporarily moved all AHB bandwidth votes to F-states to help work around
+ // 64K size issue in the final AML.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // P-State Set Index
+ "ROTATOR_CORE_CLOCK_CONTROL",
+ "*", // HW Revisions
+ "CORE_CLOCK", // Resource Type
+ 8, // Num P-States in Set
+ 5, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level Thermal Thresholds
+ // --- ---------- ----- --------------------
+ Package() { "PSTATE", 0, 430000000, 1, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 1, 412500000, 1, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 2, 344000000, 2, Package() { "GPU", 66, } },
+ Package() { "PSTATE", 3, 300000000, 2, Package() { "GPU", 66, } },
+ Package() { "PSTATE", 4, 171428571, 3, Package() { "GPU", 33, } },
+ Package() { "PSTATE", 5, 165000000, 3, Package() { "GPU", 33, } },
+ Package() { "PSTATE", 6, 19200000, 3, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 7, 0, 3, Package() { "GPU", 0, } },
+ },
+
+ //----------------------------------------------------------------------------------
+ // C3.PS3 - Rotator Core P-State Set: Rotator Bandwidth to EBI
+ //
+ // @Brief:
+ // Note (TODO - Update comment):
+ // - AXI port 1 is strictly used by the BLT engine. The BLT engine will have definite
+ // modes of operation based on surface sizes and refresh rates. Instead of bothering
+ // to identify all possible modes, however, we simply build a table based on the
+ // possible combination of frequency levels between the core and EBI. With
+ // arbitrated and instantaneous bandwidth requests, these frequency levels represent
+ // all of the possible system configurations that can result from any request.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 3, // P-State Set Index
+ "ROTATOR_AXI_BANDWIDTH_CONTROL",
+ "*", // HW Revisions
+ "BANDWIDTH", // Resource Type
+ 50, // Num P-States in Set
+ 0xFFFFFFFF, // Initial P-State (i.e. none)
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level Thermal Thresholds
+ // --- ---------- ----- --------------------
+ Package() { "PSTATE", 0, 13326000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 1, 12926000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 2, 12526000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 3, 12126000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 4, 11726000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 5, 11326000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 6, 10926000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 7, 10526000000, 0, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 8, 10126000000, 1, Package() { "GPU", 100, } },
+ Package() { "PSTATE", 9, 9726000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 10, 9326000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 11, 8926000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 12, 8526000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 13, 8126000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 14, 7726000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 15, 7326000000, 1, Package() { "GPU", 75, } },
+ Package() { "PSTATE", 16, 6926000000, 1, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 17, 6526000000, 1, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 18, 6126000000, 1, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 19, 5726000000, 1, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 20, 5326000000, 2, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 21, 4926000000, 2, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 22, 4526000000, 2, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 23, 4126000000, 2, Package() { "GPU", 50, } },
+ Package() { "PSTATE", 24, 3726000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 25, 3326000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 26, 2926000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 27, 2526000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 28, 2400000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 29, 2300000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 30, 2200000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 31, 2100000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 32, 2000000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 33, 1900000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 34, 1800000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 35, 1700000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 36, 1600000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 37, 1500000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 38, 1400000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 39, 1300000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 40, 1200000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 41, 1100000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 42, 1000000000, 2, Package() { "GPU", 25, } },
+ Package() { "PSTATE", 43, 900000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 44, 800000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 45, 700000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 46, 600000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 47, 500000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 48, 400000000, 2, Package() { "GPU", 0, } },
+ Package() { "PSTATE", 49, 0, 2, Package() { "GPU", 0, } },
+ },
+
+
+ },
+
+ //----------------------------------------------------------------------------------
+ // C4 - Video Engine Power States
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "COMPONENT",
+ 4, // Component Index
+ Buffer()
+ {
+ 0x1A, 0xBB, 0xE1, 0xD0, 0x3D, 0x70, 0xE8, 0x4B, // GUID: {D0E1BB1A-703D-4BE8-B450-64A4FBFCA6A8}
+ 0xB4, 0x50, 0x64, 0xA4, 0xFB, 0xFC, 0xA6, 0xA8
+ },
+
+ "VIDEO_POWER_STATES", // Common Name
+ "HW_BLOCK_VIDEO", // Hw Block associated with this component
+
+ Package()
+ {
+ "ENGINE", // Dxgkrnl Component Type
+ "VIDEO",
+ },
+
+ 3, // Number of F-States
+ 4, // Number of P-State Sets
+
+ // Logical Transition Residency Nominal
+ // ID Power State Latency Requirement Power
+ // --- ----------- ---------- ----------- -------
+ Package() { "FSTATE", 0, "ALL_ON", 0, 0, 3 },
+ Package() { "FSTATE", 1, "CLK_OFF", 10000, 0, 2 },
+ Package() { "FSTATE", 2, "PWR_OFF", 100000, 0, 1 },
+
+ //----------------------------------------------------------------------------------
+ // C4.PS0 - Video Core P-State Set: Reset
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // P-State Set Index
+ "VIDEO_RESET",
+ "*", // HW Revisions
+ "RESET", // Resource Type
+ 2, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Do Nothing
+ Package() { "PSTATE", 1, 0, 2 }, // Reset Venus Core
+ },
+
+ //----------------------------------------------------------------------------------
+ // C4.PS1 - Video Core P-State Set: Footswitch override
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // P-State Set Index
+ "VIDEO_FOOTSWITCH_OVERRIDE",
+ "*", // HW Revisions
+ "FOOTSWITCH_OVERRIDE", // Resource Type
+ 2, // Num P-States in Set
+ 1, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Footswitch On
+ Package() { "PSTATE", 1, 0, 2 }, // Footswitch Off
+ },
+
+ //----------------------------------------------------------------------------------
+ // C4.PS2 - Video Core Performance: Core Clock Frequency
+ //
+ // @Brief:
+ // Notes:
+ // - The use of a "CLOSEST" match for the highest frequency is defensive. Any attempt
+ // to request a frequency that's even 1 Hz higher than the maximum entry in Clkrgm's
+ // table will result in a silent failure and no change in clock frequency.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // P-State Set Index
+ "VIDEO_CORE_CLOCK_CONTROL",
+ "*", // HW Revisions
+ "CORE_CLOCK", // Resource Type
+ 7, // Num P-States in Set
+ 4, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 533000000, 0 },
+ Package() { "PSTATE", 1, 444000000, 1 },
+ Package() { "PSTATE", 2, 380000000, 2 },
+ Package() { "PSTATE", 3, 320000000, 2 },
+ Package() { "PSTATE", 4, 200000000, 2 },
+ Package() { "PSTATE", 5, 100000000, 2 },
+ Package() { "PSTATE", 6, 0, 3 },
+ },
+
+ //----------------------------------------------------------------------------------
+ // C4.PS3 - Video Performance: Bandwidth to EBI
+ //
+ // @Brief:
+ // AXI bandwidth values are represented by a max, min and step which covers all
+ // possible bandwidth values requested by video core for different decode and
+ // encode scenarios.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 3, // P-State Set Index
+ "VIDEO_AXI_PORT_BW",
+ "*", // HW Revisions
+ "BANDWIDTH", // Resource Type
+ 111, // Num P-States in Set
+ 108, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 22000000000, 0 },
+ Package() { "PSTATE", 1, 21800000000, 0 },
+ Package() { "PSTATE", 2, 21600000000, 0 },
+ Package() { "PSTATE", 3, 21400000000, 0 },
+ Package() { "PSTATE", 4, 21200000000, 0 },
+ Package() { "PSTATE", 5, 21000000000, 0 },
+ Package() { "PSTATE", 6, 20800000000, 0 },
+ Package() { "PSTATE", 7, 20600000000, 0 },
+ Package() { "PSTATE", 8, 20400000000, 0 },
+ Package() { "PSTATE", 9, 20200000000, 0 },
+ Package() { "PSTATE", 10, 20000000000, 0 },
+ Package() { "PSTATE", 11, 19800000000, 0 },
+ Package() { "PSTATE", 12, 19600000000, 0 },
+ Package() { "PSTATE", 13, 19400000000, 0 },
+ Package() { "PSTATE", 14, 19200000000, 0 },
+ Package() { "PSTATE", 15, 19000000000, 0 },
+ Package() { "PSTATE", 16, 18800000000, 0 },
+ Package() { "PSTATE", 17, 18600000000, 0 },
+ Package() { "PSTATE", 18, 18400000000, 0 },
+ Package() { "PSTATE", 19, 18200000000, 0 },
+ Package() { "PSTATE", 20, 18000000000, 0 },
+ Package() { "PSTATE", 21, 17800000000, 0 },
+ Package() { "PSTATE", 22, 17600000000, 0 },
+ Package() { "PSTATE", 23, 17400000000, 0 },
+ Package() { "PSTATE", 24, 17200000000, 0 },
+ Package() { "PSTATE", 25, 17000000000, 0 },
+ Package() { "PSTATE", 26, 16800000000, 0 },
+ Package() { "PSTATE", 27, 16600000000, 0 },
+ Package() { "PSTATE", 28, 16400000000, 0 },
+ Package() { "PSTATE", 29, 16200000000, 0 },
+ Package() { "PSTATE", 30, 16000000000, 0 },
+ Package() { "PSTATE", 31, 15800000000, 0 },
+ Package() { "PSTATE", 32, 15600000000, 0 },
+ Package() { "PSTATE", 33, 15400000000, 0 },
+ Package() { "PSTATE", 34, 15200000000, 0 },
+ Package() { "PSTATE", 35, 15000000000, 0 },
+ Package() { "PSTATE", 36, 14800000000, 0 },
+ Package() { "PSTATE", 37, 14600000000, 0 },
+ Package() { "PSTATE", 38, 14400000000, 0 },
+ Package() { "PSTATE", 39, 14200000000, 0 },
+ Package() { "PSTATE", 40, 14000000000, 0 },
+ Package() { "PSTATE", 41, 13800000000, 0 },
+ Package() { "PSTATE", 42, 13600000000, 0 },
+ Package() { "PSTATE", 43, 13400000000, 0 },
+ Package() { "PSTATE", 44, 13200000000, 0 },
+ Package() { "PSTATE", 45, 13000000000, 0 },
+ Package() { "PSTATE", 46, 12800000000, 0 },
+ Package() { "PSTATE", 47, 12600000000, 0 },
+ Package() { "PSTATE", 48, 12400000000, 0 },
+ Package() { "PSTATE", 49, 12200000000, 0 },
+ Package() { "PSTATE", 50, 12000000000, 0 },
+ Package() { "PSTATE", 51, 11800000000, 0 },
+ Package() { "PSTATE", 52, 11600000000, 0 },
+ Package() { "PSTATE", 53, 11400000000, 0 },
+ Package() { "PSTATE", 54, 11200000000, 0 },
+ Package() { "PSTATE", 55, 11000000000, 0 },
+ Package() { "PSTATE", 56, 10800000000, 0 },
+ Package() { "PSTATE", 57, 10600000000, 0 },
+ Package() { "PSTATE", 58, 10400000000, 0 },
+ Package() { "PSTATE", 59, 10200000000, 0 },
+ Package() { "PSTATE", 60, 10000000000, 0 },
+ Package() { "PSTATE", 61, 9800000000, 0 },
+ Package() { "PSTATE", 62, 9600000000, 0 },
+ Package() { "PSTATE", 63, 9400000000, 0 },
+ Package() { "PSTATE", 64, 9200000000, 0 },
+ Package() { "PSTATE", 65, 9000000000, 0 },
+ Package() { "PSTATE", 66, 8800000000, 0 },
+ Package() { "PSTATE", 67, 8600000000, 0 },
+ Package() { "PSTATE", 68, 8400000000, 0 },
+ Package() { "PSTATE", 69, 8200000000, 0 },
+ Package() { "PSTATE", 70, 8000000000, 0 },
+ Package() { "PSTATE", 71, 7800000000, 0 },
+ Package() { "PSTATE", 72, 7600000000, 0 },
+ Package() { "PSTATE", 73, 7400000000, 0 },
+ Package() { "PSTATE", 74, 7200000000, 0 },
+ Package() { "PSTATE", 75, 7000000000, 0 },
+ Package() { "PSTATE", 76, 6800000000, 0 },
+ Package() { "PSTATE", 77, 6600000000, 0 },
+ Package() { "PSTATE", 78, 6400000000, 0 },
+ Package() { "PSTATE", 79, 6200000000, 0 },
+ Package() { "PSTATE", 80, 6000000000, 0 },
+ Package() { "PSTATE", 81, 5800000000, 0 },
+ Package() { "PSTATE", 82, 5600000000, 0 },
+ Package() { "PSTATE", 83, 5400000000, 0 },
+ Package() { "PSTATE", 84, 5200000000, 0 },
+ Package() { "PSTATE", 85, 5000000000, 0 },
+ Package() { "PSTATE", 86, 4800000000, 0 },
+ Package() { "PSTATE", 87, 4600000000, 0 },
+ Package() { "PSTATE", 88, 4400000000, 0 },
+ Package() { "PSTATE", 89, 4200000000, 0 },
+ Package() { "PSTATE", 90, 4000000000, 0 },
+ Package() { "PSTATE", 91, 3800000000, 0 },
+ Package() { "PSTATE", 92, 3600000000, 0 },
+ Package() { "PSTATE", 93, 3400000000, 0 },
+ Package() { "PSTATE", 94, 3200000000, 0 },
+ Package() { "PSTATE", 95, 3000000000, 0 },
+ Package() { "PSTATE", 96, 2800000000, 0 },
+ Package() { "PSTATE", 97, 2600000000, 0 },
+ Package() { "PSTATE", 98, 2400000000, 0 },
+ Package() { "PSTATE", 99, 2200000000, 0 },
+ Package() { "PSTATE", 100, 2000000000, 0 },
+ Package() { "PSTATE", 101, 1800000000, 0 },
+ Package() { "PSTATE", 102, 1600000000, 0 },
+ Package() { "PSTATE", 103, 1400000000, 0 },
+ Package() { "PSTATE", 104, 1200000000, 0 },
+ Package() { "PSTATE", 105, 1000000000, 0 },
+ Package() { "PSTATE", 106, 800000000, 1 },
+ Package() { "PSTATE", 107, 600000000, 1 },
+ Package() { "PSTATE", 108, 400000000, 2 },
+ Package() { "PSTATE", 109, 200000000, 2 },
+ Package() { "PSTATE", 110, 0, 2 },
+ },
+
+
+ },
+
+ //----------------------------------------------------------------------------------
+ // C5 - Crypto Engine Power States
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "COMPONENT",
+ 5, // Component Index
+ Buffer()
+ {
+ 0xFA, 0x73, 0x4D, 0xCC, 0xC2, 0xC3, 0x7E, 0x4C, // GUID: {CC4D73FA-C3C2-4C7E-A217-D468F4611BBD}
+ 0xA2, 0x17, 0xD4, 0x68, 0xF4, 0x61, 0x1B, 0xBD
+ },
+
+ "CRYPTO_POWER_STATES", // Common Name
+ "HW_BLOCK_NONE", // Hw Block associated with this component
+
+ Package()
+ {
+ "ENGINE", // Dxgkrnl Component Type
+ "CRYPTO",
+ },
+
+ 2, // Number of F-States
+ 3, // Number of P-State Sets
+
+ // Logical Transition Residency Nominal
+ // ID Power State Latency Requirement Power
+ // --- ----------- ---------- ----------- -------
+ Package() { "FSTATE", 0, "ALL_ON", 0, 0, 3 },
+ Package() { "FSTATE", 1, "PWR_OFF", 100000, 0, 1 },
+
+ //----------------------------------------------------------------------------------
+ // C5.PS0 - Crypto P-State Set: Reset
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // P-State Set Index
+ "CRYPTO_RESET",
+ "*", // HW Revisions
+ "RESET", // Resource Type
+ 2, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Do Nothing
+ Package() { "PSTATE", 1, 0, 2 }, // Do Nothing
+ },
+
+ //----------------------------------------------------------------------------------
+ // C5.PS1 - Crypto P-State Set: Footswitch override
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // P-State Set Index
+ "CRYPTO_FOOTSWITCH_OVERRIDE",
+ "*", // HW Revisions
+ "FOOTSWITCH_OVERRIDE", // Resource Type
+ 2, // Num P-States in Set
+ 1, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Footswitch On
+ Package() { "PSTATE", 1, 0, 2 }, // Footswitch Off
+ },
+
+ //----------------------------------------------------------------------------------
+ // C5.PS2 - Crypto Core Performance: Core Clock Frequency
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // P-State Set Index
+ "CRYPTO_CORE_CLOCK_CONTROL",
+ "*", // HW Revisions
+ "CORE_CLOCK", // Resource Type
+ 1, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 0, 0 },
+ },
+
+
+ },
+
+ //----------------------------------------------------------------------------------
+ // C6 - Video Encoder Engine Power States
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "COMPONENT",
+ 6, // Component Index
+ Buffer()
+ {
+ 0x96, 0x50, 0xBE, 0xE6, 0xEC, 0x55, 0x91, 0x48, // GUID: {E6BE5096-55EC-4891-884B-0760BFC533B6}
+ 0x88, 0x4B, 0x07, 0x60, 0xBF, 0xC5, 0x33, 0xB6
+ },
+
+ "VIDEO_ENCODER_POWER_STATES", // Common Name
+ "HW_BLOCK_VIDEO", // Hw Block associated with this component
+
+ Package()
+ {
+ "ENGINE", // Dxgkrnl Component Type
+ "VIDEO_ENCODER",
+ },
+
+ 3, // Number of F-States
+ 4, // Number of P-State Sets
+
+ // Logical Transition Residency Nominal
+ // ID Power State Latency Requirement Power
+ // --- ----------- ---------- ----------- -------
+ Package() { "FSTATE", 0, "ALL_ON", 0, 0, 3 },
+ Package() { "FSTATE", 1, "CLK_OFF", 10000, 0, 2 },
+ Package() { "FSTATE", 2, "PWR_OFF", 100000, 0, 1 },
+
+ //----------------------------------------------------------------------------------
+ // C6.PS0 - Video Encoder P-State Set: Reset
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // P-State Set Index
+ "VIDEO_ENCODER_RESET",
+ "*", // HW Revisions
+ "RESET", // Resource Type
+ 2, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Do Nothing
+ Package() { "PSTATE", 1, 0, 2 }, // Reset Venus Core
+ },
+
+ //----------------------------------------------------------------------------------
+ // C6.PS1 - Video Encoder P-State Set: Footswitch override
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // P-State Set Index
+ "VIDEO_ENCODER_FOOTSWITCH_OVERRIDE",
+ "*", // HW Revisions
+ "FOOTSWITCH_OVERRIDE", // Resource Type
+ 2, // Num P-States in Set
+ 1, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Footswitch On
+ Package() { "PSTATE", 1, 0, 2 }, // Footswitch Off
+ },
+
+ //----------------------------------------------------------------------------------
+ // C6.PS2 - Video Encoder Core Performance: Core Clock Frequency
+ //
+ // @Brief:
+ // Notes:
+ // - The use of a "CLOSEST" match for the highest frequency is defensive. Any attempt
+ // to request a frequency that's even 1 Hz higher than the maximum entry in Clkrgm's
+ // table will result in a silent failure and no change in clock frequency.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // P-State Set Index
+ "VIDEO_ENCODER_CORE_CLOCK_CONTROL",
+ "*", // HW Revisions
+ "CORE_CLOCK", // Resource Type
+ 7, // Num P-States in Set
+ 4, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 533000000, 0 },
+ Package() { "PSTATE", 1, 444000000, 1 },
+ Package() { "PSTATE", 2, 404000000, 2 },
+ Package() { "PSTATE", 3, 330000000, 2 },
+ Package() { "PSTATE", 4, 200000000, 2 },
+ Package() { "PSTATE", 5, 100000000, 2 },
+ Package() { "PSTATE", 6, 0, 3 },
+ },
+
+ //----------------------------------------------------------------------------------
+ // C6.PS3 - Video Encoder Performance: Bandwidth to EBI
+ //
+ // @Brief:
+ // AXI bandwidth values are represented by a max, min and step which covers all
+ // possible bandwidth values requested by video core for different decode and
+ // encode scenarios.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 3, // P-State Set Index
+ "VIDEO_ENCODER_AXI_PORT_BW",
+ "*", // HW Revisions
+ "BANDWIDTH", // Resource Type
+ 111, // Num P-States in Set
+ 108, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 22000000000, 0 },
+ Package() { "PSTATE", 1, 21800000000, 0 },
+ Package() { "PSTATE", 2, 21600000000, 0 },
+ Package() { "PSTATE", 3, 21400000000, 0 },
+ Package() { "PSTATE", 4, 21200000000, 0 },
+ Package() { "PSTATE", 5, 21000000000, 0 },
+ Package() { "PSTATE", 6, 20800000000, 0 },
+ Package() { "PSTATE", 7, 20600000000, 0 },
+ Package() { "PSTATE", 8, 20400000000, 0 },
+ Package() { "PSTATE", 9, 20200000000, 0 },
+ Package() { "PSTATE", 10, 20000000000, 0 },
+ Package() { "PSTATE", 11, 19800000000, 0 },
+ Package() { "PSTATE", 12, 19600000000, 0 },
+ Package() { "PSTATE", 13, 19400000000, 0 },
+ Package() { "PSTATE", 14, 19200000000, 0 },
+ Package() { "PSTATE", 15, 19000000000, 0 },
+ Package() { "PSTATE", 16, 18800000000, 0 },
+ Package() { "PSTATE", 17, 18600000000, 0 },
+ Package() { "PSTATE", 18, 18400000000, 0 },
+ Package() { "PSTATE", 19, 18200000000, 0 },
+ Package() { "PSTATE", 20, 18000000000, 0 },
+ Package() { "PSTATE", 21, 17800000000, 0 },
+ Package() { "PSTATE", 22, 17600000000, 0 },
+ Package() { "PSTATE", 23, 17400000000, 0 },
+ Package() { "PSTATE", 24, 17200000000, 0 },
+ Package() { "PSTATE", 25, 17000000000, 0 },
+ Package() { "PSTATE", 26, 16800000000, 0 },
+ Package() { "PSTATE", 27, 16600000000, 0 },
+ Package() { "PSTATE", 28, 16400000000, 0 },
+ Package() { "PSTATE", 29, 16200000000, 0 },
+ Package() { "PSTATE", 30, 16000000000, 0 },
+ Package() { "PSTATE", 31, 15800000000, 0 },
+ Package() { "PSTATE", 32, 15600000000, 0 },
+ Package() { "PSTATE", 33, 15400000000, 0 },
+ Package() { "PSTATE", 34, 15200000000, 0 },
+ Package() { "PSTATE", 35, 15000000000, 0 },
+ Package() { "PSTATE", 36, 14800000000, 0 },
+ Package() { "PSTATE", 37, 14600000000, 0 },
+ Package() { "PSTATE", 38, 14400000000, 0 },
+ Package() { "PSTATE", 39, 14200000000, 0 },
+ Package() { "PSTATE", 40, 14000000000, 0 },
+ Package() { "PSTATE", 41, 13800000000, 0 },
+ Package() { "PSTATE", 42, 13600000000, 0 },
+ Package() { "PSTATE", 43, 13400000000, 0 },
+ Package() { "PSTATE", 44, 13200000000, 0 },
+ Package() { "PSTATE", 45, 13000000000, 0 },
+ Package() { "PSTATE", 46, 12800000000, 0 },
+ Package() { "PSTATE", 47, 12600000000, 0 },
+ Package() { "PSTATE", 48, 12400000000, 0 },
+ Package() { "PSTATE", 49, 12200000000, 0 },
+ Package() { "PSTATE", 50, 12000000000, 0 },
+ Package() { "PSTATE", 51, 11800000000, 0 },
+ Package() { "PSTATE", 52, 11600000000, 0 },
+ Package() { "PSTATE", 53, 11400000000, 0 },
+ Package() { "PSTATE", 54, 11200000000, 0 },
+ Package() { "PSTATE", 55, 11000000000, 0 },
+ Package() { "PSTATE", 56, 10800000000, 0 },
+ Package() { "PSTATE", 57, 10600000000, 0 },
+ Package() { "PSTATE", 58, 10400000000, 0 },
+ Package() { "PSTATE", 59, 10200000000, 0 },
+ Package() { "PSTATE", 60, 10000000000, 0 },
+ Package() { "PSTATE", 61, 9800000000, 0 },
+ Package() { "PSTATE", 62, 9600000000, 0 },
+ Package() { "PSTATE", 63, 9400000000, 0 },
+ Package() { "PSTATE", 64, 9200000000, 0 },
+ Package() { "PSTATE", 65, 9000000000, 0 },
+ Package() { "PSTATE", 66, 8800000000, 0 },
+ Package() { "PSTATE", 67, 8600000000, 0 },
+ Package() { "PSTATE", 68, 8400000000, 0 },
+ Package() { "PSTATE", 69, 8200000000, 0 },
+ Package() { "PSTATE", 70, 8000000000, 0 },
+ Package() { "PSTATE", 71, 7800000000, 0 },
+ Package() { "PSTATE", 72, 7600000000, 0 },
+ Package() { "PSTATE", 73, 7400000000, 0 },
+ Package() { "PSTATE", 74, 7200000000, 0 },
+ Package() { "PSTATE", 75, 7000000000, 0 },
+ Package() { "PSTATE", 76, 6800000000, 0 },
+ Package() { "PSTATE", 77, 6600000000, 0 },
+ Package() { "PSTATE", 78, 6400000000, 0 },
+ Package() { "PSTATE", 79, 6200000000, 0 },
+ Package() { "PSTATE", 80, 6000000000, 0 },
+ Package() { "PSTATE", 81, 5800000000, 0 },
+ Package() { "PSTATE", 82, 5600000000, 0 },
+ Package() { "PSTATE", 83, 5400000000, 0 },
+ Package() { "PSTATE", 84, 5200000000, 0 },
+ Package() { "PSTATE", 85, 5000000000, 0 },
+ Package() { "PSTATE", 86, 4800000000, 0 },
+ Package() { "PSTATE", 87, 4600000000, 0 },
+ Package() { "PSTATE", 88, 4400000000, 0 },
+ Package() { "PSTATE", 89, 4200000000, 0 },
+ Package() { "PSTATE", 90, 4000000000, 0 },
+ Package() { "PSTATE", 91, 3800000000, 0 },
+ Package() { "PSTATE", 92, 3600000000, 0 },
+ Package() { "PSTATE", 93, 3400000000, 0 },
+ Package() { "PSTATE", 94, 3200000000, 0 },
+ Package() { "PSTATE", 95, 3000000000, 0 },
+ Package() { "PSTATE", 96, 2800000000, 0 },
+ Package() { "PSTATE", 97, 2600000000, 0 },
+ Package() { "PSTATE", 98, 2400000000, 0 },
+ Package() { "PSTATE", 99, 2200000000, 0 },
+ Package() { "PSTATE", 100, 2000000000, 0 },
+ Package() { "PSTATE", 101, 1800000000, 0 },
+ Package() { "PSTATE", 102, 1600000000, 0 },
+ Package() { "PSTATE", 103, 1400000000, 0 },
+ Package() { "PSTATE", 104, 1200000000, 0 },
+ Package() { "PSTATE", 105, 1000000000, 0 },
+ Package() { "PSTATE", 106, 800000000, 1 },
+ Package() { "PSTATE", 107, 600000000, 1 },
+ Package() { "PSTATE", 108, 400000000, 2 },
+ Package() { "PSTATE", 109, 200000000, 2 },
+ Package() { "PSTATE", 110, 0, 2 },
+ },
+
+
+ Package()
+ {
+ "PROVIDERS",
+ 1, // Number of providers
+ Package()
+ {
+ 4, // VIDEO_POWER_STATES
+ },
+ },
+ },
+
+ //----------------------------------------------------------------------------------
+ // C7 - Internal (Secondary) Display Power States
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "COMPONENT",
+ 7, // Component Index
+ Buffer()
+ {
+ 0x28, 0xE6, 0x2B, 0xC4, 0xBC, 0xD6, 0x55, 0x47, // GUID: {C42BE628-D6BC-4755-BFD5-5AF776797228}
+ 0xBF, 0xD5, 0x5A, 0xF7, 0x76, 0x79, 0x72, 0x28
+ },
+
+ "SECDISPLAY_POWER_STATES", // Common Name
+ "HW_BLOCK_MDP", // Hw Block associated with this component
+
+ Package()
+ {
+ "DISPLAY", // Dxgkrnl Component Type
+ "INTERNAL2",
+ },
+
+ 2, // Number of F-States
+ 5, // Number of P-State Sets
+
+ // Logical Transition Residency Nominal
+ // ID Power State Latency Requirement Power
+ // --- ----------- ---------- ----------- -------
+ Package() { "FSTATE", 0, "ALL_ON", 0, 0, 2 },
+ Package() { "FSTATE", 1, "PWR_OFF", 1, 1, 1 },
+
+ //----------------------------------------------------------------------------------
+ // C7.PS0 - Internal (Secondary) Display: MDP Reset Control
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // P-State Set Index
+ "INTERNAL2_RESET",
+ "*", // HW Revisions
+ "RESET", // Resource Type
+ 2, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Do Nothing
+ Package() { "PSTATE", 1, 0, 2 }, // Reset Display Core
+ },
+
+ //----------------------------------------------------------------------------------
+ // C7.PS1 - Internal (Secondary) Display : MDP Footswitch override
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // P-State Set Index
+ "INTERNAL2_FOOTSWITCH_OVERRIDE",
+ "*", // HW Revisions
+ "FOOTSWITCH_OVERRIDE", // Resource Type
+ 2, // Num P-States in Set
+ 0xFFFFFFFF, // Initial P-State (i.e. none)
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Footswitch On
+ Package() { "PSTATE", 1, 0, 2 }, // Footswitch Off
+ },
+
+ //----------------------------------------------------------------------------------
+ // C7.PS2 - Internal (Secondary) Display : Power states for MDP scan-out HW
+ //
+ // @Brief:
+ // - Used to dynamically control MDP related clocks within a PState
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // P-State Set Index
+ "INTERNAL2_SCAN_CONTROL",
+ "*", // HW Revisions
+ "DISPLAY_SOURCE_SCAN_CTRL", // Resource Type
+ 5, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 4, 2 }, // Vote for all scan-out resources
+ Package() { "PSTATE", 1, 3, 2 }, // Vote for only MDP, DSI 0 and DSI 1 scan-out resources
+ Package() { "PSTATE", 2, 2, 2 }, // Vote for only MDP and DSI 0 scan-out resources
+ Package() { "PSTATE", 3, 1, 2 }, // Vote for only MDP and DSI 1 scan-out resources
+ Package() { "PSTATE", 4, 0, 2 }, // Remove votes for all scan-out resources
+ },
+
+ //----------------------------------------------------------------------------------
+ // C7.PS3 - Internal (Secondary) Display : MDP Core Clock Frequency
+ //
+ // @Brief:
+ // Notes:
+ // - This table reflects the frequency plan for the v1 part.
+ // - All core frequency votes are based on specific clock plan values and are cast
+ // 2 MHz below what we actually desire. This helps avoid potential issues with
+ // round-up when the actual clock frequency on real HW is slightly less than
+ // that which was advertized in the clock plan.
+ // - [NC] Temporarily moved all AHB bandwidth votes to F-states to help work around
+ // 64K size issue in the final AML.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 3, // P-State Set Index
+ "INTERNAL2_CORE_CLOCK_CONTROL",
+ "*", // HW Revisions
+ "CORE_CLOCK", // Resource Type
+ 13, // Num P-States in Set
+ 4, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 430000000, 1 },
+ Package() { "PSTATE", 1, 412500000, 1 },
+ Package() { "PSTATE", 2, 344000000, 2 },
+ Package() { "PSTATE", 3, 300000000, 2 },
+ Package() { "PSTATE", 4, 275000000, 2 },
+ Package() { "PSTATE", 5, 200000000, 2 },
+ Package() { "PSTATE", 6, 171428571, 3 },
+ Package() { "PSTATE", 7, 165000000, 3 },
+ Package() { "PSTATE", 8, 150000000, 3 },
+ Package() { "PSTATE", 9, 100000000, 3 },
+ Package() { "PSTATE", 10, 85710000, 3 },
+ Package() { "PSTATE", 11, 19200000, 3 },
+ Package() { "PSTATE", 12, 0, 3 },
+ },
+
+ //----------------------------------------------------------------------------------
+ // C7.PS4 - Internal (Secondary) Display : Display Bandwidth to EBI
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 4, // P-State Set Index
+ "INTERNAL2_EBI_BANDWIDTH",
+ "*", // HW Revisions
+ "BANDWIDTH", // Resource Type
+ 43, // Num P-States in Set
+ 28, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 13326000000, 0 },
+ Package() { "PSTATE", 1, 12926000000, 0 },
+ Package() { "PSTATE", 2, 12526000000, 0 },
+ Package() { "PSTATE", 3, 12126000000, 0 },
+ Package() { "PSTATE", 4, 11726000000, 0 },
+ Package() { "PSTATE", 5, 11326000000, 0 },
+ Package() { "PSTATE", 6, 10926000000, 0 },
+ Package() { "PSTATE", 7, 10526000000, 0 },
+ Package() { "PSTATE", 8, 10126000000, 1 },
+ Package() { "PSTATE", 9, 9600000000, 1 },
+ Package() { "PSTATE", 10, 9200000000, 1 },
+ Package() { "PSTATE", 11, 8800000000, 1 },
+ Package() { "PSTATE", 12, 8400000000, 1 },
+ Package() { "PSTATE", 13, 8000000000, 1 },
+ Package() { "PSTATE", 14, 7600000000, 1 },
+ Package() { "PSTATE", 15, 7200000000, 1 },
+ Package() { "PSTATE", 16, 6800000000, 1 },
+ Package() { "PSTATE", 17, 6400000000, 1 },
+ Package() { "PSTATE", 18, 6000000000, 1 },
+ Package() { "PSTATE", 19, 5600000000, 1 },
+ Package() { "PSTATE", 20, 5200000000, 2 },
+ Package() { "PSTATE", 21, 4800000000, 2 },
+ Package() { "PSTATE", 22, 4400000000, 2 },
+ Package() { "PSTATE", 23, 4000000000, 2 },
+ Package() { "PSTATE", 24, 3600000000, 2 },
+ Package() { "PSTATE", 25, 3200000000, 2 },
+ Package() { "PSTATE", 26, 2800000000, 2 },
+ Package() { "PSTATE", 27, 2400000000, 2 },
+ Package() { "PSTATE", 28, 2000000000, 2 },
+ Package() { "PSTATE", 29, 1600000000, 2 },
+ Package() { "PSTATE", 30, 1500000000, 2 },
+ Package() { "PSTATE", 31, 1400000000, 2 },
+ Package() { "PSTATE", 32, 1300000000, 2 },
+ Package() { "PSTATE", 33, 1200000000, 2 },
+ Package() { "PSTATE", 34, 1100000000, 2 },
+ Package() { "PSTATE", 35, 1000000000, 2 },
+ Package() { "PSTATE", 36, 900000000, 2 },
+ Package() { "PSTATE", 37, 800000000, 2 },
+ Package() { "PSTATE", 38, 700000000, 2 },
+ Package() { "PSTATE", 39, 600000000, 2 },
+ Package() { "PSTATE", 40, 500000000, 2 },
+ Package() { "PSTATE", 41, 400000000, 2 },
+ Package() { "PSTATE", 42, 0, 2 },
+ },
+
+
+ },
+
+ //----------------------------------------------------------------------------------
+ // C8 - Display Port Power States
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "COMPONENT",
+ 8, // Component Index
+ Buffer()
+ {
+ 0xD2, 0xAE, 0x8D, 0x81, 0x63, 0x9E, 0xD5, 0x49, // GUID: {818DAED2-9E63-49D5-BD12-B0951F7B0F6B}
+ 0xBD, 0x12, 0xB0, 0x95, 0x1F, 0x7B, 0x0F, 0x6B
+ },
+
+ "DP_POWER_STATES", // Common Name
+ "HW_BLOCK_MDP", // Hw Block associated with this component
+
+ Package()
+ {
+ "DISPLAY", // Dxgkrnl Component Type
+ "EXTERNAL1",
+ },
+
+ 2, // Number of F-States
+ 4, // Number of P-State Sets
+
+ // Logical Transition Residency Nominal
+ // ID Power State Latency Requirement Power
+ // --- ----------- ---------- ----------- -------
+ Package() { "FSTATE", 0, "ALL_ON", 0, 0, 2 },
+ Package() { "FSTATE", 1, "PWR_OFF", 1, 1, 1 },
+
+ //----------------------------------------------------------------------------------
+ // C8.PS0 - DP: MDP Reset Control
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 0, // P-State Set Index
+ "EXTERNAL1_RESET",
+ "*", // HW Revisions
+ "RESET", // Resource Type
+ 2, // Num P-States in Set
+ 0, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Do Nothing
+ Package() { "PSTATE", 1, 0, 2 }, // Reset MDSS Core
+ },
+
+ //----------------------------------------------------------------------------------
+ // C8.PS1 - External Display: MDP Footswitch override
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 1, // P-State Set Index
+ "EXTERNAL1_FOOTSWITCH_OVERRIDE",
+ "*", // HW Revisions
+ "FOOTSWITCH_OVERRIDE", // Resource Type
+ 2, // Num P-States in Set
+ 0xFFFFFFFF, // Initial P-State (i.e. none)
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 1, 2 }, // Footswitch On
+ Package() { "PSTATE", 1, 0, 2 }, // Footswitch Off
+ },
+
+ //----------------------------------------------------------------------------------
+ // C8.PS2 - DP: MDP Core Clock Frequency
+ //
+ // @Brief:
+ // Notes:
+ // - This table reflects the frequency plan for the v1 part.
+ // - All core frequency votes are based on specific clock plan values and are cast
+ // 2 MHz below what we actually desire. This helps avoid potential issues with
+ // round-up when the actual clock frequency on real HW is slightly less than
+ // that which was advertized in the clock plan.
+ // - [NC] Temporarily moved all AHB bandwidth votes to F-states to help work around
+ // 64K size issue in the final AML.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 2, // P-State Set Index
+ "EXTERNAL1_CORE_CLOCK_CONTROL",
+ "*", // HW Revisions
+ "CORE_CLOCK", // Resource Type
+ 13, // Num P-States in Set
+ 4, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 430000000, 1 },
+ Package() { "PSTATE", 1, 412500000, 1 },
+ Package() { "PSTATE", 2, 344000000, 2 },
+ Package() { "PSTATE", 3, 300000000, 2 },
+ Package() { "PSTATE", 4, 275000000, 2 },
+ Package() { "PSTATE", 5, 200000000, 2 },
+ Package() { "PSTATE", 6, 171428571, 3 },
+ Package() { "PSTATE", 7, 165000000, 3 },
+ Package() { "PSTATE", 8, 150000000, 3 },
+ Package() { "PSTATE", 9, 100000000, 3 },
+ Package() { "PSTATE", 10, 85710000, 3 },
+ Package() { "PSTATE", 11, 19200000, 3 },
+ Package() { "PSTATE", 12, 0, 3 },
+ },
+
+ //----------------------------------------------------------------------------------
+ // C8.PS3 - DP: Display Bandwidth to EBI
+ //
+ // @Brief:
+ // Notes:
+ // - AXI port 0 is strictly used by the scanout logic today, so the bandwidth values
+ // in this table were selected to span the full range of potential scanout needs for
+ // 8064 in such a way that no request will be rounded up by more than 10%. The
+ // bottom end of the range is driven by the simple scenario of a single RGB layer on
+ // a VGA sized primary display:
+ //
+ // 640 * 400 * 60Hz * 4Bytes/pixel = 73,728,000 Bytes/Sec
+ //
+ // The top end of the range is meant to support the maximum allowable primary display
+ // resolution (i.e. WUXGA) with one RGB layer and one YUV layer, plus an DP display
+ // with one RGB layer and one YUV layer:
+ //
+ // 1920 * 1200 * 60Hz * 4Bytes/Pixel = 552,960,000 Bytes/Sec
+ // + 1920 * 1200 * 60Hz * 1.5Bytes/Pixel = 207,360,000 Bytes/Sec
+ // + 1920 * 1080 * 60Hz * 4Bytes/Pixel = 497,664,000 Bytes/Sec
+ // + 1920 * 1080 * 60Hz * 1.5Bytes/Pixel = 186,624,000 Bytes/Sec
+ // -----------------------
+ // 1,444,608,000 Bytes/Sec
+ //
+ // Within the table, the arbitrated bandwidth values are each padded by 10 0.000000or
+ // headroom, and the instantaneous bandwidth values are padded by an additional 10%
+ // to help account for the bursty nature of scan-line fetches.
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "PSTATE_SET",
+ 3, // P-State Set Index
+ "EXTERNAL1_EBI_BANDWIDTH",
+ "*", // HW Revisions
+ "BANDWIDTH", // Resource Type
+ 43, // Num P-States in Set
+ 28, // Initial P-State
+ 0, // Stable Power P-State (i.e. none)
+
+ // Voltage
+ // ID Value Level
+ // --- ---------- -----
+ Package() { "PSTATE", 0, 13326000000, 0 },
+ Package() { "PSTATE", 1, 12926000000, 0 },
+ Package() { "PSTATE", 2, 12526000000, 0 },
+ Package() { "PSTATE", 3, 12126000000, 0 },
+ Package() { "PSTATE", 4, 11726000000, 0 },
+ Package() { "PSTATE", 5, 11326000000, 0 },
+ Package() { "PSTATE", 6, 10926000000, 0 },
+ Package() { "PSTATE", 7, 10526000000, 0 },
+ Package() { "PSTATE", 8, 10126000000, 1 },
+ Package() { "PSTATE", 9, 9600000000, 1 },
+ Package() { "PSTATE", 10, 9200000000, 1 },
+ Package() { "PSTATE", 11, 8800000000, 1 },
+ Package() { "PSTATE", 12, 8400000000, 1 },
+ Package() { "PSTATE", 13, 8000000000, 1 },
+ Package() { "PSTATE", 14, 7600000000, 1 },
+ Package() { "PSTATE", 15, 7200000000, 1 },
+ Package() { "PSTATE", 16, 6800000000, 1 },
+ Package() { "PSTATE", 17, 6400000000, 1 },
+ Package() { "PSTATE", 18, 6000000000, 1 },
+ Package() { "PSTATE", 19, 5600000000, 1 },
+ Package() { "PSTATE", 20, 5200000000, 2 },
+ Package() { "PSTATE", 21, 4800000000, 2 },
+ Package() { "PSTATE", 22, 4400000000, 2 },
+ Package() { "PSTATE", 23, 4000000000, 2 },
+ Package() { "PSTATE", 24, 3600000000, 2 },
+ Package() { "PSTATE", 25, 3200000000, 2 },
+ Package() { "PSTATE", 26, 2800000000, 2 },
+ Package() { "PSTATE", 27, 2400000000, 2 },
+ Package() { "PSTATE", 28, 2000000000, 2 },
+ Package() { "PSTATE", 29, 1600000000, 2 },
+ Package() { "PSTATE", 30, 1500000000, 2 },
+ Package() { "PSTATE", 31, 1400000000, 2 },
+ Package() { "PSTATE", 32, 1300000000, 2 },
+ Package() { "PSTATE", 33, 1200000000, 2 },
+ Package() { "PSTATE", 34, 1100000000, 2 },
+ Package() { "PSTATE", 35, 1000000000, 2 },
+ Package() { "PSTATE", 36, 900000000, 2 },
+ Package() { "PSTATE", 37, 800000000, 2 },
+ Package() { "PSTATE", 38, 700000000, 2 },
+ Package() { "PSTATE", 39, 600000000, 2 },
+ Package() { "PSTATE", 40, 500000000, 2 },
+ Package() { "PSTATE", 41, 400000000, 2 },
+ Package() { "PSTATE", 42, 0, 2 },
+ },
+
+
+ },
+
+ //----------------------------------------------------------------------------------
+ // C9 - Dummy Component for WP Workaround
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "COMPONENT",
+ 9, // Component Index
+ Buffer()
+ {
+ 0xDF, 0x0B, 0xD4, 0x8D, 0xBD, 0x6F, 0xED, 0x45, // GUID: {8DD40BDF-6FBD-45ED-8538-711D434B6BA1}
+ 0x85, 0x38, 0x71, 0x1D, 0x43, 0x4B, 0x6B, 0xA1
+ },
+
+ "ALWAYS_ACTIVE_WP", // Common Name
+ "HW_BLOCK_NONE", // Hw Block associated with this component
+
+ Package()
+ {
+ "UNMANAGED", // Dxgkrnl Component Type
+ },
+
+ 1, // Number of F-States
+ 0, // Number of P-State Sets
+
+ // Logical Transition Residency Nominal
+ // ID Power State Latency Requirement Power
+ // --- ----------- ---------- ----------- -------
+ Package() { "FSTATE", 0, "ALL_ON", 0, 0, 1 },
+
+
+ },
+ })
+
+
+ //
+ //=========================================================================================
+ // Chip-Specific Patches
+ //=========================================================================================
+ //
+
+ //-----------------------------------------------------------------------------------------
+ // Patch for C1.PS3 when:
+ // ChipVersion >= 2.0
+ //-----------------------------------------------------------------------------------------
+ //
+ Name (P001,
+ //----------------------------------------------------------------------------------
+ // C1.PS3 - 3D Graphics Core P-State Set: Engine Controlled Core Clock
+ //
+ // @Brief:
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "ENGINE_PSTATE_SET",
+ 3,
+ "GRAPHICS_FREQ_CONTROL",
+ "CORE_CLOCK", // Resource Type
+ 9, // Num P-States in Set
+ 1, // Num CustomData fields in Set
+ TRUE, // Has Thermal Thresholds
+ 5, // Initial P-State
+ 3, // Stable Power P-State
+
+ // Voltage
+ // ID Value Level Thermal Thresholds Custom Data Fields
+ // --- ---------- ----- -------------------- --------------------
+ Package() { "PSTATE", 0, 710000000, 0, Package() { "GPU", 100, }, Package() { 416 , } },
+ Package() { "PSTATE", 1, 675000000, 1, Package() { "GPU", 91, }, Package() { 384 , } },
+ Package() { "PSTATE", 2, 596000000, 2, Package() { "GPU", 81, }, Package() { 320 , } },
+ Package() { "PSTATE", 3, 520000000, 3, Package() { "GPU", 71, }, Package() { 256 , } },
+ Package() { "PSTATE", 4, 414000000, 4, Package() { "GPU", 56, }, Package() { 192 , } },
+ Package() { "PSTATE", 5, 342000000, 5, Package() { "GPU", 47, }, Package() { 128 , } },
+ Package() { "PSTATE", 6, 247000000, 6, Package() { "GPU", 35, }, Package() { 64 , } },
+ Package() { "PSTATE", 7, 180000000, 7, Package() { "GPU", 0, }, Package() { 48 , } },
+ Package() { "PSTATE", 8, 0, 8, Package() { "GPU", 0, }, Package() { 0 , } },
+ }
+ )
+
+ //-----------------------------------------------------------------------------------------
+ // Patch for C1.PS3 when:
+ // No other matching conditions
+ //-----------------------------------------------------------------------------------------
+ //
+ Name (P002,
+ //----------------------------------------------------------------------------------
+ // C1.PS3 - 3D Graphics Core P-State Set: Engine Controlled Core Clock
+ //
+ // @Brief:
+ //----------------------------------------------------------------------------------
+ //
+ Package()
+ {
+ "ENGINE_PSTATE_SET",
+ 3,
+ "GRAPHICS_FREQ_CONTROL",
+ "CORE_CLOCK", // Resource Type
+ 2, // Num P-States in Set
+ 1, // Num CustomData fields in Set
+ TRUE, // Has Thermal Thresholds
+ 0, // Initial P-State
+ 0, // Stable Power P-State
+
+ // Voltage
+ // ID Value Level Thermal Thresholds Custom Data Fields
+ // --- ---------- ----- -------------------- --------------------
+ Package() { "PSTATE", 0, 280000000, 0, Package() { "GPU", 0, }, Package() { 128 , } },
+ Package() { "PSTATE", 1, 0, 1, Package() { "GPU", 0, }, Package() { 0 , } },
+ }
+ )
+
+
+ //
+ //=========================================================================================
+ // Chip-Specific Patch Logic
+ //=========================================================================================
+ //
+
+ // Apply C1.PS3 patch
+ //
+ If (LGreaterEqual(\_SB.SIDV,0x00020000))
+ {
+ // ChipVersion >= 2.0
+ //
+ Store(P001, Index(DeRefOf(Index(RBUF, 4)), 14))
+ }
+ Else
+ {
+ // All other chips
+ //
+ Store(P002, Index(DeRefOf(Index(RBUF, 4)), 14))
+ }
+
+ Return (RBUF)
+ }
+
+ // Include Display ACPI extensions, which include panel configuration (_ROM) method
+ //
+ Include("display.asl")
+
+ // Include display adapter configuration for secondary display
+ //
+ Include("display2.asl")
+
+ // Include display adapter configuration for external display
+ //
+ Include("displayext.asl")
+
+ NAME(_DOD, Package()
+ {
+ 0x00024321,
+ })
+
+ // Enumeration and device info for the AVStream child driver
+ //
+ Device (AVS0)
+ {
+ // The address for this device (Same as in _DOD, above)
+ //
+ Name(_ADR, 0x00024321)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ })
+ Return (RBUF)
+ }
+
+ Name (_DEP, Package(0x3)
+ {
+ \_SB_.MMU0,
+ \_SB_.IMM0,
+ \_SB_.VFE0
+ })
+ }
+
+ //------------------------------------------------------------------------------
+ // _STA method
+ // _STA method, would be used to enable/disable GPU device from uefi menu.
+ //------------------------------------------------------------------------------
+ //
+ Method (_STA, 0x0)
+ {
+ Return (0x0f)
+ }
+
+ //------------------------------------------------------------------------------
+ // Child Device Info
+ // This method includes information for child devices
+ //------------------------------------------------------------------------------
+ //
+ Method (CHDV)
+ {
+ Name (CHIF, Package()
+ {
+ 1, // Number of Child devices
+ Package()
+ {
+ "CHILDDEV",
+ 0, // Child ID
+ 0x24321, // ACPI UID
+ "QCOM_AVStream_850", // Hardware ID
+ 0, // Instance ID
+ "Qualcomm Camera AVStream Mini Driver", // Device Text
+
+ Package()
+ {
+ "COMPATIBLEIDS",
+ 2, // Number of Compatible IDs
+ "VEN_QCOM&DEV__AVSTREAM", // Compatible ID 1
+ "QCOM_AVSTREAM", // Compatible ID 2
+ },
+ },
+ })
+ Return (CHIF)
+ }
+
+ //------------------------------------------------------------------------------
+ // DP CC status method, 0:CC1(Normal plugin), 1:CC2(Inverted plugin), 2: Open(unplugged in)
+ //------------------------------------------------------------------------------
+ //
+ Method (DPCC, 2, NotSerialized)
+ {
+ // Arg0 - Panel ID
+
+ // Arg1 - Data size
+
+ return (\_SB_.CCST)
+ }
+
+ //------------------------------------------------------------------------------
+ // DP Pin assignment method
+ // 0x00: No DP cable is connected
+ // 0x01: DFP_D(Downstream Facing Port DP) Pin A
+ // 0x02: DFP_D(Downstream Facing Port DP) Pin B
+ // 0x03: DFP_D(Downstream Facing Port DP) Pin C
+ // 0x04: DFP_D(Downstream Facing Port DP) Pin D
+ // 0x05: DFP_D(Downstream Facing Port DP) Pin E
+ // 0x06: DFP_D(Downstream Facing Port DP) Pin F
+ // 0x07: UFP_D(Upstream Facing Port DP) Pin A
+ // 0x08: UFP_D(Upstream Facing Port DP) Pin B
+ // 0x09: UFP_D(Upstream Facing Port DP) Pin C
+ // 0x0A: UFP_D(Upstream Facing Port DP) Pin D
+ // 0x0B: UFP_D(Upstream Facing Port DP) Pin E
+ //------------------------------------------------------------------------------
+ //
+
+ // Method (DPIN, 2, NotSerialized)
+ // {
+ // // Arg0 - Panel ID
+
+ // // Arg1 - Data size
+
+ // return (\_SB_.PINA)
+ // }
+
+ Method (REGR)
+ {
+ Name (RBUF, Package()
+ {
+ Package()
+ {
+ "ForceMaxPerf",
+ 0,
+ },
+ Package()
+ {
+ "ForceStablePowerSettings",
+ 0,
+ },
+ Package()
+ {
+ "ForceActive",
+ 1,
+ },
+ Package()
+ {
+ "DeferForceActive",
+ 0,
+ },
+ Package()
+ {
+ "PreventPowerCollapse",
+ 0,
+ },
+ Package()
+ {
+ "DisableThermalMitigation",
+ 0,
+ },
+ Package()
+ {
+ "DisableTzMDSSRestore", // 8998 Does not need TZ MDSS restore of registers.
+ 1,
+ },
+ Package()
+ {
+ "UseLowPTForGfxPerProcess", // Use Low TTBR for Graphics Per-process page table.
+ 1,
+ },
+ Package()
+ {
+ "DisableCDI",
+ 1,
+ },
+ Package()
+ {
+ "GPU64bAddrEnabled", // Enabled GPU 64bit addressing
+ 1,
+ },
+ Package()
+ {
+ "MaxPreemptionOffsets", // Maximum number of Preemption offsets.
+ 128,
+ },
+ Package()
+ {
+ "MaxRequiredDmaQueueEntry", // Required DMA queue entries.
+ 8,
+ },
+ Package()
+ {
+ "SupportsSecureInAperture", // Supports secure surfaces in the Aperture segment.
+ 1,
+ },
+ Package()
+ {
+ "ZeroFlagSupportInPTE", // Supports zero flag in PTE
+ 1,
+ },
+ Package()
+ {
+ "SupportsCacheCoherency", // Supports System wide coherency.
+ 1,
+ },
+ Package()
+ {
+ "SupportsSHMBridge", // Supports SHM Bridge registration.
+ 0,
+ },
+ Package()
+ {
+ "SecureCarveoutSize", // SecureCarveout Size for DRM playback
+ 2097152,
+ },
+ Package()
+ {
+ "UBWCEnable", // 0 = Disable , 1 = Enable
+ 0,
+ },
+ Package()
+ {
+ "allowDrmAbove1080p", // Allow DRM playback above 1080p
+ 1,
+ },
+ Package()
+ {
+ "ZeroPageLowAddr", // Lower address of zero marker page
+ 0x85F00000,
+ },
+ Package()
+ {
+ "ZeroPageHighAddr", // Higher address of zero marker page
+ 0x0,
+ },
+ Package()
+ {
+ "KeepUefiBuffer",
+ 1,
+ },
+ Package()
+ {
+ "GRAPHICS",
+ Package()
+ {
+ "EnableSystemCache", // 0 = Disable , 1 = Enable
+ 1,
+ },
+ Package()
+ {
+ "EnableSysCacheForGpuhtw", // 0 = Disable , 1 = Enable(enable SystemCache to take effect)
+ 1,
+ },
+ Package()
+ {
+ "DCVS",
+ Package()
+ {
+ "Enable", // 0 = FALSE, 1 = TRUE
+ 1,
+ },
+ Package()
+ {
+ "IncreaseFilterBw", // Hz / 65536
+ 131072,
+ },
+ Package()
+ {
+ "DecreaseFilterBw", // Hz / 65536
+ 13107,
+ },
+ Package()
+ {
+ "TargetBusyPct", // Percentage
+ 85,
+ },
+ Package()
+ {
+ "SampleRate", // Hz
+ 60,
+ },
+ Package()
+ {
+ "TargetBusyPctOffscreen", // Percentage
+ 75,
+ },
+ Package()
+ {
+ "SampleRateOffscreen", // Hz
+ 20,
+ },
+ Package()
+ {
+ "GpuResetValue", // Hz
+ 290000000,
+ },
+ Package()
+ {
+ "BusResetValue", // MB/s
+ 1200,
+ },
+ },
+ Package()
+ {
+ "A6x",
+ Package()
+ {
+ "DisableICG", // 1 = Disable GPU Clock Gating
+ 0,
+ },
+ Package()
+ {
+ "DisableGmuCG", // 1 = Disable GMU Clock Gating. GMU CG cannot be enabled when ICG is disabled.
+ 0,
+ },
+ Package()
+ {
+ "EnableFallbackToDisableSecureMode", // 1 = Enable the fallback. Fallback is only supported with non secure TZ.
+ 0,
+ },
+ Package()
+ {
+ "DisableCPCrashDump", // 1 = Disable the Crash Dumper
+ 0,
+ },
+ Package()
+ {
+ "Preemption", // 1 = SW preemption, 16 (0x10) = L0, 26 (0x1A) = L1A, 27 (0x1B) = L1B, 18 (0x12) = L2
+ 26,
+ },
+ },
+ },
+ Package()
+ {
+ "VIDEO",
+ Package()
+ {
+ "EnableSystemCache", // 0 = Disable , 1 = Enable
+ 1,
+ },
+ },
+ Package()
+ {
+ "CRYPTO",
+ Package()
+ {
+ "EnableCryptoVA",
+ 1,
+ },
+ },
+ Package()
+ {
+ "DISPLAY",
+ Package()
+ {
+ "DisableMiracast", // Miracast Setting
+ 1,
+ },
+ Package()
+ {
+ "EnableOEMDriverDependency", // OEM Driver Load Configuration
+ 0,
+ },
+ Package()
+ {
+ "EnableBridgeDriverDependency", // Bridge Driver Load Configuration
+ 0,
+ },
+ Package()
+ {
+ "DisableRotator", // Disable or Enable Rotator Engine
+ 0,
+ },
+ Package()
+ {
+ "DisableMDPBLT", // Disable MDP BLT Engine
+ 1,
+ },
+ Package()
+ {
+ "DisableExternal", // Disable External Display
+ 3,
+ },
+ },
+ })
+
+ Return (RBUF)
+ }
+}
--- /dev/null
+//
+// NFC entry.
+//
+Device(NFCD)
+{
+ Name(_HID, "NXP1001")
+ Name(_CID, "ACPI\NXP1001")
+ Alias(\_SB.PSUB, _SUB)
+ Name(_CRS, ResourceTemplate()
+ {
+ I2CSerialBus(0x28, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.I2C4", 0, ResourceConsumer, , )
+ GpioInt(Level, ActiveHigh, Exclusive, PullDefault, 0, "\\_SB.GIO0", 0, ResourceConsumer, , ) {63}
+ })
+// ESE SPI GPIO
+ Name(NFCS, ResourceTemplate()
+ {
+ GpioIO(Exclusive, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , ) {116}
+ })
+// NFCC VEN GPIO
+ Name(NFCP, ResourceTemplate()
+ {
+ GpioIO(Exclusive, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , ) {12}
+ })
+ Scope(GIO0)
+ {
+ OperationRegion(NFPO, GeneralPurposeIO, Zero, One)
+ }
+ Field(\_SB_.GIO0.NFPO, ByteAcc, NoLock, Preserve)
+ {
+ Connection(\_SB_.NFCD.NFCP),
+ MGPE, 1
+ }
+ Method(POON, 0x0, NotSerialized)
+ {
+ Store(One, MGPE)
+ }
+ Method(POOF, 0x0, NotSerialized)
+ {
+ Store(Zero, MGPE)
+ }
+//NFCC FW DOWNLOAD GPIO
+ Name(NFCF, ResourceTemplate()
+ {
+ GpioIO(Exclusive, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , ) {88} // Download
+ })
+ Scope(GIO0)
+ {
+ OperationRegion(NFFO, GeneralPurposeIO, Zero, One)
+ }
+ Field(\_SB_.GIO0.NFFO, ByteAcc, NoLock, Preserve)
+ {
+ Connection(\_SB_.NFCD.NFCF),
+ MGFE, 1
+ }
+ Method(FWON, 0x0, NotSerialized)
+ {
+ Store(One, MGFE)
+ }
+ Method(FWOF, 0x0, NotSerialized)
+ {
+ Store(Zero, MGFE)
+ }
+ Method(_DSM, 0x4, NotSerialized)
+ {
+ Store("Method NFC _DSM begin", Debug)
+ If(LEqual(Arg0, Buffer(0x10)
+ {
+ 0xc4, 0xf6, 0xe7, 0xa2, 0x38, 0x96, 0x85, 0x44, 0x9f, 0x12, 0x6b, 0x4e,
+ 0x20, 0xb6, 0x0d, 0x63
+ }))
+ {
+ If(LEqual(Arg2, Zero))
+ {
+ Store("Method NFC _DSM QUERY", Debug)
+ If(LEqual(Arg1, One))
+ {
+ \_SB_.NFCD.POOF()
+ Sleep(0x14)
+ Return(Buffer(One)
+ {
+ 0x0f
+ })
+ }
+ }
+ If(LEqual(Arg2, 0x2))
+ {
+ Store("Method NFC _DSM SETPOWERMODE", Debug)
+ If(LEqual(Arg3, One))
+ {
+ \_SB_.NFCD.POON()
+ Sleep(0x14)
+ }
+ If(LEqual(Arg3, Zero))
+ {
+ \_SB_.NFCD.POOF()
+ Sleep(0x14)
+ }
+ }
+ If(LEqual(Arg2, One))
+ {
+ Store("Method NFC _DSM SETFWMODE", Debug)
+//
+// Set the firmware mode to ON.
+//
+ If(LEqual(Arg3, One))
+ {
+ \_SB_.NFCD.FWON()
+//
+// Provide any delay required by the controller before toggling the power GPIO line.
+//
+ Sleep(0x14)
+ \_SB_.NFCD.POOF()
+ Sleep(0x14)
+ \_SB_.NFCD.POON()
+ Sleep(0x14)
+ }
+//
+// Set the firmware mode to OFF.
+//
+ If(LEqual(Arg3, Zero))
+ {
+ \_SB_.NFCD.FWOF()
+ Sleep(0x14)
+ \_SB_.NFCD.POOF()
+ Sleep(0x14)
+ \_SB_.NFCD.POON()
+ Sleep(0x14)
+ }
+ }
+ If(LEqual(Arg2, 0x3))
+ {
+ Store("Method NFC _DSM EEPROM Config", Debug)
+ Return(Buffer(0x13)
+ {
+ 0x9c, 0x1f, 0x38, 0x19, 0xa8, 0xb9, 0x4b, 0xab, 0xa1, 0xba, 0xd0, 0x20,
+ 0x76, 0x88, 0x2a, 0xe0, 0x03, 0x01, 0x11
+ })
+ }
+ }
+ }
+//PEP Proxy Support
+ Name(PGID, Buffer(10) {"\\_SB.NFCD"}) // Device ID buffer - PGID( Pep given ID )
+ Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID( Pep given ID )
+ CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE
+ // HIDDEN 1 BYTE ( SIZE )
+ CreateByteField(DBUF, 2, DVAL ) // Packet value, 1 BYTES Device Status
+ CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES(160 Bits)
+ Method (_S1D, 0) { Return (3) } // S1 => D3
+ Method (_S2D, 0) { Return (3) } // S2 => D3
+ Method (_S3D, 0) { Return (3) } // S3 => D3
+
+ Method(_PS0, 0x0, NotSerialized)
+ {
+ Store(Buffer(ESNL){}, DEID)
+ Store(0, DVAL)
+ Store(PGID, DEID)
+ If(\_SB.ABD.AVBL)
+ {
+ Store(DBUF, \_SB.PEP0.FLD0)
+ }
+ }
+ Method(_PS3, 0x0, NotSerialized)
+ {
+ Store(Buffer(ESNL){}, DEID)
+ Store(3, DVAL)
+ Store(PGID, DEID)
+ If(\_SB.ABD.AVBL)
+ {
+ Store(DBUF, \_SB.PEP0.FLD0)
+ }
+ }
+}
--- /dev/null
+Name (PCFG, Buffer (){
+"<?xml version='1.0' encoding='utf-8'?>
+<PanelName>SAMSUNG_EA8074_NOTCH_FHD</PanelName>
+<PanelDescription>Samsung ea8074 Notch Single DSI Command Mode Panel (1080x2248 24bpp)</PanelDescription>
+<Group id='Active Timing'>
+<HorizontalActive>1080</HorizontalActive>
+<HorizontalFrontPorch>56</HorizontalFrontPorch>
+<HorizontalBackPorch>56</HorizontalBackPorch>
+<HorizontalSyncPulse>18</HorizontalSyncPulse>
+<HorizontalSyncSkew>0</HorizontalSyncSkew>
+<HorizontalLeftBorder>0</HorizontalLeftBorder>
+<HorizontalRightBorder>0</HorizontalRightBorder>
+<VerticalActive>2248</VerticalActive>
+<VerticalFrontPorch>26</VerticalFrontPorch>
+<VerticalBackPorch>24</VerticalBackPorch>
+<VerticalSyncPulse>12</VerticalSyncPulse>
+<VerticalSyncSkew>0</VerticalSyncSkew>
+<VerticalTopBorder>0</VerticalTopBorder>
+<VerticalBottomBorder>0</VerticalBottomBorder>
+<InvertDataPolarity>False</InvertDataPolarity>
+<InvertVsyncPolairty>False</InvertVsyncPolairty>
+<InvertHsyncPolarity>False</InvertHsyncPolarity>
+<BorderColor>0x0</BorderColor>
+</Group>
+<Group id='Display Interface'>
+<InterfaceType>9</InterfaceType>
+<InterfaceColorFormat>3</InterfaceColorFormat>
+</Group>
+<Group id='DSI Interface'>
+<DSIChannelId>2</DSIChannelId>
+<DSIVirtualId>0</DSIVirtualId>
+<DSIColorFormat>36</DSIColorFormat>
+<DSITrafficMode>1</DSITrafficMode>
+<DSILanes>4</DSILanes>
+<DSIRefreshRate>0x3C0000</DSIRefreshRate>
+<DSICmdSwapInterface>False</DSICmdSwapInterface>
+<DSICmdUsingTrigger>False</DSICmdUsingTrigger>
+<DSIEnableAutoRefresh>True</DSIEnableAutoRefresh>
+<DSIAutoRefreshFrameNumDiv>1</DSIAutoRefreshFrameNumDiv>
+<DSIControllerMapping>00</DSIControllerMapping>
+<DSITECheckEnable>True</DSITECheckEnable>
+<DSITEUsingDedicatedTEPin>True</DSITEUsingDedicatedTEPin>
+<DSITimingCLKPrepareOverride>True</DSITimingCLKPrepareOverride>
+<DSITEvSyncStartPos>2248</DSITEvSyncStartPos>
+<DSITEvSyncInitVal>2248</DSITEvSyncInitVal>
+<DSITimingCLKPrepareValue>7</DSITimingCLKPrepareValue>
+<DSITimingHSPrepareOverride>True</DSITimingHSPrepareOverride>
+<DSITimingHSPrepareValue>7</DSITimingHSPrepareValue>
+<DSIEnterULPSPowerDown>True</DSIEnterULPSPowerDown>
+</Group>
+<DSIInitSequence>
+05 11 00
+39 2B 00 00 08 c7
+39 F0 5A 5A
+39 EF F0 31 00 33 31 14 35
+39 B0 01
+39 BB 03
+39 B0 4F
+39 CB 00
+39 B0 6B
+39 CB 00
+39 F7 03
+39 B0 05
+39 B1 10
+39 B0 02
+39 D5 02 17 54 14
+39 F0 A5 A5
+39 F0 5A 5A
+39 Fc 5A 5A
+39 D2 9F F0
+39 B0 0E
+39 d2 70
+39 b0 04
+39 d2 20
+39 F0 A5 A5
+39 Fc A5 a5
+39 35 00
+39 51 00 00
+39 53 20
+39 55 00
+05 29 00
+</DSIInitSequence>
+<Group id='Backlight Configuration'>
+<BacklightType>3</BacklightType>
+<BacklightSteps>1</BacklightSteps>
+<BrightnessMaxLuminance>430000</ BrightnessMaxLuminance>
+<BrightnessMinLuminance>323</BrightnessMinLuminance>
+<BrightnessRangeLevel0>100 400000 1 0</BrightnessRangeLevel0>
+</Group>"})
--- /dev/null
+//
+// This file contains the Panel configuration for secondary display
+//
+// Panel configuration format is similar to primary panel in panelcfg.asl
+//
+Name (PCFG, Buffer() {0x0} )
--- /dev/null
+//
+// This file contains the Panel configuration for external display
+//
+// Panel configuration format is similar to primary panel in panelcfg.asl
+//
+
+Name (PCFG, Buffer() {0x0} )
--- /dev/null
+//===========================================================================
+// <pep.asl>
+// DESCRIPTION
+// The PEP Device & Driver Related Configuration
+//
+//===========================================================================
+
+// Resources by area
+Include("../Common/pep_common.asl")
+Include("cust_camera_resources.asl")
+//Include("nfc_resources.asl") //NFC
+Include("cust_touch_resources.asl")
--- /dev/null
+//===========================================================================
+// <pep_defaults.asl>
+// DESCRIPTION
+// This file contains default resource information. These are applied at either
+// PEP boot time, on the ScreenOn event or on demand by the PEP driver.
+//
+//===========================================================================
+
+Scope(\_SB.PEP0)
+{
+ Method(LDRS){
+ return(NDRS)
+ }
+
+ Name( NDRS,
+ /**
+ * The default resources package is used by PEP to handle system default resources.
+ * Rather than having to declare them all in the SDF declaration, you define resources
+ * separately and annotate them by functionality. At runtime, the parsed resources
+ * will be placed into separate components within the SDF device node.
+ *
+ * The expected hiearchy of this package:
+ * DEFAULT_RESOURCES
+ * (WORKAROUND|OPTIMIZATION)
+ * String = Name
+ * For debugging and querying -- keep it short
+ * String = "BOOT", "SCREENON", "DEMAND"
+ * When to activate these resources
+ * RESOURCES
+ * The list of resources to activate for this set workaround / optimization
+ *
+ */
+
+ package(){
+ "DEFAULT_RESOURCES",
+
+ package()
+ {
+ "OPTIMIZATION",
+ "CPU_CNOC_VOTE",
+ "BOOT",
+
+ package()
+ {
+ "RESOURCES",
+
+ package() {"BUSARB", package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_CLK_CTL", 1, 1, "SUPPRESSIBLE" }},
+
+ package()
+ {
+ "PMICVREGVOTE", // PMIC VREG resource
+ package()
+ {
+ "PPP_RESOURCE_ID_BUCK_BOOST1_B",
+ 12, // Voltage Regulator type 12 = BOB
+ 0, // Voltage = 0V
+ 0, // SW Enable = Disable
+ 2, // BOB Mode = Auto
+ "HLOS_DRV", // Optional: DRV Id (HLOS_DRV / DISPLAY_DRV)
+ "SUPPRESSIBLE", // Optional: Set Type (REQUIRED / SUPPRESSIBLE)
+ }
+ },
+ // TZ requirement for HW DRM
+ Package(){"CLOCK", Package(){"gcc_disp_ahb_clk", 1}},// enable clock
+ Package(){"CLOCK", Package(){"gcc_disp_ahb_clk", 9,8}},// mark suppressible
+ Package(){"CLOCK", Package(){"gcc_disp_ahb_clk", 9,12}},// always ON
+ },
+ },
+ })
+}
--- /dev/null
+Scope(\_SB.PEP0)
+{
+ Method(CTSN)
+ {
+ return (THSD)
+ }
+
+ Method(PEPH)
+ {
+ Return(Package()
+ {
+ "ACPI\\VEN_QCOM&DEV_0237",
+ })
+ }
+
+ Method(BCLH)
+ {
+ Return(Package()
+ {
+ "ACPI\\VEN_QCOM&DEV_0294",
+ })
+ }
+
+ // Thermal sensors PL specific configurations
+ Name(THSD,
+
+ Package()
+ {
+ // Below package contains a list of all the identified physical thermal sensors mapped to unique HIDs
+ //
+ Package()
+ {
+ 21, //Total number of thermal physical sensors
+
+ // sensor HID, sensor number associated to HID
+ Package() {"ACPI\\VEN_QCOM&DEV_027F", 0},
+ Package() {"ACPI\\VEN_QCOM&DEV_0280", 1},
+ Package() {"ACPI\\VEN_QCOM&DEV_0281", 2},
+ Package() {"ACPI\\VEN_QCOM&DEV_0282", 3},
+ Package() {"ACPI\\VEN_QCOM&DEV_0283", 4},
+ Package() {"ACPI\\VEN_QCOM&DEV_0284", 5},
+ Package() {"ACPI\\VEN_QCOM&DEV_0285", 6},
+ Package() {"ACPI\\VEN_QCOM&DEV_0286", 7},
+ Package() {"ACPI\\VEN_QCOM&DEV_0287", 8},
+ Package() {"ACPI\\VEN_QCOM&DEV_0288", 9},
+ Package() {"ACPI\\VEN_QCOM&DEV_0289", 10},
+ Package() {"ACPI\\VEN_QCOM&DEV_02AB", 11},
+ Package() {"ACPI\\VEN_QCOM&DEV_02AC", 12},
+ Package() {"ACPI\\VEN_QCOM&DEV_02AD", 13},
+ package() {"ACPI\\VEN_QCOM&DEV_02AE", 14},
+ Package() {"ACPI\\VEN_QCOM&DEV_02AF", 15},
+ Package() {"ACPI\\VEN_QCOM&DEV_02C8", 16},
+ Package() {"ACPI\\VEN_QCOM&DEV_02C9", 17},
+ Package() {"ACPI\\VEN_QCOM&DEV_02CA", 18},
+ Package() {"ACPI\\VEN_QCOM&DEV_02CB", 19},
+ Package() {"ACPI\\VEN_QCOM&DEV_02CC", 20},
+ },
+
+ // TSENSLIST Package
+ // This package contains "lists" of thermal sensors
+ // each list maps to a virtual thermal sensor
+ // Always the first package should be BIG CPU, second one is LITTLE CPU and third one is ALL CPU SENSOR lists.
+ // Do not interchage inside packages. Always add new sensor list package at the end.
+
+ Package()
+ {
+ 3, //Number of virtual sensors.
+
+ Package() // sensors associated with Little CPU
+ {
+ "ACPI\\VEN_QCOM&DEV_02B0",
+ 21, // virtual sensor ID
+ 5, //Little cpu sensors
+ Package () {1, 2, 3, 4, 5},
+ },
+
+ Package() // sensors associated with Big CPU
+ {
+ "ACPI\\VEN_QCOM&DEV_02B1",
+ 22, // virtual sensor ID
+ 5, //Big cpu sensors
+ Package () {6, 7, 8, 9, 10}, // as per thermal floor plan
+ },
+
+ Package() // All MSM sensors
+ {
+ "ACPI\\VEN_QCOM&DEV_02B2",
+ 23, // virtual sensor ID
+ 21, //It should be total number of sensors.
+ Package () {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20},
+ },
+ },
+
+ // Sensor HID to Vadc thermistor mapping package
+ // INX and this needs to be in sync
+ // channel list/names need to obtained from tsens team
+ Package ()
+ {
+ 10, //Number of VADC channels
+
+ // channels name sensor HID, Sensor number ADC type
+ Package() {"SYS_THERM1", "ACPI\\VEN_QCOM&DEV_0299", 0, 0}, //vadc = 0, rradc = 1
+ Package() {"SYS_THERM2", "ACPI\\VEN_QCOM&DEV_029A", 1, 0 },
+ Package() {"PA_THERM", "ACPI\\VEN_QCOM&DEV_029B", 2, 0 },
+ Package() {"PA_THERM1", "ACPI\\VEN_QCOM&DEV_029C", 3, 0 },
+ Package() {"SYS_THERM3", "ACPI\\VEN_QCOM&DEV_029D", 4, 0 },
+ Package() {"PMIC_THERM", "ACPI\\VEN_QCOM&DEV_029E", 5, 0 },
+ Package() {"SKIN_THERM", "ACPI\\VEN_QCOM&DEV_029F", 6, 1 },
+ Package() {"PMIC_TEMP2", "ACPI\\VEN_QCOM&DEV_02A0", 7, 1 },
+ Package() {"CHG_TEMP", "ACPI\\VEN_QCOM&DEV_02EE", 8, 1 },
+ Package() {"BATT_THERM", "ACPI\\VEN_QCOM&DEV_02EF", 9, 1 },
+ },
+
+ // Thermal Restriction data package
+ // high/low trigger point for each thermal restriction
+ // ID has to match to one of below enum from PEP_Themal_common.h
+ //typedef enum _INT_RESTR_ID
+ //{
+ // FAST_THERMAL_MTG_RESTR_B_ID = 0x01, //Throttle just the big cluster to NOM
+ // LOW_TEMP_VOLTAGE_RESTR_ID = 0x02, //Vdd restriction at < 5C
+ // HIGH_TEMP_BOOST_RESTR_ID = 0x03, //Unused- Turn off Correlation
+ // NORMAL_TEMP_CL_RESTR_ID = 0x04, //8909 - Current Limiting - Disabled
+ // HIGH_TEMP_CL_RESTR_ID = 0x05, //8909 - Current Limiting - Disabled
+ // VERY_HIGH_TEMP_CL_RESTR_ID = 0x06, //8909 - Current Limiting - Disabled
+ // MAX_PERF_LIMITING_RESTR_ID = 0x7, //8994 - Num cores based perf limiting
+ // FAST_THERMAL_MTG_RESTR_L_ID = 0x8, //Throttle Little clusters to NOM
+ // INVALID_RESTR_ID = 0xffffffff,
+ //} INT_RESTR_ID, *PINT_RESTR_ID;
+ //
+
+ Package ()
+ {
+ 1, // number of Thermal Restrictions
+ Package ()
+ {
+ 2, // tsensList. 2 indicates third package in TSENSLIST Package. In this case its All CPU sensors list
+ 2780, // Restriction ON temperature. ACPI uses 10s of K as temperatures, so 0C = 2730 ACPI UNITS. 2730+50=2780.
+ 2830, // Restriction OFF temperature. 100 + 2730 = 2830.
+ 2, // 2 - LOW_TEMP_VOLTAGE_RESTR_ID, Vdd restriction at < 5C
+ 1, // Restriction enabled = 1, disabled = 0.
+ },
+ },
+
+ //QMI clients
+ Package ()
+ {
+ 4, // Number Of QMI Clients.
+ Package ()
+ {
+ "cpuv_restriction_cold", //mitigation device name
+ 1, //restriction ON = 1 and RESTRICTN OFF = 0
+ 0, //MODEM QMI INSTANCE ID = 0
+ },
+ Package ()
+ {
+ "cpuv_restriction_cold", //mitigation device name
+ 1, //restriction ON = 1 and RESTRICTN OFF = 0
+ 1, //ADSP QMI INSTANCE ID = 1
+ },
+ Package ()
+ {
+ "cpuv_restriction_cold", //mitigation device name
+ 1, //restriction ON = 1 and RESTRICTN OFF = 0
+ 0x43, //CDSP QMI INSTANCE ID = 0x43
+ },
+ Package ()
+ {
+ "cpuv_restriction_cold", //mitigation device name
+ 1, //restriction ON = 1 and RESTRICTN OFF = 0
+ 0x53, //SLPI QMI INSTANCE ID = 0x53
+ },
+ },
+
+ // PPP PMIC VREG clients: ACPI is being parsed in the order defined in PEP_Thermal_Common.h
+ // Client info will be parsed incorrectly, if this package is removed.
+ Package ()
+ {
+ 0,
+ },
+
+ // LTVR Package having 3 sub-packages:
+ // 1) Rail type from enum RAIL_TYPE in PEP_Thermal_Common.h
+ // 2) Voting type - available options are EnableKraitVFC(0), VoteViaPPP(1), VoteViaQMI(2), VoteViaAOP(3) and VoteViaCallBackObj(4)
+ // 3) Client subpackage number for Voting type clients package
+ // VoteViaAOP
+ // AOP does not require rail type to vote during LTVR.
+ // It just needs an event with value on or off and it places NOM vote on cx, mx & ebi.
+ // Only cx is added to get callback in LTVR.
+ // VoteViaCallBackObj
+ // LTVR callback notifies to all the registered clients. it is independent of rail type and voting type.
+ //
+
+ Package () // LTVR VFC vote table
+ {
+ 7, // Available Rails
+ Package() { 0, //KRAIT = 0,
+ 0, //EnableKraitVFC = 0
+ 0, // NULL
+ },
+ Package() { 1, //CX = 1,
+ 3, //VoteViaAOP = 3
+ 0, // NULL : Client data is not required;
+ },
+ Package() { 3, //MSS = 3,
+ 2, //VoteViaQMI = 2
+ 0, // 0 represents first package in QMI clients list
+ },
+ Package() { 4, //ADSP = 4,
+ 2, //VoteViaQMI = 2
+ 1, // 1 represents second package in QMI clients list
+ },
+ Package() { 6, //CDSP = 6,
+ 2, //VoteViaQMI = 2
+ 2, // 2 represents third package in QMI clients
+ },
+ Package() { 8, //SLPI = 8,
+ 2, //VoteViaQMI = 2
+ 3, // 3 represents forth package in QMI clients
+ },
+ Package() { 2, //GFX = 2, NOP because call backs will be notified for all the registered clients.
+ // No need for separate rail entry for each of the rails which are relying on call backs.
+ 4, //VoteViaCallBackObj = 4.
+ 0, // NOP.
+ },
+ }
+ }
+ )
+}
--- /dev/null
+Scope(\_SB.PILC)
+{
+ Method (_SUB) {
+ return(\_SB.PSUB)
+ }
+}
+
+Scope(\_SB.AMSS)
+{
+ Method (_SUB) {
+ return(\_SB.PSUB)
+ }
+}
+
+//Disabling SCSS
+Scope(\_SB.SCSS)
+{
+ Method(_STA, 0)
+ {
+ Return (Zero)
+ }
+}
+
+Scope(\_SB.CDSP)
+{
+ Method(_STA, 0)
+ {
+ Return (0x0F)
+ }
+}
+
+Scope(\_SB.ADSP)
+{
+ Method(_STA, 0)
+ {
+ Return (0x0F)
+ }
+}
--- /dev/null
+// This file contains the Power Management IC (PMIC)
+// ACPI device definitions, configuration and look-up tables.
+//
+
+Include("cust_pmic_batt.asl")
+
+ // PMIC EIC
+ //Device (PEIC)
+ //{
+ // Name (_HID, "QCOM02D3")
+ // Alias(\_SB.PSUB, _SUB)
+ // Method (_CRS, 0x0, NotSerialized) {
+ // Name (RBUF, ResourceTemplate () {
+ // // SMB1380
+ // I2CSerialBus( 0x08, , 400000,AddressingMode7Bit, "\\_SB.IC11",,,,)
+ // })
+ // Return (RBUF)
+ // }
+ // Method (PMCF) {
+ // Name (CFG0,
+ // Package(){
+ // //Charger Info
+ // 0, // I2c Index - Resource Index
+ // 2, // Charger IC Type - PLAT_CONFIG_CHG_IC_SMB1380
+ // })
+ // Return (CFG0)
+ // }
+ //
+ // Method (_STA) {
+ // Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager
+ // }
+ //}
+
+ //
+ // PMIC Battery Manger Driver
+ //
+ Device (PMBT) {
+ Name (_HID, "QCOM0264")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_DEP, Package(0x2) {
+ \_SB_.PMIC,
+ \_SB_.ADC1,
+ //\_SB_.PEIC
+ })
+
+ Method (_STA) {
+ Return (0xF) // Device is installable, functional & should not be visible in OSPM/Device Manager
+ }
+
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate ()
+ {
+ //GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,) {208} // 0x80 - PM_INT__SCHG_CHGR__CHGR_ERROR_RT_STS - Charger Error Interrupt
+ //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {336} // 0x210 - PM_INT__FG_BCL__IBT_HI - IBAT greater than threshold Interrupt.
+ //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {337} // 0x211 - PM_INT__FG_BCL__IBT_THI - VBatt less than threshold Interrupt
+ //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {352} // 0x220 - PM_INT__FG_MEM_IF__IMA_RDY - MEMIF access Interrupt
+ //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {215} // 0x87 - PM_INT__SCHG_CHGR__CHGR_7 - Termination Current Interrupt
+ //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {209} // 0x81 - PM_INT__SCHG_CHGR__CHARGING_STATE_CHANGE - Charger Inhibit Interrupt
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {329} // 0x209 - PM_INT__FG_BATT_INFO__VBT_LOW - VBAT_LOW Interrupt
+ //GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,) {240} // 0xA0 - PM_INT__SCHG_DC__DCIN_COLLAPSE - Qi Wireless Charger Interrupt
+ GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {331} // 0x20B - PM_INT__FG_BATT_INFO__BT_MISS - BATT_MISSING Interrupt
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {237} // 0x9D - PM_INT__SCHG_USB__USBIN_SOURCE_CHANGE - AICL_DONE IRQ (Rising Only)
+ //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {232} // 0x98 - PM_INT__SCHG_USB__USBIN_COLLAPSE - USB_UV IRQ (Rising Only)
+ //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {322} // 0x202 - PM_INT__FG_BATT_SOC__BSOC_DELTA - FULL_SOC Interrupt
+ //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {323} // 0x203 - PM_INT__FG_BATT_SOC__MSOC_DELTA - EMPTY_SOC Interrupt
+ // GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {213} // 0x85 - PM_INT__SCHG_CHGR__FG_FVCAL_QUALIFIED - FVCAL_QUALIFIED IRQ
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {224} // 0x90 - PM_INT__SCHG_BATIF__BAT_TEMP - Jeita limit interrupt
+
+ })
+ Return (RBUF)
+ }
+
+ //ACPI methods for Battery Manager Device
+ Method (BMNR) {
+ Name (CFG0,
+ Package(){
+ 1, //* 0: Select Platform: 0- No HW, 1- SMChg+FGGge, 2- SMB3pChg+SMB3pGge, 3- LBChg+VMBMS
+ 0, //* 1: Error State Handling: 0- Don�t Shutdown, 1- Shutdown
+ 1, //* 2: Listen to BatteryClass: 0- No 1- Yes
+ 0, //* 3: Test Mode Power Flag: 0- Discharging, 1- PowerOnline+Charging
+ "CUST_PMIC" //* 4: cust_pmic config identifier
+ })
+ Store(CUST, Index(CFG0, 4))
+ Return (CFG0)
+ }
+
+ //ACPI methods for Timer
+ Method (BTIM) {
+ Name (CFG0,
+ Package(){
+ 30000, // Charging Heartbeat Timer
+ 10000, // Charging Tolerable Delay
+ 300000, // Discharging Heartbeat Timer
+ 120000, // Discharging Tolerable Delay
+ 0, // Poll Timer , 0=Timer not used.
+ 0, // Poll Tolerable Delay
+ 28080000, //Charging Timeout (TDone) Timer
+ 0, //Charging Timeout(TDone) Tolerable Delay
+ })
+ Return (CFG0)
+ }
+
+
+ //ACPI methods for Battery Info
+ Method (BBAT) {
+ Name (CFG0,
+ Package(){
+ 1, //* 0: Battery Technology
+ 0x4C494F4E, //* 1: Battery Chemistry: hex(LION)
+ 0xFFFFFFFF, //* 2: BFCC: (mWh), Design Capacity
+ 0xFFFFFFFF, //* 3: BFCC: (mWh), Full Charge Capacity
+ 0xFFFFFFFF, //* 4: PCT1: (% of FCC), Default Alert 1
+ 0xFFFFFFFF, //* 5: PCT2: (% of FCC), Default Alert 2
+ "QCOMBATT01", //* 6: Device Name
+ "Qualcomm", //* 7: Manufacture Name
+ "QCOMBAT01_07012011", //* 8: Battery Unique ID
+ "07012011", //* 9: Battery Serial Number
+ 19, //* 10: Battery Manufacture Date
+ 04, //* 11: Battery Manufacture Month
+ 2014 //* 12: Battery Manufacture Year
+ })
+ //Local2 = Default Alert1 = PCT1 * BFCC / 100
+ Multiply(PCT1,BFCC,Local0)
+ Divide(Local0, 100, Local1, Local2)
+ //Local3 = Default Alert2 = PCT2 * BFCC / 100
+ Multiply(PCT2,BFCC,Local0)
+ Divide(Local0, 100, Local1, Local3)
+ Store(BFCC, Index(CFG0, 2))
+ Store(BFCC, Index(CFG0, 3))
+ Store(Local2, Index(CFG0, 4))
+ Store(Local3, Index(CFG0, 5))
+ Return (CFG0)
+ }
+
+ //ACPI methods for Proprietary chargers
+ Method (BPCH) {
+ Name (CFG0,
+ Package(){
+ 3000, // QC2.0 charger current = 3000mA
+ 3000, // QC3.0 charger current = 3000mA
+ 1500 // Invalid Wall charger current = 1500mA
+ })
+ Return (CFG0)
+ }
+
+ //ACPI methods for foldback chargers
+ Method (BFCH) {
+ Name (CFG0,
+ Package(){
+ 1, // Feature enable/disable
+ 5, // No of consecutive times charger attach/detach
+ 5000, // msecs, Time elapsed between attach/detach
+ 900, // mA, Current setting for foldback charger
+ })
+ Return (CFG0)
+ }
+
+ //ACPI methods for coin cell charger
+ Method (BCCC) {
+ Name (CFG0,
+ Package(){
+ 1, //Enable coin cell charger; 1 = enable, 0 = disable
+ 0, // RSET, 0=2K1, 1=1K7, 2=1K2, 3 = 0K8
+ 0 // VSET, 0=2V5, 1=3V2, 2=3V1, 3=3V0
+ })
+ Return (CFG0)
+ }
+
+ //ACPI methods for Recharge/Maintenance Mode
+ Method (BRCH) {
+ Name (CFG0,
+ Package(){
+ 100, // Delta V Recharge threshold = 100mV
+ 0 // Delta V Recharge Reduction below Normal= 0mV
+ })
+ Return (CFG0)
+ }
+
+ //ACPI methods for Qi Charging
+ Method (_BQI) {
+ Name (CFG0,
+ Package(){
+ 0,
+ })
+ Return (CFG0)
+ }
+
+ //ACPI methods for Interrupt Name
+ Method (BIRQ) {
+ Name (CFG0,
+ Package(){
+ //"ChgError", //Charger Error
+ //"BclIrq1", //IBAT greater than threshold IRQ
+ //"BclIrq2", // VBAT less than threshold IRQ
+ //"MEMIFaccess", //MEMIF access granted IRQ
+ //"TccReached", // Termination Current IRQ
+ // "ChargerInhibit" // Charger Inhibit IRQ
+ "VbatLow", // VBAT LOW IRQ
+ //"QiWlcDet", // Qi charging
+ "BattMissing", // BATT_MISSING IRQ
+ "AiclDone", // AICL Done
+ // "UsbUv", //USB UV
+ //"SOCFull", //SOC Full IRQ
+ //"SOCEmpty", //SOC Empty IRQ
+ //"FvCal", //FVCAl IRQ
+ "JeitaLimit" //JEITA limit IRQ
+ })
+ Return (CFG0)
+ }
+ //ACPI methods for Platform File
+ Method (BPLT) {
+ Name (CFG0,
+ Package(){
+ 1024, //* 0: ACPI Version
+ 0xFFFFFFFF, //* 1: VNOM: (mV), Nominal Battery Voltage
+ 0xFFFFFFFF, //* 2: VLOW: (mV), Low Battery Voltage
+ 0xFFFFFFFF, //* 3: EMPT: (mV), VcutOff
+ 0xFFFFFFFF, //* 4: DCMA: (mA), DC Current
+ 1, //* 5: ChargePath Priority: Select 0 for DC, 1 for USB
+ 50, //* 6: RSLOW for maxFlashCurrentPrediction
+ 50, //* 7: RPARA for maxFlashCurrentPrediction
+ 5000, //* 8: VINFLASH for maxFlashCurrentPrediction
+ 8, //* 9: FlashParam for maxFlashCurrentPrediction
+ 1, //* 10: AFP Mode Supported
+ 80, //* 11: AFP Trigger Max Battery Temp (+80 deg C)
+ 0xFFFFFFEC, //* 12: AFP Trigger Min Battery Temp (-20 deg C)
+ 72, //* 13: Watchdog timer in secs
+ 100, //* 14: Charger iterm 100 mA for now
+ 30, //* 15: SRAM logging timer
+ 5, //* 16: VBATT average Window Size
+ 6, //* 17: Emergency Shutdown Initial SOC
+ 500, //* 18: SoC convergent point
+ 126, //* 19: LM_Threshold
+ 400, //* 20: MH_Threshold
+ 0xFFFFFFFF, //* 21: BOCP: (mA), OCP current used in BCL
+ 750, //* 22: soc (75%) below which no soc linearization even in CV charging
+ 1, //* 23: BMD - Battery Missing Detection Source when source is attached: BATT_ID (1=BATT_ID, 4=HW Misssing Algorithm)
+ 2, //* 24: ibat src sensing : 0 for batfet and 1 for external sensing
+ 50, //* 25: IFGD: (mA), FG Iterm delta; (iterm + this value) determines when FG report 100%
+ 10, //* 26: VFGD: (mV), CC to CV Vdelta; (Vfloat - this value) determine when FG report 100%
+ 1, //* 27: 0 - disable SOC linearization; 1 (nonzero): enable SOC linearization
+ 0xFFFFFFEC, //* 28: (Celcius), Temperature threshold do have different SOC slope limiter
+ 10, //* 29: (milli%) - SOC slope limiter when charging and at lower temperature than threshold
+ 10, //* 30: (milli%) - SOC slope limiter when charging and at higher temperature than threshold
+ 10, //* 31: (milli%) - SOC slope limiter when discharging and at lower temperature than threshold
+ 10, //* 32: (milli%) - SOC slope limiter when discharging and at higher temperature than threshold
+ 1, //* 33: 0 - disable FCC learning; 1 (nonzero): enable FCC leearning
+ 150, //* 34: maximum starting SOC (in tenth percent)at which FCC learning would be turned on during charging
+ 100, //* 35: maximum allowable decrement (in tenth percent) of battery capacity in FCC learning
+ 5, //* 36: maximum allowable increment (in tenth percent) of battery capacity in FCC learning
+ 10, //* 37: battery temperature in degree C below which switch to low temp ESR update steps
+ 0x02, //* 38: ESR update step tight, (2 * 0.001953 = 0.0039 = 0.4% max change each update)
+ 0x33, //* 39: ESR update step broad, (51* 0.001953 = 0.099603 = 10% max change each update)
+ 0x02, //* 40: ESR update step tight at low temp (below 10 degree, 0.4% max change each update)
+ 0x0A, //* 41: ESR update step broad at low temp (below 10 degree, 2% max change each update)
+ 0, //* 42: mOhm, RConn
+ 0, //* 43: Type C Thermal Mitigation Enable
+ 70, //* 44: Temperature to arm mitigation (degree C)
+ 50, //* 45: ICL adjustment (percent)
+ 60 //* 46: Temperature to disarm mitigation (degree C)
+ })
+ Store(VNOM, Index(CFG0, 1))
+ Store(VLOW, Index(CFG0, 2))
+ Store(EMPT, Index(CFG0, 3))
+ Store(DCMA, Index(CFG0, 4))
+ Store(BOCP, Index(CFG0, 21))
+ Store(IFGD, Index(CFG0, 25))
+ Store(VFGD, Index(CFG0, 26))
+ Return (CFG0)
+ }
+
+ //ACPI methods for Platform File
+ Method (BPTM) {
+ Name (CFG0,
+ Package(){
+ 15000, // Emergency Timer
+ 0, // Emergency Tolerable Delay
+ })
+ Return (CFG0)
+ }
+
+ //*****************************************************
+ // Battery Charge Table 1 (BCT1)
+ // Notes: used in Method(BJTA) & Method (BAT1)
+ //*****************************************************
+ Name (BCT1, Package(){
+ 4350, //* 0: VDD1: (mV), Float Voltage (FV)
+ 2100, //* 1: FCC1: (mA), Full Charge Current (FCC)
+ 0, //* 2: HCLI: (C) hard cold limit - at which temperature charging will be disabled
+ 10, //* 3: SCLI: (C) soft cold limit - at which temperature charge current/float voltage will be reduced to JEITA compensated value
+ 45, //* 4: SHLI: (C) soft hot limit - at which temperature float voltage/charge current will be reduced to JEITA compensated value
+ 55, //* 5: HHLI: (C) hard hot limit - at which temperature charging will be disabled
+ 105, //* 6: FVC1: (mV) Float Voltage compensation (amount of FV reduction) when in battery hot-soft limit
+ 0, //* 7: (mV) Float Voltage compensation (amount of FV reduction) when in battery cold-soft limit
+ //* notes: put 0 value to disable
+ //* These values (10 vs 11) should be the same when HW JEITA is enabled
+ 0, //* 8: (mA) Charge Current compensation (amount of CC reduction) when in battery hot-soft limit
+ 1000, //* 9: CCC1: (mA) Charge Current compensation (amount of CC reduction) when in battery cold-soft limit
+ //* notes: put 0 value to disable
+ //* These values (12 vs 13) should be the same when HW JEITA is enabled
+ })
+
+ //ACPI methods for JEITA
+ Method (BJTA) {
+ Name (CFG0,
+ Package(){
+ 2, //* 0: Select JEITA Configuration: 0- No JEITA, 1- SW JEITA, 2- HW JEITA
+ 2, //* 1: Temperature Hysteresis (in deg C)
+ Package(0xa){0,0,0,0,0,0,0,0,0,0}
+ //* 2: Structure for default charge table
+ })
+ Store(VDD1, Index(\_SB_.PMBT.BCT1, 0))
+ Store(FCC1, Index(\_SB_.PMBT.BCT1, 1))
+ Store(HCLI, Index(\_SB_.PMBT.BCT1, 2))
+ Store(SCLI, Index(\_SB_.PMBT.BCT1, 3))
+ Store(SHLI, Index(\_SB_.PMBT.BCT1, 4))
+ Store(HHLI, Index(\_SB_.PMBT.BCT1, 5))
+ Store(FVC1, Index(\_SB_.PMBT.BCT1, 6))
+ Store(CCC1, Index(\_SB_.PMBT.BCT1, 9))
+
+ //Use BCT1 as the Default Charge Table
+ Store(\_SB_.PMBT.BCT1, Index(CFG0, 2))
+ Return (CFG0)
+ }
+
+ //ACPI methods for Battery-1 (Ascent 860-82209-0000 3450mAh)
+ Method (BAT1)
+ {
+ Name (CFG0,
+ Package(){
+ 0, //* 0: Battery Category: 0-NORMAL, 1-SMART
+ 0xFFFFFFEC, //* 1: min operating battery temp (-20 deg C)
+ 65, //* 2: max operating battery temp (+65 deg C)
+ Package(4){0,0,0,0}, //* 3: 128-bit battery info for future expansion
+ Package(0xa){0,0,0,0,0,0,0,0,0,0}
+ //* 4: Structure for charge table
+ })
+
+ //assign Charge Table to BCT1
+ //Notes: 1) If the default charge table and desire charge table are different,
+ // Create another table (ex: BCT2) with the same structure as BCT1 and modify BCT1 below with the new table name
+ // 2) Method(BJTA) is parsed before this(BAT1) method in Battmngr module
+ // Method(BJTA) may be updating BCT1 parameters using configuration from cust_pmic_batt.asl (refer to BJTA method details)
+ // If BAT1 desires different value to be used (than what used in BJTA), pls change/update relevant parameter(s) here.
+ Store(\_SB_.PMBT.BCT1, Index(CFG0, 4))
+
+ Return (CFG0)
+ }
+
+ //ACPI methods for Battery Error Handling
+ Method (BEHC)
+ {
+ //Actions for Battery Error Handling
+ // 0x0 - Do Nothing
+ // 0x1 - Reload Charge Table
+ // 0x2 - Error Shutdown
+ // 0x4 - Emergency Shutdown
+ // 0x8 - Enter Test Mode
+ Name (CFG0,
+ Package(){
+ 1, //1-Feature Enable, 0-Feature Disable
+ 0x8, //Action(s) for DEBUG state -> Enter Test Mode
+ 0x1, //Action(s) for NORMAL state -> Reload Charge Table
+ 0x0, //Action(s) for SMART_AUTHENTICATED state -> Do nothing
+ 0x0, //Action(s) for UNKNOWN state -> Do nothing
+ 0x2, //Action(s) for NOT_PRESENT state -> Error Shutdown
+ 0x2, //Action(s) for INVALID state -> Error Shutdown
+ 0x4 //Action(s) for OUT_OP_RANGE state -> AFP for out of operational range
+ })
+ Return (CFG0)
+ }
+
+ //ACPI methods for Charge Table Management Configuration
+ Method (CTMC)
+ {
+ Name (CFG0,
+ Package(){
+ 2000, //* 0: min RID for DEBUG category: 2K
+ 14000, //* 1: max RID for DEBUG category: 14K
+ 0xFFFFFFFF, //* 2: RID2: min RID for NORMAL category: 15K
+ 0xFFFFFFFF, //* 3: RID3: max RID for NORMAL category: 140K
+ 240000, //* 4: min RID for SMART category: 240K
+ 450000, //* 5: max RID for SMART category: 450K
+ 1, //* 6: Number of charging table
+ })
+ Store(RID2, Index(CFG0, 2))
+ Store(RID3, Index(CFG0, 3))
+ Return (CFG0)
+ }
+
+ //ACPI methods for Parallel Charging
+ Method (BMPC) {
+ Name (CFG0,
+ Package(){
+ 0, //* 0: Feaature Enable. 1: Enabled, 0: Disable
+ 1, //* 1: Input Power Disctribution (HW) configuration: 0: MID-MID, 1: USBIN-USBIN
+ 7000, //* 2: (mW) Input Power Threshold to decide if parallel charging to be enabled or not
+ //* Note: Not applicable for MID-MID configuration
+ 1000, //* 3: (mA) Charge Current Threshold to decide if parallel charging to be enabled or not
+ 50, //* 4: (%) Slave Charger Initial Power Distribution
+ 60, //* 5: (mV) Slave Charger Float Voltage Headroom
+ 500, //* 6: (mA) Slave Charger Charge Current Done Threshold
+ 90, //* 7: Slave Charger Minimum Efficiency
+ 0, //* 8: Slave Charger HW ID. 0: SMB1380/1
+ 70, //* 9: (%)Slave Charger Max Power Distribution: 70%
+ 0, //* 10: (%)Slave Charger Min Power Distribution: 0%
+ Package(0x4)//* 11: Thermal Balancing Configuration
+ {
+ 5, //11.1: (C)Temperature Difference to trigger thermal balancing. 0 to disable the feature
+ 5, //11.2: (%)Step to redistrubute the power
+ 120, //11.3: (Sec)Minimum Wait Time for each redistribution attempt
+ 5, //11.4: (C)Temperature Margin for Master Charger
+ }
+ })
+ Return (CFG0)
+ }
+ }
+
+ //
+ // PMIC Battery Miniclass Driver
+ //
+ Device (PMBM) {
+ Name (_HID, "QCOM0263")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.PMBT
+ })
+
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ })
+ Return (RBUF)
+ }
+
+ Method (_STA) {
+ Return (0xF) // Device is installable, functional & should not be visible in OSPM/Device Manager
+ }
+ }
+
+//
+//FGBCL Driver
+//
+Device (BCL1) {
+ Name (_HID, "QCOM02D6")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.PMIC
+ })
+
+ Method (_STA) {
+ Return (0xF) // Device is installable, functional & should not be visible in OSPM/Device Manager
+ }
+
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {64} // 0x1E8 - PM_INT__BCL_COMP__VCOMP_LOW0 - VCOMP_LOW0 IRQ
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {65} // 0x1E9 - PM_INT__BCL_COMP__VCOMP_LOW1 - VCOMP_LOW1 IRQ
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {66} // 0x1EA - PM_INT__BCL_COMP__VCOMP_LOW2 - VCOMP_LOW2 IRQ
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {67} // 0x1EB - PM_INT__BCL_COMP__VCOMP_HI - VCOMP_HI IRQ
+ //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {68} // 0x1EC - PM_INT__BCL_COMP__SYS_OK - SYS_OK IRQ
+ //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {72} // 0x1F0 - PM_INT__BCL_PLM__VCOMP_LVL0_PLM - LVL0_PLM IRQ
+ //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {74} // 0x1F2 -PM_INT__BCL_PLM__VCOMP_LVL2_PLM - LVL2_PLM IRQ
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {75} // 0x1F3 - PM_INT__BCL_PLM__VCOMP_BA - BAN alarm IRQ
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {336} // 0x210 - PM_INT__FG_BCL__IBT_HI - ibatt high IRQ
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {337} // 0x211 - PM_INT__FG_BCL__IBT_THI - ibatt too high IRQ
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {339} // 0x213 - PM_INT__FG_BCL__VBT_LO_CMP - vbatt low irq
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {340} // 0x214 - PM_INT__FG_BCL__VBT_TLO_CMP - vbatt too low irq
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {324} // 0x204 - PM_INT__FG_BATT_SOC__MSOC_LOW - MSOC_Low Interrupt
+ GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {326} // 0x206 - PM_INT__FG_BATT_SOC__MSOC_HIGH - MSOC_HI Interrupt
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {344} // 0x218 - PM_INT__FG_LMH__LMH_LVL0 - LMH_LVL0 IRQ
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {345} // 0x219 - PM_INT__FG_LMH__LMH_LVL1 - LMH_LVL1 IRQ
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {346} // 0x21A - PM_INT__FG_LMH__LMH_LVL2 - LMH_LVL2 IRQ
+
+ })
+ Return (RBUF)
+ }
+ //ACPI methods for FGBCL device
+ Method (BCLS) {
+ Name (CFG0,
+ Package(){
+ 3, //* FGBCL ACPI revision
+ 7, //* 0: BCL disabled, 1: vph_pwr bcl enabled, 2: fg vbatt enabled, 4: fg ibatt enabled
+ 5000, //* battery ocp current
+ 80, //* ibatt high threshold is set to 80 for 80% of OCP
+ 90, //* ibatt too high is set to 90 for 90% of OCP
+ 2800, //* vbatt low is set to 2800 mV
+ 2600, //* vbatt too low is set to 2600 mV
+ 3200, //* vcomp_low0 threshold is 3200 mv
+ 2750, //* vcomp_low1 threshold is 2750 mv
+ 2500, //* vcomp_low2 threshold is 2500 mV
+ 10, //* poll timer for battery soc polling.
+ 1, //* 1- enable battery percent notification. 0-disable battery percent notification
+ 2000, //* debug board Min battery ID in Ohm
+ 14000 //* debug board Max battery ID in Ohm
+ })
+ Return (CFG0)
+ }
+ //ACPI methods for Interrupt Name
+ Method (BCLQ) {
+ Name (CFG0,
+ Package(){
+ "VCOMP_LOW0", //vcomp_low0 IRQ
+ "VCOMP_LOW1", //vcomp_low1 IRQ
+ "VCOMP_LOW2", //vcomp_low2 IRQ
+ "VCOMP_HI", //vcomp_hi IRQ
+ //"SYS_OK", // sys_ok irq
+ //"LVL0_PLM", // LVL0_PLM IRQ
+ //"LVL1_PLM" // LVL1_PLM IRQ
+ //"LVL2_PLM", //LVL2_PLM IRQ
+ "BAN_ALARM", // BAN_ALARM IRQ
+ "IBATT_HI", // IBATT HIGH IRQ
+ "IBATT_THI", // IBATT TOO HIGH IRQ
+ "VBATT_LOW", // VBATT_LOW IRQ
+ "VBATT_TLOW", // VBATT TOO LOW IRQ
+ "MSOC_LOW", //monotonic soc low IRQ
+ "MSOC_HI", //monotonic soc high IRQ
+ "LMH_LVL0", //LMH_LVL0 IRQ
+ "LMH_LVL1", //LMH_LVL1 IRQ
+ "LMH_LVL2", //LMH_LVL2 IRQ
+ })
+ Return (CFG0)
+ }
+}
+
+//
+//PMIC Type-C Controler Driver (PMICTCC) Driver
+//
+Device(PTCC)
+{
+ Name (_HID, "QCOM02E6")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_DEP, Package(0x1) {\_SB_.PMIC})
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {239} // 0x9F - PM_INT__SCHG_USB__TYPE_C_OR_RID_DETECTION_CHANGE - CC State Changed IRQ
+ GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {270} // 0xBE - PM_INT__USB_PD__MESSAGE_RX_DISCARDED - Message RX Discarded IRQ
+ GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {269} // 0xBD - PM_INT__USB_PD__MESSAGE_TX_DISCARDED - Message TX Discarded IRQ
+ GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {268} // 0xBC - PM_INT__USB_PD__MESSAGE_TX_FAILED - Message TX Failed IRQ
+ GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {267} // 0xBB - PM_INT__USB_PD__MESSAGE_RECEIVED - Message Received IRQ
+ GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {266} // 0xBA - PM_INT__USB_PD__MESSAGE_SENT - Message Sent IRQ
+ GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {265} // 0xB9 - PM_INT__USB_PD__SIGNAL_RECEIVED - Singal Received IRQ
+ GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {264} // 0xB8 - PM_INT__USB_PD__SIGNAL_SENT - Signal Sent IRQ
+ GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {217} // 0x89 - PM_INT__SCHG_OTG__OTG_OVERCURRENT - OTG_OC_IRQ
+ GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {263} // 0xB7 - PM_INT__SCHG_MISC__SWITCHER_POWER_OK - SWITCHER_POWER_OK (CHG_MISC)
+ GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {235} // 0x9B - PM_INT__SCHG_USB__USBIN_OV - USBIN_OV (CHG_USB)
+ // GpioIo (Exclusive, PullUp, 0, 0, , "\\_SB.PM01", , , , ) {493} // 0x668 - PM_INT__PM2_GPIO14__GPIO_IN_STS - GPIO14B � For Type-C Debug Accessory Mode
+ })
+ Return (RBUF)
+ }
+}
--- /dev/null
+//
+// TLMM controller.
+//
+Device (GIO0)
+{
+ Name (_HID, "QCOM0217")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 0)
+
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // TLMM register address space
+ Memory32Fixed (ReadWrite, 0x03400000, 0x00C00000)
+
+ // Summary Interrupt shared by all banks
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240}
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240}
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240}
+ Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {648} // For PDC Wake up ::TLMM GPIo 126 SD Card Detection
+ Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {568} // For PDC Wake up ::TLMM GPIo 54
+ Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {646} // For PDC Wake up ::TLMM GPIo 124, Hall sensor used for lid
+ })
+ Return (RBUF)
+ }
+ // ACPI method to return Num pins
+ Method(OFNI, 0x0, NotSerialized) {
+ Name(RBUF, Buffer()
+ {
+ 0x96, // 0: TOTAL_GPIO_PINS
+ 0x00 // 1: TOTAL_GPIO_PINS
+ })
+ Return (RBUF)
+ }
+
+ Name(GABL, Zero)
+ Method(_REG, 0x2, NotSerialized)
+ {
+ If(LEqual(Arg0, 0x8))
+ {
+ Store(Arg1, GABL)
+ }
+ }
+}
--- /dev/null
+\r
+ // SPI1 - EPM\r
+ //\r
+ Device (SPI1)\r
+ {\r
+ Name (_HID, "QCOM021E")\r
+ Alias(\_SB.PSUB, _SUB)\r
+ Name (_UID, 1)\r
+ Name (_DEP, Package(){\_SB_.PEP0, \_SB_.BAM3})\r
+ Name (_CCA, 0)\r
+\r
+ Method (_CRS)\r
+ {\r
+ Name (RBUF, ResourceTemplate()\r
+ {\r
+\r
+ Memory32Fixed(ReadWrite, 0xf9923000, 0x00000800)\r
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {127}\r
+ })\r
+ Return (RBUF)\r
+ }\r
+ Method (FNOC)\r
+ {\r
+ Name(RBUF, Buffer()\r
+ {\r
+ 0x01, // Controller Number\r
+ 0x00, // BamBaseAddress\r
+ 0x40, // BamBaseAddress\r
+ 0x90, // BamBaseAddress\r
+ 0xf9, // BamBaseAddress\r
+ 0x0d, // Input Pipe\r
+ 0x0c, // Output Pipe\r
+ 0x00, // Threshold\r
+ 0x01 // Threshold\r
+ })\r
+ Return (RBUF)\r
+ }\r
+ }\r
--- /dev/null
+Name(QUFN, 0x0 ) //enable flag for QcUsbFN driver stack
+
+//Holds the DPDM Polarity
+//USB_DPDM_INVALID_INVALID = 0
+//USB_DPDM_INVALID_FALLING = 1
+//USB_DPDM_INVALID_RISING = 2
+//USB_DPDM_FALLING_INVALID = 3
+//USB_DPDM_RISING_INVALID = 4
+//USB_DPDM_FALLING_FALLING = 5
+//USB_DPDM_FALLING_RISING = 6
+//USB_DPDM_RISING_FALLING = 7
+//USB_DPDM_RISING_RISING = 8
+Name(DPP0, Buffer(){0x0})
+
+//
+// USB Role Switch
+//
+Device(URS0)
+{
+ //select HID based on flag for QcUsbFN driver stack
+ Method (URSI) {
+ If(Lequal(\_SB.QUFN, 0x0)) {
+ return("QCOM0304")
+ }
+ Else{
+ return ("QCOM0305")
+ }
+ }
+
+ Alias(URSI, _HID)
+
+ Name(_CID, "PNP0CA1")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 0)
+ Name(_CCA, Zero) // Cache-incoherent bus-master, Hardware does not manage cache coherency
+ Name(_DEP, Package(0x1)
+ {
+ \_SB_.PEP0
+ })
+
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x0A600000, 0x000FFFFF)
+ })
+
+ // Dynamically enumerated device (host mode stack) on logical USB bus
+ Device(USB0)
+ {
+ Name(_ADR, 0)
+ Name(_S0W, 3) // Enable power management for SDM850 BU
+
+ // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to
+ // derive a unique "Connector ID". The other fields are not really important.
+ Name(_PLD, Package()
+ {
+ Buffer()
+ {
+ 0x82, // Revision 2, ignore color.
+ 0x00,0x00,0x00, // Color (ignored).
+ 0x00,0x00,0x00,0x00, // Width and height.
+ 0x69, // User visible; Back panel; VerticalPos:Center.
+ 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0.
+ 0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1.
+ 0x00,0x00,0x00,0x00, // Not ejectable.
+ 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied.
+ }
+ })
+ // _UPC as defined in the ACPI spec.
+ Name(_UPC, Package()
+ {
+ 0x01, // Port is connectable.
+ 0x09, // Connector type: Type C connector - USB2 and SS with switch.
+ 0x00000000, // Reserved0 - must be zero.
+ 0x00000000 // Reserved1 - must be zero.
+ })
+ Name(_CRS, ResourceTemplate() {
+ // usb30_ctrl_irq[0]
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xA5}
+ // Qusb2Phy_intr
+ Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x17A}
+ // qmp_usb3_lfps_rxterm_irq
+ Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x206}
+ // eud_p0_dmse_int_mx - Rising Edge
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x208}
+ // eud_p0_dpse_int_mx - Rising Edge
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x209}
+ })
+
+ Method(_STA)
+ {
+ Return (0xf)
+ }
+
+ //Method to set DPDM Polarity for Pep Driver
+ Method(DPM0, 0x1, NotSerialized) {
+ // ARG 0 � DPDM polarity
+ Store(Arg0, \_SB.DPP0) //DPDM Polarity
+ Notify(\_SB.PEP0, 0xA0)
+ }
+
+ // Returns CC Out
+ Method(CCVL) {
+ // Return CC OUT
+ Return(\_SB.CCST)
+ }
+ //Returns High Speed Enumeration Flag
+ Method(HSEN) {
+ // Return High Speed Enumeration Flag
+ Return(\_SB.HSFL)
+ }
+
+ /* HS enumeration fix
+ //HSEI: High Speed pullup gpio
+ Name (HSEI, ResourceTemplate ()
+ {
+ GpioIo (Exclusive,PullNone,0,0, ,"\\_SB.GIO0", ,) {8}
+ })
+
+ //define 1 byte long operation region HLEN w/ base address == 0 under GPIO0 devnode namespace
+ Scope(\_SB.GIO0) {
+ OperationRegion(HLEN, GeneralPurposeIO, 0, 1) // Note: Region is less than 8 pins long
+ }
+
+ //now connect HLEN field in op region w/ HSEI resource
+ Field(\_SB.GIO0.HLEN, ByteAcc, NoLock, Preserve)
+ {
+ //Connect field to HSEI physical object
+ Connection (\_SB.URS0.USB0.HSEI), // Following fields will be accessed atomically
+ MOD1, 1 //MOD1 - variable name, 1 == 1bit wide
+ }
+ */
+
+ // Device Specific Method takes 4 args:
+ // Arg0 : Buffer containing a UUID [16 bytes]
+ // Arg1 : Integer containing the Revision ID
+ // Arg2 : Integer containing the Function Index
+ // Arg3 : Empty Package (Not used)
+ Method (_DSM, 0x4, NotSerialized)
+ {
+ // UUID selector
+ switch(ToBuffer(Arg0)) {
+ // UFX interface identifier
+ case(ToUUID("CE2EE385-00E6-48CB-9F05-2EDB927C4899")) {
+ // Function selector
+ switch(ToInteger(Arg2)) {
+ // Function 0: Return supported functions, based on revision
+ case(0) {
+ // Version selector
+ switch(ToInteger(Arg1)) {
+ // Revision0: functions {0,2,3,4} supported
+ case(0) { Return(Buffer(){0x1D}); Break; }
+ // Function 0 only supported for invalid revision
+ default { Return(Buffer(){0x01}); Break; }
+ }
+ // default
+ Return (Buffer(){0x00}); Break;
+ }
+
+ // Function 2: Port type identification
+ // 0x00 � Regular USB
+ // 0x01 � HSIC
+ // 0x02 � SSIC
+ // 0x03 � 0xff reserved
+ case(2) { Return(0x0); Break; }
+
+ // Function 3: Query Controller Capabilities
+ // bit 0 represents the support for software assisted USB endpoint offloading feature
+ // 1 - Offloading endpoint supported
+ case(3) { Return(0x1); Break; }
+
+ // Function 4: Interrupter Number
+ case(4) { Return(0x2); Break; }
+
+ default { Return (Buffer(){0x00}); Break; }
+ } // Function
+ } // {CE2EE385-00E6-48CB-9F05-2EDB927C4899}
+ default { Return (Buffer(){0x00}); Break; }
+ } // UUID
+ } // _DSM
+ //
+ // The following values of PHY will be configured if OEMs do not
+ // overwrite the values.
+ //
+ // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY.
+ // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing
+ // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis.
+ //
+ // AccessMethod:
+ // 0 - DirectAccess: The register address is accessed directly from the mapped memory.
+ //
+ Method(PHYC, 0x0, NotSerialized) {
+ Name (CFG0, Package()
+ {
+ // AccessMethod, REG ADDR, Value
+ // -------------------------------
+ //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR
+ //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing
+ //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis
+ })
+ Return (CFG0)
+ }
+
+ /*
+ Device(RHUB)
+ {
+ Name(_ADR, 0) // Value zero reserved for Root Hub
+
+ // Device Specific Method takes 4 args:
+ // Arg0 : Buffer containing a UUID [16 bytes]
+ // Arg1 : Integer containing the Revision ID
+ // Arg2 : Integer containing the Function Index
+ // Arg3 : Empty Package (Not used)
+ Method (_DSM, 0x4, NotSerialized)
+ {
+ // UUID selector
+ switch(ToBuffer(Arg0)) {
+ // HS enumeration fix
+ case(ToUUID("A9A82A56-95A1-4B4A-B014-3BE47DF1B7D5"))
+ {
+ // Version selector
+ switch(ToInteger(Arg1))
+ {
+ case(1) //DSM_SDM845_HS_RH_PORT_RESET_REVISION_1
+ {
+ switch(ToInteger(Arg2)) //DSM_SDM845_HS_RH_PORT_RESET_FUNCTION_
+ {
+ //DSM_SDM845_HS_RH_PORT_RESET_FUNCTION_PRE_RESET_ON - set GPIO high
+ case(1)
+ {
+ Store (0x01, \_SB.URS0.USB0.MOD1)
+ Return (Buffer(){0x01}) //return success
+ }
+ //DSM_SDM845_HS_RH_PORT_RESET_FUNCTION_POST_RESET_OFF - set GPIO low
+ case(0)
+ {
+ Store (0x00, \_SB.URS0.USB0.MOD1)
+ Return (Buffer(){0x01}) //return success
+ }
+
+ default { Return (Buffer(){0x00})}
+ }
+ }
+ default { Return (Buffer(){0x00}) }
+ }
+ }//end (A9A82A56-95A1-4B4A-B014-3BE47DF1B7D5)
+
+ default { Return (Buffer(){0x00}); Break; }
+ } // UUID
+ } // _DSM
+ } // Root Hub
+ */
+
+ } // USB0
+
+ // Dynamically enumerated device (peripheral mode stack) on logical USB bus
+ Device(UFN0)
+ {
+ Name(_ADR, 1)
+ Name(_S0W, 3) // Enable power management for Napali BU
+ // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to
+ // derive a unique "Connector ID". The other fields are not really important.
+ Name(_PLD, Package()
+ {
+ Buffer()
+ {
+ 0x82, // Revision 2, ignore color.
+ 0x00,0x00,0x00, // Color (ignored).
+ 0x00,0x00,0x00,0x00, // Width and height.
+ 0x69, // User visible; Back panel; VerticalPos:Center.
+ 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0.
+ 0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1.
+ 0x00,0x00,0x00,0x00, // Not ejectable.
+ 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied.
+ }
+ })
+ // _UPC as defined in the ACPI spec.
+ Name(_UPC, Package()
+ {
+ 0x01, // Port is connectable.
+ 0x09, // Connector type: Type C connector - USB2 and SS with switch.
+ 0x00000000, // Reserved0 - must be zero.
+ 0x00000000 // Reserved1 - must be zero.
+ })
+ Name(_CRS, ResourceTemplate() {
+ // usb30_ctrl_irq[0]
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xA5}
+ //usb30_power_event_irq
+ Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0xA2}
+ })
+
+ // Returns CC Out
+ Method(CCVL) {
+ // Return CC OUT
+ Return(\_SB.CCST)
+ }
+
+ // Device Specific Method takes 4 args:
+ // Arg0 : Buffer containing a UUID [16 bytes]
+ // Arg1 : Integer containing the Revision ID
+ // Arg2 : Integer containing the Function Index
+ // Arg3 : Package that contains function-specific arguments
+ Method (_DSM, 0x4, NotSerialized)
+ {
+ // UUID selector
+ switch(ToBuffer(Arg0)) {
+ // UFX interface identifier
+ case(ToUUID("FE56CFEB-49D5-4378-A8A2-2978DBE54AD2")) {
+ // Function selector
+ switch(ToInteger(Arg2)) {
+ // Function 0: Return supported functions, based on revision
+ case(0) {
+ // Version selector
+ switch(ToInteger(Arg1)) {
+ // Revision0: functions {1} supported
+ case(0) { Return(Buffer(){0x03}); Break; }
+ default { Return(Buffer(){0x01}); Break; }
+ }
+ // default
+ Return (Buffer(){0x00}); Break;
+ }
+
+ // Function 1: Return number of supported USB PHYSICAL endpoints
+ // Synopsys core configured to support 16 IN/16 OUT EPs, including EP0
+ case(1) { Return(32); Break; }
+
+ default { Return (Buffer(){0x00}); Break; }
+ } // Function
+ } // {FE56CFEB-49D5-4378-A8A2-2978DBE54AD2}
+
+ // QCOM specific interface identifier
+ case(ToUUID("18DE299F-9476-4FC9-B43B-8AEB713ED751")) {
+ // Function selector
+ switch(ToInteger(Arg2)) {
+ // Function 0: Return supported functions, based on revision
+ case(0) {
+ // Version selector
+ switch(ToInteger(Arg1)) {
+ // Revision0: functions {1} supported
+ case(0) { Return(Buffer(){0x03}); Break; }
+ default { Return(Buffer(){0x01}); Break; }
+ }
+ // default
+ Return (Buffer(){0x00}); Break;
+ }
+
+ // Function 1: Return device capabilities bitmap
+ // Bit Description
+ // --- -------------------------------
+ // 0 Superspeed Gen1 supported
+ // 1 PMIC VBUS detection supported
+ // 2 USB PHY interrupt supported
+ // 3 Type-C supported
+ // 4 Delay USB initialization
+ // 5 HW based charger detection
+ case(1) { Return(0x39); Break; }
+
+ default { Return (Buffer(){0x00}); Break; }
+ } // Function
+ } // {18DE299F-9476-4FC9-B43B-8AEB713ED751}
+
+ default { Return (Buffer(){0x00}); Break; }
+ } // UUID
+ } // _DSM
+
+ //
+ // The following values of PHY will be configured if OEMs do not
+ // overwrite the values.
+ //
+ // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY.
+ // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing
+ // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis.
+ //
+ // AccessMethod:
+ // 0 - DirectAccess: The register address is accessed directly from the mapped memory.
+ //
+ Method(PHYC, 0x0, NotSerialized) {
+ Name (CFG0, Package()
+ {
+ // AccessMethod, REG ADDR, Value
+ // -------------------------------
+ //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR
+ //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing
+ //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis
+ })
+ Return (CFG0)
+ }
+ } // UFN0
+} // URS0
+
+// HPD Notification Event in Display Driver
+// HPD_STATUS_LOW_NOTIFY_EVENT - 0x92
+// HPD_STATUS_HIGH_NOTIFY_EVENT - 0x93
+// All other valus are invalid
+Name(HPDB, 0x00000000)
+
+// DP Pin Assignment
+// TYPEC_DISPLAYPORT_PINASSIGNMENTINVALID = 0x0
+// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTA = 0x01
+// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTB = 0x02
+// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTC = 0x03
+// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTD = 0x04
+// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTE = 0x05
+// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTF = 0x06
+// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTA = 0x07
+// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTB = 0x08
+// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTC = 0x09
+// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTD = 0x0A
+// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTE = 0x0B
+Name(PINA, 0x00000000)
+
+// Holds the CC OUT Status
+// 0 -> CC1
+// 1 -> CC2
+// 2 -> CC Open
+Name(CCST, Buffer(){0x02})
+
+// Holds the HS Only enumeration Flag for display alternate mode
+// 0 -> Super Speed Controller Enumeration support
+// 1 -> High Speed Controller Enumeration support
+// 2 -> Invalid
+Name(HSFL, Buffer(){0x00})
+
+// USB Capabilities bitmap
+// Indicates the platform's USB capabilities, extend as required.
+// Bit Description
+// --- ---------------------------------------------------
+// 0 Super Speed Gen1 supported (Synopsys IP)
+// 1 PMIC VBUS detection supported
+// 2 USB PHY interrupt supported (seperate from ULPI)
+// 3 TypeC supported
+Name(USBC, Buffer(){0x0B})
+
+
+//
+// USB Type-C/PD Switch
+//
+Device(UCP0)
+{
+ Name(_HID, "QCOM02D0") // QCOM24D3
+ Name(_DEP, Package(0x3)
+ {
+ \_SB_.PEP0,
+ \_SB_.PTCC,
+ \_SB_.URS0
+ })
+
+ Device(CON0)
+ {
+ // These devices are not meant to be enumerated by ACPI, hence you should not assign
+ // HWIDs to them. Instead, use _ADR to assign unique addresses to them.
+ // The addresses are required to be a 0-based index of the connector. First connector
+ // should have "0", second one "1", etc.
+ Name(_ADR, 0x00000000)
+ // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to
+ // derive a unique "Connector ID". The other fields are not really important.
+ Name(_PLD, Package()
+ {
+ Buffer()
+ {
+ 0x82, // Revision 2, ignore color.
+ 0x00,0x00,0x00, // Color (ignored).
+ 0x00,0x00,0x00,0x00, // Width and height.
+ 0x69, // User visible; Back panel; VerticalPos:Center.
+ 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0.
+ 0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1.
+ 0x00,0x00,0x00,0x00, // Not ejectable.
+ 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied.
+ }
+ })
+ // _UPC as defined in the ACPI spec.
+ Name(_UPC, Package()
+ {
+ 0x01, // Port is connectable.
+ 0x09, // Connector type: Type C connector - USB2 and SS with switch.
+ 0x00000000, // Reserved0 - must be zero.
+ 0x00000000 // Reserved1 - must be zero.
+ })
+ Name(_DSD, Package()
+ {
+ // The UUID for Type-C connector capabilities.
+ ToUUID("6b856e62-40f4-4688-bd46-5e888a2260de"),
+ // The data structure which contains the connector capabilities. Each package
+ // element contains two elements: the capability type ID, and the capability data
+ // (which depends on the capability type). Note that any information defined here
+ // will override similar information described by the driver itself. For example, if
+ // the driver claims the port controller is DRP-capable, but ACPI says it is UFP-only
+ // ACPI will take precedence.
+ Package()
+ {
+ Package() {1, 4}, // Supported operating modes (DRP).
+ Package() {2, 3}, // Supported Type-C sourcing capabilities (DefaultUSB & 1500mA).
+ Package() {3, 0}, // Audio accessory capable (False).
+ Package() {4, 1}, // Is PD supported (True).
+ Package() {5, 3}, // Supported power roles (Sink and Source).
+ Package()
+ {
+ 6, // Capability type ID of PD Source Capabilities.
+ Package()
+ {
+ 0x00019096 // Source PDO #0: Fixed:5V, 1.5A. No need to describe fixed bits.
+ }
+ },
+ Package()
+ {
+ 7, // Capability type ID of PD Sink Capabilities.
+ Package ()
+ {
+ 0x0001912C, // Sink PDO #0: Fixed:5V, 3.0A. No need to describe fixed bits.
+ 0x0002D0C8, // Sink PDO #1: Fixed:9V, 2.0A. No need to describe fixed bits.
+ 0x0003C096, // Sink PDO #2: Fixed:12V, 1.5A. No need to describe fixed bits.
+ }
+ },
+ Package()
+ {
+ 8, // Capability type ID of supported PD Alternate Modes.
+ Package()
+ {
+ 0xFF01, 0x3C86 // DFP_D capable (B0:1); DFP v1.3 signalling (B2:5); DP on Type-C plug (B6);
+ // usb r2.0 signalling not required (B7); Pin Assignment Supported - C,D,E,F (B8:15)
+ }
+ },
+ Package()
+ {
+ 9, // Add Delay in loading of host stack
+ 1
+ },
+ Package() // Hardware CC debounce is supported
+ {
+ 0xA,
+ 1
+ }
+ }
+ })
+ } // Device(CON0)
+
+ // Device Specific Method takes 4 args:
+ // Arg0 : Buffer containing a UUID [16 bytes]
+ // Arg1 : Integer containing the Revision ID
+ // Arg2 : Integer containing the Function Index
+ // Arg3 : Package that contains function-specific arguments
+ Method (_DSM, 0x4, NotSerialized)
+ {
+ // UUID selector
+ switch(ToBuffer(Arg0)) {
+ // QCOM specific interface identifier
+ case(ToUUID("18DE299F-9476-4FC9-B43B-8AEB713ED751")) {
+ // Function selector
+ switch(ToInteger(Arg2)) {
+ // Function 0: Return supported functions, based on revision
+ case(0) {
+ // Version selector
+ switch(ToInteger(Arg1)) {
+ // Revision0: functions {0,1} supported
+ case(0) { Return(Buffer(){0x01}); Break; } // TypeC support only, No PD
+ default { Return(Buffer(){0x01}); Break; }
+ }
+ // default
+ Return (Buffer(){0x00}); Break;
+ }
+
+ // Function1: Return Capabilities Data Objects
+ case(1) {
+ switch(ToInteger(Arg3)) {
+ // Source Power PDO
+ case (0) { Return(Package(){0x36019050}); Break; }
+ // Sink Power PDO
+ case (1) { Return(Package(){0x3601912C}); Break; }
+ //default
+ default { Return (Package(){0x00}); Break; }
+ }
+ }
+ default { Return (Buffer(){0x00}); Break; }
+ } // Function
+ } // {18DE299F-9476-4FC9-B43B-8AEB713ED751}
+
+ default { Return (Buffer(){0x00}); Break; }
+ } // UUID
+ } // _DSM
+ // Method for updating the CC Out status and HS Mode Flag
+ // Arg 0 - CC Out value (CC1/CC2/CC Open)
+ // Arg 1 - HS Mode Flag (SS/HS/Invalid)
+ Method(CCOT, 0x2, NotSerialized) {
+ // ARG 0 - CC_OUT
+ Store(Arg0, \_SB.CCST)
+ Store(Arg1, \_SB.HSFL)
+ }
+ // Method for reading CC Out Value from Type-C client driver
+ // Only for sanity testing
+ Method(CCVL) {
+ // Return CC OUT
+ Return(\_SB.CCST)
+ }
+
+ Method(HPDS, 0x0, NotSerialized) {
+ // Notify event ID - 0x92 to GFX driver on a hot plug-in event
+ Notify(\_SB.GPU0, 0x94)
+ }
+
+ Method(HPDF, 0x2, NotSerialized) {
+ // ARG 0 - HPD Status
+ Store(Arg0, \_SB.HPDB)
+ // Arg 1 - Pin Assignment
+ Store(Arg1, \_SB.PINA)
+ // Invoke Display Driver HPD event
+ Notify(\_SB.GPU0, \_SB.HPDB)
+ }
+
+ // Method for reading CC Out Value from Type-C client driver
+ // Only for sanity testing
+ Method(HPDV) {
+ // Return HPD
+ Return(\_SB.HPDB)
+ }
+ // Method for reading HPD and Pin Assignment values from Type-C client driver
+ // Only for sanity testing
+ Method(PINV) {
+ // Return Pin Assignment
+ Return(\_SB.PINA)
+ }
+
+} // UCP0
+
+//Dummy device to allow KDNET on 2ndary port debugger registration
+// Device (USB1)
+// {
+// Name (_DEP, Package(0x1)
+// {
+// \_SB_.PEP0
+// })
+// Name (_HID, "QCOM02BA") // QCOM02BA
+// Name (_UID, 1)
+
+// //set device status as not present, disabled, not shown in UI, not functioning properly
+// Name(STVL, 0x0)
+
+// Method (_STA) {
+// Return (STVL) // return the current device status
+// }
+// } // USB1
+
+
+//
+// USB Type-C Audio Driver
+//
+// Device (USBA)
+// {
+// Name (_DEP, Package(0x1)
+// {
+// \_SB_.IMM0
+// })
+// Name (_HID, "QCOM0300")
+// Alias(\_SB.PSUB, _SUB)
+// }
+
+
+//URS1 specific
+/*
+
+//Holds the DPDM Polarity
+//USB_DPDM_INVALID_INVALID = 0
+//USB_DPDM_INVALID_FALLING = 1
+//USB_DPDM_INVALID_RISING = 2
+//USB_DPDM_FALLING_INVALID = 3
+//USB_DPDM_RISING_INVALID = 4
+//USB_DPDM_FALLING_FALLING = 5
+//USB_DPDM_FALLING_RISING = 6
+//USB_DPDM_RISING_FALLING = 7
+//USB_DPDM_RISING_RISING = 8
+Name(DPP1, Buffer(){0x0})
+
+//USB Role Switch For Secondary Port
+Device(URS1)
+{
+ Name(_HID, "QCOM0304")
+ Name(_CID, "PNP0CA1")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 1)
+ Name(_CCA, Zero) // Cache-incoherent bus-master, Hardware does not manage cache coherency
+ Name(_DEP, Package(0x1)
+ {
+ \_SB_.PEP0
+ })
+
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x0A800000, 0x000FFFFF)
+ //USBID pin Interrupt [USB_ID]
+ GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {488}
+ })
+
+ // Dynamically enumerated device (host mode stack) on logical USB bus
+ Device(USB1)
+ {
+ Name(_ADR, 0)
+ Name(_S0W, 3) // Enable power management
+ // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to
+ // derive a unique "Connector ID". The other fields are not really important.
+ Name(_PLD, Package()
+ {
+ Buffer()
+ {
+ 0x82, // Revision 2, ignore color.
+ 0x00,0x00,0x00, // Color (ignored).
+ 0x00,0x00,0x00,0x00, // Width and height.
+ 0x69, // User visible; Back panel; VerticalPos:Center.
+ 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0.
+ 0x80,0x01, // Group Token:0; Group Position:1; So Connector ID is 1.
+ 0x00,0x00,0x00,0x00, // Not ejectable.
+ 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied.
+ }
+ })
+ // _UPC as defined in the ACPI spec.
+ Name(_UPC, Package()
+ {
+ 0x01, // Port is connectable.
+ 0x06, // Connector type: uAB
+ 0x00000000, // Reserved0 - must be zero.
+ 0x00000000 // Reserved1 - must be zero.
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ //usb30_sec_ctrl_irq[0]
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xAA}
+ })
+ Store(RBUF, Local0)
+
+ ConcatenateResTemplate(Local0, ResourceTemplate()
+ {
+ //Qusb2Phy_sec_intr
+ Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x17B}
+ // qmp_usb3_lfps_rxterm_irq
+ Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x207}
+ // eud_p1_dmse_int_mx - Rising Edge
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x20A}
+ // eud_p1_dpse_int_mx - Rising Edge
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x20B}
+ }, Local1)
+
+ Return(Local1)
+ }
+
+ Method(_STA)
+ {
+ Return (0xf)
+ }
+
+ //Method to set DPDM Polarity for Pep Driver
+ Method(DPM1, 0x1, NotSerialized) {
+ // ARG 0 � DPDM polarity
+ Store(Arg0, \_SB.DPP1) //DPDM Polarity
+ Notify(\_SB.PEP0, 0xA1)
+ }
+
+ // Device Specific Method takes 4 args:
+ // Arg0 : Buffer containing a UUID [16 bytes]
+ // Arg1 : Integer containing the Revision ID
+ // Arg2 : Integer containing the Function Index
+ // Arg3 : Empty Package (Not used)
+ Method (_DSM, 0x4, NotSerialized)
+ {
+ // UUID selector
+ switch(ToBuffer(Arg0)) {
+ // UFX interface identifier
+ case(ToUUID("CE2EE385-00E6-48CB-9F05-2EDB927C4899")) {
+ // Function selector
+ switch(ToInteger(Arg2)) {
+ // Function 0: Return supported functions, based on revision
+ case(0) {
+ // Version selector
+ switch(ToInteger(Arg1)) {
+ // Revision0: functions {0,2,3} supported
+ case(0) { Return(Buffer(){0x0D}); Break; }
+ // Function 0 only supported for invalid revision
+ default { Return(Buffer(){0x01}); Break; }
+ }
+ // default
+ Return (Buffer(){0x00}); Break;
+ }
+
+ // Function 2: Port type identification
+ // 0x00 � Regular USB
+ // 0x01 � HSIC
+ // 0x02 � SSIC
+ // 0x03 � 0xff reserved
+ case(2) { Return(0x0); Break; }
+
+ // Function 3: Query Controller Capabilities
+ // bit 0 represents the support for software assisted USB endpoint offloading feature
+ // 1 - Offloading endpoint supported
+ case(3) { Return(0x1); Break; }
+
+ default { Return (Buffer(){0x00}); Break; }
+ } // Function
+ } // {CE2EE385-00E6-48CB-9F05-2EDB927C4899}
+ default { Return (Buffer(){0x00}); Break; }
+ } // UUID
+ } // _DSM
+ //
+ // The following values of PHY will be configured if OEMs do not
+ // overwrite the values.
+ //
+ // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY.
+ // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing
+ // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis.
+ //
+ // AccessMethod:
+ // 0 - DirectAccess: The register address is accessed directly from the mapped memory.
+ //
+ Method(PHYC, 0x0, NotSerialized) {
+ Name (CFG0, Package()
+ {
+ // AccessMethod, REG ADDR, Value
+ // -------------------------------
+ //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR
+ //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing
+ //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis
+ })
+ Return (CFG0)
+ }
+ } // USB1
+
+ // Dynamically enumerated device (peripheral mode stack) on logical USB bus
+ Device(UFN1)
+ {
+ Name(_ADR, 1)
+ Name(_S0W, 3) // Enable power management
+ // _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to
+ // derive a unique "Connector ID". The other fields are not really important.
+ Name(_PLD, Package()
+ {
+ Buffer()
+ {
+ 0x82, // Revision 2, ignore color.
+ 0x00,0x00,0x00, // Color (ignored).
+ 0x00,0x00,0x00,0x00, // Width and height.
+ 0x69, // User visible; Back panel; VerticalPos:Center.
+ 0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0.
+ 0x80,0x01, // Group Token:0; Group Position:1; So Connector ID is 1.
+ 0x00,0x00,0x00,0x00, // Not ejectable.
+ 0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied.
+ }
+ })
+ // _UPC as defined in the ACPI spec.
+ Name(_UPC, Package()
+ {
+ 0x01, // Port is connectable.
+ 0x09, // Connector type: Type C connector - USB2 and SS with switch.
+ 0x00000000, // Reserved0 - must be zero.
+ 0x00000000 // Reserved1 - must be zero.
+ })
+ Name(_CRS, ResourceTemplate() {
+ // usb30_sec_ctrl_irq[0]
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xAA}
+ //usb30_sec_power_event_irq
+ Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0xA7}
+ //Attach,Detach Interrupt [USB2_VUSB_DET]
+ GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0, "\\_SB.PM01",,,,RawDataBuffer() {0x00, 0x00, 0x00, 0x00}) {487}
+ })
+
+ // Device Specific Method takes 4 args:
+ // Arg0 : Buffer containing a UUID [16 bytes]
+ // Arg1 : Integer containing the Revision ID
+ // Arg2 : Integer containing the Function Index
+ // Arg3 : Package that contains function-specific arguments
+ Method (_DSM, 0x4, NotSerialized)
+ {
+ // UUID selector
+ switch(ToBuffer(Arg0)) {
+ // UFX interface identifier
+ case(ToUUID("FE56CFEB-49D5-4378-A8A2-2978DBE54AD2")) {
+ // Function selector
+ switch(ToInteger(Arg2)) {
+ // Function 0: Return supported functions, based on revision
+ case(0) {
+ // Version selector
+ switch(ToInteger(Arg1)) {
+ // Revision0: functions {1} supported
+ case(0) { Return(Buffer(){0x03}); Break; }
+ default { Return(Buffer(){0x01}); Break; }
+ }
+ // default
+ Return (Buffer(){0x00}); Break;
+ }
+
+ // Function 1: Return number of supported USB PHYSICAL endpoints
+ // Synopsys core configured to support 16 IN/16 OUT EPs, including EP0
+ case(1) { Return(32); Break; }
+
+ default { Return (Buffer(){0x00}); Break; }
+ } // Function
+ } // {FE56CFEB-49D5-4378-A8A2-2978DBE54AD2}
+
+ // QCOM specific interface identifier
+ case(ToUUID("18DE299F-9476-4FC9-B43B-8AEB713ED751")) {
+ // Function selector
+ switch(ToInteger(Arg2)) {
+ // Function 0: Return supported functions, based on revision
+ case(0) {
+ // Version selector
+ switch(ToInteger(Arg1)) {
+ // Revision0: functions {1} supported
+ case(0) { Return(Buffer(){0x03}); Break; }
+ default { Return(Buffer(){0x01}); Break; }
+ }
+ // default
+ Return (Buffer(){0x00}); Break;
+ }
+
+ // Function 1: Return device capabilities bitmap
+ // Bit Description
+ // --- -------------------------------
+ // 0 Superspeed Gen1 supported
+ // 1 PMIC VBUS detection supported
+ // 2 USB PHY interrupt supported
+ // 3 Type-C supported
+ // 4 Delay USB initialization
+ // 5 HW based charger detection
+ case(1) { Return(0x33); Break; }
+
+ default { Return (Buffer(){0x00}); Break; }
+ } // Function
+ } // {18DE299F-9476-4FC9-B43B-8AEB713ED751}
+
+ default { Return (Buffer(){0x00}); Break; }
+ } // UUID
+ } // _DSM
+
+ //
+ // The following values of PHY will be configured if OEMs do not
+ // overwrite the values.
+ //
+ // For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY.
+ // For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing
+ // and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis.
+ //
+ // AccessMethod:
+ // 0 - DirectAccess: The register address is accessed directly from the mapped memory.
+ //
+ Method(PHYC, 0x0, NotSerialized) {
+ Name (CFG0, Package()
+ {
+ // AccessMethod, REG ADDR, Value
+ // -------------------------------
+ //Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR
+ //Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing
+ //Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis
+ })
+ Return (CFG0)
+ }
+ } // UFN1
+} // URS1
+*/
--- /dev/null
+//
+// iHelium WLAN
+//
+Device (QWLN)
+{
+ Name(_ADR, 0)
+ Name(_DEP, Package(2)
+ {
+ \_SB.PEP0,
+ \_SB.MMU0
+ })
+ Name(_PRW, Package() {0,0}) // wakeable from S0
+ Name(_S0W, 2) // S0 should put device in D2 for wake
+ Name(_S4W, 2) // all other Sx (just in case) should also wake from D2
+ Name(_PRR, Package(0x1) { \_SB.AMSS.QWLN.WRST }) // Power resource reference for device reset and recovery.
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // Shared memory
+ Memory32Fixed (ReadWrite, 0x18800000, 0x800000) //CE registers
+ Memory32Fixed (ReadWrite, 0xC250000, 0x10) //WCSSAON registers
+ Memory32Fixed (ReadWrite, 0x8E300000, 0x100000) //MSA image address
+ // CE interrupts
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {446} //CE0 interrupt
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {447} //CE1 interrupt
+ Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {448} //CE2 interrupt
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {449} //CE3 interrupt
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {450} //CE4 interrupt
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {451} //CE5 interrupt
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {452} //CE6 interrupt
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {453} //CE7 interrupt
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {454} //CE8 interrupt
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {455} //CE9 interrupt
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {456} //CE10 interrupt
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {457} //CE11 interrupt
+ })
+ Return (RBUF)
+ }
+
+ // wlan msa memory size
+ Method (WMSA)
+ {
+ Return(Package ()
+ {
+ 0x100000
+ })
+ }
+
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ }
+
+ Method (_PS2, 0, NotSerialized) // _PS2: Power State 2
+ {
+ }
+
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ }
+
+ OperationRegion (WOPR, 0x80, Zero, 0x10)
+ Field (WOPR, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ WTRG, 32
+ }
+
+ PowerResource(WRST, 0x5, 0x0)
+ {
+ //
+ // Dummy _ON, _OFF, and _STA methods. All power resources must have these
+ // three defined.
+ //
+ Method(_ON, 0x0, NotSerialized)
+ {
+ }
+ Method(_OFF, 0x0, NotSerialized)
+ {
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ Return(0xf)
+ }
+ Method(_RST, 0x0, NotSerialized)
+ {
+ WTRG = 0xABCD
+ }
+ }
+}
+
+//agent driver of wlan for supporting windows thermal framework
+Scope(\_SB)
+{
+ Device (COEX)
+ {
+ Name (_HID, "QCOM0295")
+ Alias(\_SB.PSUB, _SUB)
+ }
+}
--- /dev/null
+//WLAN_11ad driver ACPI Enumeration
+
+Method(_STA, 0)
+{
+ Return (0xF)
+}
é¡¹ç® / edk2-sdm845-acpi.git / commitdiff