--- /dev/null
+//
+// Copyright (c) 2015, Mmoclauq Technologies Inc. All rights reserved.
+//
+// This file contains ASL Bridge Device definitions
+//
+
+//
+// ASL Bridge Device
+//
+Device (ABD)
+{
+ Name (_DEP, Package (One) // _DEP: Dependencies
+ {
+ \_SB.PEP0
+ })
+ Name (_HID, "QCOM0242") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ OperationRegion (ROP1, GenericSerialBus, Zero, 0x0100)
+ Name (AVBL, Zero)
+ Method (_REG, 2, NotSerialized) // _REG: Region Availability
+ {
+ If ((Arg0 == 0x09))
+ {
+ AVBL = Arg1
+ }
+ }
+}
--- /dev/null
+//
+// Copyright (c) 2015, Mmoclauq Technologies, Inc. All rights reserved.
+//
+
+//
+// ADSP RPC Driver
+//
+Device (ARPC)
+{
+ Name (_DEP, Package (0x03) // _DEP: Dependencies
+ {
+ \_SB.MMU0,
+ \_SB.GLNK,
+ \_SB.SCM0
+ })
+ Name (_HID, "QCOM0297") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+}
+// ARPD AUDIO Daemon Driver
+Device (ARPD)
+{
+ Name (_DEP, Package (0x02) // _DEP: Dependencies
+ {
+ \_SB.ADSP,
+ \_SB.ARPC
+ })
+ Name (_HID, "QCOM02F3") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+}
+
--- /dev/null
+//--------------------------------------------------------------------------------------------------
+// Copyright (c) 2019 Mmoclauq Technologies, Inc.
+// All Rights Reserved.
+// Confidential and Proprietary - Mmoclauq Technologies, Inc.
+//--------------------------------------------------------------------------------------------------
+
+
+Include("Qdss.asl")
+Include("qcsp.asl")
+Include("qcdb.asl")
+Include("data_att.asl")
+Include("win_mproc_att.asl")
+Include("cust_hwn_att.asl")
+
+
+
+
+
--- /dev/null
+///
+// BLCP Method
+// Backlight control packet method, returns a
+// command buffer for a specific backlight level
+//
+// Input Parameters
+// Backlight level - Integer from 0 to 0xFFFF where 0xFFFF is the highest level - must be converted to the required range (e.g. 0 - 255) in the method
+// Brightness level - absolute brightness in millinits
+//
+// Output Parameters
+//
+// Packet format:
+// +--32bits--+-----variable (8bit alignment)--+
+// | Header | Packet payload |
+// +----------+--------------------------------+
+//
+// For DSI Command packets, payload data must be in this format
+//
+// +-- 8 bits-+----variable (8bit alignment)----+
+// | Cmd Type | Packet Data |
+// +----------+---------------------------------+
+//
+// For I2C Command packets, payload data must be in this format
+//
+// +-- 16 bits-+----variable (8bit alignment)----+
+// | Address | Command Data |
+// +-----------+---------------------------------+
+//
+// All packets must follow with a DWORD header with 0x0
+//
+Method (BLCP, 2, NotSerialized) {
+
+ // Create Response buffer
+ Name(RBUF, Buffer(0x100){})
+
+ // Details to be populated by OEM based on the platform requirements
+
+ // Return the packet data
+ Return(RBUF)
+}
+
+
+///
+// BLCP Method (legacy method for 100 levels)
+// Backlight control packet method, returns a
+// command buffer for a specific backlight level
+//
+// Input Parameters
+// Backlight level - Integer from 0% to 100%
+//
+// Output Parameters
+//
+// Packet format:
+// +--32bits--+-----variable (8bit alignment)--+
+// | Header | Packet payload |
+// +----------+--------------------------------+
+//
+// For DSI Command packets, payload data must be in this format
+//
+// +-- 8 bits-+----variable (8bit alignment)----+
+// | Cmd Type | Packet Data |
+// +----------+---------------------------------+
+//
+// For I2C Command packets, payload data must be in this format
+//
+// +-- 16 bits-+----variable (8bit alignment)----+
+// | Address | Command Data |
+// +-----------+---------------------------------+
+//
+// All packets must follow with a DWORD header with 0x0
+//
+
--- /dev/null
+//
+// Copyright (c) 2013-2017, Mmoclauq Technologies Inc. All rights reserved.
+//
+// This file contains the Bus Access Modules (BAM)
+// ACPI device definitions and pipe configurations
+//
+
+//
+// Device Map:
+// 0x2401 - BAM
+//
+// List of Devices
+// BAM1 - CRYPTO1
+// BAM5 - SLIMBUS1
+// BAM6 - SLIMBUS
+// BAM7 - TSIF
+// BAMD - USB3.0 secondary
+// BAME - QDSS
+// BAMF - USB3.0 primary
+Device (BAM1)
+{
+ Name (_HID, "QCOM0213") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_UID, One) // _UID: Unique ID
+ Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x01DC4000, // Address Base
+ 0x00024000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000130,
+ }
+ })
+ Return (RBUF) /* \_SB_.BAM1._CRS.RBUF */
+ }
+}
+
+Device (BAM5)
+{
+ Name (_HID, "QCOM0213") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x17184000, // Address Base
+ 0x00032000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000000C4,
+ }
+ })
+ Return (RBUF) /* \_SB_.BAM5._CRS.RBUF */
+ }
+}
+
+Device (BAM6)
+{
+ Name (_HID, "QCOM0213") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x17204000, // Address Base
+ 0x00026000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000144,
+ }
+ })
+ Return (RBUF) /* \_SB_.BAM6._CRS.RBUF */
+ }
+}
+
+Device (BAM7)
+{
+ Name (_HID, "QCOM0213") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x08884000, // Address Base
+ 0x00023000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000009A,
+ }
+ })
+ Return (RBUF) /* \_SB_.BAM7._CRS.RBUF */
+ }
+}
+
+Device (BAMD)
+{
+ Name (_HID, "QCOM0213") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_UID, 0x0D) // _UID: Unique ID
+ Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A904000, // Address Base
+ 0x00017000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000000A9,
+ }
+ })
+ Return (RBUF) /* \_SB_.BAMD._CRS.RBUF */
+ }
+}
+
+Device (BAME)
+{
+ Name (_HID, "QCOM0213") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_UID, 0x0E) // _UID: Unique ID
+ Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x06064000, // Address Base
+ 0x00015000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000000C7,
+ }
+ })
+ Return (RBUF) /* \_SB_.BAME._CRS.RBUF */
+ }
+}
+
+Device (BAMF)
+{
+ Name (_HID, "QCOM0213") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_UID, 0x0F) // _UID: Unique ID
+ Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A704000, // Address Base
+ 0x00017000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000000A4,
+ }
+ })
+ Return (RBUF) /* \_SB_.BAMF._CRS.RBUF */
+ }
+}
+
--- /dev/null
+//
+// Copyright (c) 2017, Mmoclauq Technologies, Inc. All rights reserved.
+//
+
+//
+// Core-BSP MPROC Drivers (IPC Router & GLINK)
+//
+
+//
+// IPC Router
+//
+Device (IPC0)
+{
+ Name (_DEP, Package(0x1)
+ {
+ \_SB.GLNK
+ })
+ Name (_HID, "QCOM021C")
+ Alias(\_SB.PSUB, _SUB)
+}
+
+//
+// GLINK
+//
+// Order of incoming and outgoing interrupts depend on the number of interrupts mentioned in INTR method
+Device (GLNK)
+{
+ Name (_DEP, Package(0x1)
+ {
+ \_SB.RPEN
+ })
+ Name (_HID, "QCOM02F9")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 0)
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001E3,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000000BE,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000000CC,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000260,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001E1,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000000BC,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000000CA,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000025E,
+ }
+ })
+ Return (RBUF) /* \_SB_.GLNK._CRS.RBUF */
+ }
+}
--- /dev/null
+//===========================================================================
+// <corebsp_resources.asl>
+// DESCRIPTION
+// This file contans the resources needed by core BSP drivers.
+//
+//
+// Copyright (c) 2010-2011, 2014 by Mmoclauq Technologies Inc. All Rights Reserved.
+// Mmoclauq Confidential and Proprietary
+//
+//===========================================================================
+
+
+Scope(\_SB_.PEP0)
+{
+
+}
--- /dev/null
+//
+// Copyright (c) 2015 Mmoclauq Technologies Inc. All rights reserved.
+// Mmoclauq Technologies Proprietary and Confidential.
+//
\ No newline at end of file
--- /dev/null
+//--------------------------------------------------------------------------------------------------
+// Copyright (c) 2016 Mmoclauq Technologies, Inc.
+// All Rights Reserved.
+// Confidential and Proprietary - Mmoclauq Technologies, Inc.
+//--------------------------------------------------------------------------------------------------
+
+//customizable resource for wlan/bt/fm
+// PEP resources for iHelium
+// END iHelium
+
+// PEP resources for Bluetooth SOC
+// END BTH0
+
+// PEP resources for FM SOC
+// END FM
--- /dev/null
+//
+// Copyright (c) 2017 Mmoclauq Technologies, Inc. All Rights Reserved.
+// Mmoclauq Technologies Proprietary and Confidential.
+//
+// ===================================================================
+// EDIT HISTORY
+//
+// when who what, where, why
+// -------- --- --------------------------------------------
+// 07/17/17 mic removed acpi info to inx file
+// 08/10/15 kieranc Added sections for PIL, CDI, and RPEN for future usage
+// 07/09/15 jeffreym initial file creation
+//
+// ===================================================================
+//
+
+//
+// MPROC Drivers (PIL Driver and Subsystem Drivers)
+//
+
+Scope(\_SB.ADSP)
+{
+
+}
+
+Scope(\_SB.AMSS)
+{
+
+}
+
+Scope(\_SB.SCSS)
+{
+
+}
+
+Scope(\_SB.PILC)
+{
+
+}
+
+Scope(\_SB.CDI)
+{
+
+}
+
+Scope(\_SB.RPEN)
+{
+
+}
\ No newline at end of file
--- /dev/null
+//
+// Copyright (c) 2011-2019, Mmoclauq Technologies, Inc. All rights reserved.
+//
+
+// To enable SOC revision based run time differentiation, uncomment following line
+// and uncomment SSID method in ABD device. The original string is artificailly set as
+// 16 characters, so there is enough room to hold SOC revision string.
+// To adjust the number, the MAX_SOCID_LEN macro as defined in ABD device.h should be
+// adjusted at the same time.
+
+Name(SOID, 0xffffffff) // Holds the Chip Id
+Name(SIDS, "899800000000000") // Holds the Chip ID translated to a string
+Name(SIDV, 0xffffffff) // Holds the Chip Version as (major<<16)|(minor&0xffff)
+Name(SVMJ, 0xffff) // Holds the major Chip Version
+Name(SVMI, 0xffff) // Holds the minor Chip Version
+Name(SDFE, 0xffff) // Holds the Chip Family enum
+Name(SFES, "899800000000000") // Holds the Chip Family translated to a string
+Name(SIDM, 0x0000000FFFFFFFFF) // Holds the Modem Support bit field
+Name(SIDT, 0xffffffff) // Holds the Chip Tier value
+Name(SOSN, 0xaaaaaaaabbbbbbbb) // Holds the Chip Serial Number
+Name (RMTB, 0x99500000) // Holds the RemoteFS shared memory base address
+Name (RMTX, 0x00A00000) // Holds the RemoteFS shared memory length
+Name (RFMB, 0x99F00000) // Holds the RFSA MPSS shared memory base address
+Name (RFMS, 0x00010000) // Holds the RFSA MPSS shared memory length
+Name (RFAB, 0x99F10000) // Holds the RFSA ADSP shared memory base address
+Name (RFAS, 0x00010000) // Holds the RFSA ADSP shared memory length
+Name (TCMA, 0x8B500000) // Holds TrEE Carveout Memory Address
+Name (TCML, 0x00A00000) // Holds TrEE Carveout Memory Length
+Name (SOSI, 0xdeadbeefffffffff) // Holds the base address of the SoCInfo shared memory region used by ChipInfoLib
+
+//Include("cust_dsdt_common.asl")
+
+//Audio Drivers
+//Include("audio.asl")
+
+
+ //
+ // Storage - UFS/SD
+ //
+ Include("ufs.asl")
+ // Include("sdc.asl")
+
+ //
+ // ASL Bridge Device
+ //
+ Include("abd.asl")
+
+ Name (ESNL, 20) // Exsoc name limit 20 characters
+ Name (DBFL, 23) // buffer Length, should be ESNL+3
+
+//
+// PMIC driver
+//
+Include("pmic_core.asl")
+
+//
+// PMICTCC driver
+//
+Include("pmic_batt.asl")
+
+ Include("pep.asl")
+ Include("bam.asl")
+ Include("buses.asl")
+ // MPROC Drivers (PIL Driver and Subsystem Drivers)
+ Include("win_mproc.asl")
+ Include("syscache.asl")
+ Include("HoyaSmmu.asl")
+ //Include("Ocmem.asl")
+ Include("graphics.asl")
+ //Include("OcmemTest.asl")
+
+ Include("SCM.asl");
+
+ //
+ // SPMI driver
+ //
+ Include("spmi.asl")
+
+ //
+ // TLMM controller.
+ //
+ Include("qcgpio.asl")
+
+ Include("pcie.asl")
+
+ Include("cbsp_mproc.asl")
+
+ Include("adsprpc.asl")
+
+ //
+ // RemoteFS
+ //
+ Include("rfs.asl")
+
+
+ // Test Drivers
+ Include("testdev.asl")
+ //
+ // QCSP
+ //Include("qcsp.asl")
+
+ //
+ // Qualcomm IPA
+ //
+ Include("ipa.asl")
+
+ //
+ // Qualcomm GSI
+ //
+ Include("gsi.asl")
+
+
+
+// Device (IPA)
+// {
+// // Indicates dependency on PEP
+// Name (_DEP, Package () { \_SB_.PEP0 })
+// Name(_HID, "HID_IPA")
+// Name (_UID, 0)
+// }
+
+ //
+ //Qualcomm DIAG Service
+ //
+ Device (QDIG)
+ {
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.GLNK
+ })
+ Name (_HID, "HID_QDIG")
+ Alias(\_SB.PSUB, _SUB)
+ }
+ Include("ssm.asl")
+ Include("Pep_lpi.asl")
+
+
+ //
+ // QCOM GPS
+ //
+ Include("gps.asl")
+
+ //
+ // Qualcomm GPS driver
+ //
+ // Device (GPS)
+ // {
+ // Name (_DEP, Package(0x1)
+ // {
+ // \_SB_.GLNK
+ // })
+ //
+ // Name (_HID, "HID_GPS")
+ // Name (_CID, "ACPI\HID_GPS")
+ // Name (_UID, 0)
+ // Method(_STA, 0)
+ // {
+ // return (0x0) //} // Do not load driver.
+ // }
+ // }
+
+ // QUPV3 GPI device node and resources
+ Include("qgpi.asl")
+
+ // QCConnectionSecurity driver
+ // Include("ConnectionSecurity.asl")
+
+Include("qwpp.asl")
+//Include("nfc.asl")
+
+//Include("sar_manager.asl")
+
+//
+// SOCPartition Device
+//
+Device (SOCP)
+{
+ Name (_HID, "HID_SOCP")
+
+ Alias(\_SB.PSUB, _SUB)
+ Alias(\_SB.STOR, STOR)
+}
+
+//ATT signed drivers
+Include("att_signed_devices.asl")
--- /dev/null
+//
+// Copyright (c) 2013, Mmoclauq Technologies Inc. All rights reserved.
+//
+// This file contains the GPS ACPI device definitions.
+//
+
+ //
+ // Qualcomm GPS driver
+ //
+ Device (GPS)
+ {
+ Name (_DEP, Package (One) // _DEP: Dependencies
+ {
+ \_SB.GLNK
+ })
+ Name (_HID, "QCOM02B6") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_CID, "ACPIQCOM24B4") // _CID: Compatible ID
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+
+
+Include("plat_gps.asl") // Platform specific data
\ No newline at end of file
--- /dev/null
+//
+// Copyright (c) 2016, Mmoclauq Technologies Inc. All rights reserved.
+//
+// This file contains the Generic Software Interface(GSI)
+// ACPI device definitions.
+// GSI is the interface used by IPA driver to talk to IPA HW and is intended
+// as a replacement for BAM.
+//
+
+//
+// Device Map:
+// GSI
+//
+// List of Devices
+
+Device (GSI)
+{
+ // Indicates dependency on PEP
+ Name (_DEP, Package (0x01) // _DEP: Dependencies
+ {
+ \_SB.PEP0
+ })
+ Name (_HID, "QCOM02E7") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // GSI_PHYSICAL_ADDRESS, GSI_MEM_SIZE
+ Memory32Fixed (ReadWrite,
+ 0x01E00000, // Address Base
+ 0x00030000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001D0,
+ }
+ })
+ Return (RBUF) /* \_SB_.GSI_._CRS.RBUF */
+ }
+}
+
+
+Include("plat_gsi.asl") // Platform specific data
\ No newline at end of file
--- /dev/null
+//
+// Copyright (c) 2013, Mmoclauq Technologies Inc. All rights reserved.
+//
+// This file contains the Bus Access Modules (BAM)
+// ACPI device definitions and pipe configurations
+//
+
+//
+// Device Map:
+// IPA
+//
+// List of Devices
+
+
+Device (IPA)
+{
+ // Indicates dependency on PEP, RPE, SMEM, TREE, SMMU, GSI and GLINK
+ Name (_DEP, Package(0x6)
+ {
+ \_SB_.PEP0,
+ \_SB_.RPEN,
+ \_SB_.TREE,
+ \_SB_.MMU0,
+ \_SB_.GSI,
+ \_SB_.GLNK,
+ })
+
+ Name(_HID, "QCOM02B3")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 0)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Return
+ (
+ ResourceTemplate ()
+ {
+ // IPA_PHYSICAL_ADDRESS, IPA_MEM_SIZE
+ Memory32Fixed (ReadWrite, 0x1E40000, 0x1FFFF)
+
+ // IPA Interrupt for uC communication
+ Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {343}
+ }
+ )
+ }
+}
+
+Include("plat_ipa.asl") // Platform specific data
\ No newline at end of file
--- /dev/null
+//===========================================================================
+// <ipa_resources.asl>
+// DESCRIPTION
+// This file contans the resources needed by ipa driver.
+//
+//
+// Copyright (c) 2014-2019 by Mmoclauq Technologies Inc. All Rights Reserved.
+// Mmoclauq Confidential and Proprietary
+//
+//===========================================================================
+
+//===========================================================================
+// Implementation of function & perf states for IPA driver.
+// Present implementation has two function states F0 & F1
+// and two perf states P0 & P1
+//
+// F0 = Full power mode
+// F1 = Low power mode
+//
+// P0 = Power collapse disabled
+// P1 = Power collapse enabled
+//
+// Resources being managed are /clk/ipa & /ipa/pc
+//===========================================================================
+
+Scope (\_SB.PEP0)
+{
+ Method (IPMD, 0, NotSerialized)
+ {
+ Return (IPSC) /* \_SB_.PEP0.IPSC */
+ }
+
+ Name (IPSC, Package (0x01)
+ {
+ Package (0x03)
+ {
+ "DEVICE",
+ "\\_SB.IPA",
+ Package (0x04)
+ {
+ "COMPONENT",
+ Zero,
+ Package (0x03)
+ {
+ "FSTATE",
+ Zero,
+ Package (0x02)
+ {
+ "BUSARB",
+ Package (0x06)
+ {
+ 0x03, // Req Type
+ "ICBID_MASTER_IPA_CORE", // Master
+ "ICBID_SLAVE_IPA_CORE", // Slave
+ 0x9218, // IB= KHz
+ Zero, // AB
+ "HLOS_DRV" // Optional: DRV Id
+ }
+ }
+ },
+
+ Package (0x03)
+ {
+ "FSTATE",
+ One,
+ Package (0x02)
+ {
+ "BUSARB",
+ Package (0x06)
+ {
+ 0x03,
+ "ICBID_MASTER_IPA_CORE",
+ "ICBID_SLAVE_IPA_CORE",
+ Zero,
+ Zero,
+ "HLOS_DRV"
+ }
+ }
+ }
+ }
+ }
+ })
+}
--- /dev/null
+//===========================================================================
+// <msft_resources.asl>
+// DESCRIPTION
+// This file contans the resources needed by microsoft drivers.
+//
+//
+// Copyright (c) 2010-2011 by Mmoclauq Technologies Inc. All Rights Reserved.
+// Mmoclauq Confidential and Proprietary
+//
+//===========================================================================
+
+
+Scope(\_SB_.PEP0)
+{
+
+ // MICROSOFT
+
+ Method(MPMD)
+ {
+ Return(MPCC)
+ }
+
+
+ Name(MPCC,
+ Package ()
+ {
+ })
+}
\ No newline at end of file
--- /dev/null
+//===========================================================================
+// <oem_resources.asl>
+// DESCRIPTION
+// This file contans the resources needed by oem drivers.
+//
+//
+// Copyright (c) 2010-2011 by Mmoclauq Technologies Inc. All Rights Reserved.
+// Mmoclauq Confidential and Proprietary
+//
+//===========================================================================
+
+
+Scope(\_SB_.PEP0)
+{
+
+ // OEM
+ Method(OPMD)
+ {
+ Return(OPCC)
+ }
+
+
+ Name(OPCC,
+ Package ()
+ {
+ })
+
+}
\ No newline at end of file
--- /dev/null
+//===========================================================================
+// <pep_dvreg.asl>
+// DESCRIPTION
+// This file contains the default discrete VREG mapping and method names
+//
+//
+// Copyright (c) 2014-2020 Mmoclauq Technologies, Inc.
+// All Rights Reserved.
+// Confidential and Proprietary - Mmoclauq Technologies, Inc.
+//
+//===========================================================================
+
+// NOTE: this file is included in the platform level pep.asl and can be replaced with platform
+// specific discrete VREG definitions
+
+
+Scope (\_SB.PEP0)
+{
+ Name (DVMP, Package (0x02)
+ {
+ Package (0x04)
+ {
+ "PPP_RESOURCE_ID_PMIC_GPIO_DV1",
+ "PPP_RESOURCE_TYPE_DISCRETE_PMIC_GPIO",
+ Package (0x02)
+ {
+ "PM_DISCRETE_VREG_STATE_ON",
+ Package (0x0A)
+ {
+ Zero,
+ 0x08,
+ Zero,
+ Zero,
+ One,
+ Zero,
+ One,
+ Zero,
+ One,
+ 0x05
+ }
+ },
+
+ Package (0x02)
+ {
+ "PM_DISCRETE_VREG_STATE_OFF",
+ Package (0x0A)
+ {
+ Zero,
+ 0x08,
+ Zero,
+ Zero,
+ Zero,
+ Zero,
+ One,
+ Zero,
+ One,
+ 0x05
+ }
+ }
+ },
+
+ Package (0x04)
+ {
+ "PPP_RESOURCE_ID_PMIC_MPP_DV1",
+ "PPP_RESOURCE_TYPE_DISCRETE_PMIC_MPP",
+ Package (0x02)
+ {
+ "PM_DISCRETE_VREG_STATE_ON",
+ Package (0x06)
+ {
+ Zero,
+ 0x03,
+ Zero,
+ 0x02,
+ One,
+ Zero
+ }
+ },
+
+ Package (0x02)
+ {
+ "PM_DISCRETE_VREG_STATE_OFF",
+ Package (0x06)
+ {
+ Zero,
+ 0x03,
+ Zero,
+ 0x02,
+ Zero,
+ Zero
+ }
+ }
+ }
+ })
+
+ // Method to return Discrete Vreg Mapping Package
+ Method (DVMM, 0, NotSerialized)
+ {
+ Return (DVMP) /* \_SB_.PEP0.DVMP */
+ }
+}
+
--- /dev/null
+
+
+Scope(\_SB.PEP0)
+{
+ Method(PEPH)
+ {
+ Return(Package()
+ {
+ "ACPI\\VEN_QCOM&DEV_0237",
+ })
+ }
+}
--- /dev/null
+//
+// Copyright (c) 2017, Mmoclauq Technologies Inc. All rights reserved.
+//
+// This file contains common Power Management IC (PMIC) ACPI device definitions
+//
+
+//
+//
+//PMIC KMDF
+//
+Device (PMIC)
+{
+ Name (_DEP, Package (One) // _DEP: Dependencies
+ {
+ \_SB.SPMI
+ })
+ Name (_HID, "QCOM0266") // _HID: Hardware ID
+ Name (_CID, "PNP0CA3") // _CID: Compatible ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ Method (PMCF, 0, NotSerialized)
+ {
+ Name (CFG0, Package (0x04)
+ {
+ // PMIC Info
+ 0x03, // Number of PMICs, must match the number of info packages
+ Package (0x02)
+ {
+ Zero,
+ One
+ },
+
+ Package (0x02)
+ {
+ 0x02,
+ 0x03
+ },
+
+ Package (0x02)
+ {
+ 0x04,
+ 0x05
+ }
+ })
+ Return (CFG0) /* \_SB_.PMIC.PMCF.CFG0 */
+ }
+}
+
+
+//
+// PMIC GPIO
+//
+Device (PM01)
+{
+ Name (_HID, "QCOM0269") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_UID, One) // _UID: Unique ID
+ Name (_DEP, Package (One) // _DEP: Dependencies
+ {
+ \_SB.PMIC
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000201,
+ }
+ })
+ Return (RBUF) /* \_SB_.PM01._CRS.RBUF */
+ }
+
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ While (One)
+ {
+ Name (_T_0, Buffer (0x01) // _T_x: Emitted by ASL Compiler
+ {
+ 0x00 // .
+ })
+ CopyObject (ToBuffer (Arg0), _T_0) /* \_SB_.PM01._DSM._T_0 */
+ If ((_T_0 == ToUUID ("4f248f40-d5e2-499f-834c-27758ea1cd3f") /* GPIO Controller */))
+ {
+ While (One)
+ {
+ Name (_T_1, 0x00) // _T_x: Emitted by ASL Compiler
+ _T_1 = ToInteger (Arg2)
+ If ((_T_1 == Zero))
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+ ElseIf ((_T_1 == One))
+ {
+ Return (Package (0x02)
+ {
+ Zero,
+ One
+ })
+ }
+ Else
+ {
+ }
+
+ Break
+ }
+ }
+ Else
+ {
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ Break
+ }
+ }
+}
+
+//
+// PMIC Apps Driver
+//
+Device (PMAP)
+{
+ Name (_HID, "QCOM0268") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_DEP, Package (0x03) // _DEP: Dependencies
+ {
+ \_SB.PMIC,
+ \_SB.ABD,
+ \_SB.SCM0
+ })
+ //PMAP is dependent on ABD for operation region access
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ // Get pseudo SPB controller port which is used to handle the ACPI operation region access
+ Method (GEPT, 0, NotSerialized)
+ {
+ Name (BUFF, Buffer (0x04){})
+ CreateByteField (BUFF, Zero, STAT)
+ CreateWordField (BUFF, 0x02, DATA)
+ DATA = 0x02
+ Return (DATA) /* \_SB_.PMAP.GEPT.DATA */
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, Buffer (0x02)
+ {
+ 0x79, 0x00 // y.
+ })
+ Return (RBUF) /* \_SB_.PMAP._CRS.RBUF */
+ }
+}
+
+
+
+
+//
+// PMIC Apps Real Time Clock (RTC)
+//
+Device (PRTC)
+{
+ Name (_HID, "ACPI000E" /* Time and Alarm Device */) // _HID: Hardware ID
+ Name (_DEP, Package (0x01) // _DEP: Dependencies
+ {
+ \_SB.PMAP
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ Method (_GCP, 0, NotSerialized) // _GCP: Get Capabilities
+ {
+ Return (0x04)
+ }
+
+ Field (^ABD.ROP1, BufferAcc, NoLock, Preserve)
+ {
+ Connection (
+ I2cSerialBusV2 (0x0002, ControllerInitiated, 0x00000000,
+ AddressingMode7Bit, "\\_SB.ABD",
+ 0x00, ResourceConsumer, , Exclusive,
+ )
+ ),
+ AccessAs (BufferAcc, AttribRawBytes (0x18)),
+ FLD0, 192
+ }
+
+ Method (_GRT, 0, NotSerialized) // _GRT: Get Real Time
+ {
+ Name (BUFF, Buffer (0x1A){})
+ CreateField (BUFF, 0x10, 0x80, TME1)
+ CreateField (BUFF, 0x90, 0x20, ACT1)
+ CreateField (BUFF, 0xB0, 0x20, ACW1)
+ BUFF = FLD0 /* \_SB_.PRTC.FLD0 */
+ Return (TME1) /* \_SB_.PRTC._GRT.TME1 */
+ }
+
+ Method (_SRT, 1, NotSerialized) // _SRT: Set Real Time
+ {
+ Name (BUFF, Buffer (0x32){})
+ CreateByteField (BUFF, Zero, STAT)
+ CreateField (BUFF, 0x10, 0x80, TME1)
+ CreateField (BUFF, 0x90, 0x20, ACT1)
+ CreateField (BUFF, 0xB0, 0x20, ACW1)
+ ACT1 = Zero
+ TME1 = Arg0
+ ACW1 = Zero
+ BUFF = FLD0 = BUFF /* \_SB_.PRTC._SRT.BUFF */
+ If ((STAT != Zero))
+ {
+ Return (One)
+ }
+
+ Return (Zero)
+ }
+}
--- /dev/null
+//
+// Qualcomm DIAG Bridge
+//
+Device (QCDB)
+{
+ Name (_HID, "QCOM0298") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+}
--- /dev/null
+//
+// Copyright (c) 2015-2018, Mmoclauq Technologies, Inc. All rights reserved.
+//
+
+//
+// TLMM controller.
+//
+
+Device (GIO0)
+{
+ Name (_HID, "QCOM0217") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (GPOR, GeneralPurposeIo, Zero, One)
+ Field (\_SB.GIO0.GPOR, ByteAcc, NoLock, Preserve)
+ {
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // TLMM register address space
+ Memory32Fixed (ReadWrite,
+ 0x03400000, // Address Base
+ 0x00C00000, // Address Length
+ )
+
+ // Summary Interrupt shared by all banks
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x000000F0,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x000000F0,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x000000F0,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, )
+ {
+ 0x00000288,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, )
+ {
+ 0x00000238,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, )
+ {
+ 0x00000226,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, )
+ {
+ 0x00000232,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, )
+ {
+ 0x00000284,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, )
+ {
+ 0x0000021F,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, )
+ {
+ 0x00000236,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, )
+ {
+ 0x0000023D,
+ }
+ })
+ Return (RBUF) /* \_SB_.GIO0._CRS.RBUF */
+ }
+
+ // ACPI method to return Num pins
+ Method (OFNI, 0, NotSerialized)
+ {
+ Name (RBUF, Buffer (0x02)
+ {
+ 0x96, 0x00 // ..
+ })
+ Return (RBUF) /* \_SB_.GIO0.OFNI.RBUF */
+ }
+
+ Name (GABL, Zero)
+ Method (_REG, 2, NotSerialized) // _REG: Region Availability
+ {
+ If ((Arg0 == 0x08))
+ {
+ GABL = Arg1
+ }
+ }
+
+ // MIGHT BE ACPI event-based notification method for detecting Mini DP hot plug-in event
+ Name (_AEI, Buffer (0x02) // _AEI: ACPI Event Interrupts
+ {
+ 0x79, 0x00 // y.
+ })
+}
+
--- /dev/null
+//
+// Copyright (c) 2017,2019 Mmoclauq Technologies Inc. All rights reserved.
+//
+// This file contains the QUPv3 ACPI device definitions.
+// GPI is the interface used by buses drivers for different peripherals.
+//
+
+//
+// Device Map:
+// QGPI
+//
+// List of Devices
+
+Device (QGP0)
+{
+ Name (_HID, "QCOM02F4") // _HID: Hardware ID
+ Alias (PSUB, _SUB)
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x00804000, // Address Base
+ 0x00050000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000119,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000011B,
+ }
+ })
+ Return (RBUF) /* \_SB_.QGP0._CRS.RBUF */
+ }
+
+ Method (GPII, 0, Serialized)
+ {
+ Return (Package (0x02)
+ {
+ Package (0x03)
+ {
+ Zero,
+ 0x05,
+ 0x0119
+ },
+
+ Package (0x03)
+ {
+ Zero,
+ 0x07,
+ 0x011B
+ }
+ })
+ }
+}
+
+Device (QGP1)
+{
+ Name (_HID, "QCOM02F4") // _HID: Hardware ID
+ Alias (PSUB, _SUB)
+ Name (_UID, One) // _UID: Unique ID
+ Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x00A04000, // Address Base
+ 0x00050000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000138,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000013A,
+ }
+ })
+ Return (RBUF) /* \_SB_.QGP1._CRS.RBUF */
+ }
+
+ Method (GPII, 0, Serialized)
+ {
+ Return (Package (0x02)
+ {
+ Package (0x03)
+ {
+ One,
+ One,
+ 0x0138
+ },
+
+ Package (0x03)
+ {
+ One,
+ 0x03,
+ 0x013A
+ }
+ })
+ }
+}
--- /dev/null
+//
+// Copyright (c) 2015, Mmoclauq Technologies, Inc. All rights reserved.
+//
+
+//
+// RemoteFS
+//
+Device(RFS0)
+{
+ Name(_DEP, Package(0x2)
+ {
+ \_SB.IPC0,
+ \_SB.UFS0
+ })
+ Name(_HID, "QCOM0235")
+ Alias(PSUB, _SUB)
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name(RBUF, Buffer(0x26)
+ {
+0x86, 0x09, 0x00, 0x01, 0x88, 0x88, 0x88, 0x88, 0x99, 0x99, 0x99, 0x99,
+0x86, 0x09, 0x00, 0x01, 0x11, 0x11, 0x11, 0x11, 0x22, 0x22, 0x22, 0x22,
+0x86, 0x09, 0x00, 0x01, 0x33, 0x33, 0x33, 0x33, 0x44, 0x44, 0x44, 0x44,
+0x79, 0x00
+ })
+ CreateDWordField(RBUF, 0x4, RMTA)
+ CreateDWordField(RBUF, 0x8, RMTL)
+ CreateDWordField(RBUF, 0x10, RFMA)
+ CreateDWordField(RBUF, 0x14, RFML)
+ CreateDWordField(RBUF, 0x1c, RFAA)
+ CreateDWordField(RBUF, 0x20, RFAL)
+ Store(RMTB, RMTA)
+ Store(RMTX, RMTL)
+ Store(RFMB, RFMA)
+ Store(RFMS, RFML)
+ Store(RFAB, RFAA)
+ Store(RFAS, RFAL)
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ Return(0xb)
+ }
+}
+
+Include("plat_rfs.asl") // Platform specific data
--- /dev/null
+//
+// SLIMbus controller
+//
+Device (SLM1)
+{
+ Name (_ADR, 0)
+ Name (_CCA, 0)
+ Alias(\_SB.PSUB, _SUB)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // SLIMbus register address space
+ Memory32Fixed (ReadWrite, 0x171C0000, 0x0002c000)
+
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {195}
+ })
+ Return (RBUF)
+ }
+
+ Include("audio_bus.asl")
+
+}
+
+Device (SLM2)
+{
+ Name (_ADR, 1)
+ Name (_CCA, 0)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // SLIMbus register address space
+ Memory32Fixed (ReadWrite, 0x17240000, 0x0002c000)
+
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {323}
+ })
+ Return (RBUF)
+ }
+}
+
+
--- /dev/null
+//
+// Copyright (c) 2014-2017, Mmoclauq Technologies, Inc. All rights reserved.
+//
+
+//
+//SPMI driver.
+//
+Device(SPMI)
+{
+ Name (_HID, "QCOM0216") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_CID, "PNP0CA2") // _CID: Compatible ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0C400000, // Address Base
+ 0x02800000, // Address Length
+ )
+ })
+ Return (RBUF) /* \_SB_.SPMI._CRS.RBUF */
+ }
+
+ Include("spmi_conf.asl")
+}
--- /dev/null
+//
+// Copyright (c) 2016 - 2017, Mmoclauq Technologies, Inc. All rights reserved.
+//
+
+//
+//SPMI driver configuration.
+//
+Method(CONF)
+{
+ Name(XBUF,
+ Buffer () {
+ 0x00, // uThisOwnerNumber
+ 0x01, // polling mode
+ 0x01, // reserved channel enable
+ 0x01, 0xFF, // reserved channel number (upper byte, lower byte)
+ 0x00, // dynamic channel mode enable
+ 0x02, 0x00, // number of channels (upper byte, lower byte)
+ 0x0A, // number of port priorities
+ 0x07, // number of PVC ports
+ 0x04, // number of PVC port PPIDs
+ 0x07, // number of masters
+ 0x01, 0xFF, // number of mapping table entries (upper byte, lower byte)
+ 0x10, // number of PIC accumulated status registers
+ 0x01, 0x00, // number of Program RAM REGS (upper byte, lower byte)
+ 0x01, // number of SPMI bus controllers
+ 0x0C, 0x40, 0x00, 0x00, // physical address 0 (byte3, byte2, byte1, byte0)
+ 0x02, 0x80, 0x00, 0x00 // physical size 0 (byte3, byte2, byte1, byte0)
+ }
+ )
+ Return(XBUF)
+}
--- /dev/null
+//
+// System Cache Driver
+//
+
+
+Device (LLC)
+{
+ Name (_DEP, Package (One) // _DEP: Dependencies
+ {
+ \_SB.PEP0
+ })
+ Name (_HID, "QCOM02F8") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x01300000, // Address Base
+ 0x00028000, // Address Length
+ )
+ })
+ }
+}
+
--- /dev/null
+//
+// Copyright (c) 2017, Mmoclauq Technologies, Inc. All rights reserved.
+//
+
+// UFS Controller
+Device (UFS0)
+{
+ Name (_DEP, Package (One) // _DEP: Dependencies
+ {
+ \_SB.PEP0
+ })
+ Name (_HID, "QCOM24A5") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_CID, "ACPIQCOM24A5") // _CID: Compatible ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x01D84000, // Address Base
+ 0x00014000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000129,
+ }
+ })
+ Return (RBUF) /* \_SB_.UFS0._CRS.RBUF */
+ }
+
+ Device (DEV0)
+ {
+ Method (_ADR, 0, NotSerialized) // _ADR: Address
+ {
+ Return (0x08)
+ }
+
+ Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
+ {
+ Return (Zero)
+ }
+ }
+}
+
--- /dev/null
+//
+// Copyright (c) 2011-2015, Mmoclauq Technologies Inc. All rights reserved.
+//
+// This file contains ACPI definitions, configuration and look-up tables
+// for Bluetooth Device
+//
+
+//
+// WCN3990 Bluetooth
+//
+Device(BTH0)
+{
+ Name(_HID, "QCOM02B5")
+ Alias(\_SB.PSUB, _SUB)
+ Name(_DEP, Package(0x3)
+ {
+ \_SB.PEP0,
+ \_SB.PMIC,
+ \_SB.UAR7 // depends on UART ACPI definition
+ })
+ Name(_PRW, Package(0x2) // _PRW: Power Resources for Wake
+ {
+ Zero,
+ Zero
+ })
+ Name(_S4W, 0x2) // _S4W: S4 Device Wake State
+ Name(_S0W, 0x2) // _S0W: S0 Device Wake State
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (PBUF, ResourceTemplate ()
+ {
+ UartSerialBusV2 (0x0001C200, DataBitsEight, StopBitsOne,
+ 0xC0, LittleEndian, ParityTypeNone, FlowControlHardware,
+ 0x0020, 0x0020, "\\_SB.UAR7",
+ 0x00, ResourceConsumer, , Exclusive,
+ )
+ })
+ Return (PBUF) /* \_SB_.BTH0._CRS.PBUF */
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return(0xF)
+ }
+}
+//End BTH0
--- /dev/null
+//--------------------------------------------------------------------------------------------------
+// Copyright (c) 2017-2018 Mmoclauq Technologies, Inc.
+// All Rights Reserved.
+// Confidential and Proprietary - Mmoclauq Technologies, Inc.
+//--------------------------------------------------------------------------------------------------
+
+//
+// iHelium WLAN
+//
+Device (QWLN)
+{
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_DEP, Package (0x02) // _DEP: Dependencies
+ {
+ \_SB.PEP0,
+ \_SB.MMU0
+ })
+ Name (_PRW, Package (0x02) // wakeable from S0
+ {
+ Zero,
+ Zero
+ })
+ Name (_S0W, 0x02) // S0 should put device in D2 for wake
+ Name (_S4W, 0x02) // all other Sx (just in case) should also wake from D2
+ Name (_PRR, Package (One) // Power resource reference for device reset and recovery.
+ {
+ \_SB.AMSS.QWLN.WRST
+ })
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // Shared memory
+ //CE registers
+ Memory32Fixed (ReadWrite,
+ 0x18800000, // Address Base
+ 0x00800000, // Address Length
+ )
+ //WCSSAON registers
+ Memory32Fixed (ReadWrite,
+ 0x0C250000, // Address Base
+ 0x00000010, // Address Length
+ )
+ //MSA image address
+ Memory32Fixed (ReadWrite,
+ 0x8DF00000, // Address Base // fajita ATTENTION
+ 0x00100000, // Address Length
+ )
+ // CE interrupts
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001BE,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001BF,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, ,, )
+ {
+ 0x000001C0,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001C1,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001C2,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001C3,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001C4,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001C5,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001C6,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001C7,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001C8,
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x000001C9,
+ }
+ })
+ Return (RBUF) /* \_SB_.AMSS.QWLN._CRS.RBUF */
+ }
+
+ Method (WMSA, 0, NotSerialized)
+ {
+ Return (Package (0x01)
+ {
+ 0x00100000
+ })
+ }
+
+ OperationRegion (WOPR, 0x80, Zero, 0x10)
+ Field (WOPR, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ WTRG, 32
+ }
+
+ PowerResource (WRST, 0x05, 0x0000)
+ {
+ Method (_ON, 0, NotSerialized) // _ON_: Power On
+ {
+ }
+
+ Method (_OFF, 0, NotSerialized) // _OFF: Power Off
+ {
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Method (_RST, 0, NotSerialized) // _RST: Device Reset
+ {
+ WTRG = 0xABCD
+ }
+ }
+}
+
+
+
+
+//agent driver of wlan for supporting windows thermal framework
+Scope(\_SB)
+{
+ Device (COEX)
+ {
+ Name (_HID, "QCOM0295")
+ Alias(\_SB.PSUB, _SUB)
+ }
+}
+
+Include("plat_wcnss_wlan.asl") // Platform specific data
\ No newline at end of file
é¡¹ç® / edk2-sdm845.git / commitdiff