--- /dev/null
+#include "Platform.h"
+#include "Socdata.h"
+#include <ACPI.h>
+#include <ACPIDmaRGDefs.h>
+
+#pragma pack(push, 1)
+
+#define ACPI_CSRT_RG_DEVICE_ID_TIMER 0x100A
+#define ACPI_CSRT_RG_DEVICE_ID_DMA 0x1002
+#define ACPI_CSRT_RG_DEVICE_ID_INTERRUPT 0x1003
+#define ACPI_CSRT_RG_DEVICE_ID_WDOG_TIMER 0x100B
+
+typedef enum _RD_TIMER_TYPE {
+ UnknownTimer = 0,
+ QWdogTimer = 2
+} RD_TIMER_TYPE, *PRD_TIMER_TYPE;
+
+typedef struct {
+ CSRT_RESOURCE_DESCRIPTOR_HEADER Header;
+ RD_TIMER_TYPE Type;
+ UINT64 BaseAddress;
+ UINT32 Frequency;
+ UINT32 Gsi;
+} RD_TIMER, *PRD_TIMER;
+
+typedef struct {
+ CSRT_RESOURCE_GROUP_HEADER Header;
+ RD_TIMER Timer1;
+} RG_TIMER;
+
+// number of ADM channels mapped into Scorpion domain
+// CSRT structure for this platform
+//------------------------------------------------------------------------
+
+typedef struct {
+ ACPI_HEADER Header;
+ RG_TIMER TimerResourceGroup;
+} CSRT;
+
+#define RG_HEADER(_TYPE, _DEVID, _SHARED_SIZE) \
+ sizeof(_TYPE), /* Resource Group Length */\
+ SIGNATURE4('Q','C','O','M'), /* VendorId */\
+ 0, /* SubvendorId */\
+ _DEVID, /* DeviceId */\
+ 0, /* SubdeviceId */\
+ 0, /* Revision */\
+ 0, /* Reserved */\
+ _SHARED_SIZE /* Size of shared area */\
+
+//------------------------------------------------------------------------
+// CSRT structure for this platform
+//------------------------------------------------------------------------
+typedef struct {
+ ACPI_HEADER CsrtHeader;
+ RG_TIMER Timer1;
+ SOCDTABLE_SOCD SocData;
+} ACPI_CSRT_TABLE;
+
+ACPI_CSRT_TABLE Csrt = {
+ //------------------------------------------------------------------------
+ // CSRT Header
+ //------------------------------------------------------------------------
+ ACPI_CSRT_SIGNATURE, // Signature
+ sizeof(ACPI_CSRT_TABLE), // Length
+ ACPI_CSRT_REVISION, // Revision
+ 0x00, // Checksum calculated at runtime.
+ ACPI_OEM_ID, // OEMID is a 6 bytes long field.
+ ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long).
+ ACPI_OEM_REVISION, // OEM revision number.
+ ACPI_CREATOR_ID, // ASL compiler vendor ID.
+ ACPI_CREATOR_REVISION, // ASL compiler revision number.
+
+ //------------------------------------------------------------------------
+ // Timer Resource Group - Shared (memory-mapped) QTimer
+ //------------------------------------------------------------------------
+
+ RG_HEADER(RG_TIMER, ACPI_CSRT_RG_DEVICE_ID_WDOG_TIMER, 0),
+
+
+ // Timer1 Resource Descriptor
+
+
+ sizeof(RD_TIMER),
+ CSRT_RD_TYPE_TIMER,
+ CSRT_RD_SUBTYPE_TIMER,
+ 1,
+ QWdogTimer,
+ 0x17980000, // Timer base address
+ 32765, // frequency
+ 32, // GSIV
+ .SocData=SOCDTABLE_SOCD_VAR,
+};
+
+#pragma pack(pop)
+
--- /dev/null
+#include "Platform.h"
+
+ACPI_FACP FACP = {
+ {
+ ACPI_FACP_SIGNATURE,
+ sizeof (ACPI_FACP),
+ ACPI_FACP_REVISION,
+ 0,
+ ACPI_OEM_ID,
+ ACPI_OEM_TABLE_ID,
+ ACPI_OEM_REVISION,
+ ACPI_CREATOR_ID,
+ ACPI_CREATOR_REVISION
+ },
+
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_PM_PROFILE_SLATE, // Preferred_PM_Profile
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+
+ ACPI_HARDWARE_REDUCED|LOW_POWER_S0_CAPABLE,
+
+ {
+ ACPI_GAS_ID_EMBEDDED_CONTROLLER,
+ 0,
+ 0,
+ ACPI_GAS_ACCESS_DWORD,
+ HWIO_SCSS_RESET_ADDR
+ },
+
+ SCSS_SYS_POR, // RESET_VALUE;
+ // Bit 0 is for PSCI support
+ // Bit 1 is to tell the OS to use HVC instead of SMC.
+ // 0x0 to disable PSCI
+ 0x1, // ARM_BOOT_ARCH;
+ ACPI_RESERVED, // FADT Minor Version;
+ ACPI_RESERVED, // X_FIRMWARE_CTRL;
+ ACPI_RESERVED, // X_DSDT;
+ { // X_PM1a_EVT_BLK;
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ },
+ { // X_PM1b_EVT_BLK;
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ },
+ { // X_PM1a_CNT_BLK;
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ },
+ { // X_PM1b_CNT_BLK;
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ },
+ { // X_PM2_CNT_BLK;
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ },
+ { // X_PM_TMR_BLK;
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ },
+ { // X_GPE0_BLK;
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ },
+ { // X_GPE1_BLK;
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ },
+ { // SLEEP_CONTROL_REG;
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ },
+ { // SLEEP_STATUS_REG;
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ },
+ HYP_VENDOR_ID, // Hypervisor Vendor Identity
+};
+
--- /dev/null
+#include "Platform.h"
+
+ACPI_FACS FACS = {
+ ACPI_FACS_SIGNATURE,
+ sizeof (ACPI_FACS),
+ 0x00000000,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00000000,
+ 0x02,
+ {
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ },
+ 0x00,
+ {
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED,
+ ACPI_RESERVED
+ }
+};
--- /dev/null
+#include "Platform.h"
+#include <ACPI.h>
+
+#pragma pack(push, 1)
+
+#define UNSUPPORTED_ADDR 0xFFFFFFFFFFFFFFFF
+#define QTIMER_PHYS_AC_ADDR 0x17C90000
+#define QTIMER_CNTBASE_PHYS_ADDR 0x17CA0000
+#define QTIMER_CNTEL0BASE_PHYS_ADDR 0x17CB0000
+
+ACPI_GTDT Gtdt = {
+ //------------------------------------------------------------------------
+ // GTDT Header
+ //------------------------------------------------------------------------
+ ACPI_GTDT_SIGNATURE, // Signature (4 bytes)
+ sizeof(ACPI_GTDT), // Length (4 bytes)
+ ACPI_GTDT_REVISION, // Revision (1 byte)
+ 0x00, // Checksum calculated at runtime (1 byte)
+ ACPI_OEM_ID, // OEMID is a 6 bytes long field (6 bytes)
+ ACPI_OEM_TABLE_ID, // OEM table identification (8 bytes)
+ ACPI_OEM_REVISION, // OEM revision number (4 bytes)
+ ACPI_CREATOR_ID, // ASL compiler vendor ID (4 bytes)
+ ACPI_CREATOR_REVISION, // ASL compiler revision number (4 bytes)
+
+ //------------------------------------------------------------------------
+ // Content
+ //------------------------------------------------------------------------
+
+ UNSUPPORTED_ADDR, // CntControlBase Physical Address (8 bytes)
+ 0x0, // GlobalFlags - memory mapped, level (4 bytes)
+ 17, // SecurePL1GSIV (4 bytes)
+ 0x0, // SecurePL1Flags - level, active high (4 bytes)
+ 18, // NonSecurePL1GSIV (4 bytes)
+ 0x0, // NonSecurePL1Flags - level, active high (4 bytes)
+ 19, // VirtualGSIV (4 bytes)
+ 0, // VirtualFlags - level, active high (4 bytes)
+ 16, // NonSecurePL2GSIV - not really supported (4 bytes)
+ 0, // NonSecurePL2Flags - level, active high (4 bytes)
+
+ // ------------------------------------------------------------------------
+ // Platform timer definitions
+ // ------------------------------------------------------------------------
+
+ UNSUPPORTED_ADDR, // CntReadBase Phys Addr (8 bytes)
+ 1, // Platform Timer Count (4 bytes)
+ 96, // Platform timer offset (4 bytes)
+ {
+ {
+ 0, // GT block type (1 byte)
+ 60, // Length, 20 + n * 40 (2 bytes)
+ 0, // Reserved (1 byte)
+ QTIMER_PHYS_AC_ADDR, // Physical address for CntControlBase (8 bytes)
+ 1, // Number of timers (4 bytes)
+ 20, // Offset to the platform timer from start of this struct (4 bytes)
+
+ {{
+ 0, // Frame number (1 byte)
+ 0,0,0, // Reserved (3 bytes)
+ QTIMER_CNTBASE_PHYS_ADDR, // CntBase phys addr (8 bytes)
+ QTIMER_CNTEL0BASE_PHYS_ADDR, // CntEl0Base phys addr (8 bytes)
+ 39, // GSIV for physical timer (4 bytes)
+ 0, // Trigger for physical timer - Level High (4 bytes)
+ 38, // GSIV for virtual timer, 0 if not implemented (4 bytes)
+ 0, // Flags for virtual timer - Level High (4 bytes)
+ 2, // Common flags; 0x2 = always-on (4 bytes)
+ }}
+ }
+ }
+};
+
+#pragma pack(pop)
--- /dev/null
+#include "Platform.h"
+#define offsetof(s,m) (UINT64)&(((s *)0)->m)
+
+#pragma pack(1)
+typedef struct _INTERRUPT {
+ UINT32 GSIV;
+ UINT32 InterruptFlags;
+}INTERRUPT;
+
+
+
+typedef struct _SMMUV2NODE_SMMU_APPSTCU{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT64 BaseAddress;
+ UINT64 Span;
+ UINT32 Model;
+ UINT32 Flags;
+ UINT32 GlobalIntOffset;
+ UINT32 NumContextInterrupts;
+ UINT32 ContextIntOffset;
+ UINT32 NumPMUInterrupts;
+ UINT32 PMUIntOffset;
+ UINT32 NSGIRPT_GSIV;
+ UINT32 NSGIRPT_FLAGS;
+ UINT32 NSGCFGIRPT_GSIV;
+ UINT32 NSGCFGIRPT_FLAGS;
+ INTERRUPT ContextInterrupts[64];
+ INTERRUPT PMUInterrupts[8];
+}SMMUV2NODE_SMMU_APPSTCU;
+
+#define SMMUV2NODE_SMMU_APPSTCU_VAR { \
+ .Type = 3, \
+ .Length = sizeof(SMMUV2NODE_SMMU_APPSTCU), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 0, \
+ .MappingsOffset = 0, \
+ .BaseAddress = 0x15000000, \
+ .Span = 0x110000, \
+ .Model = 3, \
+ .Flags = 0, \
+ .GlobalIntOffset = offsetof(SMMUV2NODE_SMMU_APPSTCU,NSGIRPT_GSIV), \
+ .NumContextInterrupts = 64, \
+ .ContextIntOffset = offsetof(SMMUV2NODE_SMMU_APPSTCU,ContextInterrupts), \
+ .NumPMUInterrupts = 8, \
+ .PMUIntOffset = offsetof(SMMUV2NODE_SMMU_APPSTCU,PMUInterrupts), \
+ .NSGIRPT_GSIV = 97, \
+ .NSGIRPT_FLAGS = 0, \
+ .NSGCFGIRPT_GSIV = 261, \
+ .NSGCFGIRPT_FLAGS = 0, \
+ .ContextInterrupts ={ \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 128, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 129, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 130, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 131, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 132, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 133, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 134, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 135, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 136, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 137, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 138, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 139, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 140, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 141, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 142, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 143, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 144, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 145, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 146, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 147, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 148, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 149, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 150, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 213, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 214, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 215, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 216, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 217, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 218, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 219, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 220, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 221, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 222, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 223, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 224, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 347, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 348, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 349, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 350, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 351, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 352, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 353, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 354, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 355, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 356, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 357, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 358, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 359, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 360, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 361, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 362, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 363, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 364, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 365, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 366, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 367, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 368, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 369, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 370, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 371, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 372, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 373, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 374, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 375, \
+ }, \
+ }, \
+ .PMUInterrupts ={ \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 100, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 101, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 102, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 103, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 104, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 105, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 126, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 127, \
+ }, \
+ }, \
+}
+
+typedef struct _SMMUV2NODE_QSMMU_GPU{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT64 BaseAddress;
+ UINT64 Span;
+ UINT32 Model;
+ UINT32 Flags;
+ UINT32 GlobalIntOffset;
+ UINT32 NumContextInterrupts;
+ UINT32 ContextIntOffset;
+ UINT32 NumPMUInterrupts;
+ UINT32 PMUIntOffset;
+ UINT32 NSGIRPT_GSIV;
+ UINT32 NSGIRPT_FLAGS;
+ UINT32 NSGCFGIRPT_GSIV;
+ UINT32 NSGCFGIRPT_FLAGS;
+ INTERRUPT ContextInterrupts[8];
+ INTERRUPT PMUInterrupts[1];
+}SMMUV2NODE_QSMMU_GPU;
+
+#define SMMUV2NODE_QSMMU_GPU_VAR { \
+ .Type = 3, \
+ .Length = sizeof(SMMUV2NODE_QSMMU_GPU), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 0, \
+ .MappingsOffset = 0, \
+ .BaseAddress = 0x5040000, \
+ .Span = 0x10000, \
+ .Model = 1, \
+ .Flags = 0, \
+ .GlobalIntOffset = offsetof(SMMUV2NODE_QSMMU_GPU,NSGIRPT_GSIV), \
+ .NumContextInterrupts = 8, \
+ .ContextIntOffset = offsetof(SMMUV2NODE_QSMMU_GPU,ContextInterrupts), \
+ .NumPMUInterrupts = 1, \
+ .PMUIntOffset = offsetof(SMMUV2NODE_QSMMU_GPU,PMUInterrupts), \
+ .NSGIRPT_GSIV = 263, \
+ .NSGIRPT_FLAGS = 0, \
+ .NSGCFGIRPT_GSIV = 261, \
+ .NSGCFGIRPT_FLAGS = 0, \
+ .ContextInterrupts ={ \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 396, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 397, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 398, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 399, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 400, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 401, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 402, \
+ }, \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 403, \
+ }, \
+ }, \
+ .PMUInterrupts ={ \
+ { \
+ .InterruptFlags = 1, \
+ .GSIV = 225, \
+ }, \
+ }, \
+}
+
+typedef struct _SIDMAPPING {
+ UINT32 InputBase;
+ UINT32 NumIDs;
+ UINT32 OutputBase;
+ UINT32 OutputReference;
+ UINT32 Flags;
+}SIDMAPPING;
+
+
+
+typedef struct _PCIROOTCOMPLEX_PCI{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT64 MemAccessProps;
+ UINT32 ATSAttribute;
+ UINT32 PCISegmentNumber;
+ SIDMAPPING SIDMappings[2];
+}PCIROOTCOMPLEX_PCI;
+
+#define PCIROOTCOMPLEX_PCI_VAR { \
+ .Type = 2, \
+ .Length = sizeof(PCIROOTCOMPLEX_PCI), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 2, \
+ .MappingsOffset = offsetof(PCIROOTCOMPLEX_PCI,SIDMappings), \
+ .MemAccessProps = 0x0100000000000001, \
+ .ATSAttribute = 1, \
+ .PCISegmentNumber = 0, \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x87030000, \
+ .NumIDs = 0xF, \
+ .OutputBase = 0x1C00, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x87030010, \
+ .NumIDs = 0xF, \
+ .OutputBase = 0x1C10, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_GPU0{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[37];
+}NAMEDNODE_GPU0;
+
+#define NAMEDNODE_GPU0_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_GPU0), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 37, \
+ .MappingsOffset = offsetof(NAMEDNODE_GPU0,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 40, \
+ .DevObjectName = "\\_SB.GPU0", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x03030000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x0, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_qsmmu_gpu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x030A0000, \
+ .NumIDs = 0x1, \
+ .OutputBase = 0x1, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_qsmmu_gpu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x031C0000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x3, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_qsmmu_gpu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x03030001, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x4, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_qsmmu_gpu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x03030002, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x5, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_qsmmu_gpu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x03030003, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x7, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_qsmmu_gpu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x00030000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x880, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x00030001, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x888, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x00030002, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0xC80, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x00030003, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0xC88, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x06030004, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1090, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x04030000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10A0, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x04030001, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10A8, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x04030002, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10B0, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x000A0000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x881, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x000A0001, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x889, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x000A0002, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0xC81, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x000A0003, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0xC89, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x060A0004, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1091, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x040A0000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10A3, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x040A0001, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10AB, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x040A0002, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10A4, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x040A0003, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10AC, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x040A0004, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10B4, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x04090000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10A1, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x04090001, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10A5, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x04090002, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10A9, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x04090003, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10AD, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x040C0000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x10B2, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0C030000, \
+ .NumIDs = 3, \
+ .OutputBase = 0x704, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0c030004, \
+ .NumIDs = 1, \
+ .OutputBase = 0x708, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0C030006, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x712, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0C030007, \
+ .NumIDs = 0, \
+ .OutputBase = 0x71F, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0C030008, \
+ .NumIDs = 5, \
+ .OutputBase = 0x714, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0C03000E, \
+ .NumIDs = 1, \
+ .OutputBase = 0x71C, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0C090000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x71E, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0C090001, \
+ .NumIDs = 0, \
+ .OutputBase = 0x713, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_VFE0{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[33];
+}NAMEDNODE_VFE0;
+
+#define NAMEDNODE_VFE0_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_VFE0), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 33, \
+ .MappingsOffset = offsetof(NAMEDNODE_VFE0,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.GPU0.AVS0", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x01030000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1078, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x01030001, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x107A, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x01030002, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1070, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x01030003, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1020, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x01030004, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1028, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x01030005, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1040, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x01030006, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1048, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x01030007, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1030, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x01030008, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1050, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x01030009, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1038, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0103000A, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1058, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0103000B, \
+ .NumIDs = 0, \
+ .OutputBase = 0xC08, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0103000C, \
+ .NumIDs = 0, \
+ .OutputBase = 0xC10, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0103000D, \
+ .NumIDs = 0, \
+ .OutputBase = 0x808, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0103000E, \
+ .NumIDs = 0, \
+ .OutputBase = 0x810, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0103000F, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0xC18, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x01030010, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x818, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x01030011, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1000, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D0000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x809, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D0001, \
+ .NumIDs = 0, \
+ .OutputBase = 0x811, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D0002, \
+ .NumIDs = 0, \
+ .OutputBase = 0x819, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D0003, \
+ .NumIDs = 0, \
+ .OutputBase = 0xC09, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D0004, \
+ .NumIDs = 0, \
+ .OutputBase = 0xC11, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D0005, \
+ .NumIDs = 0, \
+ .OutputBase = 0xC19, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D0006, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1001, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D0007, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1021, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D0008, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1029, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D0009, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1031, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D000A, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1039, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D000B, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1041, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D000C, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1049, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D000D, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1051, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x010D000E, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1059, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_JPGE{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[2];
+}NAMEDNODE_JPGE;
+
+#define NAMEDNODE_JPGE_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_JPGE), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 2, \
+ .MappingsOffset = offsetof(NAMEDNODE_JPGE,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.JPGE", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x02030000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1060, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x02030001, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1068, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_ADCM{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[10];
+}NAMEDNODE_ADCM;
+
+#define NAMEDNODE_ADCM_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_ADCM), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 10, \
+ .MappingsOffset = offsetof(NAMEDNODE_ADCM,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.ADSP.SLM1.ADCM", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x07030000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1821, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x07030004, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1806, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x07030005, \
+ .NumIDs = 4, \
+ .OutputBase = 0x180D, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0703000A, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1813, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x07160000, \
+ .NumIDs = 0x5, \
+ .OutputBase = 0x1807, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x07160006, \
+ .NumIDs = 0x5, \
+ .OutputBase = 0x1800, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0716000C, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1812, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0716000D, \
+ .NumIDs = 0x6, \
+ .OutputBase = 0x1814, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x07060000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1820, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x071F0000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1822, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_URS0{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[1];
+}NAMEDNODE_URS0;
+
+#define NAMEDNODE_URS0_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_URS0), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 1, \
+ .MappingsOffset = offsetof(NAMEDNODE_URS0,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.URS0", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x80030000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x740, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_USB0{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[1];
+}NAMEDNODE_USB0;
+
+#define NAMEDNODE_USB0_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_USB0), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 1, \
+ .MappingsOffset = offsetof(NAMEDNODE_USB0,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.USB0", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x80030000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x740, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_URS1{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[1];
+}NAMEDNODE_URS1;
+
+#define NAMEDNODE_URS1_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_URS1), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 1, \
+ .MappingsOffset = offsetof(NAMEDNODE_URS1,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.URS1", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x80030001, \
+ .NumIDs = 0, \
+ .OutputBase = 0x760, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_USB1{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[1];
+}NAMEDNODE_USB1;
+
+#define NAMEDNODE_USB1_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_USB1), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 1, \
+ .MappingsOffset = offsetof(NAMEDNODE_USB1,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.USB1", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x80030001, \
+ .NumIDs = 0, \
+ .OutputBase = 0x760, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_CDSP{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[5];
+}NAMEDNODE_CDSP;
+
+#define NAMEDNODE_CDSP_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_CDSP), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 5, \
+ .MappingsOffset = offsetof(NAMEDNODE_CDSP,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.CDSP", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x830A0000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1409, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x84030000, \
+ .NumIDs = 0x5, \
+ .OutputBase = 0x1411, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x840A0000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1419, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0F1E0000, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x1420, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x0F2A0000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x142A, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_IPA{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[1];
+}NAMEDNODE_IPA;
+
+#define NAMEDNODE_IPA_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_IPA), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 1, \
+ .MappingsOffset = offsetof(NAMEDNODE_IPA,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.IPA", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x0B030000, \
+ .NumIDs = 2, \
+ .OutputBase = 0x720, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_QUP{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[4];
+}NAMEDNODE_QUP;
+
+#define NAMEDNODE_QUP_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_QUP), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 4, \
+ .MappingsOffset = offsetof(NAMEDNODE_QUP,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.QUP", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x10030000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x3, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x10030001, \
+ .NumIDs = 0, \
+ .OutputBase = 0x16, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x12030002, \
+ .NumIDs = 0, \
+ .OutputBase = 0x6C3, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x12030003, \
+ .NumIDs = 0, \
+ .OutputBase = 0x6D6, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_SEN1{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[4];
+}NAMEDNODE_SEN1;
+
+#define NAMEDNODE_SEN1_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_SEN1), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 4, \
+ .MappingsOffset = offsetof(NAMEDNODE_SEN1,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.SEN1", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x85030000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x6E3, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x85030001, \
+ .NumIDs = 2, \
+ .OutputBase = 0x7A1, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x85050000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x6EB, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x85050001, \
+ .NumIDs = 0, \
+ .OutputBase = 0x7A0, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_WLAN{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[3];
+}NAMEDNODE_WLAN;
+
+#define NAMEDNODE_WLAN_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_WLAN), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 3, \
+ .MappingsOffset = offsetof(NAMEDNODE_WLAN,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.AMSS.QWLN", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x11030000, \
+ .NumIDs = 1, \
+ .OutputBase = 0x40, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x11190000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x42, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x11180000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x43, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_UFS0{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[2];
+}NAMEDNODE_UFS0;
+
+#define NAMEDNODE_UFS0_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_UFS0), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 2, \
+ .MappingsOffset = offsetof(NAMEDNODE_UFS0,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.UFS0", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x81030000, \
+ .NumIDs = 0, \
+ .OutputBase = 0xE0, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x81030001, \
+ .NumIDs = 0, \
+ .OutputBase = 0x100, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_SDC2{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[2];
+}NAMEDNODE_SDC2;
+
+#define NAMEDNODE_SDC2_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_SDC2), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 2, \
+ .MappingsOffset = offsetof(NAMEDNODE_SDC2,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.SDC2", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x86030000, \
+ .NumIDs = 0xF, \
+ .OutputBase = 0xA0, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x86030010, \
+ .NumIDs = 0xF, \
+ .OutputBase = 0xC0, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_TSC5{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[1];
+}NAMEDNODE_TSC5;
+
+#define NAMEDNODE_TSC5_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_TSC5), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 1, \
+ .MappingsOffset = offsetof(NAMEDNODE_TSC5,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.TSC5", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x88030000, \
+ .NumIDs = 0xF, \
+ .OutputBase = 0x20, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_QDSS{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[1];
+}NAMEDNODE_QDSS;
+
+#define NAMEDNODE_QDSS_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_QDSS), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 1, \
+ .MappingsOffset = offsetof(NAMEDNODE_QDSS,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.QDSS", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x89030000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x460, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_ARPC{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[5];
+}NAMEDNODE_ARPC;
+
+#define NAMEDNODE_ARPC_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_ARPC), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 5, \
+ .MappingsOffset = offsetof(NAMEDNODE_ARPC,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.ARPC", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x1703000C, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1823, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x1703000D, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1824, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x17030000, \
+ .NumIDs = 5, \
+ .OutputBase = 0x1401, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x17030006, \
+ .NumIDs = 5, \
+ .OutputBase = 0x1421, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ { \
+ .InputBase = 0x170A0000, \
+ .NumIDs = 0, \
+ .OutputBase = 0x1429, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _NAMEDNODE_USBA{
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumberofMappings;
+ UINT32 MappingsOffset;
+ UINT32 NodeFlags;
+ UINT64 MemAccessProps;
+ UINT8 DeviceMemAddressSize;
+ UINT8 DevObjectName[32];
+ SIDMAPPING SIDMappings[1];
+}NAMEDNODE_USBA;
+
+#define NAMEDNODE_USBA_VAR { \
+ .Type = 1, \
+ .Length = sizeof(NAMEDNODE_USBA), \
+ .Revision = 0, \
+ .Reserved = 0, \
+ .NumberofMappings = 1, \
+ .MappingsOffset = offsetof(NAMEDNODE_USBA,SIDMappings), \
+ .NodeFlags = 0, \
+ .MemAccessProps = 0, \
+ .DeviceMemAddressSize = 36, \
+ .DevObjectName = "\\_SB.USBA", \
+ .SIDMappings ={ \
+ { \
+ .InputBase = 0x0703000B, \
+ .NumIDs = 0x0, \
+ .OutputBase = 0x182C, \
+ .OutputReference = offsetof(IORT,SMMUV2Nodes_smmu_appstcu), \
+ .Flags = 0, \
+ }, \
+ }, \
+}
+
+typedef struct _IORT{
+ UINT32 Signature;
+ UINT32 Length;
+ UINT8 Revision;
+ UINT8 Checksum;
+ UINT8 OEMID[6];
+ UINT64 OEMTableID;
+ UINT32 OEMRevision;
+ UINT32 CreatorID;
+ UINT32 CreatorRevision;
+ UINT32 NumberofIORTNodes;
+ UINT32 IORTNodesOffset;
+ UINT32 Reserved;
+ SMMUV2NODE_SMMU_APPSTCU SMMUV2Nodes_smmu_appstcu;
+ SMMUV2NODE_QSMMU_GPU SMMUV2Nodes_qsmmu_gpu;
+ PCIROOTCOMPLEX_PCI PCIRootComplexes_pci;
+ NAMEDNODE_GPU0 NamedNodes_gpu0;
+ NAMEDNODE_JPGE NamedNodes_jpge;
+ NAMEDNODE_VFE0 NamedNodes_vfe0;
+ NAMEDNODE_ADCM NamedNodes_adcm;
+ NAMEDNODE_URS0 NamedNodes_urs0;
+ NAMEDNODE_USB0 NamedNodes_usb0;
+ NAMEDNODE_URS1 NamedNodes_urs1;
+ NAMEDNODE_USB1 NamedNodes_usb1;
+ NAMEDNODE_CDSP NamedNodes_cdsp;
+ NAMEDNODE_IPA NamedNodes_ipa;
+ NAMEDNODE_QUP NamedNodes_qup;
+ NAMEDNODE_SEN1 NamedNodes_sen1;
+ NAMEDNODE_WLAN NamedNodes_wlan;
+ NAMEDNODE_UFS0 NamedNodes_ufs0;
+ NAMEDNODE_SDC2 NamedNodes_sdc2;
+ NAMEDNODE_TSC5 NamedNodes_tsc5;
+ NAMEDNODE_QDSS NamedNodes_qdss;
+ NAMEDNODE_ARPC NamedNodes_arpc;
+ NAMEDNODE_USBA NamedNodes_usba;
+}IORT;
+
+IORT IORT_TABLE = {
+ .Signature = 'TROI',
+ .Length = sizeof(IORT),
+ .Revision = 0,
+ .Checksum = 0,
+ .OEMID = ACPI_OEM_ID,
+ .OEMTableID = ACPI_OEM_TABLE_ID,
+ .OEMRevision = ACPI_OEM_REVISION,
+ .CreatorID = ACPI_CREATOR_ID,
+ .CreatorRevision = ACPI_CREATOR_REVISION,
+ .NumberofIORTNodes = 22,
+ .IORTNodesOffset = offsetof(IORT,Reserved)+4,
+ .Reserved = 0,
+ .SMMUV2Nodes_smmu_appstcu = SMMUV2NODE_SMMU_APPSTCU_VAR ,
+ .SMMUV2Nodes_qsmmu_gpu = SMMUV2NODE_QSMMU_GPU_VAR ,
+ .PCIRootComplexes_pci = PCIROOTCOMPLEX_PCI_VAR ,
+ .NamedNodes_gpu0 = NAMEDNODE_GPU0_VAR ,
+ .NamedNodes_jpge = NAMEDNODE_JPGE_VAR ,
+ .NamedNodes_vfe0 = NAMEDNODE_VFE0_VAR ,
+ .NamedNodes_adcm = NAMEDNODE_ADCM_VAR ,
+ .NamedNodes_urs0 = NAMEDNODE_URS0_VAR ,
+ .NamedNodes_usb0 = NAMEDNODE_USB0_VAR ,
+ .NamedNodes_urs1 = NAMEDNODE_URS1_VAR ,
+ .NamedNodes_usb1 = NAMEDNODE_USB1_VAR ,
+ .NamedNodes_cdsp = NAMEDNODE_CDSP_VAR ,
+ .NamedNodes_ipa = NAMEDNODE_IPA_VAR ,
+ .NamedNodes_qup = NAMEDNODE_QUP_VAR ,
+ .NamedNodes_sen1 = NAMEDNODE_SEN1_VAR ,
+ .NamedNodes_wlan = NAMEDNODE_WLAN_VAR ,
+ .NamedNodes_ufs0 = NAMEDNODE_UFS0_VAR ,
+ .NamedNodes_sdc2 = NAMEDNODE_SDC2_VAR ,
+ .NamedNodes_tsc5 = NAMEDNODE_TSC5_VAR ,
+ .NamedNodes_qdss = NAMEDNODE_QDSS_VAR ,
+ .NamedNodes_arpc = NAMEDNODE_ARPC_VAR ,
+ .NamedNodes_usba = NAMEDNODE_USBA_VAR ,
+};
+
+#pragma pack()
--- /dev/null
+#include "Platform.h"
+#include "Acpi.h"
+
+
+#define ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x00000005
+
+
+//
+// Local APIC GIC address
+// These are physical addresses on SDM850
+//
+#define DISTRIBUTOR_PHYSICAL_ADDRESS 0x17A00000
+#define APCS_QGICDR_QGICDR_GICA 0x17A10000
+#define APCS_QGICDR_QGICDR_GICR 0x17A60000
+
+//These addresses are defined by the MP shared region defined in the UEFI memory map.
+#define MP_MAILBOX_ADDRESS_GIC0 0x0
+#define MP_MAILBOX_ADDRESS_GIC1 0x0
+#define MP_MAILBOX_ADDRESS_GIC2 0x0
+#define MP_MAILBOX_ADDRESS_GIC3 0x0
+#define MP_MAILBOX_ADDRESS_GIC4 0x0
+#define MP_MAILBOX_ADDRESS_GIC5 0x0
+#define MP_MAILBOX_ADDRESS_GIC6 0x0
+#define MP_MAILBOX_ADDRESS_GIC7 0x0
+
+#define ACPI_PROCESSOR_LOCAL_GIC 11
+#define ACPI_GIC_DISTRIBUTOR 12
+#define ACPI_GIC_MSI_FRAME 13
+#define ACPI_GIC_REDISTRIBUTOR 14
+
+#define PLGF_ENABLED_BIT 0
+#define PLGF_ENABLED (1 << PLGF_ENABLED_BIT)
+
+#pragma pack (1)
+
+typedef struct _ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 Identifier;
+ UINT32 AcpiProcessorId;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsi;
+ UINT64 MailboxPhysicalAddress;
+ UINT64 ControllerPhysicalAddress;
+ UINT64 GICVirtual; // GIC virtual CPU interface registers.
+ UINT64 GICH; // GIC virtual interface control block registers.
+ UINT32 VGICMaintenanceInterrupt; // GVIS for Virtual GIC maintenance interrupt.
+ UINT64 GICRedistributorBaseAddress; // 64-bit address of the GIC Redistributor.
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass; // added towards ACPI 6
+ UINT8 Reserved2[3];
+} ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+typedef struct _ACPI_GIC_DISTRIBUTOR_STRUCTURE {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 Identifier;
+ UINT64 ControllerPhysicalAddress;
+ UINT32 GsivBase;
+ UINT8 GicVersion;
+ UINT32 Reserved;
+} ACPI_GIC_DISTRIBUTOR_STRUCTURE;
+
+typedef struct _ACPI_GIC_REDISTRIBUTOR_STRUCTURE {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 GICRedistributorPhysicalBaseAddress;
+ UINT32 GICRDiscoveryRangeLength;
+} ACPI_GIC_REDISTRIBUTOR_STRUCTURE;
+
+typedef struct _ACPI_GIC_MSI_FRAME_STRUCTURE {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 Identifier;
+ UINT64 ControllerPhysicalAddress;
+ UINT32 Flags;
+ UINT16 SPI_Count;
+ UINT16 SPI_Base;
+} ACPI_GIC_MSI_FRAME_STRUCTURE;
+
+typedef struct {
+ ACPI_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} APIC_DESCRIPTION_TABLE_HEADER;
+
+
+//
+// ACPI 5.0 MADT structure
+//
+typedef struct {
+
+ APIC_DESCRIPTION_TABLE_HEADER Header;
+ ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic0;
+ ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic1;
+ ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic2;
+ ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic3;
+ ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic4;
+ ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic5;
+ ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic6;
+ ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE LocalGic7;
+ ACPI_GIC_DISTRIBUTOR_STRUCTURE Distributor;
+ ACPI_GIC_REDISTRIBUTOR_STRUCTURE ReDistributor;
+ ACPI_GIC_MSI_FRAME_STRUCTURE MSIFrame0;
+} ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+
+#pragma pack(1)
+//
+// Multiple APIC Description Table
+//
+ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =
+{
+ //Header
+ {
+ {
+ ACPI_APIC_SIGNATURE, //Signature
+ sizeof (ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE), //Length
+ ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, //Revision
+ 0, //Checksum
+ ACPI_OEM_ID, //OEMID
+ ACPI_OEM_TABLE_ID, //OEMTableID
+ ACPI_OEM_REVISION, //OEMRevision
+ ACPI_CREATOR_ID, //CreatorID
+ ACPI_CREATOR_REVISION //CreatorRevision
+ },
+ 0x00000000, //LocalApicAddress
+ 0 //Flags
+ },
+
+ //LocalGic0
+ {
+ ACPI_PROCESSOR_LOCAL_GIC, //Type
+ sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length
+ 0x00, //Reserved
+ 0x00, //Identifier
+ 0x00, //AcpiProcessorId
+ PLGF_ENABLED, //Flags
+ 0x00, //ParkingProtocolVersion
+ (16 + 5), //PerformanceInterruptGsi
+ MP_MAILBOX_ADDRESS_GIC0, //MailboxPhysicalAddress
+ 0x0000000000000000, //ControllerPhysicalAddress
+ 0x0000000000000000, // GIC virtual CPU interface registers.
+ 0x0000000000000000, // GIC virtual interface control block registers.
+ 0x18, // GVIS for Virtual GIC maintenance interrupt.
+ 0x0000000000000000, // 64-bit address of the GIC Redistributor.
+ 0x0000000000000000, //MPIDR
+ 0x00, //ProcessorPowerEfficiencyClass
+ {0x00, 0x00, 0x00} //Reserved
+ },
+
+ //LocalGic1
+ {
+ ACPI_PROCESSOR_LOCAL_GIC, //Type
+ sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length
+ 0x00, //Reserved
+ 0x01, //Identifier
+ 0x01, //AcpiProcessorId
+ PLGF_ENABLED, //Flags
+ 0x00, //ParkingProtocolVersion
+ (16 + 5), //PerformanceInterruptGsi
+ MP_MAILBOX_ADDRESS_GIC1, //MailboxPhysicalAddress
+ 0x0000000000000000, //ControllerPhysicalAddress
+ 0x0000000000000000, // GIC virtual CPU interface registers.
+ 0x0000000000000000, // GIC virtual interface control block registers.
+ 0x18, // GVIS for Virtual GIC maintenance interrupt.
+ 0x0000000000000000, // 64-bit address of the GIC Redistributor.
+ 0x0000000000000100, //MPIDR
+ 0x00, //ProcessorPowerEfficiencyClass
+ {0x00, 0x00, 0x00} //Reserved
+ },
+
+ //LocalGic2
+ {
+ ACPI_PROCESSOR_LOCAL_GIC, //Type
+ sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length
+ 0x00, //Reserved
+ 0x02, //Identifier
+ 0x02, //AcpiProcessorId
+ PLGF_ENABLED, //Flags
+ 0x00, //ParkingProtocolVersion
+ (16 + 5), //PerformanceInterruptGsi
+ MP_MAILBOX_ADDRESS_GIC2, //MailboxPhysicalAddress
+ 0x0000000000000000, //ControllerPhysicalAddress
+ 0x0000000000000000, // GIC virtual CPU interface registers.
+ 0x0000000000000000, // GIC virtual interface control block registers.
+ 0x18, // GVIS for Virtual GIC maintenance interrupt.
+ 0x0000000000000000, // 64-bit address of the GIC Redistributor.
+ 0x0000000000000200, //MPIDR
+ 0x00, //ProcessorPowerEfficiencyClass
+ {0x00, 0x00, 0x00} //Reserved
+ },
+
+ //LocalGic3
+ {
+ ACPI_PROCESSOR_LOCAL_GIC, //Type
+ sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length
+ 0x00, //Reserved
+ 0x03, //Identifier
+ 0x03, //AcpiProcessorId
+ PLGF_ENABLED, //Flags
+ 0x0000, //ParkingProtocolVersion
+ (16 + 5), //PerformanceInterruptGsi
+ MP_MAILBOX_ADDRESS_GIC3, //MailboxPhysicalAddress
+ 0x0000000000000000, //ControllerPhysicalAddress
+ 0x0000000000000000, // GIC virtual CPU interface registers.
+ 0x0000000000000000, // GIC virtual interface control block registers.
+ 0x18, // GVIS for Virtual GIC maintenance interrupt.
+ 0x0000000000000000, // 64-bit address of the GIC Redistributor.
+ 0x0000000000000300, //MPIDR
+ 0x00, //ProcessorPowerEfficiencyClass
+ {0x00, 0x00, 0x00} //Reserved
+ },
+
+ //LocalGic4
+ {
+ ACPI_PROCESSOR_LOCAL_GIC, //Type
+ sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length
+ 0x00, //Reserved
+ 0x04, //Identifier
+ 0x04, //AcpiProcessorId
+ PLGF_ENABLED, //Flags
+ 0x00, //ParkingProtocolVersion
+ (16 + 5), //PerformanceInterruptGsi
+ MP_MAILBOX_ADDRESS_GIC4, //MailboxPhysicalAddress
+ 0x0000000000000000, //ControllerPhysicalAddress
+ 0x0000000000000000, // GIC virtual CPU interface registers.
+ 0x0000000000000000, // GIC virtual interface control block registers.
+ 0x18, // GVIS for Virtual GIC maintenance interrupt.
+ 0x0000000000000000, // 64-bit address of the GIC Redistributor.
+ 0x0000000000000400, //MPIDR
+ 0x01, //ProcessorPowerEfficiencyClass
+ {0x00, 0x00, 0x00} //Reserved
+ },
+
+ //LocalGic5
+ {
+ ACPI_PROCESSOR_LOCAL_GIC, //Type
+ sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length
+ 0x00, //Reserved
+ 0x05, //Identifier
+ 0x05, //AcpiProcessorId
+ PLGF_ENABLED, //Flags
+ 0x00, //ParkingProtocolVersion
+ (16 + 5), //PerformanceInterruptGsi
+ MP_MAILBOX_ADDRESS_GIC5, //MailboxPhysicalAddress
+ 0x0000000000000000, //ControllerPhysicalAddress
+ 0x0000000000000000, // GIC virtual CPU interface registers.
+ 0x0000000000000000, // GIC virtual interface control block registers.
+ 0x18, // GVIS for Virtual GIC maintenance interrupt.
+ 0x0000000000000000, // 64-bit address of the GIC Redistributor.
+ 0x0000000000000500, //MPIDR
+ 0x01, //ProcessorPowerEfficiencyClass
+ {0x00, 0x00, 0x00} //Reserved
+ },
+
+ //LocalGic6
+ {
+ ACPI_PROCESSOR_LOCAL_GIC, //Type
+ sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length
+ 0x00, //Reserved
+ 0x06, //Identifier
+ 0x06, //AcpiProcessorId
+ PLGF_ENABLED, //Flags
+ 0x00, //ParkingProtocolVersion
+ (16 + 5), //PerformanceInterruptGsi
+ MP_MAILBOX_ADDRESS_GIC6, //MailboxPhysicalAddress
+ 0x0000000000000000, //ControllerPhysicalAddress
+ 0x0000000000000000, // GIC virtual CPU interface registers.
+ 0x0000000000000000, // GIC virtual interface control block registers.
+ 0x18, // GVIS for Virtual GIC maintenance interrupt.
+ 0x0000000000000000, // 64-bit address of the GIC Redistributor.
+ 0x0000000000000600, //MPIDR
+ 0x01, //ProcessorPowerEfficiencyClass
+ {0x00, 0x00, 0x00} //Reserved
+ },
+
+ //LocalGic7
+ {
+ ACPI_PROCESSOR_LOCAL_GIC, //Type
+ sizeof (ACPI_PROCESSOR_LOCAL_APIC_STRUCTURE), //Length
+ 0x00, //Reserved
+ 0x07, //Identifier
+ 0x07, //AcpiProcessorId
+ PLGF_ENABLED, //Flags
+ 0x00, //ParkingProtocolVersion
+ (16 + 5), //PerformanceInterruptGsi
+ MP_MAILBOX_ADDRESS_GIC7, //MailboxPhysicalAddress
+ 0x0000000000000000, //ControllerPhysicalAddress
+ 0x0000000000000000, // GIC virtual CPU interface registers.
+ 0x0000000000000000, // GIC virtual interface control block registers.
+ 0x18, // GVIS for Virtual GIC maintenance interrupt.
+ 0x0000000000000000, // 64-bit address of the GIC Redistributor.
+ 0x0000000000000700, //MPIDR
+ 0x01, //ProcessorPowerEfficiencyClass
+ {0x00, 0x00, 0x00} //Reserved
+ },
+
+ //Distributor
+ {
+ ACPI_GIC_DISTRIBUTOR, //Type
+ sizeof (ACPI_GIC_DISTRIBUTOR_STRUCTURE), //Length
+ 0, //Reserved1
+ 0, //Identfier
+ DISTRIBUTOR_PHYSICAL_ADDRESS, //ControllerPhysicalAddress
+ 0, //GsivBase
+ 3, //GicVersion
+ 0 //Reserved
+ },
+
+ //ReDistributor
+ {
+ ACPI_GIC_REDISTRIBUTOR, //Type
+ sizeof (ACPI_GIC_REDISTRIBUTOR_STRUCTURE), //Length
+ 0, //Reserved
+ APCS_QGICDR_QGICDR_GICR, //RedistributorPhysicalAddress
+ 0x100000 //Length
+ },
+
+ //MSI Frame0//
+ {
+ ACPI_GIC_MSI_FRAME, //Type
+ sizeof (ACPI_GIC_MSI_FRAME_STRUCTURE), //Length
+ 0x0, //Reserved1
+ 0x0, //Identfier
+ APCS_QGICDR_QGICDR_GICA, //ControllerPhysicalAddress
+ 0x1, //Flags
+ 0x40, //SPI_Count
+ 0x2A0 //SPI_Base
+ }
+};
+#pragma pack()
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Madt;
+}
+
--- /dev/null
+#include "Platform.h"
+#include <ACPI.h>
+
+#pragma pack(push, 1)
+
+typedef struct
+{
+ UINT64 BASE_ADDRESS ;
+ UINT16 PCI_SEGMENT_GROUP_NUMBER;
+ UINT8 START_BUS_NUMBER;
+ UINT8 END_BUS_NUMBER;
+ UINT32 RESERVED;
+} MEMORY_MAPPED_CONFIG_BASE_ADDRESS;
+
+typedef struct
+{
+ ACPI_HEADER Header ;
+ UINT64 Reserved ;
+ MEMORY_MAPPED_CONFIG_BASE_ADDRESS Buses[2];
+}ENHANCED_CONFIGURATION_SPACE_ACCESS;
+
+
+ENHANCED_CONFIGURATION_SPACE_ACCESS MCFG ={
+ {
+ ACPI_MCFG_SIGNATURE,
+ sizeof (ENHANCED_CONFIGURATION_SPACE_ACCESS),
+ 1,
+ 0, // to make sum of entire table == 0,
+ ACPI_OEM_ID,
+ ACPI_OEM_TABLE_ID,
+ ACPI_OEM_REVISION,
+ ACPI_CREATOR_ID,
+ ACPI_CREATOR_REVISION
+ },
+ 0x0, // reserved
+ {
+ {
+ 0x0000000060000000, //PCIE_0_PCIE20_DBI
+ 0, //PCI Segment Group Number
+ 0, //Start Bus Number
+ 1, // End Bus Number
+ 0x0, //Reserved
+ },
+ {
+ 0x0000000040000000, //PCIE_1_GEN3_DBI
+ 1, //PCI Segment Group Number
+ 0, //Start Bus Number
+ 1, // End Bus Number
+ 0x0, //Reserved
+ }
+ }
+};
+#pragma pack(pop)
+
+
--- /dev/null
+#include "Platform.h"
+#include "Acpi.h"
+
+#define ACPI_PROCESSOR_PROPERTIES_DESCRIPTION_TABLE_REVISION 0x00000001
+
+
+//
+// Types defined for Node/Cache/Id Type from Document
+//
+
+#define offsetof(s,m) (UINT32)&(((s *)0)->m)
+
+#define ACPI_PROCESSOR_NODE 0
+#define ACPI_CACHE_TYPE 1
+#define ACPI_ID_TYPE 2
+
+#pragma pack (1)
+
+typedef struct _ACPI_CACHE_TYPE_STRUCTURE { // 5-152
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 Flags;
+ UINT32 NextLevelCache;
+ UINT32 Size;
+ UINT32 NumOfSets;
+ UINT8 Associativity;
+ UINT8 Attributes;
+ UINT16 LineSize;
+} ACPI_CACHE_TYPE_STRUCTURE;
+
+typedef struct _ACPI_PROCESSOR_NODE_STRUCTURE { // 5-150
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 Flags;
+ UINT32 Parent; // may not be required (container concept)
+ UINT32 AcpiProcessorId;
+ UINT32 numPrivateResources;
+ UINT32 localCacheL1D;
+ UINT32 LocalCacheL1I;
+} ACPI_PROCESSOR_NODE_STRUCTURE;
+
+typedef struct _ACPI_ID_TYPE_STRUCTURE { // Table 5-154
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 vendorId;
+ UINT64 level1Id;
+ UINT64 level2Id;
+ UINT16 majorRev;
+ UINT16 minorRev;
+ UINT16 spinRev;
+} ACPI_ID_TYPE_STRUCTURE;
+
+typedef struct _ACPI_PROCESSOR_NODE_STRUCTURE_L3 { // dummy node which has L3 as next cache
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 Flags;
+ UINT32 Parent; // may not be required (container concept)
+ UINT32 AcpiProcessorId;
+ UINT32 numPrivateResources;
+ UINT32 CommonCacheL3;
+ UINT32 SocId;
+} ACPI_PROCESSOR_NODE_STRUCTURE_L3;
+
+//
+// ACPI 5.0 PPTT structure
+//
+typedef struct {
+ ACPI_HEADER Header;
+ ACPI_CACHE_TYPE_STRUCTURE localCacheL3U;
+ ACPI_ID_TYPE_STRUCTURE SocId;
+ ACPI_PROCESSOR_NODE_STRUCTURE_L3 NodeForL3;
+ ACPI_CACHE_TYPE_STRUCTURE localCacheL2U;
+ ACPI_CACHE_TYPE_STRUCTURE localCacheL1D;
+ ACPI_CACHE_TYPE_STRUCTURE localCacheL1I;
+ ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt0;
+ ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt1;
+ ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt2;
+ ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt3;
+ ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt4;
+ ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt5;
+ ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt6;
+ ACPI_PROCESSOR_NODE_STRUCTURE LocalPpt7;
+} ACPI_PROC_TOPOLOGY_TABLE;
+
+//
+//
+// PPTT Description Table
+//
+ACPI_PROC_TOPOLOGY_TABLE Pptt =
+{
+ // Header
+ {
+ ACPI_PPTT_SIGNATURE, //Signature
+ sizeof (ACPI_PROC_TOPOLOGY_TABLE), //Length
+ ACPI_PROCESSOR_PROPERTIES_DESCRIPTION_TABLE_REVISION, //Revision
+ 0, //Checksum
+ ACPI_OEM_ID, //OEMID
+ ACPI_OEM_TABLE_ID, //OEMTableID
+ ACPI_OEM_REVISION, //OEMRevision
+ ACPI_CREATOR_ID, //CreatorID
+ ACPI_CREATOR_REVISION //CreatorRevision
+ },
+
+ // L3 Cache Details
+ {
+ ACPI_CACHE_TYPE, // Type;
+ sizeof (ACPI_CACHE_TYPE_STRUCTURE), // Length;
+ 0, // Reserved;
+ 0, // flags
+ 0, // NextLevelCache
+ 0, // Size;
+ 0, // NumOfSets;
+ 0, // Associativity
+ 0, // Attributes
+ 0, // LineSize;
+ },
+
+ // id type structure
+ {
+ ACPI_ID_TYPE, // Type
+ sizeof (ACPI_ID_TYPE_STRUCTURE), // Length;
+ 0, // Reserved;
+ 0, // vendorId;
+ 0, // level1Id;
+ 0, // level2Id;
+ 0, // majorRev;
+ 0, // minorRev;
+ 0, // spinRev;
+ },
+
+ // L3 Node
+ {
+ ACPI_PROCESSOR_NODE, // type
+ sizeof (ACPI_PROCESSOR_NODE_STRUCTURE_L3), // length
+ 0x00, // Reserved
+ 0x01, // Flags
+ 0, // Parent
+ 0x00, // AcpiProcessorId
+ 2, // numPrivateResources
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL3U),
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, SocId),
+ },
+
+ // L2 unified Cache
+ {
+ ACPI_CACHE_TYPE, // Type
+ sizeof (ACPI_CACHE_TYPE_STRUCTURE), // Length
+ 0x00, // Reserved
+ 0, // flags
+ 0, // NextLevelCache
+ 0, // Size
+ 0, // NumOfSets
+ 0, // Associativity
+ 0, // Attributes
+ 0, // LineSize
+ },
+
+ // L1 Data Cache
+ {
+ ACPI_CACHE_TYPE, // Type
+ sizeof (ACPI_CACHE_TYPE_STRUCTURE), // Length
+ 0x00, // Reserved
+ 0, // flags
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL2U), // NextLevelCache
+ 0, // Size
+ 0, // NumOfSets
+ 0, // Associativity
+ 0, // Attributes
+ 0, // LineSize
+ },
+
+ // L1 Instruction Cache
+ {
+ ACPI_CACHE_TYPE, // Type
+ sizeof (ACPI_CACHE_TYPE_STRUCTURE), // Length
+ 0x00, // Reserved
+ 0, // flags
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL2U), // NextLevelCache
+ 0, // Size
+ 0, // NumOfSets
+ 0, // Associativity
+ 0, // Attributes
+ 0, // LineSize
+ },
+
+ // LocalPpt0
+ {
+ ACPI_PROCESSOR_NODE, // Type
+ sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length
+ 0x00, // Reserved
+ 0x02, // Flags
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent
+ 0x00, // AcpiProcessorId
+ 2, // numPrivateResources
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D),
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I),
+ },
+
+ // LocalPpt1
+ {
+ // node structure
+ ACPI_PROCESSOR_NODE, // Type
+ sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length
+ 0x00, // Reserved
+ 0x02, // Flags
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent
+ 0x01, // AcpiProcessorId
+ 2, // numPrivateResources
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D),
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I),
+ },
+
+ // LocalPpt2
+ {
+ // node structure
+ ACPI_PROCESSOR_NODE, // Type
+ sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length
+ 0x00, // Reserved
+ 0x02, // Flags
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent
+ 0x02, // AcpiProcessorId
+ 2, // numPrivateResources
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D),
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I),
+ },
+
+ // LocalPpt3
+ {
+ // node structure
+ ACPI_PROCESSOR_NODE, // Type
+ sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length
+ 0x00, // Reserved
+ 0x02, // Flags
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent
+ 0x03, // AcpiProcessorId
+ 2, // numPrivateResources
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D),
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I),
+ },
+
+ // LocalPpt4
+ {
+ // node structure
+ ACPI_PROCESSOR_NODE, // Type
+ sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length
+ 0x00, // Reserved
+ 0x02, // Flags
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent
+ 0x04, // AcpiProcessorId
+ 2, // numPrivateResources
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D),
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I),
+ },
+
+ // LocalPpt5
+ {
+ // node structure
+ ACPI_PROCESSOR_NODE, // Type
+ sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length
+ 0x00, // Reserved
+ 0x02, // Flags
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent
+ 0x05, // AcpiProcessorId
+ 2, // numPrivateResources
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D),
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I),
+ },
+
+ // LocalPpt6
+ {
+ // node structure
+ ACPI_PROCESSOR_NODE, // Type
+ sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length
+ 0x00, // Reserved
+ 0x02, // Flags
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent
+ 0x06, // AcpiProcessorId
+ 2, // numPrivateResources
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D),
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I),
+ },
+
+ // LocalPpt7
+ {
+ // node structure
+ ACPI_PROCESSOR_NODE, // Type
+ sizeof (ACPI_PROCESSOR_NODE_STRUCTURE), // Length
+ 0x00, // Reserved
+ 0x02, // Flags
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, NodeForL3), // Parent
+ 0x07, // AcpiProcessorId
+ 2, // numPrivateResources
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1D),
+ offsetof(ACPI_PROC_TOPOLOGY_TABLE, localCacheL1I),
+ },
+};
+
+#pragma pack()
+
+VOID*
+ReferenceAcpiTable (VOID)
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Pptt;
+}
\ No newline at end of file
//===========================================================================
-// <qdss.asl>
+// <Qdss.asl>
// DESCRIPTION
// This file contans the resources needed by qdss driver.
//
-//
//===========================================================================
-// You won't have qdss on your phone xD
-
+//
+// Disable QDSS device
+//
--- /dev/null
+//
+// Secure Channel Manager (SCM) Driver
+//
+Device (SCM0)
+{
+ Name (_HID, "QCOM0214")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 0)
+}
+
+//
+// TrEE Driver
+//
+Device (TREE)
+{
+ Name (_HID, "QCOM02BB")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 0)
+
+ Method (IMPT)
+ {
+ Name(TPPK, Package()
+ {
+ Package ()
+ {
+ // Holds whether TPM is seperate app or not
+ 0x00000000, // Will be filled by TPMA
+ // Holds TPM type
+ 0x00000000, // Will be filled by TDTV
+ // Holds TrEE Carveout address
+ 0x00000000, // Will be filled by TCMA
+ // Holds TrEE Carveout length
+ 0x00000000 // Will be filled by TCML
+ }
+ })
+
+ // Copy ACPI globals for Address for this subsystem into above package for use in driver
+ Store (TPMA, Index(DeRefOf(Index (TPPK, 0)), 0))
+ Store (TDTV, Index(DeRefOf(Index (TPPK, 0)), 1))
+ Store (TCMA, Index(DeRefOf(Index (TPPK, 0)), 2))
+ Store (TCML, Index(DeRefOf(Index (TPPK, 0)), 3))
+
+ Return (TPPK)
+ }
+}
Name (_DEP, Package(0x3)
{
\_SB_.MMU0,
- \_SB_.GLNK,
- \_SB_.SCM0
+ \_SB_.GLNK,
+ \_SB_.SCM0
})
Name (_HID, "QCOM0297")
- Alias(\_SB.PSUB, _SUB)
+ Alias(\_SB.PSUB, _SUB)
}
// ARPD AUDIO Daemon Driver
Device (ARPD)
\_SB_.ADSP,
\_SB_.ARPC
})
- Name (_HID, "QCOM02F3")
- Alias(\_SB.PSUB, _SUB)
+ Name (_HID, "QCOM02F3")
+ Alias(\_SB.PSUB, _SUB)
}
//
//===========================================================================
-
-
Scope(\_SB_.PEP0)
{
--- /dev/null
+//===========================================================================
+// <corebsp_resources.asl>
+// DESCRIPTION
+// This file contans the resources needed by core BSP drivers.
+//
+//===========================================================================
+
+
+Scope(\_SB_.PEP0)
+{
+
+ Method(BPMD)
+ {
+ Return(BPCC)
+ }
+
+ Method(LPMD)
+ {
+ Return(LPCC)
+ }
+
+ Name(BPCC,
+ Package ()
+ {
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.UFS0",
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0.
+ Package()
+ {
+ "FSTATE",
+ 0x0, // f0 state
+ Package() { "PSTATE_ADJUST", Package() { 0, 0 } },
+ Package() { "PSTATE_ADJUST", Package() { 1, 0 } },
+ Package() { "PSTATE_ADJUST", Package() { 2, 0 } },
+ },
+ Package()
+ {
+ "FSTATE",
+ 0x1, // f1 state
+ Package() { "PSTATE_ADJUST", Package() { 2, 1 } },
+ Package() { "PSTATE_ADJUST", Package() { 1, 1 } },
+ Package() { "PSTATE_ADJUST", Package() { 0, 1 } },
+ },
+
+ Package()
+ {
+ "PSTATE_SET",
+ 0x0,
+
+ Package()
+ {
+ "PSTATE",
+ 0x0,
+ Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 1 }},
+ },
+ Package()
+ {
+ "PSTATE",
+ 0x1,
+ Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 2 }},
+ },
+ },
+
+ Package()
+ {
+ "PSTATE_SET",
+ 0x1,
+
+ Package()
+ {
+ "PSTATE",
+ 0x0,
+
+ Package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 8, 200000000, 2}},
+ package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 8, 150000000, 2}},
+ package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 8, 300000000, 2}},
+
+ Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 1,}},
+ Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 1,}},
+ Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 1,}},
+ Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 1,}},
+ Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 1,}},
+ Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 1,}},
+ Package() {"CLOCK", Package() {"gcc_ufs_mem_clkref_en", 1,}},
+ },
+ Package()
+ {
+ "PSTATE",
+ 0x1,
+
+ Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 2,}},
+ Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 2,}},
+ Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 2,}},
+ Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 2,}},
+ Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 2,}},
+ Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 2,}},
+ package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 2,}},
+ package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 2,}},
+ package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 2,}},
+ package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 2,}},
+ },
+ },
+
+ Package()
+ {
+ "PSTATE_SET",
+ 0x2,
+
+ Package()
+ {
+ "PSTATE",
+ 0x0,
+ Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 900000000, 900000000}},
+ Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 299000000, 0}},
+ },
+ Package()
+ {
+ "PSTATE",
+ 0x1,
+ Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 0, 0}},
+ Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 0, 0}},
+ },
+ },
+ },
+
+ Package()
+ {
+ "DSTATE",
+ 0x0, // D0 state
+
+ Package() {"PSTATE_ADJUST", Package() { 2, 0 } },
+
+ Package() {"PSTATE_ADJUST", Package() { 0, 0 } },
+
+ // Vcc supply = L20
+ Package()
+ {
+ "PMICVREGVOTE",
+ Package()
+ {
+ "PPP_RESOURCE_ID_LDO20_A", // VREG ID
+ 1, // Voltage Regulator type = LDO
+ 2960000, // Voltage is in micro volts
+ 1, // force enable from software
+ 7, // power mode - Normal Power Mode
+ 0, // head room voltage
+ },
+ },
+
+ // Vccq supply = L2
+ Package()
+ {
+ "PMICVREGVOTE",
+ Package()
+ {
+ "PPP_RESOURCE_ID_LDO2_A", // VREG ID
+ 1, // Voltage Regulator type = LDO
+ 1200000, // Voltage is in micro volts
+ 1, // force enable from software
+ 7, // power mode - Normal Power Mode
+ 0, // head room voltage
+ },
+ },
+
+ // Vccq2 supply = S4
+ Package()
+ {
+ "PMICVREGVOTE",
+ Package()
+ {
+ "PPP_RESOURCE_ID_SMPS4_A",
+ 2, // Voltage Regulator type = SMPS
+ 1800000, // 1.8V
+ 1, // Force enable from software
+ 0, // Power mode - AUTO
+ 0, // head room voltage
+ },
+ },
+
+ // PHY VDDA supply: L26
+ Package()
+ {
+ "PMICVREGVOTE",
+ Package()
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // VREG ID
+ 1, // Voltage Regulator type = LDO
+ 1200000, // Voltage is in micro volts
+ 1, // force enable from software
+ 7, // power mode - Normal Power Mode
+ 0, // head room voltage
+ },
+ },
+
+ // VDDA_UFS_CORE supply: L1
+ Package()
+ {
+ "PMICVREGVOTE",
+ Package()
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // VREG ID
+ 1, // Voltage Regulator type = LDO
+ 880000, // Voltage is in micro volts
+ 1, // force enable from software
+ 7, // power mode - Normal Power Mode
+ 0, // head room voltage
+ },
+ },
+
+ Package() {"DELAY", package() { 35 }},
+
+ Package() {"PSTATE_ADJUST", Package() { 1, 0 } },
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x3, // D3 state
+
+ Package() {"PSTATE_ADJUST", Package() { 1, 1 } },
+
+ Package()
+ {
+ "PMICVREGVOTE",
+ Package()
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // VREG ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage is in micro volts
+ 0, // force enable from software
+ 0, // power mode - Normal Power Mode
+ 0, // head room voltage
+ },
+ },
+
+ Package()
+ {
+ "PMICVREGVOTE",
+ Package()
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // VREG ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage is in micro volts
+ 0, // force enable from software
+ 0, // power mode - Normal Power Mode
+ 0, // head room voltage
+ },
+ },
+
+ Package()
+ {
+ "PMICVREGVOTE",
+ Package()
+ {
+ "PPP_RESOURCE_ID_LDO20_A", // VREG ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage is in micro volts
+ 0, // force enable from software
+ 0, // power mode - Normal Power Mode
+ 0, // head room voltage
+ },
+ },
+
+ Package() {"PSTATE_ADJUST", Package() { 0, 1 } },
+
+ Package() {"PSTATE_ADJUST", Package() { 2, 1 } },
+ },
+ },
+
+ // No sdcard
+
+ // Package()
+ // {
+ // "DEVICE",
+ // "\\_SB.SDC2",
+ // Package()
+ // {
+ // "COMPONENT",
+ // 0x0, // Component 0.
+ // Package()
+ // {
+ // "FSTATE",
+ // 0x0, // f0 state
+ // },
+ // Package()
+ // {
+ // "FSTATE",
+ // 0x1, // f1 state
+ // },
+
+ // Package()
+ // {
+ // "PSTATE_SET",
+ // 0x0,
+
+ // //
+ // // Contract with SDBUS for card frequencies
+ // //
+ // // P-State Note
+ // // -------- -----
+ // // 0 - 19 Reserved (Legacy)
+ // // 20 Reset to 3.3v signal voltage (max fixed at 2.95v)
+ // // 21 1.8v signal voltage (max fixed at 1.85v)
+ // Package(){"PSTATE", 0, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 1, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 2, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 3, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 4, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 5, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 6, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 7, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 8, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 9, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 11, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 12, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 13, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 14, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 15, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 16, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 17, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 18, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 19, Package(){"DELAY", package() { 1 }}},
+ // Package(){"PSTATE", 20,
+ // Package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // Package()
+ // {
+ // "PPP_RESOURCE_ID_LDO21_A", // VREG ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage is in micro volts
+ // 0, // force disable from software
+ // 0, // power mode - Low Power Mode
+ // 0, // head room voltage
+ // },
+ // },
+ // Package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // Package()
+ // {
+ // "PPP_RESOURCE_ID_LDO13_A", // VREG ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage is in micro volts
+ // 0, // force disable from software
+ // 0, // power mode - Low Power Mode
+ // 0, // head room voltage
+ // },
+ // },
+ // Package() {"DELAY", package() { 35 }},
+ // Package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // Package()
+ // {
+ // "PPP_RESOURCE_ID_LDO21_A", // VREG ID
+ // 1, // Voltage Regulator type = LDO
+ // 2960000, // Voltage is in micro volts
+ // 1, // force enable from software
+ // 7, // power mode - Normal Power Mode
+ // 0, // head room voltage
+ // },
+ // },
+ // Package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // Package()
+ // {
+ // "PPP_RESOURCE_ID_LDO13_A", // VREG ID
+ // 1, // Voltage Regulator type = LDO
+ // 2960000, // Voltage is in micro volts
+ // 1, // force enable from software
+ // 7, // power mode - Normal Power Mode
+ // 0, // head room voltage
+ // },
+ // },
+ // Package() {"DELAY", package() { 35 }},
+ // },
+ // Package(){"PSTATE", 21,
+ // Package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // Package()
+ // {
+ // "PPP_RESOURCE_ID_LDO13_A", // VREG ID
+ // 1, // Voltage Regulator type = LDO
+ // 1850000, // Voltage is in micro volts
+ // 1, // force enable from software
+ // 7, // power mode - Normal Power Mode
+ // 0, // head room voltage
+ // },
+ // },
+ // Package() {"DELAY", package() { 35 }},
+ // },
+ // Package(){"PSTATE", 22,
+ // Package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // Package()
+ // {
+ // "PPP_RESOURCE_ID_LDO21_A", // VREG ID
+ // 1, // Voltage Regulator type = LDO
+ // 2960000, // Voltage is in micro volts
+ // 1, // force enable from software
+ // 7, // power mode - Normal Power Mode
+ // 0, // head room voltage
+ // },
+ // },
+ // Package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // Package()
+ // {
+ // "PPP_RESOURCE_ID_LDO13_A", // VREG ID
+ // 1, // Voltage Regulator type = LDO
+ // 2960000, // Voltage is in micro volts
+ // 1, // force enable from software
+ // 7, // power mode - Normal Power Mode
+ // 0, // head room voltage
+ // },
+ // },
+ // Package() {"DELAY", package() { 35 }},
+ // },
+ // Package(){"PSTATE", 23,
+ // Package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // Package()
+ // {
+ // "PPP_RESOURCE_ID_LDO21_A", // VREG ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage is in micro volts
+ // 0, // force disable from software
+ // 0, // power mode - Low Power Mode
+ // 0, // head room voltage
+ // },
+ // },
+ // Package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // Package()
+ // {
+ // "PPP_RESOURCE_ID_LDO13_A", // VREG ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage is in micro volts
+ // 0, // force disable from software
+ // 0, // power mode - Low Power Mode
+ // 0, // head room voltage
+ // },
+ // },
+ // Package() {"DELAY", package() { 35 }},
+ // },
+ // },
+
+ // // P-state set 1: APPS Clock frequencies
+ // // 0: Disable
+ // // 1: 20 MHz (SVS2)
+ // // 2: 100 MHz (SVS)
+ // // 3: 201.5 MHz (Nominal)
+ // Package()
+ // {
+ // "PSTATE_SET",
+ // 0x1,
+
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x0,
+ // package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 2}},
+ // },
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x1,
+ // package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 20000000, 2}},
+ // },
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x2,
+ // package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 100000000, 2}},
+ // },
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x3,
+ // package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 201500000, 2}},
+ // },
+ // },
+
+ // // P-state set 2: Bus Bandwidth requests
+ // // P0: IB = 400 MBps, AB = 200 MBps
+ // // P1: IB = 200 MBps, AB = 100 MBps
+ // // P2: IB = 40 MBps, AB = 20 MBps
+ // // P3: IB = 0 MBps, AB = 0 MBps
+ // Package()
+ // {
+ // "PSTATE_SET",
+ // 0x2,
+
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x0,
+ // package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 400000000, 200000000}},
+ // },
+
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x1,
+ // package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 200000000, 100000000}},
+ // },
+
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x2,
+ // package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 40000000, 20000000}},
+ // },
+
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x3,
+ // package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 0, 0}},
+ // },
+ // },
+
+ // // P-state set 3: MSFT P-states
+ // // P0: Clk = 200 MHz, IB = 400 MBps, AB = 200 MBps
+ // // P1: Clk = 100 MHz, IB = 200 MBps, AB = 100 MBps
+ // // P2: Clk = 20 MHz, IB = 40 MBps, AB = 20 MBps
+ // Package()
+ // {
+ // "PSTATE_SET",
+ // 0x3,
+
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x0,
+ // Package() { "PSTATE_ADJUST", Package() { 1, 3 } },
+ // Package() { "PSTATE_ADJUST", Package() { 2, 0 } },
+ // },
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x1,
+ // Package() { "PSTATE_ADJUST", Package() { 1, 2 } },
+ // Package() { "PSTATE_ADJUST", Package() { 2, 1 } },
+ // },
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x2,
+ // Package() { "PSTATE_ADJUST", Package() { 1, 1 } },
+ // Package() { "PSTATE_ADJUST", Package() { 2, 2 } },
+ // },
+ // },
+
+
+ // // P-state set 4: AHB clock
+ // Package()
+ // {
+ // "PSTATE_SET",
+ // 0x4,
+
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x0,
+ // package() {"CLOCK", package() {"gcc_sdcc2_ahb_clk", 1,}}, // AHB freq should be 100 MHz
+ // },
+ // Package()
+ // {
+ // "PSTATE",
+ // 0x1,
+ // package() {"CLOCK", package() {"gcc_sdcc2_ahb_clk", 2}},
+ // },
+ // },
+ // },
+
+ // Package()
+ // {
+ // "DSTATE",
+ // 0x0, // D0 state
+
+ // Package() {"PSTATE_ADJUST", Package () { 0, 22 }},
+ // package() {"TLMMPORT", package() { 0x99A000, 0x7FFF, 0x1FE4 }},
+ // Package() {"PSTATE_ADJUST", Package() { 2, 0 }},
+ // Package() {"PSTATE_ADJUST", Package() { 4, 0 }},
+ // Package() {"PSTATE_ADJUST", Package() { 1, 3 }},
+ // },
+ // Package()
+ // {
+ // "DSTATE",
+ // 0x3, // D3 state
+
+ // Package() {"PSTATE_ADJUST", Package() { 1, 0 }},
+ // Package() {"PSTATE_ADJUST", Package() { 4, 1 }},
+ // Package() {"PSTATE_ADJUST", Package() { 2, 3 }},
+ // package() {"TLMMPORT", package() { 0x99A000, 0x7FFF, 0xA00 }},
+ // Package() {"PSTATE_ADJUST", Package () { 0, 23 }},
+ // },
+ // },
+ ///////////////////////////////////////////////////////////////////////////////////////
+
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.ADSP.SLM1",
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0
+ Package()
+ {
+ "FSTATE",
+ 0x0, // f0 state
+ },
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x0, // D0 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x1, // D1 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x2, // D2 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x3, // D3 state
+ },
+ },
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.ADSP.SLM2",
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0
+ Package()
+ {
+ "FSTATE",
+ 0x0, // f0 state
+ },
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x0, // D0 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x1, // D1 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x2, // D2 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x3, // D3 state
+ },
+ },
+ /////////////////////////////////////////////////////////////////////////////////////
+ })
+
+ Name(LPCC,
+ package ()
+ {
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.UCP0",
+ Package()
+ {
+ "COMPONENT",0, //Component 0: USB HS Rails for Charger Detection
+ Package(){"FSTATE", 0 }, //Dummy F-State, required for P-State operation
+ Package()
+ {
+ "PSTATE", 0, // P0 state - Component ON
+ //Nominal==block vdd_min:
+ package()
+ {
+ "NPARESOURCE",
+ Package() {1, "/arc/client/rail_cx", 256}
+ },
+ // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ //BUS Arbiter Request (Type-3)
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 400000000, // IB=400 MBps
+ 0 // AB=0 MBps
+ }
+ },
+ // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
+ },
+ Package()
+ {
+ "PSTATE", 1, // P1 state - Component OFF
+ // Remove Vote for CNOC 100 MHz
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // BUS Arbiter Request (Type-3)
+ // Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 0, // IB=0 MBps
+ 0 // AB=0 MBps
+ }
+ },
+
+ // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+ //Enable vdd_min:
+ package()
+ {
+ "NPARESOURCE",
+ Package() {1, "/arc/client/rail_cx", 0}
+ },
+
+ },
+ },
+ //D states
+ package() {
+ "DSTATE", 0x0, // D0 state
+ },
+ package() {
+ "DSTATE", 0x1, // D1 state
+ },
+ package() {
+ "DSTATE", 0x2, // D2 state
+ },
+ package() {
+ "DSTATE", 0x3, // D3 state
+ },
+ },
+
+ //PMIC Type-C Controller
+ //Component 0: USB HS rails for Automiatic Port Source Detection (APSD)
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.PTCC",
+ Package()
+ {
+ "COMPONENT",0, //Component 0: USB HS Rails for Charger Detection
+ Package(){"FSTATE", 0 }, //Dummy F-State, required for P-State operation
+ Package()
+ {
+ "PSTATE", 0, // P0 state - Component ON
+ // LDO 24: ON, 3.075V, LDO 12: ON, 1.8V
+ package()
+ {
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L24 @3.075v
+ {
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 3075000, // Voltage = 3.075 V
+ 1, // SW Enable = Enable
+ 1, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L12 @1.8v
+ {
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1800000, // Voltage 1.8V : microvolts ( V )
+ 1, // SW Enable = Enable
+ 1, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ },
+ Package()
+ {
+ "PSTATE", 1, // P1 state - Component OFF
+ // LDO 24 & LDO 12 : OFF
+ package()
+ {
+ "PMICVREGVOTE", // PMICVREGVOTE resource
+ package() // Vote for L24 @0v
+ {
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // SW Enable = Disable
+ 0, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package() // Vote for L12 @0v
+ {
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage : 0 microvolts ( V )
+ 0, // SW Enable = Disable
+ 0, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ },
+ },
+ //D states
+ package() {
+ "DSTATE", 0x0, // D0 state
+ },
+ package() {
+ "DSTATE", 0x1, // D1 state
+ },
+ package() {
+ "DSTATE", 0x2, // D2 state
+ },
+ package() {
+ "DSTATE", 0x3, // D3 state
+ },
+ }, //End PMIC Type-C Controller
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.URS0",
+ Package()
+ {
+ "COMPONENT",
+ Zero,
+ Package() {"FSTATE", 0},
+ Package() {"PSTATE", 0},
+ Package() {"PSTATE", 1}
+ },
+ Package() {"DSTATE", 0 },
+ Package() {"DSTATE", 1 },
+ Package() {"DSTATE", 2 },
+ Package() {"DSTATE", 3 }
+ },
+
+
+ //USB SS/HS1 core (Host Stack)
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.URS0.USB0",
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0.
+ Package() { "FSTATE", 0x0, },
+ package()
+ {
+ "PSTATE",
+ 0x0,
+ // Enable USB 3.0 Sleep Clock
+ package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}},
+ // Mark Suppressible for USB 3.0 Sleep Clock
+ package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}},
+ // Mark Always On for USB 3.0 Sleep Clock
+ package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}},
+ //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL
+ // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}},
+ // Enable PHY pipe Clock
+ package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}},
+ // Mark Suppressible for USB PHY pipe Clock
+ package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}},
+ },
+ package()
+ {
+ "PRELOAD_PSTATE",
+ 0,
+ },// index 0 is P-state 0 here
+ },
+ //D states
+ Package()
+ { // HOST D0
+ "DSTATE",
+ 0x0,
+ //Power Grid for SDM850
+ package()
+ {
+ // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY)
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L12 @1.8v
+ {
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1800000, // Voltage 1.8V : microvolts ( V )
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // L24 - VDDA_QUSB_HS0_3P1
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L24 @3.075v
+ {
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 3075000, // Voltage = 3.075 V
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // L26 - VDDA_USB_SS_1P2 (QMP PHY)
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L26 @1.2v
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1200000, // Voltage 1.2V : microvolts ( V )
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L1 @ 0.88v
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 880000, // Voltage (microvolts)
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+
+ // Enable usb30_prim_gdsc power domain
+ package()
+ {
+ "FOOTSWITCH", // Footswitch
+ package()
+ {
+ "usb30_prim_gdsc", // USB 3.0 Core Power domain
+ 1, //1==Enable
+ },
+ },
+
+ // Now Enable all the clocks
+
+ //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}},
+
+ // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
+ // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}},
+
+ // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}},
+
+ //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz
+ package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 8, 19200, 7}},
+
+ // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
+ package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}},
+
+ //Vote for max freq: BUS Arbiter Request (Type-3)
+ // Instantaneous BW BytesPerSec = 671088640;
+ // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
+ package()
+ {
+ "BUSARB",
+ Package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_USB3_0", // Master
+ "ICBID_SLAVE_EBI1", // Slave
+ 671088640, // IB=5Gbps //LowSVS
+ 671088640 // AB=5Gbps
+ }
+ },
+
+ //Nominal==block vdd_min:
+ package()
+ {
+ "NPARESOURCE",
+ Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact)
+ //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact)
+ },
+
+ // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ //BUS Arbiter Request (Type-3)
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact)
+ //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact)
+ 0 // AB=0 MBps
+ }
+ },
+ // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
+
+ // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
+ package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}},
+ },
+ package()
+ { // HOST D1
+ "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend)
+ 0x1,
+
+ //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}},
+
+ // Disable USB 3.0 Master Clock 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
+
+ // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
+ package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
+
+ //Disable aggre_usb3_prim_axi
+ package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
+
+ // Disable UTMI clk 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
+
+ // Remove Vote for CNOC 100 MHz
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // BUS Arbiter Request (Type-3)
+ // Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 0, // IB=0 MBps
+ 0 // AB=0 MBps
+ }
+ },
+
+ // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+
+ // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ package()
+ {
+ "CLOCK",
+ package() { "gcc_usb3_prim_phy_aux_clk", 2}
+ },
+
+ // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
+
+ //BUS Arbiter Request (Type-3)
+ //Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_USB3_0",// Master
+ "ICBID_SLAVE_EBI1", // Slave
+ 0, // IB=0 Mbps
+ 0 // AB=0Mbps
+ }
+ },
+
+ //enable vdd_min
+ package()
+ {
+ "NPARESOURCE",
+ package() { 1, "/arc/client/rail_cx", 0}
+ },
+
+ package()
+ {
+ "PMICVREGVOTE",
+ package() //Vote for L12 @1.8v
+ {
+ // L12 - VDDA_QUSB_HS0_1P8
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1800000, // Voltage : microvolts ( V )
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+
+ package()
+ {
+ "PMICVREGVOTE", // PMICVREGVOTE resource
+ package() // Vote for L24 @3.075v
+ {
+ // L24 - VDDA_QUSB_HS0_3P1
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 3075000, // Voltage = 3.075 V
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+
+ package()
+ {
+ // L26 is used for QMP PHY
+ // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L26 @1.2v
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1200000, // Voltage 1.2V : microvolts ( V )
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L1 @ 0.88v
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 880000, // Voltage (microvolts)
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ },
+ package()
+ { // HOST D2
+ "DSTATE",
+ 0x2, // Slave device disconnect (host cable is still connected)
+
+ //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}},
+
+ // Disable USB 3.0 Master Clock 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
+
+ // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
+ package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
+
+ // Disable aggre_usb3_prim_axi
+ package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
+
+ // Disable UTMI clk 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
+
+ // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }},
+
+ // Remove Vote for CNOC 100 MHz
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // BUS Arbiter Request (Type-3)
+ // Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 0, // IB=0 MBps
+ 0 // AB=0 MBps
+ }
+ },
+
+ // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+ // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
+
+
+ // Enable usb30_prim_gdsc power domain
+ package()
+ {
+ "FOOTSWITCH", // Footswitch
+ package()
+ {
+ "usb30_prim_gdsc", // USB 3.0 Core Power domain
+ 1, //1==Enable
+ },
+ },
+
+ //Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ Package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_USB3_0", // Master
+ "ICBID_SLAVE_EBI1", // Slave
+ 0, // IB=0 Mbps
+ 0 // AB=0Mbps
+ }
+ },
+
+ //enable vdd_min
+ package()
+ {
+ "NPARESOURCE",
+ package() { 1, "/arc/client/rail_cx", 0}
+ },
+
+ //Power Grid for SDM850
+ package()
+ {
+ "PMICVREGVOTE",
+ package() //Vote for L12 @1.8v
+ {
+ // L12 - VDDA_QUSB_HS0_1P8
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1800000, // Voltage : microvolts ( V )
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE", // PMICVREGVOTE resource
+ package() // Vote for L24 @3.075v
+ {
+ // L24 - VDDA_QUSB_HS0_3P1
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 3075000, // Voltage = 3.075 V
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // L26 is used for QMP PHY
+ // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L2 @1.2v
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1200000, // Voltage 1.2V : microvolts ( V )
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L1 @ 0.88v
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 880000, // Voltage (microvolts)
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+
+ },
+ package()
+ { // HOST D3
+ "DSTATE",
+ 0x3, // Abandon state
+
+ //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}},
+
+ // Disable USB 3.0 Master Clock 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
+
+ // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
+ package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
+
+ // Disable aggre_usb3_prim_axi
+ package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
+
+ // Disable UTMI clk 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
+
+ // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }},
+
+ // Remove Vote for CNOC 100 MHz
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // BUS Arbiter Request (Type-3)
+ // Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 0, // IB=0 MBps
+ 0 // AB=0 MBps
+ }
+ },
+
+ // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+ // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
+
+ // Disable usb30_prim_gdsc power domain
+ package()
+ {
+ "FOOTSWITCH", // Footswitch
+ package()
+ {
+ "usb30_prim_gdsc", // USB 3.0 Core Power domain
+ 2, // 2==Disable
+ },
+ },
+
+ //Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_USB3_0",// Master
+ "ICBID_SLAVE_EBI1", // Slave
+ 0, // IB=0 Mbps
+ 0 // AB=0Mbps
+ }
+ },
+
+ //enable vdd_min
+ package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}},
+
+ //Power Grid for SDM850
+ package()
+ {
+ "PMICVREGVOTE", // PMICVREGVOTE resource
+ package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
+ {
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8
+ {
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage : 0 microvolts ( V )
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage 0 V : microvolts ( V )
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ package() // Vote for L1 @ 0 v
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage (microvolts)
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ },
+ // Define Abandon State for USB0 (host) stack ie. Power State invoked when stack unloads/tears down
+ package()
+ {
+ "ABANDON_DSTATE",
+ 3 // Abandon D state defined as D3
+ },
+ }, //End USB0
+ //
+ //************************* USB3.0 SS/HS0 core (Peripheral Stack) ****************************
+ //
+ package()
+ {
+ "DEVICE",
+ "\\_SB.URS0.UFN0",
+ package()
+ {
+ "COMPONENT",
+ 0x0,
+ // F-State placeholders
+ package()
+ {
+ "FSTATE",
+ 0x0,
+ },
+ package()
+ {
+ "PSTATE",
+ 0x0,
+ // Enable USB 3.0 Sleep Clock
+ package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}},
+ // Mark Suppressible for USB 3.0 Sleep Clock
+ package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}},
+ // Mark Always On for USB 3.0 Sleep Clock
+ package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}},
+
+ //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL
+ // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}},
+ // Enable PHY pipe Clock
+ package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}},
+ // Mark Suppressible for USB PHY pipe Clock
+ package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}},
+ },
+ package()
+ {
+ "PRELOAD_PSTATE",
+ 0,
+ },// index 0 is P-state 0 here
+ },
+
+ package()
+ { // PERIPH D0
+ "DSTATE",
+ 0x0,
+ //Power Grid for SDM850
+ package()
+ {
+ // L12 - VDDA_QUSB_HS0_1P8
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L12 @1.8v
+ {
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1800000, // Voltage 1.8V : microvolts ( V )
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // L24 - VDDA_QUSB_HS0_3P1
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L24 @ 3.075v
+ {
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 3075000, // Voltage = 3.075 V
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // L26 - VDDA_USB_SS_1P2 (QMP PHY)
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L2 @1.2v
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1200000, // Voltage 1.2V : microvolts ( V )
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L1 @ 0.88v
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 880000, // Voltage (microvolts)
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+
+ // Enable usb30_prim_gdsc power domain
+ package()
+ {
+ "FOOTSWITCH", // Footswitch
+ package()
+ {
+ "usb30_prim_gdsc", // USB 3.0 Core Power domain
+ 1, //1==Enable
+ },
+ },
+
+ //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}},
+
+ // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
+ // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}},
+
+ // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}},
+
+ // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
+ package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}},
+
+ // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ //BUS Arbiter Request (Type-3)
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 400000000, // IB=400 MBps
+ 0 // AB=0 MBps
+ }
+ },
+
+ // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
+
+ //Vote for max freq: BUS Arbiter Request (Type-3)
+ // Instantaneous BW BytesPerSec = 671088640;
+ // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
+ package()
+ {
+ "BUSARB",
+ Package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_USB3_0", // Master
+ "ICBID_SLAVE_EBI1", // Slave
+ 671088640, // IB=5Gbps
+ 671088640 // AB=5Gbps
+ }
+ },
+
+ //Nominal==block vdd_min:
+ package()
+ {
+ "NPARESOURCE",
+ Package() {1, "/arc/client/rail_cx", 256}
+ },
+
+ // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
+ package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}},
+
+ },
+ package()
+ {
+ // PERIPH D1: Not supported by USBFN driver
+ "DSTATE", //USB SS+HS suspend state
+ 0x1,
+ },
+ package()
+ { // PERIPH D2
+ "DSTATE", //USB DCP/HVDCP charger state
+ 0x2,
+
+ // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}},
+
+ // Disable USB 3.0 Master Clock 2 = Disable ;
+ package() {"CLOCK", package() { "gcc_usb30_prim_master_clk", 2 } },
+
+ // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
+ package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
+
+ //Disable aggre_usb3_prim_axi
+ package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
+
+ //Disable gcc_usb3_prim_phy_aux_clk
+ package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2}},
+
+ // Remove Vote for CNOC 100 MHz
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // BUS Arbiter Request (Type-3)
+ // Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 0, // IB=0 MBps
+ 0 // AB=0 MBps
+ }
+ },
+
+ // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+ // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
+
+
+ //BUS Arbiter Request (Type-3)
+ //Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_USB3_0", // Master
+ "ICBID_SLAVE_EBI1", // Slave
+ 0, // IB=0 MBps
+ 0 // AB=0 MBps
+ }
+ },
+
+ //Nominal==block vdd_min:
+ package()
+ {
+ "NPARESOURCE",
+ package() {1, "/arc/client/rail_cx", 256}
+ },
+
+ package()
+ {
+ "PMICVREGVOTE",
+ package() //Vote for L12 @1.8v
+ {
+ // L12 - VDDA_QUSB_HS0_1P8
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1800000, // Voltage : microvolts ( V )
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE", // PMICVREGVOTE resource
+ package() // Vote for L24 @3.075v
+ {
+ // L24 - VDDA_QUSB_HS0_3P1
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 3075000, // Voltage = 3.075 V
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // L26 is used for QMP PHY
+ // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L2 @1.2v
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage 0V : microvolts ( V )
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L1 @ 0v
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage (microvolts)
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ },
+ package()
+ {
+ // PERIPH D3
+ "DSTATE",
+ 0x3, // Detach State
+
+ //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}},
+
+ // Disable USB 3.0 Master Clock 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
+
+ // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
+ package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
+
+ //Disable aggre_usb3_prim_axi
+ package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
+
+ // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }},
+
+ // Remove Vote for CNOC 100 MHz
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // BUS Arbiter Request (Type-3)
+ // Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 0, // IB=0 MBps
+ 0 // AB=0 MBps
+ }
+ },
+
+ // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+ // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization
+ // No option of enabling it through ACPI
+
+ // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
+
+
+ // Disable usb30_prim_gdsc power domain
+ package()
+ {
+ "FOOTSWITCH", // Footswitch
+ package()
+ {
+ "usb30_prim_gdsc", // USB 3.0 Core Power domain
+ 2, // 2==Disable
+ },
+ },
+
+ //Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_USB3_0",// Master
+ "ICBID_SLAVE_EBI1", // Slave
+ 0, // IB=0 MBps
+ 0 // AB=0 Mbps
+ }
+ },
+
+ //enable vdd_min
+ package()
+ {
+ "NPARESOURCE",
+ package() { 1, "/arc/client/rail_cx", 0}
+ },
+
+ package()
+ {
+ "PMICVREGVOTE", // PMICVREGVOTE resource
+ package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
+ {
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package() // Vote for L12 @0V - VDDA_QUSB_HS0_1P8
+ {
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage : 0 microvolts ( V )
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L2 @0v - VDDA_USB_SS_1P2
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage : 0 microvolts ( V )
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ package() // Vote for L1 @ 0.88v
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage (microvolts)
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ },
+ // Define Abandon State for UFN0 (peripheral) stack ie. Power State invoked when stack unloads/tears down
+ package()
+ {
+ "ABANDON_DSTATE",
+ 3 // Abandon D state defined as D3
+ },
+ }, //End UFN0
+
+ //USB Primary Core (Host Stack) Standalone
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.USB0",
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0.
+ Package() { "FSTATE", 0x0, },
+ package()
+ {
+ "PSTATE",
+ 0x0,
+ // Enable USB 3.0 Sleep Clock
+ package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}},
+ // Mark Suppressible for USB 3.0 Sleep Clock
+ package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}},
+ // Mark Always On for USB 3.0 Sleep Clock
+ package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}},
+ //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL
+ // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}},
+ // Enable PHY pipe Clock
+ package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}},
+ // Mark Suppressible for USB PHY pipe Clock
+ package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}},
+ },
+ package()
+ {
+ "PRELOAD_PSTATE",
+ 0,
+ },// index 0 is P-state 0 here
+ },
+ //D states
+ Package()
+ { // HOST D0
+ "DSTATE",
+ 0x0,
+ //Power Grid for SDM850
+ package()
+ {
+ // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY)
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L12 @1.8v
+ {
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1800000, // Voltage 1.8V : microvolts ( V )
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // L24 - VDDA_QUSB_HS0_3P1
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L24 @3.075v
+ {
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 3075000, // Voltage = 3.075 V
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // L26 - VDDA_USB_SS_1P2 (QMP PHY)
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L26 @1.2v
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1200000, // Voltage 1.2V : microvolts ( V )
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L1 @ 0.88v
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 880000, // Voltage (microvolts)
+ 1, // SW Enable = Enable
+ 7, // SW Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+
+ // Enable usb30_prim_gdsc power domain
+ package()
+ {
+ "FOOTSWITCH", // Footswitch
+ package()
+ {
+ "usb30_prim_gdsc", // USB 3.0 Core Power domain
+ 1, //1==Enable
+ },
+ },
+
+ // Now Enable all the clocks
+
+ //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}},
+
+ // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
+ // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}},
+
+ // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}},
+
+ //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz
+ package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 8, 19200, 7}},
+
+ // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
+ package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}},
+
+ //Vote for max freq: BUS Arbiter Request (Type-3)
+ // Instantaneous BW BytesPerSec = 671088640;
+ // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
+ package()
+ {
+ "BUSARB",
+ Package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_USB3_0", // Master
+ "ICBID_SLAVE_EBI1", // Slave
+ 671088640, // IB=5Gbps //LowSVS
+ 671088640 // AB=5Gbps
+ }
+ },
+
+ //Nominal==block vdd_min:
+ package()
+ {
+ "NPARESOURCE",
+ Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact)
+ //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact)
+ },
+
+ // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ //BUS Arbiter Request (Type-3)
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact)
+ //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact)
+ 0 // AB=0 MBps
+ }
+ },
+ // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
+
+ // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
+ package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}},
+ },
+ package()
+ { // HOST D1
+ "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend)
+ 0x1,
+
+ //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}},
+
+ // Disable USB 3.0 Master Clock 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
+
+ // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
+ package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
+
+ //Disable aggre_usb3_prim_axi
+ package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
+
+ // Disable UTMI clk 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
+
+ // Remove Vote for CNOC 100 MHz
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // BUS Arbiter Request (Type-3)
+ // Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 0, // IB=0 MBps
+ 0 // AB=0 MBps
+ }
+ },
+
+ // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+
+ // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ package()
+ {
+ "CLOCK",
+ package() { "gcc_usb3_prim_phy_aux_clk", 2}
+ },
+
+ // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
+
+ //BUS Arbiter Request (Type-3)
+ //Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_USB3_0",// Master
+ "ICBID_SLAVE_EBI1", // Slave
+ 0, // IB=0 Mbps
+ 0 // AB=0Mbps
+ }
+ },
+
+ //enable vdd_min
+ package()
+ {
+ "NPARESOURCE",
+ package() { 1, "/arc/client/rail_cx", 0}
+ },
+
+ package()
+ {
+ "PMICVREGVOTE",
+ package() //Vote for L12 @1.8v
+ {
+ // L12 - VDDA_QUSB_HS0_1P8
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1800000, // Voltage : microvolts ( V )
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+
+ package()
+ {
+ "PMICVREGVOTE", // PMICVREGVOTE resource
+ package() // Vote for L24 @3.075v
+ {
+ // L24 - VDDA_QUSB_HS0_3P1
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 3075000, // Voltage = 3.075 V
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+
+ package()
+ {
+ // L26 is used for QMP PHY
+ // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L26 @1.2v
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1200000, // Voltage 1.2V : microvolts ( V )
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L1 @ 0.88v
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 880000, // Voltage (microvolts)
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ },
+ package()
+ { // HOST D2
+ "DSTATE",
+ 0x2, // Slave device disconnect (host cable is still connected)
+
+ //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}},
+
+ // Disable USB 3.0 Master Clock 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
+
+ // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
+ package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
+
+ // Disable aggre_usb3_prim_axi
+ package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
+
+ // Disable UTMI clk 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
+
+ // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }},
+
+ // Remove Vote for CNOC 100 MHz
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // BUS Arbiter Request (Type-3)
+ // Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 0, // IB=0 MBps
+ 0 // AB=0 MBps
+ }
+ },
+
+ // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+ // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization
+ // No option of enabling it through ACPI
+
+ // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
+
+
+ // Enable usb30_prim_gdsc power domain
+ package()
+ {
+ "FOOTSWITCH", // Footswitch
+ package()
+ {
+ "usb30_prim_gdsc", // USB 3.0 Core Power domain
+ 1, //1==Enable
+ },
+ },
+
+ //Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ Package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_USB3_0", // Master
+ "ICBID_SLAVE_EBI1", // Slave
+ 0, // IB=0 Mbps
+ 0 // AB=0Mbps
+ }
+ },
+
+ //enable vdd_min
+ package()
+ {
+ "NPARESOURCE",
+ package() { 1, "/arc/client/rail_cx", 0}
+ },
+
+ //Power Grid for SDM850
+ package()
+ {
+ "PMICVREGVOTE",
+ package() //Vote for L12 @1.8v
+ {
+ // L12 - VDDA_QUSB_HS0_1P8
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1800000, // Voltage : microvolts ( V )
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE", // PMICVREGVOTE resource
+ package() // Vote for L24 @3.075v
+ {
+ // L24 - VDDA_QUSB_HS0_3P1
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 3075000, // Voltage = 3.075 V
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // L26 is used for QMP PHY
+ // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L2 @1.2v
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 1200000, // Voltage 1.2V : microvolts ( V )
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L1 @ 0.88v
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 880000, // Voltage (microvolts)
+ 1, // SW Enable = Enable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+
+ },
+ package()
+ { // HOST D3
+ "DSTATE",
+ 0x3, // Abandon state
+
+ //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}},
+
+ // Disable USB 3.0 Master Clock 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
+
+ // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
+ package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
+
+ // Disable aggre_usb3_prim_axi
+ package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
+
+ // Disable UTMI clk 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
+
+ // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }},
+
+ // Remove Vote for CNOC 100 MHz
+ // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // BUS Arbiter Request (Type-3)
+ // Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_APPSS_PROC", // Master
+ "ICBID_SLAVE_USB3_0", // Slave
+ 0, // IB=0 MBps
+ 0 // AB=0 MBps
+ }
+ },
+
+ // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+ // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
+
+ // Disable usb30_prim_gdsc power domain
+ package()
+ {
+ "FOOTSWITCH", // Footswitch
+ package()
+ {
+ "usb30_prim_gdsc", // USB 3.0 Core Power domain
+ 2, // 2==Disable
+ },
+ },
+
+ //Vote for 0 freq
+ package()
+ {
+ "BUSARB",
+ package()
+ {
+ 3, // Req Type
+ "ICBID_MASTER_USB3_0",// Master
+ "ICBID_SLAVE_EBI1", // Slave
+ 0, // IB=0 Mbps
+ 0 // AB=0Mbps
+ }
+ },
+
+ //enable vdd_min
+ package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}},
+
+ //Power Grid for SDM850
+ package()
+ {
+ "PMICVREGVOTE", // PMICVREGVOTE resource
+ package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
+ {
+ "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8
+ {
+ "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage : 0 microvolts ( V )
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE", // PMIC VREG resource
+ package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2
+ {
+ "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage 0 V : microvolts ( V )
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ package() // Vote for L1 @ 0 v
+ {
+ "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ 1, // Voltage Regulator type = LDO
+ 0, // Voltage (microvolts)
+ 0, // SW Enable = Disable
+ 5, // SW Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ },
+ // Define Abandon State for USB0 (host) stack ie. Power State invoked when stack unloads/tears down
+ package()
+ {
+ "ABANDON_DSTATE",
+ 3 // Abandon D state defined as D3
+ },
+ }, //End USB0
+
+ //USB secondary core (Host Stack)
+ // Package()
+ // {
+ // "DEVICE",
+ // "\\_SB.USB1",
+ // Package()
+ // {
+ // "COMPONENT",
+ // 0x0, // Component 0.
+ // Package() { "FSTATE", 0x0, },
+ // package()
+ // {
+ // "PSTATE",
+ // 0x0,
+ // // Enable USB 3.0 Sleep Clock
+ // package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}},
+ // // Mark Suppressible for USB 3.0 Sleep Clock
+ // package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}},
+ // // Mark Always On for USB 3.0 Sleep Clock
+ // package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}},
+ // //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL
+ // // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}},
+ // // Enable PHY pipe Clock
+ // package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}},
+ // // Mark Suppressible for USB PHY pipe Clock
+ // package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}},
+ // },
+ // package()
+ // {
+ // "PRELOAD_PSTATE",
+ // 0,
+ // },// index 0 is P-state 0 here
+ // },
+ // //D states
+ // Package()
+ // { // HOST D0
+ // "DSTATE",
+ // 0x0,
+ // //Power Grid for SDM850
+ // package()
+ // {
+ // // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY)
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L12 @1.8v
+ // {
+ // "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1800000, // Voltage 1.8V : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // L24 - VDDA_QUSB_HS0_3P1
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L24 @3.075v
+ // {
+ // "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type 1 = LDO
+ // 3075000, // Voltage = 3.075 V
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // L26 - VDDA_USB_SS_1P2 (QMP PHY)
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L26 @1.2v
+ // {
+ // "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1200000, // Voltage 1.2V : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L1 @ 0.88v
+ // {
+ // "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 880000, // Voltage (microvolts)
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+
+ // // Enable usb30_sec_gdsc power domain
+ // package()
+ // {
+ // "FOOTSWITCH", // Footswitch
+ // package()
+ // {
+ // "usb30_sec_gdsc", // USB 3.0 Core Power domain
+ // 1, //1==Enable
+ // },
+ // },
+
+ // // Now Enable all the clocks
+
+ // //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ // package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}},
+
+ // // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
+ // // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ // package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}},
+
+ // // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}},
+
+ // //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz
+ // package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}},
+
+ // // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
+ // package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}},
+
+ // //Vote for max freq: BUS Arbiter Request (Type-3)
+ // // Instantaneous BW BytesPerSec = 671088640;
+ // // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
+ // package()
+ // {
+ // "BUSARB",
+ // Package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_USB3_1", // Master
+ // "ICBID_SLAVE_EBI1", // Slave
+ // 671088640, // IB=5Gbps //LowSVS
+ // 671088640 // AB=5Gbps
+ // }
+ // },
+
+ // //Nominal==block vdd_min:
+ // package()
+ // {
+ // "NPARESOURCE",
+ // Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact)
+ // //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact)
+ // },
+
+ // // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
+ // // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // //BUS Arbiter Request (Type-3)
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_APPSS_PROC", // Master
+ // "ICBID_SLAVE_USB3_1", // Slave
+ // 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact)
+ // //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact)
+ // 0 // AB=0 MBps
+ // }
+ // },
+ // // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
+ // package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
+
+ // // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
+ // package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}},
+
+ // },
+ // package()
+ // { // HOST D1
+ // "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend)
+ // 0x1,
+
+ // //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}},
+
+ // // Disable USB 3.0 Master Clock 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
+
+ // // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
+ // package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
+
+ // //Disable aggre_usb3_sec_axi
+ // package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
+
+ // // Disable UTMI clk 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
+
+ // // Remove Vote for CNOC 100 MHz
+ // // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // // BUS Arbiter Request (Type-3)
+ // // Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_APPSS_PROC", // Master
+ // "ICBID_SLAVE_USB3_1", // Slave
+ // 0, // IB=0 MBps
+ // 0 // AB=0 MBps
+ // }
+ // },
+
+ // // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ // package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+
+ // // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ // package()
+ // {
+ // "CLOCK",
+ // package() { "gcc_usb3_sec_phy_aux_clk", 2}
+ // },
+
+
+ // // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
+
+ // //BUS Arbiter Request (Type-3)
+ // //Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_USB3_1",// Master
+ // "ICBID_SLAVE_EBI1", // Slave
+ // 0, // IB=0 Mbps
+ // 0 // AB=0Mbps
+ // }
+ // },
+
+ // //enable vdd_min
+ // package()
+ // {
+ // "NPARESOURCE",
+ // package() { 1, "/arc/client/rail_cx", 0}
+ // },
+
+ // package()
+ // {
+ // "PMICVREGVOTE",
+ // package() //Vote for L12 @1.8v
+ // {
+ // // L12 - VDDA_QUSB_HS0_1P8
+ // "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1800000, // Voltage : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // package() // Vote for L24 @3.075v
+ // {
+ // // L24 - VDDA_QUSB_HS0_3P1
+ // "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type 1 = LDO
+ // 3075000, // Voltage = 3.075 V
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+
+ // package()
+ // {
+ // // L26 is used for QMP PHY
+ // // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L26 @1.2v
+ // {
+ // "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1200000, // Voltage 1.2V : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L1 @ 0.88v
+ // {
+ // "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 880000, // Voltage (microvolts)
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // },
+ // package()
+ // { // HOST D2
+ // "DSTATE",
+ // 0x2, // Slave device disconnect (host cable is still connected)
+
+ // //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}},
+
+ // // Disable USB 3.0 Master Clock 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
+
+ // // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
+ // package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
+
+ // // Disable aggre_usb3_sec_axi
+ // package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
+
+ // // Disable UTMI clk 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
+
+ // // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ // package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }},
+
+ // // Remove Vote for CNOC 100 MHz
+ // // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // // BUS Arbiter Request (Type-3)
+ // // Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_APPSS_PROC", // Master
+ // "ICBID_SLAVE_USB3_1", // Slave
+ // 0, // IB=0 MBps
+ // 0 // AB=0 MBps
+ // }
+ // },
+
+ // // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ // package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+ // // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization
+ // // No option of enabling it through ACPI
+
+ // // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
+
+ // // Enable usb30_sec_gdsc power domain
+ // package()
+ // {
+ // "FOOTSWITCH", // Footswitch
+ // package()
+ // {
+ // "usb30_sec_gdsc", // USB 3.0 Core Power domain
+ // 1, //1==Enable
+ // },
+ // },
+
+ // //Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // Package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_USB3_1", // Master
+ // "ICBID_SLAVE_EBI1", // Slave
+ // 0, // IB=0 Mbps
+ // 0 // AB=0Mbps
+ // }
+ // },
+
+ // //enable vdd_min
+ // package()
+ // {
+ // "NPARESOURCE",
+ // package() { 1, "/arc/client/rail_cx", 0}
+ // },
+
+ // //Power Grid for SDM850
+ // package()
+ // {
+ // "PMICVREGVOTE",
+ // package() //Vote for L12 @1.8v
+ // {
+ // // L12 - VDDA_QUSB_HS0_1P8
+ // "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1800000, // Voltage : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // package() // Vote for L24 @3.075v
+ // {
+ // // L24 - VDDA_QUSB_HS0_3P1
+ // "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type 1 = LDO
+ // 3075000, // Voltage = 3.075 V
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // L26 is used for QMP PHY
+ // // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L2 @1.2v
+ // {
+ // "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1200000, // Voltage 1.2V : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L1 @ 0.88v
+ // {
+ // "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 880000, // Voltage (microvolts)
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+
+ // },
+ // package()
+ // { // HOST D3
+ // "DSTATE",
+ // 0x3, // Abandon state
+
+ // //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}},
+
+ // // Disable USB 3.0 Master Clock 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
+
+ // // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
+ // package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
+
+ // // Disable aggre_usb3_sec_axi
+ // package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
+
+ // // Disable UTMI clk 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
+
+ // // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ // package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }},
+
+ // // Remove Vote for CNOC 100 MHz
+ // // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // // BUS Arbiter Request (Type-3)
+ // // Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_APPSS_PROC", // Master
+ // "ICBID_SLAVE_USB3_1", // Slave
+ // 0, // IB=0 MBps
+ // 0 // AB=0 MBps
+ // }
+ // },
+
+ // // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ // package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+
+ // // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
+
+ // // Disable usb30_sec_gdsc power domain
+ // package()
+ // {
+ // "FOOTSWITCH", // Footswitch
+ // package()
+ // {
+ // "usb30_sec_gdsc", // USB 3.0 Core Power domain
+ // 2, // 2==Disable
+ // },
+ // },
+
+ // //Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_USB3_1",// Master
+ // "ICBID_SLAVE_EBI1", // Slave
+ // 0, // IB=0 Mbps
+ // 0 // AB=0Mbps
+ // }
+ // },
+
+ // //enable vdd_min
+ // package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}},
+
+ // //Power Grid for SDM850
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
+ // {
+ // "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type 1 = LDO
+ // 0, // Voltage = 0 V
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE",
+ // package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8
+ // {
+ // "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage : 0 microvolts ( V )
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2
+ // {
+ // "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage 0 V : microvolts ( V )
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ // package() // Vote for L1 @ 0 v
+ // {
+ // "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage (microvolts)
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // },
+ // // Define Abandon State for USB1 (host) stack ie. Power State invoked when stack unloads/tears down
+ // package()
+ // {
+ // "ABANDON_DSTATE",
+ // 3 // Abandon D state defined as D3
+ // },
+ // }, //End USB1
+
+ // Package()
+ // {
+ // "DEVICE",
+ // "\\_SB.URS1",
+ // Package()
+ // {
+ // "COMPONENT",
+ // Zero,
+ // Package() {"FSTATE", 0},
+ // Package()
+ // {
+ // "PSTATE",
+ // 0, // P0 -Disable Vbus
+ // package()
+ // {
+ // "PMICGPIO",
+ // Package()
+ // {
+ // "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT",
+ // 1, // PMI8998
+ // 9, // GPIO #10: USBOTG_VBUS_EN
+ // 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS
+ // 0, // PM_GPIO_VIN0
+ // 0, // EN_AND_SOURCE_SEL, 1: LOW
+ // 1, // PM_GPIO_OUT_BUFFER_LOW
+ // 4, // PM_GPIO_I_SOURCE_PULL_DOWN_10uA
+ // },
+ // },
+ // },
+ // Package()
+ // {
+ // "PSTATE",
+ // 1, // P1 - Enable Vbus
+ // package()
+ // {
+ // "PMICGPIO",
+ // Package()
+ // {
+ // "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT",
+ // 1, // PMI8998
+ // 9, // GPIO #10: USBOTG_VBUS_EN
+ // 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS
+ // 0, // PM_GPIO_VIN0
+ // 1, // EN_AND_SOURCE_SEL, 1: HIGH
+ // 3, // PM_GPIO_OUT_BUFFER_HIGH
+ // 5, // PM_GPIO_I_SOURCE_PULL_NO_PULL
+ // },
+ // },
+ // }
+ // },
+ // Package() {"DSTATE", 0 },
+ // Package() {"DSTATE", 1 },
+ // Package() {"DSTATE", 2 },
+ // Package() {"DSTATE", 3 }
+ // },
+
+
+ // //USB secondary core (Host Stack)
+ // Package()
+ // {
+ // "DEVICE",
+ // "\\_SB.URS1.USB1",
+ // Package()
+ // {
+ // "COMPONENT",
+ // 0x0, // Component 0.
+ // Package() { "FSTATE", 0x0, },
+ // package()
+ // {
+ // "PSTATE",
+ // 0x0,
+ // // Enable USB 3.0 Sleep Clock
+ // package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}},
+ // // Mark Suppressible for USB 3.0 Sleep Clock
+ // package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}},
+ // // Mark Always On for USB 3.0 Sleep Clock
+ // package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}},
+ // //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL
+ // // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}},
+ // // Enable PHY pipe Clock
+ // package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}},
+ // // Mark Suppressible for USB PHY pipe Clock
+ // package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}},
+ // },
+ // package()
+ // {
+ // "PRELOAD_PSTATE",
+ // 0,
+ // },// index 0 is P-state 0 here
+ // },
+ // //D states
+ // Package()
+ // { // HOST D0
+ // "DSTATE",
+ // 0x0,
+ // //Power Grid for SDM850
+ // package()
+ // {
+ // // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY)
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L12 @1.8v
+ // {
+ // "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1800000, // Voltage 1.8V : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // L24 - VDDA_QUSB_HS0_3P1
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L24 @3.075v
+ // {
+ // "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type 1 = LDO
+ // 3075000, // Voltage = 3.075 V
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // L26 - VDDA_USB_SS_1P2 (QMP PHY)
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L26 @1.2v
+ // {
+ // "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1200000, // Voltage 1.2V : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L1 @ 0.88v
+ // {
+ // "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 880000, // Voltage (microvolts)
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+
+ // // Enable usb30_sec_gdsc power domain
+ // package()
+ // {
+ // "FOOTSWITCH", // Footswitch
+ // package()
+ // {
+ // "usb30_sec_gdsc", // USB 3.0 Core Power domain
+ // 1, //1==Enable
+ // },
+ // },
+
+ // // Now Enable all the clocks
+
+ // //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ // package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}},
+
+ // // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
+ // // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ // package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}},
+
+ // // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}},
+
+ // //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz
+ // package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}},
+
+ // // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
+ // package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}},
+
+ // //Vote for max freq: BUS Arbiter Request (Type-3)
+ // // Instantaneous BW BytesPerSec = 671088640;
+ // // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
+ // package()
+ // {
+ // "BUSARB",
+ // Package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_USB3_1", // Master
+ // "ICBID_SLAVE_EBI1", // Slave
+ // 671088640, // IB=5Gbps //LowSVS
+ // 671088640 // AB=5Gbps
+ // }
+ // },
+
+ // //Nominal==block vdd_min:
+ // package()
+ // {
+ // "NPARESOURCE",
+ // Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact)
+ // //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact)
+ // },
+
+ // // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
+ // // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // //BUS Arbiter Request (Type-3)
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_APPSS_PROC", // Master
+ // "ICBID_SLAVE_USB3_1", // Slave
+ // 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact)
+ // //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact)
+ // 0 // AB=0 MBps
+ // }
+ // },
+ // // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
+ // package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
+
+ // // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
+ // package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}},
+
+ // },
+ // package()
+ // { // HOST D1
+ // "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend)
+ // 0x1,
+
+ // //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}},
+
+ // // Disable USB 3.0 Master Clock 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
+
+ // // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
+ // package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
+
+ // //Disable aggre_usb3_sec_axi
+ // package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
+
+ // // Disable UTMI clk 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
+
+ // // Remove Vote for CNOC 100 MHz
+ // // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // // BUS Arbiter Request (Type-3)
+ // // Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_APPSS_PROC", // Master
+ // "ICBID_SLAVE_USB3_1", // Slave
+ // 0, // IB=0 MBps
+ // 0 // AB=0 MBps
+ // }
+ // },
+
+ // // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ // package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+
+ // // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ // package()
+ // {
+ // "CLOCK",
+ // package() { "gcc_usb3_sec_phy_aux_clk", 2}
+ // },
+
+ // // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
+
+ // //BUS Arbiter Request (Type-3)
+ // //Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_USB3_1",// Master
+ // "ICBID_SLAVE_EBI1", // Slave
+ // 0, // IB=0 Mbps
+ // 0 // AB=0Mbps
+ // }
+ // },
+
+ // //enable vdd_min
+ // package()
+ // {
+ // "NPARESOURCE",
+ // package() { 1, "/arc/client/rail_cx", 0}
+ // },
+
+ // package()
+ // {
+ // "PMICVREGVOTE",
+ // package() //Vote for L12 @1.8v
+ // {
+ // // L12 - VDDA_QUSB_HS0_1P8
+ // "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1800000, // Voltage : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // package() // Vote for L24 @3.075v
+ // {
+ // // L24 - VDDA_QUSB_HS0_3P1
+ // "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type 1 = LDO
+ // 3075000, // Voltage = 3.075 V
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+
+ // package()
+ // {
+ // // L26 is used for QMP PHY
+ // // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L26 @1.2v
+ // {
+ // "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1200000, // Voltage 1.2V : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L1 @ 0.88v
+ // {
+ // "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 880000, // Voltage (microvolts)
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // },
+ // package()
+ // { // HOST D2
+ // "DSTATE",
+ // 0x2, // Slave device disconnect (host cable is still connected)
+
+ // //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}},
+
+ // // Disable USB 3.0 Master Clock 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
+
+ // // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
+ // package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
+
+ // // Disable aggre_usb3_sec_axi
+ // package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
+
+ // // Disable UTMI clk 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
+
+ // // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ // package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }},
+
+ // // Remove Vote for CNOC 100 MHz
+ // // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // // BUS Arbiter Request (Type-3)
+ // // Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_APPSS_PROC", // Master
+ // "ICBID_SLAVE_USB3_1", // Slave
+ // 0, // IB=0 MBps
+ // 0 // AB=0 MBps
+ // }
+ // },
+
+ // // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ // package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+ // // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization
+ // // No option of enabling it through ACPI
+
+ // // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
+
+
+ // // Enable usb30_sec_gdsc power domain
+ // package()
+ // {
+ // "FOOTSWITCH", // Footswitch
+ // package()
+ // {
+ // "usb30_sec_gdsc", // USB 3.0 Core Power domain
+ // 1, //1==Enable
+ // },
+ // },
+
+ // //Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // Package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_USB3_1", // Master
+ // "ICBID_SLAVE_EBI1", // Slave
+ // 0, // IB=0 Mbps
+ // 0 // AB=0Mbps
+ // }
+ // },
+
+ // //enable vdd_min
+ // package()
+ // {
+ // "NPARESOURCE",
+ // package() { 1, "/arc/client/rail_cx", 0}
+ // },
+
+ // //Power Grid for SDM850
+ // package()
+ // {
+ // "PMICVREGVOTE",
+ // package() //Vote for L12 @1.8v
+ // {
+ // // L12 - VDDA_QUSB_HS0_1P8
+ // "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1800000, // Voltage : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // package() // Vote for L24 @3.075v
+ // {
+ // // L24 - VDDA_QUSB_HS0_3P1
+ // "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type 1 = LDO
+ // 3075000, // Voltage = 3.075 V
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // L26 is used for QMP PHY
+ // // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L2 @1.2v
+ // {
+ // "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1200000, // Voltage 1.2V : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L1 @ 0.88v
+ // {
+ // "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 880000, // Voltage (microvolts)
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+
+ // },
+ // package()
+ // { // HOST D3
+ // "DSTATE",
+ // 0x3, // Abandon state
+
+ // //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}},
+
+ // // Disable USB 3.0 Master Clock 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
+
+ // // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
+ // package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
+
+ // // Disable aggre_usb3_sec_axi
+ // package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
+
+ // // Disable UTMI clk 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
+
+ // // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ // package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }},
+
+ // // Remove Vote for CNOC 100 MHz
+ // // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // // BUS Arbiter Request (Type-3)
+ // // Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_APPSS_PROC", // Master
+ // "ICBID_SLAVE_USB3_1", // Slave
+ // 0, // IB=0 MBps
+ // 0 // AB=0 MBps
+ // }
+ // },
+
+ // // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ // package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+ // // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization
+ // // No option of enabling it through ACPI
+
+ // // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
+
+
+ // // Disable usb30_sec_gdsc power domain
+ // package()
+ // {
+ // "FOOTSWITCH", // Footswitch
+ // package()
+ // {
+ // "usb30_sec_gdsc", // USB 3.0 Core Power domain
+ // 2, // 2==Disable
+ // },
+ // },
+
+ // //Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_USB3_1",// Master
+ // "ICBID_SLAVE_EBI1", // Slave
+ // 0, // IB=0 Mbps
+ // 0 // AB=0Mbps
+ // }
+ // },
+
+ // //enable vdd_min
+ // package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}},
+
+ // //Power Grid for SDM850
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
+ // {
+ // "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type 1 = LDO
+ // 0, // Voltage = 0 V
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE",
+ // package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8
+ // {
+ // "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage : 0 microvolts ( V )
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2
+ // {
+ // "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage 0 V : microvolts ( V )
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ // package() // Vote for L1 @ 0 v
+ // {
+ // "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage (microvolts)
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // },
+ // // Define Abandon State for USB1 (host) stack ie. Power State invoked when stack unloads/tears down
+ // package()
+ // {
+ // "ABANDON_DSTATE",
+ // 3 // Abandon D state defined as D3
+ // },
+ // }, //End USB1
+
+ // //************************* USB3.0 SS/HS0 core (Peripheral Secondary Stack) ****************************
+ // //
+ // package()
+ // {
+ // "DEVICE",
+ // "\\_SB.URS1.UFN1",
+ // package()
+ // {
+ // "COMPONENT",
+ // 0x0,
+ // // F-State placeholders
+ // package()
+ // {
+ // "FSTATE",
+ // 0x0,
+ // },
+ // package()
+ // {
+ // "PSTATE",
+ // 0x0,
+ // // Enable USB 3.0 Sleep Clock
+ // package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}},
+ // // Mark Suppressible for USB 3.0 Sleep Clock
+ // package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}},
+ // // Mark Always On for USB 3.0 Sleep Clock
+ // package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}},
+
+ // //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL
+ // // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}},
+ // // Enable PHY pipe Clock
+ // package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}},
+ // // Mark Suppressible for USB PHY pipe Clock
+ // package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}},
+ // },
+ // package()
+ // {
+ // "PRELOAD_PSTATE",
+ // 0,
+ // },// index 0 is P-state 0 here
+ // },
+
+ // package()
+ // { // PERIPH D0
+ // "DSTATE",
+ // 0x0,
+ // //Power Grid for SDM850
+ // package()
+ // {
+ // // L12 - VDDA_QUSB_HS0_1P8
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L12 @1.8v
+ // {
+ // "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1800000, // Voltage 1.8V : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // L24 - VDDA_QUSB_HS0_3P1
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L24 @ 3.075v
+ // {
+ // "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type 1 = LDO
+ // 3075000, // Voltage = 3.075 V
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // L26 - VDDA_USB_SS_1P2 (QMP PHY)
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L2 @1.2v
+ // {
+ // "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1200000, // Voltage 1.2V : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L1 @ 0.88v
+ // {
+ // "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 880000, // Voltage (microvolts)
+ // 1, // SW Enable = Enable
+ // 7, // SW Power Mode = NPM
+ // 0, // Head Room
+ // },
+ // },
+
+ // // Enable usb30_sec_gdsc power domain
+ // package()
+ // {
+ // "FOOTSWITCH", // Footswitch
+ // package()
+ // {
+ // "usb30_sec_gdsc", // USB 3.0 Core Power domain
+ // 1, //1==Enable
+ // },
+ // },
+
+ // //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ // package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}},
+
+ // // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
+ // // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ // package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}},
+
+ // // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}},
+
+ // // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
+ // package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}},
+
+ // // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
+ // // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // //BUS Arbiter Request (Type-3)
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_APPSS_PROC", // Master
+ // "ICBID_SLAVE_USB3_1", // Slave
+ // 400000000, // IB=400 MBps
+ // 0 // AB=0 MBps
+ // }
+ // },
+
+ // // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
+ // package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
+
+ // //Vote for max freq: BUS Arbiter Request (Type-3)
+ // // Instantaneous BW BytesPerSec = 671088640;
+ // // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
+ // package()
+ // {
+ // "BUSARB",
+ // Package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_USB3_1", // Master
+ // "ICBID_SLAVE_EBI1", // Slave
+ // 671088640, // IB=5Gbps
+ // 671088640 // AB=5Gbps
+ // }
+ // },
+
+ // //Nominal==block vdd_min:
+ // package()
+ // {
+ // "NPARESOURCE",
+ // Package() {1, "/arc/client/rail_cx", 256}
+ // },
+
+ // // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
+ // package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}},
+
+ // },
+ // package()
+ // {
+ // // PERIPH D1: Not supported by USBFN driver
+ // "DSTATE", //USB SS+HS suspend state
+ // 0x1,
+ // },
+ // package()
+ // { // PERIPH D2
+ // "DSTATE", //USB DCP/HVDCP charger state
+ // 0x2,
+
+ // // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ // // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}},
+
+ // // Disable USB 3.0 Master Clock 2 = Disable ;
+ // package() {"CLOCK", package() { "gcc_usb30_sec_master_clk", 2 } },
+
+ // // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
+ // package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
+
+ // //Disable aggre_usb3_sec_axi
+ // package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
+
+ // //Disable gcc_usb3_sec_phy_aux_clk
+ // package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2}},
+
+ // // Remove Vote for CNOC 100 MHz
+ // // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // // BUS Arbiter Request (Type-3)
+ // // Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_APPSS_PROC", // Master
+ // "ICBID_SLAVE_USB3_1", // Slave
+ // 0, // IB=0 MBps
+ // 0 // AB=0 MBps
+ // }
+ // },
+
+ // // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ // package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+
+
+ // // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
+
+
+ // //BUS Arbiter Request (Type-3)
+ // //Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_USB3_1", // Master
+ // "ICBID_SLAVE_EBI1", // Slave
+ // 0, // IB=0 MBps
+ // 0 // AB=0 MBps
+ // }
+ // },
+
+ // //Nominal==block vdd_min:
+ // package()
+ // {
+ // "NPARESOURCE",
+ // package() {1, "/arc/client/rail_cx", 256}
+ // },
+
+ // package()
+ // {
+ // "PMICVREGVOTE",
+ // package() //Vote for L12 @1.8v
+ // {
+ // // L12 - VDDA_QUSB_HS0_1P8
+ // "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 1800000, // Voltage : microvolts ( V )
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // package() // Vote for L24 @3.075v
+ // {
+ // // L24 - VDDA_QUSB_HS0_3P1
+ // "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type 1 = LDO
+ // 3075000, // Voltage = 3.075 V
+ // 1, // SW Enable = Enable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // L26 is used for QMP PHY
+ // // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L2 @1.2v
+ // {
+ // "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage 0V : microvolts ( V )
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L1 @ 0v
+ // {
+ // "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage (microvolts)
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // },
+ // package()
+ // {
+ // // PERIPH D3
+ // "DSTATE",
+ // 0x3, // Detach State
+
+ // //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}},
+
+ // // Disable USB 3.0 Master Clock 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
+
+ // // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
+ // package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
+
+ // //Disable aggre_usb3_sec_axi
+ // package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
+
+ // // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
+ // package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }},
+
+ // // Remove Vote for CNOC 100 MHz
+ // // Required for gcc_usb_phy_cfg_ahb2phy_clk
+ // // BUS Arbiter Request (Type-3)
+ // // Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_APPSS_PROC", // Master
+ // "ICBID_SLAVE_USB3_1", // Slave
+ // 0, // IB=0 MBps
+ // 0 // AB=0 MBps
+ // }
+ // },
+
+ // // Disable gcc_usb_phy_cfg_ahb2phy_clk
+ // package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
+ // // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization
+ // // No option of enabling it through ACPI
+
+ // // Disable SS Phy Reference Clock (diff clock) 2 = Disable
+ // package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
+
+ // // Disable usb30_sec_gdsc power domain
+ // package()
+ // {
+ // "FOOTSWITCH", // Footswitch
+ // package()
+ // {
+ // "usb30_sec_gdsc", // USB 3.0 Core Power domain
+ // 2, // 2==Disable
+ // },
+ // },
+
+ // //Vote for 0 freq
+ // package()
+ // {
+ // "BUSARB",
+ // package()
+ // {
+ // 3, // Req Type
+ // "ICBID_MASTER_USB3_1",// Master
+ // "ICBID_SLAVE_EBI1", // Slave
+ // 0, // IB=0 MBps
+ // 0 // AB=0 Mbps
+ // }
+ // },
+
+ // //enable vdd_min
+ // package()
+ // {
+ // "NPARESOURCE",
+ // package() { 1, "/arc/client/rail_cx", 0}
+ // },
+
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMICVREGVOTE resource
+ // package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
+ // {
+ // "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type 1 = LDO
+ // 0, // Voltage = 0 V
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE",
+ // package() // Vote for L12 @0V - VDDA_QUSB_HS0_1P8
+ // {
+ // "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage : 0 microvolts ( V )
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMIC VREG resource
+ // package() // Vote for L2 @0v - VDDA_USB_SS_1P2
+ // {
+ // "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage : 0 microvolts ( V )
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // package()
+ // {
+ // "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
+ // package() // Vote for L1 @ 0.88v
+ // {
+ // "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
+ // 1, // Voltage Regulator type = LDO
+ // 0, // Voltage (microvolts)
+ // 0, // SW Enable = Disable
+ // 5, // SW Power Mode = LPM
+ // 0, // Head Room
+ // },
+ // },
+ // },
+ // // Define Abandon State for UFN1 (peripheral) stack ie. Power State invoked when stack unloads/tears down
+ // package()
+ // {
+ // "ABANDON_DSTATE",
+ // 3 // Abandon D state defined as D3
+ // },
+ // }, //End UFN1
+ })
+}
+//
+// data.asl: This file contains the Data Drivers
+// ACPI device definitions, configuration and look-up tables.
+//
+
//
// RevRmNet Driver
//
--- /dev/null
+#include "Platform.h"
+
+
+#define MAX_OEM_WRITE_ENTRIES 8
+
+#define DEBUG_DEVICE_PORT_TYPE_SERIAL 0x8000
+#define DEBUG_DEVICE_PORT_TYPE_USB 0x8002
+#define DEBUG_DEVICE_PORT_TYPE_NET 0x8003
+
+#define DEBUG_DEVICE_PORT_SUBTYPE_SERIAL_QCOM 0x0004
+#define DEBUG_DEVICE_PORT_SUBTYPE_SERIAL_QCOM_S850 0x0011
+
+#define DEBUG_DEVICE_PORT_SUBTYPE_NET_QCOM 0x5143
+
+#define DEBUG_DEVICE_PORT_SUBTYPE_USB_QCOM 0x0004
+#define DEBUG_DEVICE_PORT_SUBTYPE_USB30 0x0000
+
+#define DEBUG_DEVICE_OEM_PORT_USBFN 0x0001
+#define DEBUG_DEVICE_OEM_PORT_USBFN_SYNOPSYS 0x0005
+
+// Subtype 3 need to be used only if unaligned access to strongly ordered memory isn't supported by hardware.
+// But it works on all hardware so use this value
+#define DEBUG_DEVICE_OEM_PORT_USBFN_BUFFERED 0x0003
+
+#define NUMBER_OF_DBG_DEVICES 3
+#define MAX_NAME_SPACE_STRING_LENGTH 32
+
+#define ACPI_DDI_V2_2_REGISTER_CNT 2
+#define ACPI_DDI_V3_REGISTER_CNT 1
+
+// ACPI structure declarations.
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 Length;
+ UINT8 BaseAddressRegisterCount;
+ UINT16 NameSpaceStringLength;
+ UINT16 NameSpaceStringOffset;
+ UINT16 OemDataLength;
+ UINT16 OemDataOffset;
+ UINT16 PortType;
+ UINT16 PortSubtype;
+ UINT16 Reserved;
+ UINT16 BaseAddressRegisterOffset;
+ UINT16 AddressSizeOffset;
+} ACPI_DEBUG_DEVICE_INFORMATION_V2;
+
+//
+// v3 Debug Device Information Structure
+//
+typedef struct {
+
+ UINT8 Revision;
+ UINT16 Length;
+ UINT8 BaseAddressRegisterCount;
+ UINT16 NameSpaceStringLength;
+ UINT16 NameSpaceStringOffset;
+ UINT16 OemDataLength;
+ UINT16 OemDataOffset;
+ UINT16 PortType;
+ UINT16 PortSubtype;
+ UINT16 Reserved;
+ UINT16 BaseAddressRegisterOffset;
+ UINT16 AddressSizeOffset;
+ ACPI_GAS DEVICE_ADDRESS;
+ UINT32 ADDRESS_SIZE;
+ UINT8 NameSpacestring[MAX_NAME_SPACE_STRING_LENGTH];
+} ACPI_DEBUG_DEVICE_INFORMATION_V3;
+
+typedef struct {
+ ACPI_HEADER Header;
+ UINT32 OffsetDbgDeviceInfo;
+ UINT32 NumberDbgDeviceInfo;
+} ACPI_DEBUG_PORT_TABLE_V2;
+
+//OEM struct supported by KDNET
+typedef struct {
+ UINT16 PortType;
+ UINT16 Reserved;
+ UINT32 Signature;
+ UINT32 WriteCount;
+ struct {
+ UINT8 BaseAddressRegister;
+ UINT8 Width;
+ UINT16 Offset;
+ UINT32 AndValue;
+ UINT32 OrValue;
+ } Data[MAX_OEM_WRITE_ENTRIES];
+} ACPI_DEBUG_DEVICE_OEM_DATA;
+
+
+//OEM struct for SNPS controller supported by KDNET
+//OEM Phase: 1 = after reset
+// 2 = when configuration is done
+// 3 = on connection done
+typedef struct {
+ UINT16 PortType;
+ UINT16 Reserved;
+ UINT32 Signature;
+ UINT32 WriteCount;
+ struct {
+ UINT8 BaseAddressRegister;
+ UINT8 Phase;
+ UINT16 Reserved;
+ UINT32 Offset;
+ UINT32 AndValue;
+ UINT32 OrValue;
+ } Data[MAX_OEM_WRITE_ENTRIES];
+} ACPI_DEBUG_DEVICE_OEM_DATA_V2;
+
+// OEM Data Strucutre V3 based upon addition of secondary debugger
+//OEM struct for SNPS controller supported by KDNET
+//OEM Phase: 1 = after reset
+// 2 = when configuration is done
+// 3 = on connection done
+typedef struct {
+ UINT16 PortType;
+ UINT16 Reserved;
+ UINT32 Signature;
+ UINT32 WriteCount;
+ struct {
+ UINT8 BaseAddressRegister;
+ UINT8 Phase;
+ UINT16 Reserved;
+ UINT32 Offset;
+ UINT32 AndValue;
+ UINT32 OrValue;
+ } Data[MAX_OEM_WRITE_ENTRIES];
+ struct {
+ UINT8 UsbCore;
+ UINT8 Reserved1;
+ UINT16 Reserved2;
+ UINT32 Signature; // = 'USBC'
+ } ACPI_USB_INIT_CORE_OEM_DATA;
+} ACPI_DEBUG_DEVICE_OEM_DATA_V3;
+
+
+//OEM struct supported by KDUSB, KDNET
+typedef struct {
+
+ UINT32 StructureSize;
+ UINT64 GpioPhysicalAddress;
+ UINT32 GpioBlockSize;
+ UINT32 WriteCount;
+ UINT32 Offset[12];
+ UINT32 Value[12];
+
+} OEM_DATA;
+
+typedef struct {
+ ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation;
+
+ // not part of the actual structure
+ ACPI_GAS BaseAddressRegister;
+ UINT32 AddressSize;
+ UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH];
+} ACPI_DEBUG_DEVICE_INFORMATION_V2_IMPL;
+
+typedef struct {
+ ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation;
+
+ // not part of the actual structure
+ ACPI_GAS BaseAddressRegister;
+ UINT32 AddressSize;
+ UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH];
+ OEM_DATA OemData;
+} ACPI_DEBUG_DEVICE_INFORMATION_V2_1_OEM_IMPL;
+
+typedef struct {
+ ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation;
+
+ // not part of the actual structure
+ ACPI_GAS BaseAddressRegister[ACPI_DDI_V2_2_REGISTER_CNT];
+ UINT32 AddressSize[ACPI_DDI_V2_2_REGISTER_CNT];
+ UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH];
+ ACPI_DEBUG_DEVICE_OEM_DATA OemData;
+} ACPI_DEBUG_DEVICE_INFORMATION_V2_2_OEM_IMPL;
+
+typedef struct {
+ ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation;
+ // not part of the actual structure
+ ACPI_GAS BaseAddressRegister[ACPI_DDI_V2_2_REGISTER_CNT];
+ UINT32 AddressSize[ACPI_DDI_V2_2_REGISTER_CNT];
+ UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH];
+ ACPI_DEBUG_DEVICE_OEM_DATA_V2 OemData;
+} ACPI_DEBUG_DEVICE_INFORMATION_V2_3_OEM_IMPL;
+
+typedef struct {
+ ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation;
+ // not part of the actual structure
+ ACPI_GAS BaseAddressRegister[ACPI_DDI_V2_2_REGISTER_CNT];
+ UINT32 AddressSize[ACPI_DDI_V2_2_REGISTER_CNT];
+ UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH];
+ ACPI_DEBUG_DEVICE_OEM_DATA_V3 OemData;
+} ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL;
+
+typedef struct {
+ ACPI_DEBUG_DEVICE_INFORMATION_V3 DebugDeviceInformation;
+ OEM_DATA OemData;
+} ACPI_DEBUG_DEVICE_INFORMATION_V3_OEM_IMPL;
+
+typedef struct {
+ ACPI_DEBUG_PORT_TABLE_V2 DebugPortTable;
+
+ // not part of the actual structure
+ ACPI_DEBUG_DEVICE_INFORMATION_V2_IMPL DebugDevice1; // UART KDCOM
+ ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL DebugDevice2; // KDNET on primary port on SNPS controller
+ ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL DebugDevice3; // KDNET on secondary port on SNPS controller
+
+} ACPI_DEBUG_PORT_TABLE_V2_IMPL;
+
+#pragma pack()
+
+
+// Fixed field values.
+#define ACPI_DDI_V2_REVISION 1
+#define ACPI_DDI_V2_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_IMPL)
+#define ACPI_DDI_V2_1_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_1_OEM_IMPL)
+#define ACPI_DDI_V2_2_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_2_OEM_IMPL)
+#define ACPI_DDI_V2_3_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_3_OEM_IMPL)
+#define ACPI_DDI_V2_4_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL)
+#define ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2)
+
+// Structure has only one ACPI_GAS for register (1 base address register)
+#define ACPI_DDI_V2_1_ADDRESS_SIZE_OFFSET ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET + 1 * sizeof(ACPI_GAS)
+#define ACPI_DDI_V2_1_NAMESPACE_STRING_OFFSET ACPI_DDI_V2_1_ADDRESS_SIZE_OFFSET + 1 * sizeof(UINT32)
+#define ACPI_DDI_V2_1_OEM_DATA_OFFSET ACPI_DDI_V2_1_NAMESPACE_STRING_OFFSET + MAX_NAME_SPACE_STRING_LENGTH
+
+// Structure has ACPI_DDI_V2_2_REGISTER_CNT ACPI_GAS base registers
+// Change this macro ACPI_DDI_V2_2_REGISTER_CNT based upon number of base address register to be used
+#define ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET + ACPI_DDI_V2_2_REGISTER_CNT * sizeof(ACPI_GAS)
+#define ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET + ACPI_DDI_V2_2_REGISTER_CNT * sizeof(UINT32)
+#define ACPI_DDI_V2_2_OEM_DATA_OFFSET ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET + MAX_NAME_SPACE_STRING_LENGTH
+
+#define ACPI_DPT_V2_LENGTH sizeof(ACPI_DEBUG_PORT_TABLE_V2_IMPL)
+#define ACPI_DPT_V2_REVISION 1
+
+
+// Device namespace strings. (May not be longer than MAX_NAME_SPACE_STRING_LENGTH characters & may not point to same device.)
+#define UART_DEVICE_NAME_SPACE_STRING "\\_SB.UARD"
+#define USB_SS_DEVICE_NAME_SPACE_STRING "\\_SB.URS0" //point to USB3.0 controller
+#define USB_SS1_DEVICE_NAME_SPACE_STRING "\\_SB.USB1" //point to secondary USB3.0 controller
+//URS1 specific
+//#define USB_SS1_DEVICE_NAME_SPACE_STRING "\\_SB.URS1" //point to secondary USB3.0 controller
+
+// ACPI table definition.
+
+ACPI_DEBUG_PORT_TABLE_V2_IMPL DBG2 =
+ {
+ {
+ {
+ ACPI_DBG2_SIGNATURE, // Signature
+ ACPI_DPT_V2_LENGTH, // Length
+ ACPI_DPT_V2_REVISION, // Revision
+ 0, // Checksum
+ ACPI_OEM_ID, // OEMID[ACPI_MAX_OEM_ID]
+ ACPI_OEM_TABLE_ID, // OEMTableID[ACPI_MAX_TABLE_ID]
+ ACPI_OEM_REVISION, // OEMRevision
+ ACPI_CREATOR_ID, // CreatorID[ACPI_MAX_CREATOR_ID]
+ ACPI_CREATOR_REVISION // CreatorRev
+ },
+
+ sizeof(ACPI_DEBUG_PORT_TABLE_V2),
+ NUMBER_OF_DBG_DEVICES
+ },
+
+
+ //
+ // Debug device table.
+ //
+
+
+ // Device UART
+ {
+ {
+ ACPI_DDI_V2_REVISION, // Revision
+ ACPI_DDI_V2_LENGTH, // Length
+ 1, // BaseAddressRegisterCount
+ sizeof(UART_DEVICE_NAME_SPACE_STRING), // NameSpaceStringLength
+ ACPI_DDI_V2_1_NAMESPACE_STRING_OFFSET, // NameSpaceStringOffset
+ 0, // OemDataLength
+ 0, // OemDataOffset
+ DEBUG_DEVICE_PORT_TYPE_SERIAL, // PortType
+ DEBUG_DEVICE_PORT_SUBTYPE_SERIAL_QCOM_S850, // PortSubtype
+ 0, // Reserved
+ ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET, // BaseAddressRegisterOffset
+ ACPI_DDI_V2_1_ADDRESS_SIZE_OFFSET // AddressSizeOffset
+ },
+
+ {
+ ACPI_GAS_ID_SYSTEM_MEMORY,
+ 32,
+ 0,
+ 32,
+ 0xA84000 // BaseAddressRegister
+ },
+ 0x00001000, // AddressSize
+ UART_DEVICE_NAME_SPACE_STRING // NameSpaceString
+ },
+
+ // Device USB SS as KDNET on primary port (SNPS Controller+ QMP/QUSB2 Phy)
+ {
+ {
+ ACPI_DDI_V2_REVISION, // Revision
+ ACPI_DDI_V2_4_OEM_LENGTH, // Length
+ ACPI_DDI_V2_2_REGISTER_CNT, // BaseAddressRegisterCount
+ sizeof(USB_SS_DEVICE_NAME_SPACE_STRING), // NameSpaceStringLength
+ ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET, // NameSpaceStringOffset
+ sizeof(ACPI_DEBUG_DEVICE_OEM_DATA_V3), // OemDataLength
+ ACPI_DDI_V2_2_OEM_DATA_OFFSET, // OemDataOffset
+ DEBUG_DEVICE_PORT_TYPE_NET, // PortType
+ DEBUG_DEVICE_PORT_SUBTYPE_NET_QCOM, // PortSubtype
+ 0, // Reserved
+ ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET, // BaseAddressRegisterOffset
+ ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET // AddressSizeOffset
+ },
+ {
+ { // BaseAddressRegister
+ ACPI_GAS_ID_SYSTEM_MEMORY,
+ 32,
+ 0,
+ 32,
+ 0xA600000 // USB3.0 SNPS base
+ },
+ { // BaseAddressRegister
+ ACPI_GAS_ID_SYSTEM_MEMORY,
+ 32,
+ 0,
+ 32,
+ 0xA600000 // USB3.0 SNPS base
+ }
+ },
+ {
+ 0xFFFFF, // AddressSize
+ 0x1000, // AddressSize
+ },
+ USB_SS_DEVICE_NAME_SPACE_STRING, // NameSpaceString
+ { // OEM Data
+ DEBUG_DEVICE_OEM_PORT_USBFN_SYNOPSYS, // Controller type
+ 0,
+ 'FIX2',
+ 2, // Number of writes
+ {
+ //set HS dev speed
+ {
+ 0, // BaseAddressRegister
+ 2, // Phase
+ 0, // Reserved
+ 0xC700, // Offset
+ 0xfffffff8, // AndValue
+ 0x0 // OrValue
+ },
+ //set ULPI_VBUS_VALID
+ {
+ 0, // BaseAddressRegister
+ 2, // Phase
+ 0, // Reserved
+ 0xf8810, // Offset
+ 0, // AndValue
+ 0x10100000 // OrValue
+ }
+ },
+ {
+ 0, // USB Core Number - Primary (Core 0)
+ 0, //Reserved
+ 0, //Reserved
+ 'USBC' //Signature
+ }
+ } //end OEM data
+ },
+ // Device USB SS as KDNET on seconday port (SNPS Controller+ QMP/QUSB2 Phy)
+ {
+ {
+ ACPI_DDI_V2_REVISION, // Revision
+ ACPI_DDI_V2_4_OEM_LENGTH, // Length
+ ACPI_DDI_V2_2_REGISTER_CNT, // BaseAddressRegisterCount
+ sizeof(USB_SS1_DEVICE_NAME_SPACE_STRING), // NameSpaceStringLength
+ ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET, // NameSpaceStringOffset
+ sizeof(ACPI_DEBUG_DEVICE_OEM_DATA_V3), // OemDataLength
+ ACPI_DDI_V2_2_OEM_DATA_OFFSET, // OemDataOffset
+ DEBUG_DEVICE_PORT_TYPE_NET, // PortType
+ DEBUG_DEVICE_PORT_SUBTYPE_NET_QCOM, // PortSubtype
+ 0, // Reserved
+ ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET, // BaseAddressRegisterOffset
+ ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET // AddressSizeOffset
+ },
+ {
+ { // BaseAddressRegister
+ ACPI_GAS_ID_SYSTEM_MEMORY,
+ 32,
+ 0,
+ 32,
+ 0x0A800000 // USB3.0 SNPS base
+ },
+ { // BaseAddressRegister
+ ACPI_GAS_ID_SYSTEM_MEMORY,
+ 32,
+ 0,
+ 32,
+ 0x0A800000 // USB3.0 SNPS base
+ }
+ },
+ {
+ 0xFFFFF, // AddressSize
+ 0x1000, // AddressSize
+ },
+ USB_SS1_DEVICE_NAME_SPACE_STRING, // NameSpaceString
+ { // OEM Data
+ DEBUG_DEVICE_OEM_PORT_USBFN_SYNOPSYS, // Controller type
+ 0,
+ 'FIX2',
+ 2, // Number of writes
+ {
+ //set HS dev speed
+ {
+ 0, // BaseAddressRegister
+ 2, // Phase
+ 0, // Reserved
+ 0xC700, // Offset
+ 0xfffffff8, // AndValue
+ 0x0 // OrValue
+ },
+ //set ULPI_VBUS_VALID
+ {
+ 0, // BaseAddressRegister
+ 2, // Phase
+ 0, // Reserved
+ 0xf8810, // Offset
+ 0, // AndValue
+ 0x10100000 // OrValue
+ }
+ },
+ {
+ 1, // USB Core Number - Primary (Core 1)
+ 0, //Reserved
+ 0, //Reserved
+ 'USBC' //Signature
+ }
+ } //end OEM data
+ }
+};
+//
// This file contains the GPS ACPI device definitions.
//
{
Name (_DEP, Package(0x1)
{
- \_SB_.GLNK
+ \_SB_.GLNK
})
- Name (_HID, "QCOM02B6")
- Alias(\_SB.PSUB, _SUB)
+ Name (_HID, "QCOM02B6")
+ Alias(\_SB.PSUB, _SUB)
Name (_CID, "ACPI\QCOM24B4")
Name (_UID, 0)
}
+//--------------------------------------------------------------------------------------------------
+// GfxXMLToACPI Version 2.3.
+//--------------------------------------------------------------------------------------------------
+
Scope(\_SB_.PEP0)
{
//-----------------------------------------------------------------------------------------
{
"ENTER",
- Package()
- {
- "TLMMGPIO",
- Package()
- {
- 38, // TLMM GPIO : 38 = DP CC OUT
- 1, // State : 1 = HIGH
- 0, // Function Select : 0 = ??
- 0, // Direction : 0 = INPUT
- 0, // Pull Type : 0 = NOPULL
- 0, // Drive Strength : 0 = 2mA
- },
- },
+ // Package()
+ // {
+ // "TLMMGPIO",
+ // Package()
+ // {
+ // 38, // TLMM GPIO : 38 = DP CC OUT
+ // 1, // State : 1 = HIGH
+ // 0, // Function Select : 0 = ??
+ // 0, // Direction : 0 = INPUT
+ // 0, // Pull Type : 0 = NOPULL
+ // 0, // Drive Strength : 0 = 2mA
+ // },
+ // },
Package()
{
Package() { "CLOCK", Package() { "disp_cc_mdss_dp_aux_clk", 1 }},
Package() { "CLOCK", Package() { "disp_cc_mdss_dp_link_intf_clk", 1 }},
- Package()
- {
- "TLMMGPIO",
- Package()
- {
- 38, // TLMM GPIO : 38 = DP CC OUT
- 1, // State : 1 = HIGH
- 1, // Function Select : 1 = ??
- 1, // Direction : 1 = OUTPUT
- 0, // Pull Type : 0 = NOPULL
- 0, // Drive Strength : 0 = 2mA
- },
- },
+ // Package()
+ // {
+ // "TLMMGPIO",
+ // Package()
+ // {
+ // 38, // TLMM GPIO : 38 = DP CC OUT
+ // 1, // State : 1 = HIGH
+ // 1, // Function Select : 1 = ??
+ // 1, // Direction : 1 = OUTPUT
+ // 0, // Pull Type : 0 = NOPULL
+ // 0, // Drive Strength : 0 = 2mA
+ // },
+ // },
Package()
{
+// This file contains the Bus Access Modules (BAM)
+// ACPI device definitions and pipe configurations
+//
+
//
// Device Map:
// IPA
Return (Zero)
}
- // Wlan_11ad ACPI Enumeration, I don't think it's useful
- // Include("wlan_11ad.asl")
+ //Wlan_11ad ACPI Enumeration
+ Include("wlan_11ad.asl")
Method(_PSC) {
Return(Zero)
}
} // End PCI0
-Include("../common/pcie1.asl")
+Include("../Common/pcie1.asl")
Name (_HID, "QCOM0237")
Name (_CID, "PNP0D80")
- Include("../common/thz.asl") // Driver for Dynamically Changing Thresholds of Thermal Zones
+ Include("../Common/thz.asl")
Method(_CRS)
{
//
// The files where these methods are declared must be included
// at the bottom of this file and must exists inside the scope: \_SB.PEP0
- "DMPO", //oem dummy
+ "DMPO", //oem dummy
"DMSB", // buses resources
"DMQP", // dfs Resources
"DMMS", // SMMU
// This method allows PEP to read Polarity of
// eud_p1_dmse_int_mx & eud_p1_dpse_int_mx
// interrupts which belong to Secondary USB Port (P1)
- Method(DMRF) {
- // Return DMRF
- Return(\_SB.DPP1)
- }
+ // Method(DMRF) {
+ // // Return DMRF
+ // Return(\_SB.DPP1)
+ // }
}
-
// Data required by PEP
-Include("../common/pep_libPdc.asl")
-Include("../common/pep_libPCU.asl")
-Include("../common/pep_vddresources.asl")
-Include("../common/pep_lmh.asl")
-Include("../common/pep_dvreg.asl")
-Include("../common/pep_dbgSettings.asl")
-// Device specific
+Include("../Common/pep_libPdc.asl")
+Include("../Common/pep_libPCU.asl")
+Include("../Common/pep_vddresources.asl")
+Include("../Common/pep_lmh.asl")
+Include("../Common/pep_dvreg.asl")
+Include("../Common/pep_dbgSettings.asl")
Include("pep_defaults.asl")
-
-Include("../common/pep_idle.asl")
-Include("../common/pep_cprh.asl")
-Include("../common/pep_dcvscfg.asl")
-// Device specific, pep_tsens.asl is needed for PEP DeviceAdd
+Include("../Common/pep_idle.asl")
+Include("../Common/pep_cprh.asl")
+Include("../Common/pep_dcvscfg.asl")
+// DO NOT comment next line, since pep_tsens.asl is needed for PEP DeviceAdd
Include("pep_tsens.asl")
// Resources by area
-Include("../common/audio_resources.asl")
-Include("../common/graphics_resources.asl")
-Include("../common/HoyaSmmu_resources.asl")
-// Include("msft_resources.asl")
-Include("../common/oem_resources.asl")
-Include("../common/subsys_resources.asl")
-Include("../common/pep_resources.asl")
-Include("../common/corebsp_resources.asl")
-Include("../common/ipa_resources.asl")
-// Include("crypto_resources.asl")
-Include("../common/wcnss_resources.asl")
-// Include("cust_wcnss_resources.asl")
-Include("../common/qdss_resources.asl")
-Include("../common/pcie_resources.asl")
+Include("../Common/audio_resources.asl")
+Include("../Common/graphics_resources.asl")
+Include("../Common/HoyaSmmu_resources.asl")
+Include("../Common/oem_resources.asl")
+Include("../Common/subsys_resources.asl")
+Include("../Common/pep_resources.asl")
+Include("../Common/corebsp_resources.asl")
+Include("../Common/ipa_resources.asl")
+Include("../Common/wcnss_resources.asl")
+Include("../Common/qdss_resources.asl")
+Include("../Common/pcie_resources.asl")
//
//===========================================================================
-
-
Scope(\_SB_.PEP0)
{
-//
// This file contains common Power Management IC (PMIC) ACPI device definitions
//
Device (PRTC)
{
Name(_HID, "ACPI000E")
- Name (_DEP,
- Package(0x1) {
- \_SB_.PMAP
- }
- )
+ Name(_DEP, Package() {"\\_SB.PMAP"}) // PRTC is dependent on PMAP which implements the RTC Functions
//Get the capabilities of the time and alarm device
Method(_GCP)
//===========================================================================
//===========================================================================
-// Description & Possible use cases for Qdss's p-state implementation
+// Description & Possible use cases for Qdss's p-state implementation
// Qdss employs pstate-sets to robustly configure clock and tlmm registers
// pstate-set 0 has pstates for clock frequencies
// pstate-set 1 has pstates for managing tlmm registers for tpiu operation
+//
// This file contains the QUPv3 ACPI device definitions.
// GPI is the interface used by buses drivers for different peripherals.
//
Method(_STA, 0)
{
- return (0xB) // Loaded, but hidden
+ return (0x0) // Disabled
}
Method (_CRS, 0x0, NotSerialized)
Return(RBUF)
}
- Include("../common/spmi_conf.asl")
+ Include("../Common/spmi_conf.asl")
}
// System Cache Driver
//
-
Device (LLC)
{
Name (_DEP, Package(0x1)
+//
+// This file contains ACPI definitions, configuration and look-up tables
+// for Bluetooth Device
+//
+
//
// WCN3990 Bluetooth
//
0, // Head Room
},
},
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO7_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 1800000, // Voltage = 1.8 V
+ 1, // Software Enable = Enable
+ 7, // Software Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO17_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 1304000, // Voltage = 1.3 V
+ 1, // Software Enable = Enable
+ 7, // Software Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO25_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 3104000, // Voltage = 3.1 V
+ 1, // Software Enable = Enable
+ 7, // Software Power Mode = NPM
+ 0, // Head Room
+ },
+ },
},
Package()
{
"DSTATE",
0x2, // D2 state
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO25_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // Software Enable = Disable
+ 5, // Software Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO17_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // Software Enable = Disable
+ 5, // Software Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO7_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // Software Enable = Disable
+ 5, // Software Power Mode = LPM
+ 0, // Head Room
+ },
+ },
Package()
{
"PMICVREGVOTE",
"DSTATE",
0x3, // D3 state
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO25_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // Software Enable = Disable
+ 5, // Software Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO17_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // Software Enable = Disable
+ 5, // Software Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO7_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // Software Enable = Disable
+ 5, // Software Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+
Package()
{
"PMICVREGVOTE",
0, // Head Room
},
},
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO7_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 1800000, // Voltage = 1.8 V
+ 1, // Software Enable = Enable
+ 7, // Software Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO17_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 1304000, // Voltage = 1.3 V
+ 1, // Software Enable = Enable
+ 7, // Software Power Mode = NPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO25_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 3104000, // Voltage = 3.1 V
+ 1, // Software Enable = Enable
+ 7, // Software Power Mode = NPM
+ 0, // Head Room
+ },
+ },
},
Package()
{
"PSTATE",
0x1, // P1 state
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO25_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // Software Enable = Disable
+ 5, // Software Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO17_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // Software Enable = Disable
+ 5, // Software Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+ package()
+ {
+ "PMICVREGVOTE",
+ package()
+ {
+ "PPP_RESOURCE_ID_LDO7_A", // Resource ID
+ 1, // Voltage Regulator type 1 = LDO
+ 0, // Voltage = 0 V
+ 0, // Software Enable = Disable
+ 5, // Software Power Mode = LPM
+ 0, // Head Room
+ },
+ },
+
Package()
{
"PMICVREGVOTE",
}
- Include("../common/slimbus.asl")
+
+ Include("../Common/slimbus.asl")
}
Name (WLEN, 0x1) // Holds the enable/disable flag for WLAN
-
+ Method(_STA, 0)
+ {
+ return (0xf)
+ }
Method (_CRS, 0x0, NotSerialized)
{
})
}
- Method(_STA, 0)
- {
- return (0xf)
- }
-
Include("wcnss_wlan.asl")
}
}
// Warning: Include these files after device scopes have been defined
-// Include("cust_win_mproc.asl") // Customer specific data
-// Include("plat_win_mproc.asl") // Platform specific data
+//Include("cust_win_mproc.asl") // Customer specific data
+Include("plat_win_mproc.asl") // Platform specific data
+++ /dev/null
-//
-// Secure Channel Manager (SCM) Driver
-//
-Device (SCM0)
-{
- Name (_HID, "QCOM0214")
- Alias(\_SB.PSUB, _SUB)
- Name (_UID, 0)
-}
-
-//
-// TrEE Driver
-//
-// Device (TREE)
-// {
-// Name (_HID, "QCOM02BB")
-// Alias(\_SB.PSUB, _SUB)
-// Name (_UID, 0)
-
-// Method (IMPT)
-// {
-// Name(TPPK, Package()
-// {
-// Package ()
-// {
-// // Holds whether TPM is seperate app or not
-// 0x00000000, // Will be filled by TPMA
-// // Holds TPM type
-// 0x00000000, // Will be filled by TDTV
-// // Holds TrEE Carveout address
-// 0x00000000, // Will be filled by TCMA
-// // Holds TrEE Carveout length
-// 0x00000000 // Will be filled by TCML
-// }
-// })
-
-// // Copy ACPI globals for Address for this subsystem into above package for use in driver
-// Store (TPMA, Index(DeRefOf(Index (TPPK, 0)), 0))
-// Store (TDTV, Index(DeRefOf(Index (TPPK, 0)), 1))
-// Store (TCMA, Index(DeRefOf(Index (TPPK, 0)), 2))
-// Store (TCML, Index(DeRefOf(Index (TPPK, 0)), 3))
-
-// Return (TPPK)
-// }
-// }
-
-// HACK!
-Device (TREE)
-{
- Name (_HID, "QCOM02BB") // _HID: Hardware ID
- Alias (\_SB.PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Method (MCGT, 0, NotSerialized)
- {
- Name (TPKG, Package (One)
- {
- Package (0x02)
- {
- Zero,
- Zero
- }
- })
- DerefOf (TPKG [Zero]) [Zero] = TCMA /* \_SB_.TCMA */
- DerefOf (TPKG [Zero]) [One] = TCML /* \_SB_.TCML */
- Return (TPKG) /* \_SB_.TREE.MCGT.TPKG */
- }
-}
+++ /dev/null
-//===========================================================================
-// <corebsp_resources.asl>
-// DESCRIPTION
-// This file contans the resources needed by core BSP drivers.
-//
-//===========================================================================
-
-
-Scope(\_SB_.PEP0)
-{
-
- Method(BPMD)
- {
- Return(BPCC)
- }
-
- Method(LPMD)
- {
- Return(LPCC)
- }
-
- Name(BPCC,
- Package ()
- {
- Package()
- {
- "DEVICE",
- "\\_SB.UFS0",
- Package()
- {
- "COMPONENT",
- 0x0, // Component 0.
- Package()
- {
- "FSTATE",
- 0x0, // f0 state
- Package() { "PSTATE_ADJUST", Package() { 0, 0 } },
- Package() { "PSTATE_ADJUST", Package() { 1, 0 } },
- Package() { "PSTATE_ADJUST", Package() { 2, 0 } },
- },
- Package()
- {
- "FSTATE",
- 0x1, // f1 state
- Package() { "PSTATE_ADJUST", Package() { 2, 1 } },
- Package() { "PSTATE_ADJUST", Package() { 1, 1 } },
- Package() { "PSTATE_ADJUST", Package() { 0, 1 } },
- },
-
- Package()
- {
- "PSTATE_SET",
- 0x0,
-
- Package()
- {
- "PSTATE",
- 0x0,
- Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 1 }},
- },
- Package()
- {
- "PSTATE",
- 0x1,
- Package() { "FOOTSWITCH", Package() { "ufs_phy_gdsc", 2 }},
- },
- },
-
- Package()
- {
- "PSTATE_SET",
- 0x1,
-
- Package()
- {
- "PSTATE",
- 0x0,
-
- Package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 8, 200000000, 2}},
- package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 8, 150000000, 2}},
- package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 8, 300000000, 2}},
-
- Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 1,}},
- Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 1,}},
- Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 1,}},
- Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 1,}},
- Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 1,}},
- Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 1,}},
- Package() {"CLOCK", Package() {"gcc_ufs_mem_clkref_en", 1,}},
- },
- Package()
- {
- "PSTATE",
- 0x1,
-
- Package() {"CLOCK", Package() {"gcc_aggre_ufs_phy_axi_clk", 2,}},
- Package() {"CLOCK", Package() {"gcc_ufs_phy_ahb_clk", 2,}},
- Package() {"CLOCK", Package() {"gcc_ufs_phy_phy_aux_clk", 2,}},
- Package() {"CLOCK", Package() {"gcc_ufs_phy_tx_symbol_0_clk", 2,}},
- Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_0_clk", 2,}},
- Package() {"CLOCK", Package() {"gcc_ufs_phy_rx_symbol_1_clk", 2,}},
- package() {"CLOCK", package() {"gcc_ufs_phy_ice_core_clk", 2,}},
- package() {"CLOCK", package() {"gcc_ufs_phy_unipro_core_clk", 2,}},
- package() {"CLOCK", package() {"gcc_ufs_phy_axi_clk", 2,}},
- package() {"CLOCK", package() {"gcc_ufs_mem_clkref_en", 2,}},
- },
- },
-
- Package()
- {
- "PSTATE_SET",
- 0x2,
-
- Package()
- {
- "PSTATE",
- 0x0,
- Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 900000000, 900000000}},
- Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 299000000, 0}},
- },
- Package()
- {
- "PSTATE",
- 0x1,
- Package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_UFS_MEM_CFG", 0, 0}},
- Package() {"BUSARB", Package() { 3, "ICBID_MASTER_UFS_MEM", "ICBID_SLAVE_EBI1", 0, 0}},
- },
- },
- },
-
- Package()
- {
- "DSTATE",
- 0x0, // D0 state
-
- Package() {"PSTATE_ADJUST", Package() { 2, 0 } },
-
- Package() {"PSTATE_ADJUST", Package() { 0, 0 } },
-
- // Vcc supply = L20
- Package()
- {
- "PMICVREGVOTE",
- Package()
- {
- "PPP_RESOURCE_ID_LDO20_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 2960000, // Voltage is in micro volts
- 1, // force enable from software
- 7, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
-
- // Vccq supply = L2
- Package()
- {
- "PMICVREGVOTE",
- Package()
- {
- "PPP_RESOURCE_ID_LDO2_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage is in micro volts
- 1, // force enable from software
- 7, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
-
- // Vccq2 supply = S4
- Package()
- {
- "PMICVREGVOTE",
- Package()
- {
- "PPP_RESOURCE_ID_SMPS4_A",
- 2, // Voltage Regulator type = SMPS
- 1800000, // 1.8V
- 1, // Force enable from software
- 0, // Power mode - AUTO
- 0, // head room voltage
- },
- },
-
- // PHY VDDA supply: L26
- Package()
- {
- "PMICVREGVOTE",
- Package()
- {
- "PPP_RESOURCE_ID_LDO26_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage is in micro volts
- 1, // force enable from software
- 7, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
-
- // VDDA_UFS_CORE supply: L1
- Package()
- {
- "PMICVREGVOTE",
- Package()
- {
- "PPP_RESOURCE_ID_LDO1_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage is in micro volts
- 1, // force enable from software
- 7, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
-
- Package() {"DELAY", package() { 35 }},
-
- Package() {"PSTATE_ADJUST", Package() { 1, 0 } },
- },
- Package()
- {
- "DSTATE",
- 0x3, // D3 state
-
- Package() {"PSTATE_ADJUST", Package() { 1, 1 } },
-
- Package()
- {
- "PMICVREGVOTE",
- Package()
- {
- "PPP_RESOURCE_ID_LDO1_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage is in micro volts
- 0, // force enable from software
- 0, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
-
- Package()
- {
- "PMICVREGVOTE",
- Package()
- {
- "PPP_RESOURCE_ID_LDO26_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage is in micro volts
- 0, // force enable from software
- 0, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
-
- Package()
- {
- "PMICVREGVOTE",
- Package()
- {
- "PPP_RESOURCE_ID_LDO20_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage is in micro volts
- 0, // force enable from software
- 0, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
-
- Package() {"PSTATE_ADJUST", Package() { 0, 1 } },
-
- Package() {"PSTATE_ADJUST", Package() { 2, 1 } },
- },
- },
- Package()
- {
- "DEVICE",
- "\\_SB.SDC2",
- Package()
- {
- "COMPONENT",
- 0x0, // Component 0.
- Package()
- {
- "FSTATE",
- 0x0, // f0 state
- },
- Package()
- {
- "FSTATE",
- 0x1, // f1 state
- },
-
- Package()
- {
- "PSTATE_SET",
- 0x0,
-
- //
- // Contract with SDBUS for card frequencies
- //
- // P-State Note
- // -------- -----
- // 0 - 19 Reserved (Legacy)
- // 20 Reset to 3.3v signal voltage (max fixed at 2.95v)
- // 21 1.8v signal voltage (max fixed at 1.85v)
- Package(){"PSTATE", 0, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 1, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 2, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 3, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 4, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 5, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 6, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 7, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 8, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 9, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 11, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 12, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 13, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 14, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 15, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 16, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 17, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 18, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 19, Package(){"DELAY", package() { 1 }}},
- Package(){"PSTATE", 20,
- Package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- Package()
- {
- "PPP_RESOURCE_ID_LDO21_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage is in micro volts
- 0, // force disable from software
- 0, // power mode - Low Power Mode
- 0, // head room voltage
- },
- },
- Package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- Package()
- {
- "PPP_RESOURCE_ID_LDO13_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage is in micro volts
- 0, // force disable from software
- 0, // power mode - Low Power Mode
- 0, // head room voltage
- },
- },
- Package() {"DELAY", package() { 35 }},
- Package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- Package()
- {
- "PPP_RESOURCE_ID_LDO21_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 2960000, // Voltage is in micro volts
- 1, // force enable from software
- 7, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
- Package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- Package()
- {
- "PPP_RESOURCE_ID_LDO13_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 2960000, // Voltage is in micro volts
- 1, // force enable from software
- 7, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
- Package() {"DELAY", package() { 35 }},
- },
- Package(){"PSTATE", 21,
- Package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- Package()
- {
- "PPP_RESOURCE_ID_LDO13_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 1850000, // Voltage is in micro volts
- 1, // force enable from software
- 7, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
- Package() {"DELAY", package() { 35 }},
- },
- Package(){"PSTATE", 22,
- Package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- Package()
- {
- "PPP_RESOURCE_ID_LDO21_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 2960000, // Voltage is in micro volts
- 1, // force enable from software
- 7, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
- Package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- Package()
- {
- "PPP_RESOURCE_ID_LDO13_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 2960000, // Voltage is in micro volts
- 1, // force enable from software
- 7, // power mode - Normal Power Mode
- 0, // head room voltage
- },
- },
- Package() {"DELAY", package() { 35 }},
- },
- Package(){"PSTATE", 23,
- Package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- Package()
- {
- "PPP_RESOURCE_ID_LDO21_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage is in micro volts
- 0, // force disable from software
- 0, // power mode - Low Power Mode
- 0, // head room voltage
- },
- },
- Package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- Package()
- {
- "PPP_RESOURCE_ID_LDO13_A", // VREG ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage is in micro volts
- 0, // force disable from software
- 0, // power mode - Low Power Mode
- 0, // head room voltage
- },
- },
- Package() {"DELAY", package() { 35 }},
- },
- },
-
- // P-state set 1: APPS Clock frequencies
- // 0: Disable
- // 1: 20 MHz (SVS2)
- // 2: 100 MHz (SVS)
- // 3: 201.5 MHz (Nominal)
- Package()
- {
- "PSTATE_SET",
- 0x1,
-
- Package()
- {
- "PSTATE",
- 0x0,
- package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 2}},
- },
- Package()
- {
- "PSTATE",
- 0x1,
- package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 20000000, 2}},
- },
- Package()
- {
- "PSTATE",
- 0x2,
- package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 100000000, 2}},
- },
- Package()
- {
- "PSTATE",
- 0x3,
- package() {"CLOCK", package() {"gcc_sdcc2_apps_clk", 8, 201500000, 2}},
- },
- },
-
- // P-state set 2: Bus Bandwidth requests
- // P0: IB = 400 MBps, AB = 200 MBps
- // P1: IB = 200 MBps, AB = 100 MBps
- // P2: IB = 40 MBps, AB = 20 MBps
- // P3: IB = 0 MBps, AB = 0 MBps
- Package()
- {
- "PSTATE_SET",
- 0x2,
-
- Package()
- {
- "PSTATE",
- 0x0,
- package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 400000000, 200000000}},
- },
-
- Package()
- {
- "PSTATE",
- 0x1,
- package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 200000000, 100000000}},
- },
-
- Package()
- {
- "PSTATE",
- 0x2,
- package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 40000000, 20000000}},
- },
-
- Package()
- {
- "PSTATE",
- 0x3,
- package() {"BUSARB", Package() { 3, "ICBID_MASTER_SDCC_2", "ICBID_SLAVE_EBI1", 0, 0}},
- },
- },
-
- // P-state set 3: MSFT P-states
- // P0: Clk = 200 MHz, IB = 400 MBps, AB = 200 MBps
- // P1: Clk = 100 MHz, IB = 200 MBps, AB = 100 MBps
- // P2: Clk = 20 MHz, IB = 40 MBps, AB = 20 MBps
- Package()
- {
- "PSTATE_SET",
- 0x3,
-
- Package()
- {
- "PSTATE",
- 0x0,
- Package() { "PSTATE_ADJUST", Package() { 1, 3 } },
- Package() { "PSTATE_ADJUST", Package() { 2, 0 } },
- },
- Package()
- {
- "PSTATE",
- 0x1,
- Package() { "PSTATE_ADJUST", Package() { 1, 2 } },
- Package() { "PSTATE_ADJUST", Package() { 2, 1 } },
- },
- Package()
- {
- "PSTATE",
- 0x2,
- Package() { "PSTATE_ADJUST", Package() { 1, 1 } },
- Package() { "PSTATE_ADJUST", Package() { 2, 2 } },
- },
- },
-
-
- // P-state set 4: AHB clock
- Package()
- {
- "PSTATE_SET",
- 0x4,
-
- Package()
- {
- "PSTATE",
- 0x0,
- package() {"CLOCK", package() {"gcc_sdcc2_ahb_clk", 1,}}, // AHB freq should be 100 MHz
- },
- Package()
- {
- "PSTATE",
- 0x1,
- package() {"CLOCK", package() {"gcc_sdcc2_ahb_clk", 2}},
- },
- },
- },
-
- Package()
- {
- "DSTATE",
- 0x0, // D0 state
-
- Package() {"PSTATE_ADJUST", Package () { 0, 22 }},
- package() {"TLMMPORT", package() { 0x99A000, 0x7FFF, 0x1FE4 }},
- Package() {"PSTATE_ADJUST", Package() { 2, 0 }},
- Package() {"PSTATE_ADJUST", Package() { 4, 0 }},
- Package() {"PSTATE_ADJUST", Package() { 1, 3 }},
- },
- Package()
- {
- "DSTATE",
- 0x3, // D3 state
-
- Package() {"PSTATE_ADJUST", Package() { 1, 0 }},
- Package() {"PSTATE_ADJUST", Package() { 4, 1 }},
- Package() {"PSTATE_ADJUST", Package() { 2, 3 }},
- package() {"TLMMPORT", package() { 0x99A000, 0x7FFF, 0xA00 }},
- Package() {"PSTATE_ADJUST", Package () { 0, 23 }},
- },
- },
- ///////////////////////////////////////////////////////////////////////////////////////
-
- Package()
- {
- "DEVICE",
- "\\_SB.ADSP.SLM1",
- Package()
- {
- "COMPONENT",
- 0x0, // Component 0
- Package()
- {
- "FSTATE",
- 0x0, // f0 state
- },
- },
- Package()
- {
- "DSTATE",
- 0x0, // D0 state
- },
- Package()
- {
- "DSTATE",
- 0x1, // D1 state
- },
- Package()
- {
- "DSTATE",
- 0x2, // D2 state
- },
- Package()
- {
- "DSTATE",
- 0x3, // D3 state
- },
- },
- Package()
- {
- "DEVICE",
- "\\_SB.ADSP.SLM2",
- Package()
- {
- "COMPONENT",
- 0x0, // Component 0
- Package()
- {
- "FSTATE",
- 0x0, // f0 state
- },
- },
- Package()
- {
- "DSTATE",
- 0x0, // D0 state
- },
- Package()
- {
- "DSTATE",
- 0x1, // D1 state
- },
- Package()
- {
- "DSTATE",
- 0x2, // D2 state
- },
- Package()
- {
- "DSTATE",
- 0x3, // D3 state
- },
- },
- /////////////////////////////////////////////////////////////////////////////////////
- })
-
- Name(LPCC,
- package ()
- {
- Package()
- {
- "DEVICE",
- "\\_SB.UCP0",
- Package()
- {
- "COMPONENT",0, //Component 0: USB HS Rails for Charger Detection
- Package(){"FSTATE", 0 }, //Dummy F-State, required for P-State operation
- Package()
- {
- "PSTATE", 0, // P0 state - Component ON
- //Nominal==block vdd_min:
- package()
- {
- "NPARESOURCE",
- Package() {1, "/arc/client/rail_cx", 256}
- },
- // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- //BUS Arbiter Request (Type-3)
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 400000000, // IB=400 MBps
- 0 // AB=0 MBps
- }
- },
- // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
- },
- Package()
- {
- "PSTATE", 1, // P1 state - Component OFF
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
- //Enable vdd_min:
- package()
- {
- "NPARESOURCE",
- Package() {1, "/arc/client/rail_cx", 0}
- },
-
- },
- },
- //D states
- package() {
- "DSTATE", 0x0, // D0 state
- },
- package() {
- "DSTATE", 0x1, // D1 state
- },
- package() {
- "DSTATE", 0x2, // D2 state
- },
- package() {
- "DSTATE", 0x3, // D3 state
- },
- },
-
- //PMIC Type-C Controller
- //Component 0: USB HS rails for Automiatic Port Source Detection (APSD)
- Package()
- {
- "DEVICE",
- "\\_SB.PTCC",
- Package()
- {
- "COMPONENT",0, //Component 0: USB HS Rails for Charger Detection
- Package(){"FSTATE", 0 }, //Dummy F-State, required for P-State operation
- Package()
- {
- "PSTATE", 0, // P0 state - Component ON
- // LDO 24: ON, 3.075V, LDO 12: ON, 1.8V
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L24 @3.075v
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 1, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L12 @1.8v
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage 1.8V : microvolts ( V )
- 1, // SW Enable = Enable
- 1, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- },
- Package()
- {
- "PSTATE", 1, // P1 state - Component OFF
- // LDO 24 & LDO 12 : OFF
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @0v
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 0, // Voltage = 0 V
- 0, // SW Enable = Disable
- 0, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE",
- package() // Vote for L12 @0v
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage : 0 microvolts ( V )
- 0, // SW Enable = Disable
- 0, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- },
- //D states
- package() {
- "DSTATE", 0x0, // D0 state
- },
- package() {
- "DSTATE", 0x1, // D1 state
- },
- package() {
- "DSTATE", 0x2, // D2 state
- },
- package() {
- "DSTATE", 0x3, // D3 state
- },
- }, //End PMIC Type-C Controller
- Package()
- {
- "DEVICE",
- "\\_SB.URS0",
- Package()
- {
- "COMPONENT",
- Zero,
- Package() {"FSTATE", 0},
- Package() {"PSTATE", 0},
- Package() {"PSTATE", 1}
- },
- Package() {"DSTATE", 0 },
- Package() {"DSTATE", 1 },
- Package() {"DSTATE", 2 },
- Package() {"DSTATE", 3 }
- },
-
-
- //USB SS/HS1 core (Host Stack)
- Package()
- {
- "DEVICE",
- "\\_SB.URS0.USB0",
- Package()
- {
- "COMPONENT",
- 0x0, // Component 0.
- Package() { "FSTATE", 0x0, },
- package()
- {
- "PSTATE",
- 0x0,
- // Enable USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}},
- // Mark Suppressible for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}},
- // Mark Always On for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}},
- //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL
- // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}},
- // Enable PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}},
- // Mark Suppressible for USB PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}},
- },
- package()
- {
- "PRELOAD_PSTATE",
- 0,
- },// index 0 is P-state 0 here
- },
- //D states
- Package()
- { // HOST D0
- "DSTATE",
- 0x0,
- //Power Grid for SDM850
- package()
- {
- // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L12 @1.8v
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage 1.8V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L24 @3.075v
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 - VDDA_USB_SS_1P2 (QMP PHY)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L26 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
-
- // Enable usb30_prim_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_prim_gdsc", // USB 3.0 Core Power domain
- 1, //1==Enable
- },
- },
-
- // Now Enable all the clocks
-
- //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}},
-
- // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
- // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}},
-
- // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}},
-
- //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz
- package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 8, 19200, 7}},
-
- // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
- package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}},
-
- //Vote for max freq: BUS Arbiter Request (Type-3)
- // Instantaneous BW BytesPerSec = 671088640;
- // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
- package()
- {
- "BUSARB",
- Package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_0", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 671088640, // IB=5Gbps //LowSVS
- 671088640 // AB=5Gbps
- }
- },
-
- //Nominal==block vdd_min:
- package()
- {
- "NPARESOURCE",
- Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact)
- //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact)
- },
-
- // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- //BUS Arbiter Request (Type-3)
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact)
- //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact)
- 0 // AB=0 MBps
- }
- },
- // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
-
- // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
- package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}},
- },
- package()
- { // HOST D1
- "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend)
- 0x1,
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
-
- //Disable aggre_usb3_prim_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package()
- {
- "CLOCK",
- package() { "gcc_usb3_prim_phy_aux_clk", 2}
- },
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
-
- //BUS Arbiter Request (Type-3)
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_0",// Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package()
- {
- "NPARESOURCE",
- package() { 1, "/arc/client/rail_cx", 0}
- },
-
- package()
- {
- "PMICVREGVOTE",
- package() //Vote for L12 @1.8v
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @3.075v
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- package()
- {
- // L26 is used for QMP PHY
- // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L26 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- package()
- { // HOST D2
- "DSTATE",
- 0x2, // Slave device disconnect (host cable is still connected)
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
-
- // Disable aggre_usb3_prim_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
-
-
- // Enable usb30_prim_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_prim_gdsc", // USB 3.0 Core Power domain
- 1, //1==Enable
- },
- },
-
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- Package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_0", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package()
- {
- "NPARESOURCE",
- package() { 1, "/arc/client/rail_cx", 0}
- },
-
- //Power Grid for SDM850
- package()
- {
- "PMICVREGVOTE",
- package() //Vote for L12 @1.8v
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @3.075v
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 is used for QMP PHY
- // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- },
- package()
- { // HOST D3
- "DSTATE",
- 0x3, // Abandon state
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
-
- // Disable aggre_usb3_prim_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
-
- // Disable usb30_prim_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_prim_gdsc", // USB 3.0 Core Power domain
- 2, // 2==Disable
- },
- },
-
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_0",// Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}},
-
- //Power Grid for SDM850
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 0, // Voltage = 0 V
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE",
- package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage : 0 microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage 0 V : microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- package() // Vote for L1 @ 0 v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage (microvolts)
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- // Define Abandon State for USB0 (host) stack ie. Power State invoked when stack unloads/tears down
- package()
- {
- "ABANDON_DSTATE",
- 3 // Abandon D state defined as D3
- },
- }, //End USB0
- //
- //************************* USB3.0 SS/HS0 core (Peripheral Stack) ****************************
- //
- package()
- {
- "DEVICE",
- "\\_SB.URS0.UFN0",
- package()
- {
- "COMPONENT",
- 0x0,
- // F-State placeholders
- package()
- {
- "FSTATE",
- 0x0,
- },
- package()
- {
- "PSTATE",
- 0x0,
- // Enable USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}},
- // Mark Suppressible for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}},
- // Mark Always On for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}},
-
- //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL
- // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}},
- // Enable PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}},
- // Mark Suppressible for USB PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}},
- },
- package()
- {
- "PRELOAD_PSTATE",
- 0,
- },// index 0 is P-state 0 here
- },
-
- package()
- { // PERIPH D0
- "DSTATE",
- 0x0,
- //Power Grid for SDM850
- package()
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L12 @1.8v
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage 1.8V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L24 @ 3.075v
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 - VDDA_USB_SS_1P2 (QMP PHY)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
-
- // Enable usb30_prim_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_prim_gdsc", // USB 3.0 Core Power domain
- 1, //1==Enable
- },
- },
-
- //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}},
-
- // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
- // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}},
-
- // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}},
-
- // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
- package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}},
-
- // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- //BUS Arbiter Request (Type-3)
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 400000000, // IB=400 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
-
- //Vote for max freq: BUS Arbiter Request (Type-3)
- // Instantaneous BW BytesPerSec = 671088640;
- // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
- package()
- {
- "BUSARB",
- Package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_0", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 671088640, // IB=5Gbps
- 671088640 // AB=5Gbps
- }
- },
-
- //Nominal==block vdd_min:
- package()
- {
- "NPARESOURCE",
- Package() {1, "/arc/client/rail_cx", 256}
- },
-
- // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
- package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}},
-
- },
- package()
- {
- // PERIPH D1: Not supported by USBFN driver
- "DSTATE", //USB SS+HS suspend state
- 0x1,
- },
- package()
- { // PERIPH D2
- "DSTATE", //USB DCP/HVDCP charger state
- 0x2,
-
- // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}},
-
- // Disable USB 3.0 Master Clock 2 = Disable ;
- package() {"CLOCK", package() { "gcc_usb30_prim_master_clk", 2 } },
-
- // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
-
- //Disable aggre_usb3_prim_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
-
- //Disable gcc_usb3_prim_phy_aux_clk
- package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2}},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
-
-
- //BUS Arbiter Request (Type-3)
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_0", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- //Nominal==block vdd_min:
- package()
- {
- "NPARESOURCE",
- package() {1, "/arc/client/rail_cx", 256}
- },
-
- package()
- {
- "PMICVREGVOTE",
- package() //Vote for L12 @1.8v
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @3.075v
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 is used for QMP PHY
- // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage 0V : microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage (microvolts)
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- package()
- {
- // PERIPH D3
- "DSTATE",
- 0x3, // Detach State
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
-
- //Disable aggre_usb3_prim_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
- // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization
- // No option of enabling it through ACPI
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
-
-
- // Disable usb30_prim_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_prim_gdsc", // USB 3.0 Core Power domain
- 2, // 2==Disable
- },
- },
-
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_0",// Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 Mbps
- }
- },
-
- //enable vdd_min
- package()
- {
- "NPARESOURCE",
- package() { 1, "/arc/client/rail_cx", 0}
- },
-
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 0, // Voltage = 0 V
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE",
- package() // Vote for L12 @0V - VDDA_QUSB_HS0_1P8
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage : 0 microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @0v - VDDA_USB_SS_1P2
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage : 0 microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage (microvolts)
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- // Define Abandon State for UFN0 (peripheral) stack ie. Power State invoked when stack unloads/tears down
- package()
- {
- "ABANDON_DSTATE",
- 3 // Abandon D state defined as D3
- },
- }, //End UFN0
-
- //USB Primary Core (Host Stack) Standalone
- Package()
- {
- "DEVICE",
- "\\_SB.USB0",
- Package()
- {
- "COMPONENT",
- 0x0, // Component 0.
- Package() { "FSTATE", 0x0, },
- package()
- {
- "PSTATE",
- 0x0,
- // Enable USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}},
- // Mark Suppressible for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}},
- // Mark Always On for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}},
- //Select external source action for gcc_usb3_prim_phy_pipe_clk, Sourced by QMP Phy PLL
- // package() {"CLOCK", package() {"gcc_usb3_prim_phy_pipe_clk", 6, 0, 0, 0x0}},
- // Enable PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}},
- // Mark Suppressible for USB PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}},
- },
- package()
- {
- "PRELOAD_PSTATE",
- 0,
- },// index 0 is P-state 0 here
- },
- //D states
- Package()
- { // HOST D0
- "DSTATE",
- 0x0,
- //Power Grid for SDM850
- package()
- {
- // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L12 @1.8v
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage 1.8V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L24 @3.075v
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 - VDDA_USB_SS_1P2 (QMP PHY)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L26 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
-
- // Enable usb30_prim_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_prim_gdsc", // USB 3.0 Core Power domain
- 1, //1==Enable
- },
- },
-
- // Now Enable all the clocks
-
- //aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}},
-
- // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
- // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}},
-
- // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}},
-
- //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz
- package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 8, 19200, 7}},
-
- // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
- package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}},
-
- //Vote for max freq: BUS Arbiter Request (Type-3)
- // Instantaneous BW BytesPerSec = 671088640;
- // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
- package()
- {
- "BUSARB",
- Package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_0", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 671088640, // IB=5Gbps //LowSVS
- 671088640 // AB=5Gbps
- }
- },
-
- //Nominal==block vdd_min:
- package()
- {
- "NPARESOURCE",
- Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact)
- //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact)
- },
-
- // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- //BUS Arbiter Request (Type-3)
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact)
- //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact)
- 0 // AB=0 MBps
- }
- },
- // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
-
- // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
- package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 1}},
- },
- package()
- { // HOST D1
- "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend)
- 0x1,
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600, 5}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
-
- //Disable aggre_usb3_prim_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package()
- {
- "CLOCK",
- package() { "gcc_usb3_prim_phy_aux_clk", 2}
- },
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
-
- //BUS Arbiter Request (Type-3)
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_0",// Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package()
- {
- "NPARESOURCE",
- package() { 1, "/arc/client/rail_cx", 0}
- },
-
- package()
- {
- "PMICVREGVOTE",
- package() //Vote for L12 @1.8v
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @3.075v
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- package()
- {
- // L26 is used for QMP PHY
- // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L26 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- package()
- { // HOST D2
- "DSTATE",
- 0x2, // Slave device disconnect (host cable is still connected)
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
-
- // Disable aggre_usb3_prim_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
- // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization
- // No option of enabling it through ACPI
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
-
-
- // Enable usb30_prim_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_prim_gdsc", // USB 3.0 Core Power domain
- 1, //1==Enable
- },
- },
-
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- Package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_0", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package()
- {
- "NPARESOURCE",
- package() { 1, "/arc/client/rail_cx", 0}
- },
-
- //Power Grid for SDM850
- package()
- {
- "PMICVREGVOTE",
- package() //Vote for L12 @1.8v
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @3.075v
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 is used for QMP PHY
- // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- },
- package()
- { // HOST D3
- "DSTATE",
- 0x3, // Abandon state
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 3, 9600000, 1}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 2}},
-
- // Disable aggre_usb3_prim_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_prim_mock_utmi_clk", 2}},
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package(){"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 2 }},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_0", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_prim_clkref_en", 2}},
-
- // Disable usb30_prim_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_prim_gdsc", // USB 3.0 Core Power domain
- 2, // 2==Disable
- },
- },
-
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_0",// Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}},
-
- //Power Grid for SDM850
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 0, // Voltage = 0 V
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE",
- package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage : 0 microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage 0 V : microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- package() // Vote for L1 @ 0 v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage (microvolts)
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- // Define Abandon State for USB0 (host) stack ie. Power State invoked when stack unloads/tears down
- package()
- {
- "ABANDON_DSTATE",
- 3 // Abandon D state defined as D3
- },
- }, //End USB0
-
- //USB secondary core (Host Stack)
- Package()
- {
- "DEVICE",
- "\\_SB.USB1",
- Package()
- {
- "COMPONENT",
- 0x0, // Component 0.
- Package() { "FSTATE", 0x0, },
- package()
- {
- "PSTATE",
- 0x0,
- // Enable USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}},
- // Mark Suppressible for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}},
- // Mark Always On for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}},
- //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL
- // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}},
- // Enable PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}},
- // Mark Suppressible for USB PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}},
- },
- package()
- {
- "PRELOAD_PSTATE",
- 0,
- },// index 0 is P-state 0 here
- },
- //D states
- Package()
- { // HOST D0
- "DSTATE",
- 0x0,
- //Power Grid for SDM850
- package()
- {
- // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L12 @1.8v
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage 1.8V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L24 @3.075v
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 - VDDA_USB_SS_1P2 (QMP PHY)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L26 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
-
- // Enable usb30_sec_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_sec_gdsc", // USB 3.0 Core Power domain
- 1, //1==Enable
- },
- },
-
- // Now Enable all the clocks
-
- //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}},
-
- // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
- // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}},
-
- // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}},
-
- //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz
- package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}},
-
- // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
- package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}},
-
- //Vote for max freq: BUS Arbiter Request (Type-3)
- // Instantaneous BW BytesPerSec = 671088640;
- // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
- package()
- {
- "BUSARB",
- Package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_1", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 671088640, // IB=5Gbps //LowSVS
- 671088640 // AB=5Gbps
- }
- },
-
- //Nominal==block vdd_min:
- package()
- {
- "NPARESOURCE",
- Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact)
- //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact)
- },
-
- // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- //BUS Arbiter Request (Type-3)
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_1", // Slave
- 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact)
- //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact)
- 0 // AB=0 MBps
- }
- },
- // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
-
- // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
- package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}},
-
- },
- package()
- { // HOST D1
- "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend)
- 0x1,
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
-
- //Disable aggre_usb3_sec_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package()
- {
- "CLOCK",
- package() { "gcc_usb3_sec_phy_aux_clk", 2}
- },
-
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
-
- //BUS Arbiter Request (Type-3)
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_1",// Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package()
- {
- "NPARESOURCE",
- package() { 1, "/arc/client/rail_cx", 0}
- },
-
- package()
- {
- "PMICVREGVOTE",
- package() //Vote for L12 @1.8v
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @3.075v
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- package()
- {
- // L26 is used for QMP PHY
- // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L26 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- package()
- { // HOST D2
- "DSTATE",
- 0x2, // Slave device disconnect (host cable is still connected)
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
-
- // Disable aggre_usb3_sec_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
- // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization
- // No option of enabling it through ACPI
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
-
- // Enable usb30_sec_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_sec_gdsc", // USB 3.0 Core Power domain
- 1, //1==Enable
- },
- },
-
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- Package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_1", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package()
- {
- "NPARESOURCE",
- package() { 1, "/arc/client/rail_cx", 0}
- },
-
- //Power Grid for SDM850
- package()
- {
- "PMICVREGVOTE",
- package() //Vote for L12 @1.8v
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @3.075v
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 is used for QMP PHY
- // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- },
- package()
- { // HOST D3
- "DSTATE",
- 0x3, // Abandon state
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
-
- // Disable aggre_usb3_sec_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
-
- // Disable usb30_sec_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_sec_gdsc", // USB 3.0 Core Power domain
- 2, // 2==Disable
- },
- },
-
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_1",// Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}},
-
- //Power Grid for SDM850
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 0, // Voltage = 0 V
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE",
- package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage : 0 microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage 0 V : microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- package() // Vote for L1 @ 0 v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage (microvolts)
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- // Define Abandon State for USB1 (host) stack ie. Power State invoked when stack unloads/tears down
- package()
- {
- "ABANDON_DSTATE",
- 3 // Abandon D state defined as D3
- },
- }, //End USB1
-
- Package()
- {
- "DEVICE",
- "\\_SB.URS1",
- Package()
- {
- "COMPONENT",
- Zero,
- Package() {"FSTATE", 0},
- Package()
- {
- "PSTATE",
- 0, // P0 -Disable Vbus
- package()
- {
- "PMICGPIO",
- Package()
- {
- "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT",
- 1, // PMI8998
- 9, // GPIO #10: USBOTG_VBUS_EN
- 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS
- 0, // PM_GPIO_VIN0
- 0, // EN_AND_SOURCE_SEL, 1: LOW
- 1, // PM_GPIO_OUT_BUFFER_LOW
- 4, // PM_GPIO_I_SOURCE_PULL_DOWN_10uA
- },
- },
- },
- Package()
- {
- "PSTATE",
- 1, // P1 - Enable Vbus
- package()
- {
- "PMICGPIO",
- Package()
- {
- "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT",
- 1, // PMI8998
- 9, // GPIO #10: USBOTG_VBUS_EN
- 0, // PM_GPIO_OUT_BUFFER_CONFIG_CMOS
- 0, // PM_GPIO_VIN0
- 1, // EN_AND_SOURCE_SEL, 1: HIGH
- 3, // PM_GPIO_OUT_BUFFER_HIGH
- 5, // PM_GPIO_I_SOURCE_PULL_NO_PULL
- },
- },
- }
- },
- Package() {"DSTATE", 0 },
- Package() {"DSTATE", 1 },
- Package() {"DSTATE", 2 },
- Package() {"DSTATE", 3 }
- },
-
-
- //USB secondary core (Host Stack)
- Package()
- {
- "DEVICE",
- "\\_SB.URS1.USB1",
- Package()
- {
- "COMPONENT",
- 0x0, // Component 0.
- Package() { "FSTATE", 0x0, },
- package()
- {
- "PSTATE",
- 0x0,
- // Enable USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}},
- // Mark Suppressible for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}},
- // Mark Always On for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}},
- //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL
- // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}},
- // Enable PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}},
- // Mark Suppressible for USB PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}},
- },
- package()
- {
- "PRELOAD_PSTATE",
- 0,
- },// index 0 is P-state 0 here
- },
- //D states
- Package()
- { // HOST D0
- "DSTATE",
- 0x0,
- //Power Grid for SDM850
- package()
- {
- // L12 - VDDA_QUSB_HS0_1P8 (QUSB2 PHY)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L12 @1.8v
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage 1.8V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L24 @3.075v
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 - VDDA_USB_SS_1P2 (QMP PHY)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L26 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
-
- // Enable usb30_sec_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_sec_gdsc", // USB 3.0 Core Power domain
- 1, //1==Enable
- },
- },
-
- // Now Enable all the clocks
-
- //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}},
-
- // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
- // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}},
-
- // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}},
-
- //enable UTMI clk @19.2 MHz 8 = Set & Enable; 19.2, 7 -> Closest 19.2 Mhz
- package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 8, 19200, 7}},
-
- // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
- package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}},
-
- //Vote for max freq: BUS Arbiter Request (Type-3)
- // Instantaneous BW BytesPerSec = 671088640;
- // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
- package()
- {
- "BUSARB",
- Package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_1", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 671088640, // IB=5Gbps //LowSVS
- 671088640 // AB=5Gbps
- }
- },
-
- //Nominal==block vdd_min:
- package()
- {
- "NPARESOURCE",
- Package() {1, "/arc/client/rail_cx", 256} //Comment out->SVS for Power Optimization (Performance Impact)
- //Package() {1, "/arc/client/rail_cx", 128} //Uncomment->SVS for Power Optimization (Performance Impact)
- },
-
- // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- //BUS Arbiter Request (Type-3)
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_1", // Slave
- 400000000, // IB=400 MBps //Comment out->SVS for Power Optimization (Performance Impact)
- //149000000, // IB=149 MBps //Uncomment->SVS for Power Optimization (Performance Impact)
- 0 // AB=0 MBps
- }
- },
- // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
-
- // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
- package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}},
-
- },
- package()
- { // HOST D1
- "DSTATE", // D1 state (Suspend State - HS Suspend + SS disconnect /SS Suspend + HS disconnect/ HS + SS suspend)
- 0x1,
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
-
- //Disable aggre_usb3_sec_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package()
- {
- "CLOCK",
- package() { "gcc_usb3_sec_phy_aux_clk", 2}
- },
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
-
- //BUS Arbiter Request (Type-3)
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_1",// Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package()
- {
- "NPARESOURCE",
- package() { 1, "/arc/client/rail_cx", 0}
- },
-
- package()
- {
- "PMICVREGVOTE",
- package() //Vote for L12 @1.8v
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @3.075v
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- package()
- {
- // L26 is used for QMP PHY
- // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L26 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- package()
- { // HOST D2
- "DSTATE",
- 0x2, // Slave device disconnect (host cable is still connected)
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
-
- // Disable aggre_usb3_sec_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
- // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initialization
- // No option of enabling it through ACPI
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
-
-
- // Enable usb30_sec_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_sec_gdsc", // USB 3.0 Core Power domain
- 1, //1==Enable
- },
- },
-
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- Package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_1", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package()
- {
- "NPARESOURCE",
- package() { 1, "/arc/client/rail_cx", 0}
- },
-
- //Power Grid for SDM850
- package()
- {
- "PMICVREGVOTE",
- package() //Vote for L12 @1.8v
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @3.075v
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 is used for QMP PHY
- // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
-
- },
- package()
- { // HOST D3
- "DSTATE",
- 0x3, // Abandon state
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
-
- // Disable aggre_usb3_sec_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
-
- // Disable UTMI clk 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_mock_utmi_clk", 2}},
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
- // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization
- // No option of enabling it through ACPI
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
-
-
- // Disable usb30_sec_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_sec_gdsc", // USB 3.0 Core Power domain
- 2, // 2==Disable
- },
- },
-
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_1",// Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 Mbps
- 0 // AB=0Mbps
- }
- },
-
- //enable vdd_min
- package() {"NPARESOURCE", package() {1, "/arc/client/rail_cx", 0}},
-
- //Power Grid for SDM850
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 0, // Voltage = 0 V
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE",
- package() // Vote for L12 @ 0V - VDDA_QUSB_HS0_1P8
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage : 0 microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @ 0v - VDDA_USB_SS_1P2
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage 0 V : microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- package() // Vote for L1 @ 0 v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage (microvolts)
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- // Define Abandon State for USB1 (host) stack ie. Power State invoked when stack unloads/tears down
- package()
- {
- "ABANDON_DSTATE",
- 3 // Abandon D state defined as D3
- },
- }, //End USB1
-
- //************************* USB3.0 SS/HS0 core (Peripheral Secondary Stack) ****************************
- //
- package()
- {
- "DEVICE",
- "\\_SB.URS1.UFN1",
- package()
- {
- "COMPONENT",
- 0x0,
- // F-State placeholders
- package()
- {
- "FSTATE",
- 0x0,
- },
- package()
- {
- "PSTATE",
- 0x0,
- // Enable USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}},
- // Mark Suppressible for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}},
- // Mark Always On for USB 3.0 Sleep Clock
- package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}},
-
- //Select external source action for gcc_usb3_sec_phy_pipe_clk, Sourced by QMP Phy PLL
- // package() {"CLOCK", package() {"gcc_usb3_sec_phy_pipe_clk", 6, 0, 0, 0x0}},
- // Enable PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}},
- // Mark Suppressible for USB PHY pipe Clock
- package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}},
- },
- package()
- {
- "PRELOAD_PSTATE",
- 0,
- },// index 0 is P-state 0 here
- },
-
- package()
- { // PERIPH D0
- "DSTATE",
- 0x0,
- //Power Grid for SDM850
- package()
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L12 @1.8v
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage 1.8V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L24 @ 3.075v
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 - VDDA_USB_SS_1P2 (QMP PHY)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1200000, // Voltage 1.2V : microvolts ( V )
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 880000, // Voltage (microvolts)
- 1, // SW Enable = Enable
- 7, // SW Power Mode = NPM
- 0, // Head Room
- },
- },
-
- // Enable usb30_sec_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_sec_gdsc", // USB 3.0 Core Power domain
- 1, //1==Enable
- },
- },
-
- //aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}},
-
- // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
- // @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}},
-
- // USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}},
-
- // Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
- package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}},
-
- // Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- //BUS Arbiter Request (Type-3)
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_1", // Slave
- 400000000, // IB=400 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
-
- //Vote for max freq: BUS Arbiter Request (Type-3)
- // Instantaneous BW BytesPerSec = 671088640;
- // Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
- package()
- {
- "BUSARB",
- Package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_1", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 671088640, // IB=5Gbps
- 671088640 // AB=5Gbps
- }
- },
-
- //Nominal==block vdd_min:
- package()
- {
- "NPARESOURCE",
- Package() {1, "/arc/client/rail_cx", 256}
- },
-
- // Enable SS Phy Reference Clock (diff clock) 1 = Enable (Source controlled by RPMH clock/ LNBBCLK)
- package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 1}},
-
- },
- package()
- {
- // PERIPH D1: Not supported by USBFN driver
- "DSTATE", //USB SS+HS suspend state
- 0x1,
- },
- package()
- { // PERIPH D2
- "DSTATE", //USB DCP/HVDCP charger state
- 0x2,
-
- // Set frequency @9.6Mhz before disabling to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- // Set USB 3.0 Master Clock @ 9.6 MHz 3 = Set ; 9600,9 -> Atleast 9.6 Mhz
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600, 5}},
-
- // Disable USB 3.0 Master Clock 2 = Disable ;
- package() {"CLOCK", package() { "gcc_usb30_sec_master_clk", 2 } },
-
- // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
-
- //Disable aggre_usb3_sec_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
-
- //Disable gcc_usb3_sec_phy_aux_clk
- package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2}},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
-
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
-
-
- //BUS Arbiter Request (Type-3)
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_1", // Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- //Nominal==block vdd_min:
- package()
- {
- "NPARESOURCE",
- package() {1, "/arc/client/rail_cx", 256}
- },
-
- package()
- {
- "PMICVREGVOTE",
- package() //Vote for L12 @1.8v
- {
- // L12 - VDDA_QUSB_HS0_1P8
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 1800000, // Voltage : microvolts ( V )
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @3.075v
- {
- // L24 - VDDA_QUSB_HS0_3P1
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 3075000, // Voltage = 3.075 V
- 1, // SW Enable = Enable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // L26 is used for QMP PHY
- // VDDA_USB_SS_1P2 (V_L2A_USB_SS_1P2)
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @1.2v
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage 0V : microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- // VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L1 @ 0v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage (microvolts)
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- package()
- {
- // PERIPH D3
- "DSTATE",
- 0x3, // Detach State
-
- //set frequency @9.6Mhz to avoid issues w/ sync gcc_snoc_bus_timeout2_ahb_clk in SVS
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 3, 9600000, 1}},
-
- // Disable USB 3.0 Master Clock 2 = Disable
- package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 2}},
-
- // gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
- package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 2}},
-
- //Disable aggre_usb3_sec_axi
- package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 2}},
-
- // Disable Phy Aux Clock @ 1.2 Mhz 2 = Disable;
- package(){"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 2 }},
-
- // Remove Vote for CNOC 100 MHz
- // Required for gcc_usb_phy_cfg_ahb2phy_clk
- // BUS Arbiter Request (Type-3)
- // Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_APPSS_PROC", // Master
- "ICBID_SLAVE_USB3_1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 MBps
- }
- },
-
- // Disable gcc_usb_phy_cfg_ahb2phy_clk
- package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 2}},
- // GCC_USB_SS_PHY_LDO_EN is being enabled once in Clock Driver during initilization
- // No option of enabling it through ACPI
-
- // Disable SS Phy Reference Clock (diff clock) 2 = Disable
- package() {"CLOCK", package() {"gcc_usb3_sec_clkref_en", 2}},
-
- // Disable usb30_sec_gdsc power domain
- package()
- {
- "FOOTSWITCH", // Footswitch
- package()
- {
- "usb30_sec_gdsc", // USB 3.0 Core Power domain
- 2, // 2==Disable
- },
- },
-
- //Vote for 0 freq
- package()
- {
- "BUSARB",
- package()
- {
- 3, // Req Type
- "ICBID_MASTER_USB3_1",// Master
- "ICBID_SLAVE_EBI1", // Slave
- 0, // IB=0 MBps
- 0 // AB=0 Mbps
- }
- },
-
- //enable vdd_min
- package()
- {
- "NPARESOURCE",
- package() { 1, "/arc/client/rail_cx", 0}
- },
-
- package()
- {
- "PMICVREGVOTE", // PMICVREGVOTE resource
- package() // Vote for L24 @ 0V - VDDA_QUSB_HS0_3P1
- {
- "PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
- 1, // Voltage Regulator type 1 = LDO
- 0, // Voltage = 0 V
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE",
- package() // Vote for L12 @0V - VDDA_QUSB_HS0_1P8
- {
- "PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage : 0 microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource
- package() // Vote for L2 @0v - VDDA_USB_SS_1P2
- {
- "PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage : 0 microvolts ( V )
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- package()
- {
- "PMICVREGVOTE", // PMIC VREG resource - VDDA_USB_SS_CORE & VDDA_QUSB0_HS
- package() // Vote for L1 @ 0.88v
- {
- "PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
- 1, // Voltage Regulator type = LDO
- 0, // Voltage (microvolts)
- 0, // SW Enable = Disable
- 5, // SW Power Mode = LPM
- 0, // Head Room
- },
- },
- },
- // Define Abandon State for UFN1 (peripheral) stack ie. Power State invoked when stack unloads/tears down
- package()
- {
- "ABANDON_DSTATE",
- 3 // Abandon D state defined as D3
- },
- }, //End UFN1
- })
-}
+++ /dev/null
-// This file contains the Power Management IC (PMIC)
-// customer-modifiable ACPI configurations.
-//
-
-//******************************************
-//Configs for Battery Manager Device: PMBT
-//******************************************
-//--------------------
-//PMBT: Method(BBAT)
-//--------------------
-Name(BFCC, 13110) //* (mWh), Full Charge Capacity
-Name(PCT1, 5) //* (% of FCC), Default Alert 1
-Name(PCT2, 9) //* (% of FCC), Default Alert 2
-
-//--------------------
-//PMBT: Method(BMNR)
-//--------------------
-Name(CUST, "850_MTP") //* cust file identifier
-
-//--------------------
-//PMBT: Method(BPLT)
-//--------------------
-Name(VNOM, 3800) //* (mV), Nominal Battery Voltage
-Name(VLOW, 3300) //* (mV), Low Battery Voltage
-Name(EMPT, 3200) //* (mV), VCutOff
-Name(DCMA, 900) //* (mA), DC Current
-Name(BOCP, 4500) //* (mA), OCP current used in BCL
-Name(BVLO, 3000) //* (mV), BCL low Vbatt
-Name(BLOP, 20) //* (%), BCL Low batt percent notification
-Name(BNOP, 22) //* (%), BCL normal batt percent notification
-Name(IFGD, 50) //* (mA), FG Iterm delta; (iterm + this value) determines when FG report 100%
-Name(VFGD, 50) //* (mV), CC to CV Vdelta; (Vfloat - this value) determine when FG report 100%
-
-//--------------------------------
-//PMBT: Method(BJTA)/Method(BAT1)
-//--------------------------------
-Name(VDD1, 4350) //* (mV), Battery-1: Float Voltage (Standard Zone)
-Name(FCC1, 2100) //* (mA), Battery-1: Full Charge Current (Standard Zone)
-Name(HCLI, 0) //* (degree C), hard-cold temperature limit
-Name(SCLI, 10) //* (degree C), soft-cold temperature limit
-Name(SHLI, 45) //* (degree C), soft-hot temperature limit
-Name(HHLI, 55) //* (degree C), hard-hot temperature limit
-Name(FVC1, 105) //* (mV), Float voltage compensation, when battery in JEITA soft-limit
-Name(CCC1, 1000) //* (mA), Charge current compensation, when battery in JEITA soft-limit
-
-//--------------------
-//PMBT: Method(CTMC)
-//--------------------
-Name(RID2, 15000) //* (Ohm), min RID for NORMAL category: 15K
-Name(RID3, 140000) //* (Ohm), max RID for NORMAL category: 140K
+++ /dev/null
-//
- //CPU Aggregator Device -- Required for Thermal Parking
- Device(AGR0)
- {
- Name(_HID, "ACPI000C")
- Name(_PUR, Package() {1, 0})
- Method(_OST, 0x3, NotSerialized)
- {
- Store(Arg2, \_SB_.PEP0.ROST)
- }
- }
-
- //---------------------------------------------------------------------
- //
- // Thermal Zones for QC reference hardware
- //
- //TZ0 - TZ39 are thermal zones developed by QC for reference hardware
- //and can be modified by the OEMs.
- //---------------------------------------------------------------------
-
- //---------------------------------------------------------------------
- // Thermal Zones(0-19) for CPU sensors
- //24AD - Little CPU virtual sensor
- //24AE - Big CPU virtual sensor
- // This thermal zone is only used for temperature logging for little CPUs
- // as you may notice that _PSV, _TC1, _TC2, _TSP params are removed.
- // This is the passive cooling mechanism by dialing down frequency is now
- // done actively by hardware.
- //---------------------------------------------------------------------
- ThermalZone (TZ0) {
- Name (_HID, "QCOM02B0")
- Name (_UID, 0)
- Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3})
- Method(_DEP) {
- Return (Package() {\_SB.PEP0})
- }
- } // end of TZ0
-
- //Regular Thermal Zone for Little CPU TSENS to Park cores at 110C
- ThermalZone (TZ1) {
- Name (_HID, "QCOM02B0")
- Name (_UID, 1)
- Name(_TZD, Package (){\_SB.PEP0})
- Name(TPSV, 3830)
- Method(_PSV) { Return (\_SB.TZ1.TPSV) }
- Name(_MTL, 20) // minimum throttle limit
- //Control how aggressively the thermal manager applies thermal
- //throttling performance against temperature change.
- Name(TTC1, 0)
- Method(_TC1) { Return (\_SB.TZ1.TTC1) }
-
- // _TC2 Controls how aggressively the thermal manager applies thermal
- // throttling performance against temperature delta between the
- // current temperature and _PSV.
- // once the temp goes above _PSV, we like to have aggressive
- // throttling based on how far above the temp is above the threshold.
- // Since that is controlled via _TC2, we like it to be high.
- // please refer to the ACPI spec 6.0 to understand the significance of
- // _TC2 or take a look at the explanation at the top of this file.
- Name(TTC2, 1)
- Method(_TC2) { Return (\_SB.TZ1.TTC2) }
-
- // Appropriate temperature sampling interval for the zone in tenths
- // of a second. The thermal manager uses this interval to determine
- // how often it should evaluate the thermal throttling performance.
- // Must be greater than zero. For more information, see Thermal
- // throttling algorithm on msdn page
- // https://msdn.microsoft.com/en-us/library/windows/hardware/mt643928(v=vs.85).aspx
- Name(TTSP, 50)
- Method(_TSP) { Return (\_SB.TZ1.TTSP) }
-
- // This optional object evaluates to a recommended polling frequency
- // (in tenths of seconds) for this thermal zone. A value of zero indicates
- // that OSPM does not need to poll the temperature of this thermal zone in
- // order to detect temperature changes (the hardware is capable of
- // generating asynchronous notifications).
- // TZP should be marked 0 for all thermal zones as our TSENS sensors
- // generate interrupts to complete thermal IOCTL read call.
- Name(_TZP, 0)
-
- Method(_DEP) {
- Return (Package() {\_SB.PEP0})
- }
- } // end of TZ1
-
- // This thermal zone is only used for temperature logging for Big CPUs
- // as you may notice that _PSV, _TC1, _TC2, _TSP params are removed.
- // This is the passive cooling mechanism by dialing down frequency is now
- // done actively by hardware.
- ThermalZone (TZ2) {
- Name (_HID, "QCOM02B1")
- Name (_UID, 0)
- Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5, \_SB.SYSM.CLUS.CPU6, \_SB.SYSM.CLUS.CPU7})
- Method(_DEP) {
- Return (Package() {\_SB.PEP0})
- }
- } // end of TZ2
-
- //Regular Thermal Zone for BigCPU TSENS to Park cores at 110C
- ThermalZone (TZ3) {
- Name (_HID, "QCOM02B1")
- Name (_UID, 1)
- Name(_TZD, Package (){\_SB.PEP0})
-
- Name(TPSV, 3830)
- Method(_PSV) { Return (\_SB.TZ3.TPSV) }
- Name(TTC1, 0)
- Method(_TC1) { Return (\_SB.TZ3.TTC1) }
- Name(TTC2, 1)
- Method(_TC2) { Return (\_SB.TZ3.TTC2) }
- Name(TTSP, 1)
- Method(_TSP) { Return (\_SB.TZ3.TTSP) }
- Name(_MTL, 20) // minimum throttle limit
- Name(_TZP, 0)
-
- Method(_DEP) {
- Return (Package() {\_SB.PEP0})
- }
- } // end of TZ3
-
- //---------------------------------------------------------------------
- // Thermal Zones(20-21) for GPU TSENS
- //
- // \_SB.GPU0 should be used for GPU thermal mitigation, and
- // \_SB.GPU0.AVS0 should be used for MDSS/Video thermal mitigation.
- // Currently there is no handling for Video thermal mitigation.
- // When needed, Video will be added to GPU0.AVS0 interface.
- //---------------------------------------------------------------------
- //Thermal zone for TSENS11 dial back GPUs at 95C
- ThermalZone (TZ20) {
- Name (_HID, "QCOM02AB")
- Name (_UID, 0)
- Name(_TZD, Package (){\_SB.GPU0})
- Name(TPSV, 3680)
- Method(_PSV) { Return (\_SB.TZ20.TPSV) }
- Name(TTC1, 1)
- Method(_TC1) { Return (\_SB.TZ20.TTC1) }
- // For non-cpu devices, tc2 should be atleast 5, please refer to the
- // explanation at the top of the file or msdn link for thermal guide.
- Name(TTC2, 2)
- Method(_TC2) { Return (\_SB.TZ20.TTC2) }
- // For non-cpu devices, _tsp should be 20 or 30
- Name(TTSP, 2)
- Method(_TSP) { Return (\_SB.TZ20.TTSP) }
- Name(_TZP, 0)
- Method(_DEP) {
- Return (Package() {\_SB.PEP0})
- }
- } // end of TZ20
-
- //Thermal zone for TSENS12 to dial back GPUs at 95C
- ThermalZone (TZ21) {
- Name (_HID, "QCOM02AC")
- Name (_UID, 0)
- Name(_TZD, Package (){\_SB.GPU0})
- Name(TPSV, 3680)
- Method(_PSV) { Return (\_SB.TZ21.TPSV) }
- Name(TTC1, 1)
- Method(_TC1) { Return (\_SB.TZ21.TTC1) }
- Name(TTC2, 2)
- Method(_TC2) { Return (\_SB.TZ21.TTC2) }
- Name(TTSP, 2)
- Method(_TSP) { Return (\_SB.TZ21.TTSP) }
- Name(_TZP, 0)
- Method(_DEP) {
- Return (Package() {\_SB.PEP0})
- }
- } // end of TZ21
-
- //---------------------------------------------------------------------
- // Thermal Zones for QDSP TSENS
- //4/16/15: TODO waiting to get a new HID assigned for TSENS17
- //---------------------------------------------------------------------
- //Thermall zone for TSENS14 dial back MSM at 95C
- //ThermalZone (TZ31) {
- //Name (_HID, "QCOM02AE")
- //Name (_UID, 0)
- //Name(_TZD, Package (){
- //\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
- //\_SB.PEP0, \_SB.GPU0.MON0, \_SB.GPU0})
- //Method(_PSV) { Return (3680) }
- //Name(_TC1, 1)
- //Name(_TC2, 2)
- //Name(_TSP, 10)
- //Name(_TZP, 0)
- //Method(_DEP) {
- // Return (Package() {\_SB.PEP0})
- //}
- //} // end of TZ31
-
- //---------------------------------------------------------------------
- // Thermal Zones for Camera TSENS
- //---------------------------------------------------------------------
- //Thermal zone for TSENS17 to dial back MSM at 95C
- ThermalZone (TZ32) {
- Name (_HID, "QCOM02C9")
- Name (_UID, 0)
- Name(_TZD, Package (){\_SB.GPU0.AVS0})
- Name(TPSV, 3680)
- Method(_PSV) { Return (\_SB.TZ32.TPSV) }
- Name(TTC1, 1)
- Method(_TC1) { Return (\_SB.TZ32.TTC1) }
- // For non-cpu devices, tc2 should be atleast 5, please refer to the
- // explanation at the top of the file or msdn link for thermal guide.
- Name(TTC2, 2)
- Method(_TC2) { Return (\_SB.TZ32.TTC2) }
- // For non-cpu devices, _tsp should be 20 or 30
- Name(TTSP, 10)
- Method(_TSP) { Return (\_SB.TZ32.TTSP) }
- Name(_TZP, 0)
- Method(_DEP) {
- Return (Package() {\_SB.PEP0})
- }
- } // end of TZ32
-
- ThermalZone (TZ33) {
- Name (_HID, "QCOM02CB")
- Name (_UID, 1)
- Name(_TZD, Package (){\_SB.AMSS})
-
- Name(TPSV, 3680)
- Method(_PSV) { Return (\_SB.TZ33.TPSV) }
-
- Name(TTC1, 1)
- Method(_TC1) { Return (\_SB.TZ33.TTC1) }
-
- Name(TTC2, 2)
- Method(_TC2) { Return (\_SB.TZ33.TTC2) }
-
- Name(TTSP, 10)
- Method(_TSP) { Return (\_SB.TZ33.TTSP) }
-
- Name(_TZP, 0)
- Method(_DEP) {
- Return (Package() {\_SB.PEP0})
- }
- }
-
- //---------------------------------------------------------------------
- // Thermal Zones for MDSS TENS (Display Subsystem)
- // Only the MDP Blt engine and Rotator engines on the MDSS are cooled
- // using this interface. Display cooling is not supported currently.
- //---------------------------------------------------------------------
- //Thermal zone for TSENS18 to dial back MSM at 95C
- //ThermalZone (TZ34) {
- //Name (_HID, "QCOM02CA")
- //Name (_UID, 0)
- //Name(_TZD, Package (){\_SB.GPU0.AVS0})
- //Method(_PSV) { Return (3680) }
- //Name(_TC1, 1)
- //Name(_TC2, 2)
- //Name(_TSP, 10)
- //Name(_TZP, 0)
- //Method(_DEP) {
- // Return (Package() {\_SB.PEP0})
- //}
- //} // end of TZ34
-
- //---------------------------------------------------------------------
- // Thermal Zones for ADC Channels
- //---------------------------------------------------------------------
- //Thermal zone for PMIC_THERM
- ThermalZone (TZ36) {
- Name (_HID, "QCOM029E")
- Name (_UID, 0)
- Name(_TZD, Package (){
- \_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
- \_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5, \_SB.SYSM.CLUS.CPU6, \_SB.SYSM.CLUS.CPU7,
- \_SB.PMBM})
-
- Name(TPSV, 3780)
- Method(_PSV) { Return (\_SB.TZ36.TPSV) }
-
- Name(TTC1, 4)
- Method(_TC1) { Return (\_SB.TZ36.TTC1) }
-
- Name(TTC2, 3)
- Method(_TC2) { Return (\_SB.TZ36.TTC2) }
-
- Name(TTSP, 50)
- Method(_TSP) { Return (\_SB.TZ36.TTSP) }
-
- Name(_TZP, 0)
- Method(_DEP) {
- Return (Package() {\_SB.PEP0, \_SB.ADC1})
- }
- } // end of TZ36
-
- //Thermal zone for PMIC_THERM
- ThermalZone (TZ37) {
- Name (_HID, "QCOM029E")
- Name (_UID, 1)
- Name(_TZD, Package (){
- \_SB.PEP0, \_SB.PMBM})
- Name(TPSV, 3980)
- Method(_PSV) { Return (\_SB.TZ37.TPSV) }
- Name(TCRT, 4180)
- Method(_CRT) { Return (\_SB.TZ37.TCRT) }
- Name(TTC1, 4)
- Method(_TC1) { Return (\_SB.TZ37.TTC1) }
- Name(TTC2, 3)
- Method(_TC2) { Return (\_SB.TZ37.TTC2) }
- Name(TTSP, 50)
- Method(_TSP) { Return (\_SB.TZ37.TTSP) }
-
- Name(_TZP, 0)
- Method(_DEP) {
- Return (Package() {\_SB.PEP0, \_SB.ADC1})
- }
- } // end of TZ37
-
- //Example: Inverse Thermal zone for PMIC_THERM
- ThermalZone (TZ38) {
- Name (_HID, "QCOM029E")
- Name (_UID, 2) //Update UID on addition of new thermal zone with same HID
- Name(_TZD, Package (){
- \_SB.PEP0})
- Method(INVT) { Return (1) }
- Method(_MTL) { Return (60) }
- Name(TPSV, 2830)
- Method(_PSV) { Return (\_SB.TZ38.TPSV) }
- Name(TTC1, 4)
- Method(_TC1) { Return (\_SB.TZ38.TTC1) }
- Name(TTC2, 3)
- Method(_TC2) { Return (\_SB.TZ38.TTC2) }
- Name(TTSP, 10)
- Method(_TSP) { Return (\_SB.TZ38.TTSP) }
- Name(_TZP, 0)
- Method(_DEP) {
- Return (Package() {\_SB.PEP0, \_SB.ADC1})
- }
- } // end of TZ38
-
- //------------------------------------------------------------------------
- // Thermal Zones for Wlan
- //------------------------------------------------------------------------
- //Thermal zone for iHelium, Wlan MAC&PHY on SOC
- ThermalZone (TZ40) {
- Name (_HID, "QCOM02AF")
- Name (_UID, 0)
- Name(_TZD, Package (){\_SB.COEX})
-
- Name(TPSV, 3580)
- Method(_PSV) { Return (\_SB.TZ40.TPSV) }
- Name(TTC1, 1)
- Method(_TC1) { Return (\_SB.TZ40.TTC1) }
- Name(TTC2, 5) // For non-cpu devices, tc2 should be atleast 5
- Method(_TC2) { Return (\_SB.TZ40.TTC2) }
- Name(TTSP, 30) // For non-cpu devices, _tsp should be 20 or 30
- Method(_TSP) { Return (\_SB.TZ40.TTSP) }
-
- Name(_TZP, 0)
- Method(_DEP) {
- Return (Package() {\_SB.PEP0})
- }
- } // end of TZ40
- //Thermal zone for Cherokee, Wlan radio on WCN3990
- ThermalZone (TZ41) {
- Name (_HID, "QCOM0295")//virtual sensor by wlan WMI thermal interface
- Name (_UID, 1)
- //Name(_TZD, Package (){\_SB.COEX}) // Temperature report only
- //Method(_PSV) { Return (4030) }
- //Name(_TC1, 4)
- //Name(_TC2, 3)
- Name(_TSP, 50)
- Name(_TZP, 0)
- } // end of TZ41
-
- //------------------------------------------------------------------------
- // Thermal Zones for DDR/POP
- //------------------------------------------------------------------------
- //Thermal zone for DDR
- //Thermal zone for TSENS20 to dial back Big CPU's at 95C
-
- ThermalZone (TZ44) {
- Name (_HID, "QCOM02CC")
- Name (_UID, 0)
- Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5, \_SB.SYSM.CLUS.CPU6, \_SB.SYSM.CLUS.CPU7})
- Name(TPSV, 3680)
- Method(_PSV) { Return (\_SB.TZ44.TPSV) }
- Name(TTC1, 0)
- Method(_TC1) { Return (\_SB.TZ44.TTC1) }
- Name(TTC2, 1)
- Method(_TC2) { Return (\_SB.TZ44.TTC2) }
- Name(TTSP, 1)
- Method(_TSP) { Return (\_SB.TZ44.TTSP) }
- Name(_TZP, 0)
- Method(_DEP) {
- Return (Package() {\_SB.PEP0})
- }
- } // end of TZ44
-
- //---------------------------------------------------------------------
- //
- // QC Recommended thermal limits starts
- //
- //TZ80 - TZ98 represent the thermal zones corresponding to QC
- //recommended thermal limits. These thermal zones must not be removed
- //or tampered with.
- //---------------------------------------------------------------------
- //Thermal zone for TSENS2 at 70C to match the LA thermal limits
- //ThermalZone (TZ80) {
- //Name (_HID, "QCOM2472")
- //Name (_UID, 0)
- //Name(_TZD, Package (){
- // \_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
- //Method(_PSV) { Return (3430) }
- //Name(_TC1, 1)
- //Name(_TC2, 2)
- //Name(_TSP, 10)
- //Name(_TZP, 0)
- //Method(_DEP) {
- // Return (Package() {\_SB.PEP0})
- //}
- //} // end of TZ80
-
- //Thermal zone near for TSENS2 to shutdown the system at 85C to match LA
- //thermal limits
- //ThermalZone (TZ81) {
- //Name (_HID, "QCOM2472")
- //Name (_UID, 1)
- //Name(_TZD, Package (){
- // \_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
- // \_SB.PEP0})
- //Method(_PSV) { Return (3530) }
- //Method(_CRT) { Return (3580) }
- //Name(_TC1, 1)
- //Name(_TC2, 2)
- //Name(_TSP, 10)
- //Name(_TZP, 0)
- //Method(_DEP) {
- // Return (Package() {\_SB.PEP0})
- //}
- //} // end of TZ81
-
- //Entry for BCL thermal zone
- ThermalZone (TZ98) {
- Name (_HID, "QCOM0294")
- Name (_UID, 0)
- Name(_TZD, Package (){
- \_SB.GPU0.MON0, \_SB.GPU0})
-
- Name(TPSV, 3630)
- Method(_PSV) { Return (\_SB.TZ98.TPSV) }
- Name(TTC1, 1)
- Method(_TC1) { Return (\_SB.TZ98.TTC1) }
- //Method(_CRT) { Return (5630) }
- Name(TTC2, 5)
- Method(_TC2) { Return (\_SB.TZ98.TTC2) }
- Name(TTSP, 20)
- Method(_TSP) { Return (\_SB.TZ98.TTSP) }
-
- Name(_TZP, 0)
- Method(_DEP) {
- Return (Package(0x2) {\_SB.PEP0,\_SB_.BCL1})
- }
- } // end of TZ98
-
- //---------------------------------------------------------------------
- // Critical Thermal Zones for ALL TSENS
- //This sensor aggregates all the on chip TSENS into a single sensor
- //for ACPI thermal manager. By having a critical thermal zone on this
- //"virtual sensor" we don't have to add a critical thermal zone on every
- //sensor and hence reduce the number of thermal zones.
- //---------------------------------------------------------------------
- //Critical Thermal zone on MSM virtual sensor to shutdown entire system
- //at 110C.
- ThermalZone (TZ99) {
- Name (_HID, "QCOM02B2")
- Name (_UID, 100)
-
- Name(TCRT, 3830)
- Method(_CRT) { Return (\_SB.TZ99.TCRT) }
- Name(TTC1, 4)
- Method(_TC1) { Return (\_SB.TZ99.TTC1) }
- Name(TTC2, 3)
- Method(_TC2) { Return (\_SB.TZ99.TTC2) }
- Name(TTSP, 10)
- Method(_TSP) { Return (\_SB.TZ99.TTSP) }
- Name(_TZP, 0)
-
- Method(_DEP) {
- Return (Package() {\_SB.PEP0})
- }
- } // end of TZ99
-
- //---------------------------------------------------------------------
- // QC Recommended thermal limits ends
- //---------------------------------------------------------------------
-
- //---------------------------------------------------------------------
- //
- // Sample Thermal Zones for OEMs TZ40 - TZ79
- //
- //Sample TSENS thermal zone that can be added on any TSENS
- //---------------------------------------------------------------------
- //ThermalZone (TZ40) {
- //Name (_HID, "QCOM2470")
- //Name (_UID, 0)
- //Name(_TZD, Package (){
- //\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5,
- //\_SB.PEP0, <Your cooling device>})
- //Method(_PSV) { Return (3730) }
- //Method(_CRT) { Return (3780) }
- //Name(_TC1, 1)
- //Name(_TC2, 2)
- //Name(_TSP, 10) //Sampling rate of 1sec
- //Name(_TZP, 0)
- //Method(_DEP) {
- // Return (Package() {\_SB.PEP0})
- //}
- //} // end of TZ40
-
- //ThermalZone (TZ41) {
- //Name (_HID, "QCOM2470")
- //Name (_UID, 0)
- //Name(_TZD, Package (){
- //\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5,
- //\_SB.PEP0, <Your cooling device>})
- //Method(_PSV) { Return (3730) }
- //Method(_CRT) { Return (3780) }
- //Name(_TC1, 1)
- //Name(_TC2, 2)
- //Name(_TSP, 50) //Sampling rate of 5sec
- //Name(_TZP, 0)
- //Method(_DEP) {
- // Return (Package() {\_SB.PEP0})
- //}
- //} // end of TZ41
-
-
- //--------------------------------------------------------------------------//
- //
- // Sample VADC Thermal zones for OEMs
- //
- //Following are sample thermal zones that use the off chip ADC thermistors
- //they are all currently using CPUs as a cooling device for a lack of better
- //option. The OEMs should change this.
- //--------------------------------------------------------------------------//
-
- //Thermal zone for SYS_THERM2
- // ThermalZone (TZ51) {
- // Name (_HID, "QCOM248D")
- // Name (_UID, 0)
- // Name(_TZD, Package (){
- //\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5,})
- // Method(_PSV) { Return (3830) }
- //Name(_TC1, 4)
- //Name(_TC2, 3)
- // Name(_TSP, 50)
- //Name(_TZP, 0)
- //Method(_DEP) {
- // Return (Package() {\_SB.PEP0})
- //}
- // } // end of TZ51
-
- //Thermal zone for PA_THERM1
- // ThermalZone (TZ52) {
- // Name (_HID, "QCOM248E")
- // Name (_UID, 0)
- // Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3})
- // Method(_PSV) { Return (3430) }
- // Name(_TC1, 4)
- // Name(_TC2, 3)
- // Name(_TSP, 50)
- // Name(_TZP, 0)
- //Method(_DEP) {
- // Return (Package() {\_SB.PEP0})
- //}
- // } // end of TZ52
+++ /dev/null
-//Improve Touch Driver, no it's not for polaris
-Device (TSC5)
-{
- Name (_HID, "QCOM02F5")
- Alias(\_SB.PSUB, _SUB)
- Name (_UID, 1)
- Name(_DEP, Package()
- {
- \_SB_.ARPC
- })
-
- //Disable Touch for V1s to support new SLPI
- Method(_STA, 0)
- {
-
- If(Lequal(\_SB_.SVMJ, 1))
- {
- return (0x0)
- }
- Else
- {
- return (0xFF)
- }
- }
-}
+++ /dev/null
-//===========================================================================
-// <cust_touch_resources.asl>
-// DESCRIPTION
-// This file contains the resources needed by touch driver.
-//
-//
-//===========================================================================
-Scope(\_SB_.PEP0)
-{
-
- Method(LPMX)
- {
- Return(LPXC)
- }
-
- Name(LPXC,
- Package(){
-
- })
-}
+++ /dev/null
-// To enable SOC revision based run time differentiation, uncomment following line
-// and uncomment SSID method in ABD device. The original string is artificailly set as
-// 16 characters, so there is enough room to hold SOC revision string.
-// To adjust the number, the MAX_SOCID_LEN macro as defined in ABD device.h should be
-// adjusted at the same time.
-
-Name (SOID, 348) // Holds the Chip Id
-Name (SIDS, "SDM850") // Holds the Chip ID translated to a string
-Name (SIDV, 0x00020001) // Holds the Chip Version as (major<<16)|(minor&0xffff)
-Name (SVMJ, 2) // Holds the major Chip Version
-Name (SVMI, 1) // Holds the minor Chip Version
-Name (SDFE, 79) // Holds the Chip Family enum
-Name (SFES, "899800000000000") // Holds the Chip Family translated to a string
-Name (SIDM, 0x0000000FFFFF00FF) // Holds the Modem Support bit field
-Name (SOSN, 0x000003F48D126594)
-Name (RMTB, 0x85D00000)
-Name (RMTX, 0x00200000)
-Name (RFMB, 0x00000000)
-Name (RFMS, 0x00000000)
-Name (RFAB, 0x00000000)
-Name (RFAS, 0x00000000)
-// Who is in charge of this?
-// Name (TPMA, 0x11111111) // Holds whether TPM is seperate app or combined with Winsecapp
-// Name (TDTV, 0x6654504D) // Holds TPM type, by default it set to fTPM type
-Name (TCMA, 0x8AB00000) // Holds TrEE Carveout Memory Address
-Name (TCML, 0x01400000) // Holds TrEE Carveout Memory Length
-// WTF?
-// Name (SOSI, 0xdeadbeefffffffff) // Holds the base address of the SoCInfo shared memory region used by ChipInfoLib
-
-//Include("cust_dsdt_common.asl")
-
-//Audio Drivers
-Include("audio.asl")
-
- //
- // Storage - UFS/SD
- //
- Include("../common/ufs.asl")
- // Include("../common/sdc.asl") // No SD slot
-
- //
- // ASL Bridge Device
- //
- Include("../common/abd.asl")
-
- Name (ESNL, 20) // Exsoc name limit 20 characters
- Name (DBFL, 23) // buffer Length, should be ESNL+3
-
-//
-// PMIC driver
-//
-Include("../common/pmic_core.asl")
-
-//
-// PMICTCC driver
-//
-Include("pmic_batt.asl")
-
- Include("../common/pep_common.asl")
- Include("cust_camera_resources.asl")
- // Include("corebsp_wp_resources.asl")
- // Include("nfc_resources.asl") // NFC
- Include("cust_touch_resources.asl")
-
- Include("../common/bam.asl")
- Include("buses.asl")
-
- // MPROC Drivers (PIL Driver and Subsystem Drivers)
- Include("../common/win_mproc.asl")
- Include("../common/syscache.asl")
- Include("../common/HoyaSmmu.asl")
- //Include("Ocmem.asl")
- Include("graphics.asl")
- //Include("OcmemTest.asl")
-
- Include("../common/SCM.asl");
-
- //
- // SPMI driver
- //
- Include("../common/spmi.asl")
-
- //
- // TLMM controller.
- //
- Include("qcgpio.asl")
-
- // Disbale PCIe
- // Include("../common/pcie.asl")
-
- Include("../common/cbsp_mproc.asl")
-
-Include("../common/adsprpc.asl")
-
- //
- // RemoteFS
- //
- Include("../common/rfs.asl")
-
-
- // Test Drivers
- // Include("testdev.asl")
- //
-
- //
- // Qualcomm IPA
- Include("../common/ipa.asl")
-
- Include("../common/gsi.asl")
-
- //
- //Qualcomm DIAG Service
- //
- Device (QDIG)
- {
- Name (_DEP, Package(0x1)
- {
- \_SB_.GLNK
- })
- Name (_HID, "QCOM0225")
- Alias(\_SB.PSUB, _SUB)
- }
-
- Include("../common/qcdb.asl")
- // Include("ssm.asl")
- Include("../common/Pep_lpi.asl")
-
- //
- // QcRNG Driver (qcsecuremsm)
- //
- Device (QRNG)
- {
- Name (_DEP, Package(0x1) {
- \_SB_.PEP0,
- })
- Name (_HID, "QCOM02FE")
- Name (_UID, 0)
- Method (_CRS, 0x0, NotSerialized)
- {
- Name (RBUF, ResourceTemplate ()
- {
- // PRNG_CFG_EE2_EE2_PRNG_SUB register address space
- Memory32Fixed (ReadWrite, 0x00793000, 0x00001000)
- })
- Return (RBUF)
- }
- }
-
-
- //
- // QCOM GPS
- //
- Include("../common/gps.asl")
-
- // QDSS driver
- Include("../common/Qdss.asl")
-
-// QUPV3 GPI device node and resources
-//
-Include("../common/qgpi.asl")
-
-Include("../common/qwpp.asl")
-
-//Include("nfc.asl")
-// Disabling QCSP Changes
-//Include("qcsp.asl")
-
-Include("../common/sar_manager.asl")
+++ /dev/null
-Name (PCFG,
- Buffer() {"<?xml version='1.0' encoding='utf-8'?>
-<PanelName>TFT2P2827-E</PanelName>
-<PanelDescription>Truly Dual DSI Command Mode Panel (1440x2560 24bpp)</PanelDescription>
-<Group id='EDID Configuration'>
- <ManufactureID>0x104D</ManufactureID>
- <ProductCode>850</ProductCode>
- <SerialNumber>0x000001</SerialNumber>
- <WeekofManufacture>0x01</WeekofManufacture>
- <YearofManufacture>0x1B</YearofManufacture>
- <EDIDVersion>1</EDIDVersion>
- <EDIDRevision>3</EDIDRevision>
- <VideoInputDefinition>0x80</VideoInputDefinition>
- <HorizontalScreenSize>0x07</HorizontalScreenSize>
- <VerticalScreenSize>0x0C</VerticalScreenSize>
- <DisplayTransferCharacteristics>0x78</DisplayTransferCharacteristics>
- <FeatureSupport>0x2</FeatureSupport>
- <Red.GreenBits>0xC8</Red.GreenBits>
- <Blue.WhiteBits>0xC0</Blue.WhiteBits>
- <RedX>0xA6</RedX>
- <RedY>0x51</RedY>
- <GreenX>0x4B</GreenX>
- <GreenY>0x9E</GreenY>
- <BlueX>0x25</BlueX>
- <BlueY>0x0E</BlueY>
- <WhiteX>0x48</WhiteX>
- <WhiteY>0x4B</WhiteY>
- <EstablishedTimingsI>0x0</EstablishedTimingsI>
- <EstablishedTimingsII>0x0</EstablishedTimingsII>
- <ManufacturesTiming>0x0</ManufacturesTiming>
- <StandardTimings1/>
- <StandardTimings2/>
- <StandardTimings3/>
- <StandardTimings4/>
- <StandardTimings5/>
- <StandardTimings6/>
- <StandardTimings7/>
- <SignalTimingInterface/>
-</Group>
-<Group id='Detailed Timing'>
- <HorizontalScreenSizeMM>0x44</HorizontalScreenSizeMM>
- <VerticalScreenSizeMM>0x78</VerticalScreenSizeMM>
- <HorizontalVerticalScreenSizeMM>0x00</HorizontalVerticalScreenSizeMM>
-</Group>
-<Group id='Active Timing'>
- <HorizontalActive>1440</HorizontalActive>
- <HorizontalFrontPorch>100</HorizontalFrontPorch>
- <HorizontalBackPorch>32</HorizontalBackPorch>
- <HorizontalSyncPulse>16</HorizontalSyncPulse>
- <HorizontalSyncSkew>0</HorizontalSyncSkew>
- <HorizontalLeftBorder>0</HorizontalLeftBorder>
- <HorizontalRightBorder>0</HorizontalRightBorder>
- <VerticalActive>2560</VerticalActive>
- <VerticalFrontPorch>8</VerticalFrontPorch>
- <VerticalBackPorch>7</VerticalBackPorch>
- <VerticalSyncPulse>1</VerticalSyncPulse>
- <VerticalSyncSkew>0</VerticalSyncSkew>
- <VerticalTopBorder>0</VerticalTopBorder>
- <VerticalBottomBorder>0</VerticalBottomBorder>
- <InvertDataPolarity>False</InvertDataPolarity>
- <InvertVsyncPolairty>False</InvertVsyncPolairty>
- <InvertHsyncPolarity>False</InvertHsyncPolarity>
- <BorderColor>0x0</BorderColor>
-</Group>
-<Group id='Display Interface'>
- <InterfaceType>9</InterfaceType>
- <InterfaceColorFormat>3</InterfaceColorFormat>
-</Group>
-<Group id='DSI Interface'>
- <DSIChannelId>2</DSIChannelId>
- <DSIVirtualId>0</DSIVirtualId>
- <DSIColorFormat>36</DSIColorFormat>
- <DSITrafficMode>1</DSITrafficMode>
- <DSILanes>4</DSILanes>
- <DSIRefreshRate>0x3C0000</DSIRefreshRate>
- <DSICmdSwapInterface>False</DSICmdSwapInterface>
- <DSICmdUsingTrigger>False</DSICmdUsingTrigger>
- <DSIEnableAutoRefresh>True</DSIEnableAutoRefresh>
- <DSIAutoRefreshFrameNumDiv>1</DSIAutoRefreshFrameNumDiv>
- <DSIInitMasterTime>120</DSIInitMasterTime>
- <DSIClockHSForceRequest>1</DSIClockHSForceRequest>
- <DSITECheckEnable>False</DSITECheckEnable>
- <DSITEUsingDedicatedTEPin>True</DSITEUsingDedicatedTEPin>
- <DSITEvSyncInitVal>0</DSITEvSyncInitVal>
- <DSITEvSyncRdPtrIrqLine>2400</DSITEvSyncRdPtrIrqLine>
- <DSIControllerMapping>
- 00 01
- </DSIControllerMapping>
-</Group>
-<DSIInitSequence>
- 15 FF 20
- 15 fb 01
- 15 00 01
- 15 01 55
- 15 02 45
- 15 05 40
- 15 06 19
- 15 07 1E
- 15 0B 73
- 15 0C 73
- 15 0E B0
- 15 0F AE
- 15 11 B8
- 15 13 00
- 15 58 80
- 15 59 01
- 15 5A 00
- 15 5B 01
- 15 5C 80
- 15 5D 81
- 15 5E 00
- 15 5F 01
- 15 72 31
- 15 68 03
- 15 ff 24
- 15 fb 01
- 15 00 1C
- 15 01 0B
- 15 02 0C
- 15 03 01
- 15 04 0F
- 15 05 10
- 15 06 10
- 15 07 10
- 15 08 89
- 15 09 8A
- 15 0A 13
- 15 0B 13
- 15 0C 15
- 15 0D 15
- 15 0E 17
- 15 0F 17
- 15 10 1C
- 15 11 0B
- 15 12 0C
- 15 13 01
- 15 14 0F
- 15 15 10
- 15 16 10
- 15 17 10
- 15 18 89
- 15 19 8A
- 15 1A 13
- 15 1B 13
- 15 1C 15
- 15 1D 15
- 15 1E 17
- 15 1F 17
- 15 20 40
- 15 21 01
- 15 22 00
- 15 23 40
- 15 24 40
- 15 25 6D
- 15 26 40
- 15 27 40
- 15 E0 00
- 15 DC 21
- 15 DD 22
- 15 DE 07
- 15 DF 07
- 15 E3 6D
- 15 E1 07
- 15 E2 07
- 15 29 D8
- 15 2A 2A
- 15 4B 03
- 15 4C 11
- 15 4D 10
- 15 4E 01
- 15 4F 01
- 15 50 10
- 15 51 00
- 15 52 80
- 15 53 00
- 15 56 00
- 15 54 07
- 15 58 07
- 15 55 25
- 15 5B 43
- 15 5C 00
- 15 5F 73
- 15 60 73
- 15 63 22
- 15 64 00
- 15 67 08
- 15 68 04
- 15 72 02
- 15 7A 80
- 15 7B 91
- 15 7C D8
- 15 7D 60
- 15 7F 15
- 15 75 15
- 15 B3 C0
- 15 B4 00
- 15 B5 00
- 15 78 00
- 15 79 00
- 15 80 00
- 15 83 00
- 15 93 0A
- 15 94 0A
- 15 8A 00
- 15 9B FF
- 15 9D B0
- 15 9F 63
- 15 98 10
- 15 EC 00
- 15 ff 10
- 39 3B 03 0A 0A
- 15 35 00
- 15 E5 01
- 15 BB 10
- 15 FB 01
- 05 11 00
- ff ff
- 05 29 00
-</DSIInitSequence>
-<DSIStatusSequence>
- 06 0a 9c
-</DSIStatusSequence>
-<DSITermSequence>
- 05 28 00
- FF 20
- 05 10 00
- FF 80
-</DSITermSequence>
-<Group id='Backlight Configuration'>
- <BacklightType>1</BacklightType>
- <BacklightPmicControlType>2</BacklightPmicControlType>
- <BacklightPMICBankSelect>3</BacklightPMICBankSelect>
- <BacklightPMICPWMFrequency>800000</BacklightPMICPWMFrequency>
- <BacklightSteps>100</BacklightSteps>
- <BacklightDefault>80</BacklightDefault>
- <BacklightLowPower>40</BacklightLowPower>
- <PMIPowerPmicNum>1</PMIPowerPmicNum>
- <PMIPowerPmicModel>21</PMIPowerPmicModel>
- <PMIPowerConfig>1</PMIPowerConfig>
- <AdaptiveBrightnessFeature>1</AdaptiveBrightnessFeature>
- <CABLEnable>True</CABLEnable>
- <BrightnessMinLuminance>200</BrightnessMinLuminance>
- <BrightnessMaxLuminance>319970</BrightnessMaxLuminance>
-</Group>
-<Group id='AD Configuration'>
- <ADMaxIterations>30</ADMaxIterations>
- <ADInitParam001>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam001>
- <ADInitParam002>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam002>
- <ADInitParam003>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam003>
- <ADInitParam004>0x0000 0x0800 0x1000 0x1801 0x1D61 0x22F2 0x26A2 0x2993 0x2C23 0x2E94 0x3114 0x33A5 0x3685 0x39C6 0x3D66 0x4177 0x45E7 0x4AE8 0x5058 0x5669 0x5D29 0x648A 0x6CAA 0x759B 0x7F7B 0x8A5C 0x965C 0xA3AD 0xB25D 0xC2BE 0xD4EE 0xE93F 0xFFFF </ADInitParam004>
- <ADInitParam005>0x0001 0x0032 0x0064 0x0096 0x00FA 0x015E 0x0190 0x0384 0x04E2 0x0708 0x08FC 0x0BB8 0x1770 0x2EE0 0x5DC0 0xC350 0x04B0 0x2125 0x2EE0 0x3969 0x4A1E 0x57B2 0x5DC0 0x8CA0 0xA5BA 0xC6E0 0xE0CE 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF </ADInitParam005>
- <ADInitParam006>0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF 0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF </ADInitParam006>
- <ADInitParam007>0x0000 0x0095 0x0128 0x01B9 0x0249 0x02D8 0x0365 0x03F1 0x047B 0x0504 0x058C 0x0612 0x0697 0x071A 0x079D 0x081E 0x089E 0x091C 0x099A 0x0A16 0x0A91 0x0B0B 0x0B83 0x0BFB 0x0C71 0x0CE7 0x0D5B 0x0DCE 0x0E41 0x0EB2 0x0F22 0x0F91 0x0FFF </ADInitParam007>
- <ADInitParam008>0x00FF 0x0116 0x012E 0x0146 0x015E 0x0176 0x018E 0x01A6 0x01BE 0x01D6 0x01EE 0x0205 0x021D 0x0235 0x024D 0x0265 0x027D 0x0295 0x02AC 0x02C4 0x02DC 0x02F3 0x030B 0x0323 0x033A 0x0352 0x036A 0x0381 0x0399 0x03B1 0x03C8 0x03E0 0x03F8 </ADInitParam008>
- <ADInitParam009>0x03</ADInitParam009>
- <ADInitParam010>0x3F</ADInitParam010>
- <ADInitParam011>0x0780</ADInitParam011>
- <ADInitParam012>0x0438</ADInitParam012>
- <ADInitParam013>0x0002</ADInitParam013>
- <ADInitParam014>0x0002</ADInitParam014>
- <ADInitParam015>0xFFFF</ADInitParam015>
- <ADInitParam016>0x06</ADInitParam016>
- <ADInitParam017>0x030</ADInitParam017>
- <ADInitParam018>0x012</ADInitParam018>
- <ADInitParam019>0x044</ADInitParam019>
- <ADInitParam020>0xFFFF</ADInitParam020>
- <ADInitParam021>0x80</ADInitParam021>
- <ADInitParam022>0x80</ADInitParam022>
- <ADInitParam023>0x07AE</ADInitParam023>
- <ADInitParam024>0x0800</ADInitParam024>
- <ADInitParam025>0x0333</ADInitParam025>
- <ADInitParam026>0x0800</ADInitParam026>
- <ADInitParam027>0x0333</ADInitParam027>
- <ADInitParam028>0x0006</ADInitParam028>
- <ADInitParam029>0x0222</ADInitParam029>
- <ADInitParam030>0x1000</ADInitParam030>
- <ADInitParam031>0x012C</ADInitParam031>
- <ADInitParam032>0x0BB8</ADInitParam032>
- <ADInitParam033>0x1DB0</ADInitParam033>
- <ADInitParam034>0xFFFF</ADInitParam034>
- <ADInitParam035>0xFFFF</ADInitParam035>
- <ADInitParam036>0x10</ADInitParam036>
- <ADInitParam037>0x00</ADInitParam037>
- <ADInitParam038>0x10</ADInitParam038>
- <ADInitParam039>0x00</ADInitParam039>
- <ADInitParam040>0xFFFF</ADInitParam040>
- <ADInitParam041>0x10</ADInitParam041>
- <ADInitParam042>0x1000</ADInitParam042>
- <ADInitParam043>0x10</ADInitParam043>
- <ADInitParam044>0x0200</ADInitParam044>
- <ADInitParam045>0x0080</ADInitParam045>
- <ADInitParam046>0x0</ADInitParam046>
- <ADInitParam047>0xFF</ADInitParam047>
- <ADInitParam048>0x07</ADInitParam048>
- <ADInitParam049>0xC6</ADInitParam049>
- <ADInitParam050>0x41</ADInitParam050>
- <ADInitParam051>0x3C</ADInitParam051>
- <ADInitParam052>0x80</ADInitParam052>
- <ADInitParam053>0x000</ADInitParam053>
- <ADInitParam054>0x3FF</ADInitParam054>
- <ADInitParam055>0xF0</ADInitParam055>
- <ADInitParam056>0x00</ADInitParam056>
- <ADInitParam057>0x01</ADInitParam057>
- <ADInitParam058>0x2</ADInitParam058>
- <ADInitParam059>0x05</ADInitParam059>
- <ADInitParam060>0x00</ADInitParam060>
- <ADInitParam061>0x00</ADInitParam061>
- <ADInitParam062>0x003</ADInitParam062>
- <ADInitParam063>0x001</ADInitParam063>
- <ADInitParam064>0x001</ADInitParam064>
- <ADInitParam065>0x3FF</ADInitParam065>
- <ADInitParam066>0x08</ADInitParam066>
- <ADInitParam067>0x08</ADInitParam067>
- <ADInitParam068>0x13</ADInitParam068>
- <ADInitParam069>0x0000</ADInitParam069>
- <ADInitParam070>0x001</ADInitParam070>
- <ADInitParam071>0x00C</ADInitParam071>
- <ADInitParam072>0x050</ADInitParam072>
- <ADInitParam073>0x80</ADInitParam073>
- <ADInitParam074>0x040</ADInitParam074>
- <ADInitParam075>0x008</ADInitParam075>
-
- <ADCfgParam001>0x0000</ADCfgParam001>
- <ADCfgParam002>0xFFFF</ADCfgParam002>
- <ADCfgParam003>0x0000</ADCfgParam003>
- <ADCfgParam004>0xFFFF</ADCfgParam004>
- <ADCfgParam005>0x86</ADCfgParam005>
- <ADCfgParam006>0x10</ADCfgParam006>
- <ADCfgParam007>0x80</ADCfgParam007>
- <ADCfgParam008>0x54</ADCfgParam008>
- <ADCfgParam009>0x200</ADCfgParam009>
- <ADCfgParam010>0x500</ADCfgParam010>
- <ADCfgParam011>0x0400</ADCfgParam011>
- <ADCfgParam012>0x0400</ADCfgParam012>
- <ADCfgParam013>0x80</ADCfgParam013>
- <ADCfgParam014>0x5025</ADCfgParam014>
- <ADCfgParam015>0x0000</ADCfgParam015>
- <ADCfgParam016>0x200</ADCfgParam016>
- <ADCfgParam017>0x0020</ADCfgParam017>
- <ADCfgParam018>0x0222</ADCfgParam018>
- <ADCfgParam019>0x0400</ADCfgParam019>
- <ADCfgParam020>0x0400</ADCfgParam020>
- <ADCfgParam021>0x0001</ADCfgParam021>
- <ADCfgParam022>0x0222</ADCfgParam022>
- <ADCfgParam023>0x0400</ADCfgParam023>
- <ADCfgParam024>0x1000</ADCfgParam024>
- <ADCfgParam025>0x0018</ADCfgParam025>
- <ADCfgParam026>0x005F</ADCfgParam026>
- <ADCfgParam027>0x0008</ADCfgParam027>
- <ADCfgParam028>0x0000</ADCfgParam028>
- <ADCfgParam029>0x0000</ADCfgParam029>
- <ADCfgParam030>0x0010</ADCfgParam030>
- <ADCfgParam031>0x080</ADCfgParam031>
- <ADCfgParam032>0x200</ADCfgParam032>
- <ADCfgParam033>0x80</ADCfgParam033>
- <ADCfgParam034>0x0020</ADCfgParam034>
- <ADCfgParam035>0x022</ADCfgParam035>
- <ADCfgParam036>0x600</ADCfgParam036>
- <ADCfgParam037>0x310</ADCfgParam037>
- <ADCfgParam038>0x80</ADCfgParam038>
- <ADCfgParam039>0x30</ADCfgParam039>
- <ADCfgParam040>0x19A</ADCfgParam040>
- <ADCfgParam041>0x03</ADCfgParam041>
- <ADCfgParam042>0x200</ADCfgParam042>
- <ADCfgParam043>0x200</ADCfgParam043>
- <ADCfgParam044>0x80</ADCfgParam044>
- <ADCfgParam045>0x90</ADCfgParam045>
- <ADCfgParam046>0x2000</ADCfgParam046>
-</Group>
-<Group id='Connection Configuration'>
- <Display1Reset1Info>DSI_PANEL_RESET, 0, 30</Display1Reset1Info>
- <Display1Power1Info>DSI_PANEL_MODE_SELECT, 0, 0, 0, 0, TRUE</Display1Power1Info>
-</Group>
-"})
-
-Name (PCF1,
- Buffer() {"<?xml version='1.0' encoding='utf-8'?>
-<PanelName>TFT2P2827-E</PanelName>
-<PanelDescription>Truly Dual DSI Video Mode Panel (1440x2560 24bpp)</PanelDescription>
-<Group id='EDID Configuration'>
- <ManufactureID>0x104D</ManufactureID>
- <ProductCode>850</ProductCode>
- <SerialNumber>0x000001</SerialNumber>
- <WeekofManufacture>0x01</WeekofManufacture>
- <YearofManufacture>0x1B</YearofManufacture>
- <EDIDVersion>1</EDIDVersion>
- <EDIDRevision>3</EDIDRevision>
- <VideoInputDefinition>0x80</VideoInputDefinition>
- <HorizontalScreenSize>0x07</HorizontalScreenSize>
- <VerticalScreenSize>0x0C</VerticalScreenSize>
- <DisplayTransferCharacteristics>0x78</DisplayTransferCharacteristics>
- <FeatureSupport>0x2</FeatureSupport>
- <Red.GreenBits>0xC8</Red.GreenBits>
- <Blue.WhiteBits>0xC0</Blue.WhiteBits>
- <RedX>0xA6</RedX>
- <RedY>0x51</RedY>
- <GreenX>0x4B</GreenX>
- <GreenY>0x9E</GreenY>
- <BlueX>0x25</BlueX>
- <BlueY>0x0E</BlueY>
- <WhiteX>0x48</WhiteX>
- <WhiteY>0x4B</WhiteY>
- <EstablishedTimingsI>0x0</EstablishedTimingsI>
- <EstablishedTimingsII>0x0</EstablishedTimingsII>
- <ManufacturesTiming>0x0</ManufacturesTiming>
- <StandardTimings1/>
- <StandardTimings2/>
- <StandardTimings3/>
- <StandardTimings4/>
- <StandardTimings5/>
- <StandardTimings6/>
- <StandardTimings7/>
- <SignalTimingInterface/>
-</Group>
-<Group id='Detailed Timing'>
- <HorizontalScreenSizeMM>0x44</HorizontalScreenSizeMM>
- <VerticalScreenSizeMM>0x78</VerticalScreenSizeMM>
- <HorizontalVerticalScreenSizeMM>0x00</HorizontalVerticalScreenSizeMM>
-</Group>
-<Group id='Active Timing'>
- <HorizontalActive>1440</HorizontalActive>
- <HorizontalFrontPorch>100</HorizontalFrontPorch>
- <HorizontalBackPorch>32</HorizontalBackPorch>
- <HorizontalSyncPulse>16</HorizontalSyncPulse>
- <HorizontalSyncSkew>0</HorizontalSyncSkew>
- <HorizontalLeftBorder>0</HorizontalLeftBorder>
- <HorizontalRightBorder>0</HorizontalRightBorder>
- <VerticalActive>2560</VerticalActive>
- <VerticalFrontPorch>8</VerticalFrontPorch>
- <VerticalBackPorch>7</VerticalBackPorch>
- <VerticalSyncPulse>1</VerticalSyncPulse>
- <VerticalSyncSkew>0</VerticalSyncSkew>
- <VerticalTopBorder>0</VerticalTopBorder>
- <VerticalBottomBorder>0</VerticalBottomBorder>
- <InvertDataPolarity>False</InvertDataPolarity>
- <InvertVsyncPolairty>False</InvertVsyncPolairty>
- <InvertHsyncPolarity>False</InvertHsyncPolarity>
- <BorderColor>0x0</BorderColor>
-</Group>
-<Group id='Display Interface'>
- <InterfaceType>8</InterfaceType>
- <InterfaceColorFormat>3</InterfaceColorFormat>
- <PanelOrientation>2</PanelOrientation>
-</Group>
-<Group id='DSI Interface'>
- <DSIChannelId>1</DSIChannelId>
- <DSIVirtualId>0</DSIVirtualId>
- <DSIColorFormat>36</DSIColorFormat>
- <DSITrafficMode>1</DSITrafficMode>
- <DSILanes>4</DSILanes>
- <DSIHsaHseAfterVsVe>False</DSIHsaHseAfterVsVe>
- <DSILowPowerModeInHFP>False</DSILowPowerModeInHFP>
- <DSILowPowerModeInHBP>False</DSILowPowerModeInHBP>
- <DSILowPowerModeInHSA>False</DSILowPowerModeInHSA>
- <DSILowPowerModeInBLLPEOF>True</DSILowPowerModeInBLLPEOF>
- <DSILowPowerModeInBLLP>True</DSILowPowerModeInBLLP>
- <DSIRefreshRate>0x3C0000</DSIRefreshRate>
- <DSIPhyDCDCMode>True</DSIPhyDCDCMode>
- <DSIInitMasterTime>32</DSIInitMasterTime>
- <DSIControllerMapping>
- 00 01
- </DSIControllerMapping>
- <DSIDynamicBlankingRefreshRateList>0x3C0000 0x300000</DSIDynamicBlankingRefreshRateList>
- <DSIDynamicVFrontPorchList>8 330</DSIDynamicVFrontPorchList>
- <DSIDynamicVBackPorchList>7 329</DSIDynamicVBackPorchList>
- <DSIDynamicVSyncPulseList>1 1</DSIDynamicVSyncPulseList>
- <DSIDynamicHFrontPorchList>100 100</DSIDynamicHFrontPorchList>
- <DSIDynamicHBackPorchList>32 32</DSIDynamicHBackPorchList>
- <DSIDynamicHSyncPulseList>16 16</DSIDynamicHSyncPulseList>
-</Group>
-<DSIInitSequence>
- FF 20
- 15 FF 20
- 15 FB 01
- 15 00 01
- 15 01 55
- 15 02 45
- 15 05 40
- 15 06 19
- 15 07 1E
- 15 0B 73
- 15 0C 73
- 15 0E B0
- 15 0F AE
- 15 11 B8
- 15 13 00
- 15 58 80
- 15 59 01
- 15 5A 00
- 15 5B 01
- 15 5C 80
- 15 5D 81
- 15 5E 00
- 15 5F 01
- 15 72 31
- 15 68 03
- 15 FF 24
- 15 FB 01
- 15 00 1C
- 15 01 0B
- 15 02 0C
- 15 03 01
- 15 04 0F
- 15 05 10
- 15 06 10
- 15 07 10
- 15 08 89
- 15 09 8A
- 15 0A 13
- 15 0B 13
- 15 0C 15
- 15 0D 15
- 15 0E 17
- 15 0F 17
- 15 10 1C
- 15 11 0B
- 15 12 0C
- 15 13 01
- 15 14 0F
- 15 15 10
- 15 16 10
- 15 17 10
- 15 18 89
- 15 19 8A
- 15 1A 13
- 15 1B 13
- 15 1C 15
- 15 1D 15
- 15 1E 17
- 15 1F 17
- 15 20 40
- 15 21 01
- 15 22 00
- 15 23 40
- 15 24 40
- 15 25 6D
- 15 26 40
- 15 27 40
- 15 E0 00
- 15 DC 21
- 15 DD 22
- 15 DE 07
- 15 DF 07
- 15 E3 6D
- 15 E1 07
- 15 E2 07
- 15 29 D8
- 15 2A 2A
- 15 4B 03
- 15 4C 11
- 15 4D 10
- 15 4E 01
- 15 4F 01
- 15 50 10
- 15 51 00
- 15 52 80
- 15 53 00
- 15 56 00
- 15 54 07
- 15 58 07
- 15 55 25
- 15 5B 43
- 15 5C 00
- 15 5F 73
- 15 60 73
- 15 63 22
- 15 64 00
- 15 67 08
- 15 68 04
- 15 72 02
- 15 7A 80
- 15 7B 91
- 15 7C D8
- 15 7D 60
- 15 7F 15
- 15 75 15
- 15 B3 C0
- 15 B4 00
- 15 B5 00
- 15 78 00
- 15 79 00
- 15 80 00
- 15 83 00
- 15 93 0A
- 15 94 0A
- 15 8A 00
- 15 9B FF
- 15 9D B0
- 15 9F 63
- 15 98 10
- 15 EC 00
- 15 FF 10
- 39 3B 03 0A
- 15 35 00
- 15 E5 01
- 15 BB 03
- 15 FB 01
- 05 11 00
- ff 64
- 05 29 00
-</DSIInitSequence>
-<DSITermSequence>
- 05 28 00
- FF 20
- 05 10 00
- FF 80
-</DSITermSequence>
-<Group id='Backlight Configuration'>
- <BacklightType>1</BacklightType>
- <BacklightPmicControlType>2</BacklightPmicControlType>
- <BacklightPMICBankSelect>3</BacklightPMICBankSelect>
- <BacklightPMICPWMFrequency>800000</BacklightPMICPWMFrequency>
- <BacklightSteps>100</BacklightSteps>
- <BacklightDefault>80</BacklightDefault>
- <BacklightLowPower>40</BacklightLowPower>
- <PMIPowerPmicNum>1</PMIPowerPmicNum>
- <PMIPowerPmicModel>21</PMIPowerPmicModel>
- <PMIPowerConfig>1</PMIPowerConfig>
- <AdaptiveBrightnessFeature>1</AdaptiveBrightnessFeature>
- <CABLEnable>True</CABLEnable>
- <BrightnessMinLuminance>200</BrightnessMinLuminance>
- <BrightnessMaxLuminance>319970</BrightnessMaxLuminance>
-</Group>
-<Group id='AD Configuration'>
- <ADMaxIterations>30</ADMaxIterations>
- <ADInitParam001>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam001>
- <ADInitParam002>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam002>
- <ADInitParam003>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam003>
- <ADInitParam004>0x0000 0x0800 0x1000 0x1801 0x1D61 0x22F2 0x26A2 0x2993 0x2C23 0x2E94 0x3114 0x33A5 0x3685 0x39C6 0x3D66 0x4177 0x45E7 0x4AE8 0x5058 0x5669 0x5D29 0x648A 0x6CAA 0x759B 0x7F7B 0x8A5C 0x965C 0xA3AD 0xB25D 0xC2BE 0xD4EE 0xE93F 0xFFFF </ADInitParam004>
- <ADInitParam005>0x0001 0x0032 0x0064 0x0096 0x00FA 0x015E 0x0190 0x0384 0x04E2 0x0708 0x08FC 0x0BB8 0x1770 0x2EE0 0x5DC0 0xC350 0x04B0 0x2125 0x2EE0 0x3969 0x4A1E 0x57B2 0x5DC0 0x8CA0 0xA5BA 0xC6E0 0xE0CE 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF </ADInitParam005>
- <ADInitParam006>0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF 0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF </ADInitParam006>
- <ADInitParam007>0x0000 0x0095 0x0128 0x01B9 0x0249 0x02D8 0x0365 0x03F1 0x047B 0x0504 0x058C 0x0612 0x0697 0x071A 0x079D 0x081E 0x089E 0x091C 0x099A 0x0A16 0x0A91 0x0B0B 0x0B83 0x0BFB 0x0C71 0x0CE7 0x0D5B 0x0DCE 0x0E41 0x0EB2 0x0F22 0x0F91 0x0FFF </ADInitParam007>
- <ADInitParam008>0x00FF 0x0116 0x012E 0x0146 0x015E 0x0176 0x018E 0x01A6 0x01BE 0x01D6 0x01EE 0x0205 0x021D 0x0235 0x024D 0x0265 0x027D 0x0295 0x02AC 0x02C4 0x02DC 0x02F3 0x030B 0x0323 0x033A 0x0352 0x036A 0x0381 0x0399 0x03B1 0x03C8 0x03E0 0x03F8 </ADInitParam008>
- <ADInitParam009>0x03</ADInitParam009>
- <ADInitParam010>0x3F</ADInitParam010>
- <ADInitParam011>0x0780</ADInitParam011>
- <ADInitParam012>0x0438</ADInitParam012>
- <ADInitParam013>0x0002</ADInitParam013>
- <ADInitParam014>0x0002</ADInitParam014>
- <ADInitParam015>0xFFFF</ADInitParam015>
- <ADInitParam016>0x06</ADInitParam016>
- <ADInitParam017>0x030</ADInitParam017>
- <ADInitParam018>0x012</ADInitParam018>
- <ADInitParam019>0x044</ADInitParam019>
- <ADInitParam020>0xFFFF</ADInitParam020>
- <ADInitParam021>0x80</ADInitParam021>
- <ADInitParam022>0x80</ADInitParam022>
- <ADInitParam023>0x07AE</ADInitParam023>
- <ADInitParam024>0x0800</ADInitParam024>
- <ADInitParam025>0x0333</ADInitParam025>
- <ADInitParam026>0x0800</ADInitParam026>
- <ADInitParam027>0x0333</ADInitParam027>
- <ADInitParam028>0x0006</ADInitParam028>
- <ADInitParam029>0x0222</ADInitParam029>
- <ADInitParam030>0x1000</ADInitParam030>
- <ADInitParam031>0x012C</ADInitParam031>
- <ADInitParam032>0x0BB8</ADInitParam032>
- <ADInitParam033>0x1DB0</ADInitParam033>
- <ADInitParam034>0xFFFF</ADInitParam034>
- <ADInitParam035>0xFFFF</ADInitParam035>
- <ADInitParam036>0x10</ADInitParam036>
- <ADInitParam037>0x00</ADInitParam037>
- <ADInitParam038>0x10</ADInitParam038>
- <ADInitParam039>0x00</ADInitParam039>
- <ADInitParam040>0xFFFF</ADInitParam040>
- <ADInitParam041>0x10</ADInitParam041>
- <ADInitParam042>0x1000</ADInitParam042>
- <ADInitParam043>0x10</ADInitParam043>
- <ADInitParam044>0x0200</ADInitParam044>
- <ADInitParam045>0x0080</ADInitParam045>
- <ADInitParam046>0x0</ADInitParam046>
- <ADInitParam047>0xFF</ADInitParam047>
- <ADInitParam048>0x07</ADInitParam048>
- <ADInitParam049>0xC6</ADInitParam049>
- <ADInitParam050>0x41</ADInitParam050>
- <ADInitParam051>0x3C</ADInitParam051>
- <ADInitParam052>0x80</ADInitParam052>
- <ADInitParam053>0x000</ADInitParam053>
- <ADInitParam054>0x3FF</ADInitParam054>
- <ADInitParam055>0xF0</ADInitParam055>
- <ADInitParam056>0x00</ADInitParam056>
- <ADInitParam057>0x01</ADInitParam057>
- <ADInitParam058>0x2</ADInitParam058>
- <ADInitParam059>0x05</ADInitParam059>
- <ADInitParam060>0x00</ADInitParam060>
- <ADInitParam061>0x00</ADInitParam061>
- <ADInitParam062>0x003</ADInitParam062>
- <ADInitParam063>0x001</ADInitParam063>
- <ADInitParam064>0x001</ADInitParam064>
- <ADInitParam065>0x3FF</ADInitParam065>
- <ADInitParam066>0x08</ADInitParam066>
- <ADInitParam067>0x08</ADInitParam067>
- <ADInitParam068>0x13</ADInitParam068>
- <ADInitParam069>0x0000</ADInitParam069>
- <ADInitParam070>0x001</ADInitParam070>
- <ADInitParam071>0x00C</ADInitParam071>
- <ADInitParam072>0x050</ADInitParam072>
- <ADInitParam073>0x80</ADInitParam073>
- <ADInitParam074>0x040</ADInitParam074>
- <ADInitParam075>0x008</ADInitParam075>
-
- <ADCfgParam001>0x0000</ADCfgParam001>
- <ADCfgParam002>0xFFFF</ADCfgParam002>
- <ADCfgParam003>0x0000</ADCfgParam003>
- <ADCfgParam004>0xFFFF</ADCfgParam004>
- <ADCfgParam005>0x86</ADCfgParam005>
- <ADCfgParam006>0x10</ADCfgParam006>
- <ADCfgParam007>0x80</ADCfgParam007>
- <ADCfgParam008>0x54</ADCfgParam008>
- <ADCfgParam009>0x200</ADCfgParam009>
- <ADCfgParam010>0x500</ADCfgParam010>
- <ADCfgParam011>0x0400</ADCfgParam011>
- <ADCfgParam012>0x0400</ADCfgParam012>
- <ADCfgParam013>0x80</ADCfgParam013>
- <ADCfgParam014>0x5025</ADCfgParam014>
- <ADCfgParam015>0x0000</ADCfgParam015>
- <ADCfgParam016>0x200</ADCfgParam016>
- <ADCfgParam017>0x0020</ADCfgParam017>
- <ADCfgParam018>0x0222</ADCfgParam018>
- <ADCfgParam019>0x0400</ADCfgParam019>
- <ADCfgParam020>0x0400</ADCfgParam020>
- <ADCfgParam021>0x0001</ADCfgParam021>
- <ADCfgParam022>0x0222</ADCfgParam022>
- <ADCfgParam023>0x0400</ADCfgParam023>
- <ADCfgParam024>0x1000</ADCfgParam024>
- <ADCfgParam025>0x0018</ADCfgParam025>
- <ADCfgParam026>0x005F</ADCfgParam026>
- <ADCfgParam027>0x0008</ADCfgParam027>
- <ADCfgParam028>0x0000</ADCfgParam028>
- <ADCfgParam029>0x0000</ADCfgParam029>
- <ADCfgParam030>0x0010</ADCfgParam030>
- <ADCfgParam031>0x080</ADCfgParam031>
- <ADCfgParam032>0x200</ADCfgParam032>
- <ADCfgParam033>0x80</ADCfgParam033>
- <ADCfgParam034>0x0020</ADCfgParam034>
- <ADCfgParam035>0x022</ADCfgParam035>
- <ADCfgParam036>0x600</ADCfgParam036>
- <ADCfgParam037>0x310</ADCfgParam037>
- <ADCfgParam038>0x80</ADCfgParam038>
- <ADCfgParam039>0x30</ADCfgParam039>
- <ADCfgParam040>0x19A</ADCfgParam040>
- <ADCfgParam041>0x03</ADCfgParam041>
- <ADCfgParam042>0x200</ADCfgParam042>
- <ADCfgParam043>0x200</ADCfgParam043>
- <ADCfgParam044>0x80</ADCfgParam044>
- <ADCfgParam045>0x90</ADCfgParam045>
- <ADCfgParam046>0x2000</ADCfgParam046>
-</Group>
-<Group id='Connection Configuration'>
- <Display1Reset1Info>DSI_PANEL_RESET, 0, 30</Display1Reset1Info>
- <Display1Power1Info>DSI_PANEL_MODE_SELECT, 0, 0, 0, 0, TRUE</Display1Power1Info>
-</Group>
-"})
-
-Name (PCF2,
- Buffer() {"<?xml version=\'1.0\' encoding=\'utf-8\'?>
-<PanelName>TFT2P2827-E</PanelName>
-<PanelDescription>Truly Single DSI Cmd Mode Panel with DSC (1440x2560 24bpp)</PanelDescription>
-<Group id='EDID Configuration'>
- <ManufactureID>0x104D</ManufactureID>
- <ProductCode>850</ProductCode>
- <SerialNumber>0x000001</SerialNumber>
- <WeekofManufacture>0x01</WeekofManufacture>
- <YearofManufacture>0x1B</YearofManufacture>
- <EDIDVersion>1</EDIDVersion>
- <EDIDRevision>3</EDIDRevision>
- <VideoInputDefinition>0x80</VideoInputDefinition>
- <HorizontalScreenSize>0x07</HorizontalScreenSize>
- <VerticalScreenSize>0x0C</VerticalScreenSize>
- <DisplayTransferCharacteristics>0x78</DisplayTransferCharacteristics>
- <FeatureSupport>0x2</FeatureSupport>
- <Red.GreenBits>0xC8</Red.GreenBits>
- <Blue.WhiteBits>0xC0</Blue.WhiteBits>
- <RedX>0xA6</RedX>
- <RedY>0x51</RedY>
- <GreenX>0x4B</GreenX>
- <GreenY>0x9E</GreenY>
- <BlueX>0x25</BlueX>
- <BlueY>0x0E</BlueY>
- <WhiteX>0x48</WhiteX>
- <WhiteY>0x4B</WhiteY>
- <EstablishedTimingsI>0x0</EstablishedTimingsI>
- <EstablishedTimingsII>0x0</EstablishedTimingsII>
- <ManufacturesTiming>0x0</ManufacturesTiming>
- <StandardTimings1/>
- <StandardTimings2/>
- <StandardTimings3/>
- <StandardTimings4/>
- <StandardTimings5/>
- <StandardTimings6/>
- <StandardTimings7/>
- <SignalTimingInterface/>
-</Group>
-<Group id='Detailed Timing'>
- <HorizontalScreenSizeMM>0x44</HorizontalScreenSizeMM>
- <VerticalScreenSizeMM>0x78</VerticalScreenSizeMM>
- <HorizontalVerticalScreenSizeMM>0x00</HorizontalVerticalScreenSizeMM>
-</Group>
-<Group id='Active Timing'>
- <HorizontalActive>1440</HorizontalActive>
- <HorizontalFrontPorch>100</HorizontalFrontPorch>
- <HorizontalBackPorch>32</HorizontalBackPorch>
- <HorizontalSyncPulse>16</HorizontalSyncPulse>
- <HorizontalSyncSkew>0</HorizontalSyncSkew>
- <HorizontalLeftBorder>0</HorizontalLeftBorder>
- <HorizontalRightBorder>0</HorizontalRightBorder>
- <VerticalActive>2560</VerticalActive>
- <VerticalFrontPorch>8</VerticalFrontPorch>
- <VerticalBackPorch>7</VerticalBackPorch>
- <VerticalSyncPulse>1</VerticalSyncPulse>
- <VerticalSyncSkew>0</VerticalSyncSkew>
- <VerticalTopBorder>0</VerticalTopBorder>
- <VerticalBottomBorder>0</VerticalBottomBorder>
- <InvertDataPolarity>False</InvertDataPolarity>
- <InvertVsyncPolairty>False</InvertVsyncPolairty>
- <InvertHsyncPolarity>False</InvertHsyncPolarity>
- <BorderColor>0x0</BorderColor>
-</Group>
-<Group id='Display Interface'>
- <InterfaceType>9</InterfaceType>
- <InterfaceColorFormat>3</InterfaceColorFormat>
-</Group>
-<Group id='DSI Interface'>
- <DSIChannelId>2</DSIChannelId>
- <DSIVirtualId>0</DSIVirtualId>
- <DSIColorFormat>36</DSIColorFormat>
- <DSITrafficMode>1</DSITrafficMode>
- <DSILanes>4</DSILanes>
- <DSIRefreshRate>0x3C0000</DSIRefreshRate>
- <DSICmdSwapInterface>False</DSICmdSwapInterface>
- <DSICmdUsingTrigger>False</DSICmdUsingTrigger>
- <DSITECheckEnable>False</DSITECheckEnable>
- <DSITEUsingDedicatedTEPin>True</DSITEUsingDedicatedTEPin>
- <DSITEvSyncInitVal>0</DSITEvSyncInitVal>
- <DSITEvSyncRdPtrIrqLine>2400</DSITEvSyncRdPtrIrqLine>
- <DSIBitClkScalePercent>15</DSIBitClkScalePercent>
- <DSIDSCEnable>True</DSIDSCEnable>
- <DSIDSCMajorVersion>1</DSIDSCMajorVersion>
- <DSIDSCMinorVersion>1</DSIDSCMinorVersion>
- <DSIDSCScr>0</DSIDSCScr>
- <DSIDSCProfileID>7</DSIDSCProfileID>
- <DSIDSCSliceWidth>720</DSIDSCSliceWidth>
- <DSIDSCSliceHeight>16</DSIDSCSliceHeight>
- <DSIInitMasterTime>120</DSIInitMasterTime>
- <DSIControllerMapping>
- 01
- </DSIControllerMapping>
-</Group>
-<DSIInitSequence>
- 15 FF 20
- 15 fb 01
- 15 00 01
- 15 01 55
- 15 02 45
- 15 05 40
- 15 06 19
- 15 07 1E
- 15 0B 73
- 15 0C 73
- 15 0E B0
- 15 0F AE
- 15 11 B8
- 15 13 00
- 15 58 80
- 15 59 01
- 15 5A 00
- 15 5B 01
- 15 5C 80
- 15 5D 81
- 15 5E 00
- 15 5F 01
- 15 72 31
- 15 68 03
- 15 ff 24
- 15 fb 01
- 15 00 1C
- 15 01 0B
- 15 02 0C
- 15 03 01
- 15 04 0F
- 15 05 10
- 15 06 10
- 15 07 10
- 15 08 89
- 15 09 8A
- 15 0A 13
- 15 0B 13
- 15 0C 15
- 15 0D 15
- 15 0E 17
- 15 0F 17
- 15 10 1C
- 15 11 0B
- 15 12 0C
- 15 13 01
- 15 14 0F
- 15 15 10
- 15 16 10
- 15 17 10
- 15 18 89
- 15 19 8A
- 15 1A 13
- 15 1B 13
- 15 1C 15
- 15 1D 15
- 15 1E 17
- 15 1F 17
- 15 20 40
- 15 21 01
- 15 22 00
- 15 23 40
- 15 24 40
- 15 25 6D
- 15 26 40
- 15 27 40
- 15 E0 00
- 15 DC 21
- 15 DD 22
- 15 DE 07
- 15 DF 07
- 15 E3 6D
- 15 E1 07
- 15 E2 07
- 15 29 D8
- 15 2A 2A
- 15 4B 03
- 15 4C 11
- 15 4D 10
- 15 4E 01
- 15 4F 01
- 15 50 10
- 15 51 00
- 15 52 80
- 15 53 00
- 15 56 00
- 15 54 07
- 15 58 07
- 15 55 25
- 15 5B 43
- 15 5C 00
- 15 5F 73
- 15 60 73
- 15 63 22
- 15 64 00
- 15 67 08
- 15 68 04
- 15 72 02
- 15 7A 80
- 15 7B 91
- 15 7C D8
- 15 7D 60
- 15 7F 15
- 15 75 15
- 15 B3 C0
- 15 B4 00
- 15 B5 00
- 15 78 00
- 15 79 00
- 15 80 00
- 15 83 00
- 15 93 0A
- 15 94 0A
- 15 8A 00
- 15 9B FF
- 15 9D B0
- 15 9F 63
- 15 98 10
- 15 EC 00
- 15 FF 10
- 15 fb 01
- 15 ba 03
- 15 e5 01
- 15 b0 03
- 15 ff 28
- 15 7a 02
- 15 fb 01
- 15 ff 10
- 15 fb 01
- 15 c0 03
- 15 bb 10
- 15 ff e0
- 15 fb 01
- 15 6b 3d
- 15 6c 3d
- 15 6d 3d
- 15 6e 3d
- 15 6f 3d
- 15 35 02
- 15 36 72
- 15 37 10
- 15 08 c0
- 15 ff 24
- 15 fb 01
- 15 c6 06
- 15 ff 10
- 15 35 00
- 05 11
- ff 64
- 05 29
- ff 28
- 07 01
-</DSIInitSequence>
-<DSIStatusSequence>
- 06 0a 9c
-</DSIStatusSequence>
-<DSITermSequence>
- 05 28 00
- FF 20
- 05 10 00
- FF 80
-</DSITermSequence>
-<TLMMGPIODefaultHigh>34</TLMMGPIODefaultHigh>
-<Group id='Backlight Configuration'>
- <BacklightType>1</BacklightType>
- <BacklightPmicControlType>2</BacklightPmicControlType>
- <BacklightPMICBankSelect>3</BacklightPMICBankSelect>
- <BacklightPMICPWMFrequency>800000</BacklightPMICPWMFrequency>
- <BacklightSteps>100</BacklightSteps>
- <BacklightDefault>80</BacklightDefault>
- <BacklightLowPower>40</BacklightLowPower>
- <PMIPowerPmicNum>1</PMIPowerPmicNum>
- <PMIPowerPmicModel>21</PMIPowerPmicModel>
- <PMIPowerConfig>1</PMIPowerConfig>
- <AdaptiveBrightnessFeature>1</AdaptiveBrightnessFeature>
- <CABLEnable>True</CABLEnable>
- <BrightnessMinLuminance>200</BrightnessMinLuminance>
- <BrightnessMaxLuminance>319970</BrightnessMaxLuminance>
-</Group>
-<Group id='AD Configuration'>
- <ADMaxIterations>30</ADMaxIterations>
- <ADInitParam001>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam001>
- <ADInitParam002>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam002>
- <ADInitParam003>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam003>
- <ADInitParam004>0x0000 0x0800 0x1000 0x1801 0x1D61 0x22F2 0x26A2 0x2993 0x2C23 0x2E94 0x3114 0x33A5 0x3685 0x39C6 0x3D66 0x4177 0x45E7 0x4AE8 0x5058 0x5669 0x5D29 0x648A 0x6CAA 0x759B 0x7F7B 0x8A5C 0x965C 0xA3AD 0xB25D 0xC2BE 0xD4EE 0xE93F 0xFFFF </ADInitParam004>
- <ADInitParam005>0x0001 0x0032 0x0064 0x0096 0x00FA 0x015E 0x0190 0x0384 0x04E2 0x0708 0x08FC 0x0BB8 0x1770 0x2EE0 0x5DC0 0xC350 0x04B0 0x2125 0x2EE0 0x3969 0x4A1E 0x57B2 0x5DC0 0x8CA0 0xA5BA 0xC6E0 0xE0CE 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF </ADInitParam005>
- <ADInitParam006>0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF 0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF </ADInitParam006>
- <ADInitParam007>0x0000 0x0095 0x0128 0x01B9 0x0249 0x02D8 0x0365 0x03F1 0x047B 0x0504 0x058C 0x0612 0x0697 0x071A 0x079D 0x081E 0x089E 0x091C 0x099A 0x0A16 0x0A91 0x0B0B 0x0B83 0x0BFB 0x0C71 0x0CE7 0x0D5B 0x0DCE 0x0E41 0x0EB2 0x0F22 0x0F91 0x0FFF </ADInitParam007>
- <ADInitParam008>0x00FF 0x0116 0x012E 0x0146 0x015E 0x0176 0x018E 0x01A6 0x01BE 0x01D6 0x01EE 0x0205 0x021D 0x0235 0x024D 0x0265 0x027D 0x0295 0x02AC 0x02C4 0x02DC 0x02F3 0x030B 0x0323 0x033A 0x0352 0x036A 0x0381 0x0399 0x03B1 0x03C8 0x03E0 0x03F8 </ADInitParam008>
- <ADInitParam009>0x03</ADInitParam009>
- <ADInitParam010>0x3F</ADInitParam010>
- <ADInitParam011>0x0780</ADInitParam011>
- <ADInitParam012>0x0438</ADInitParam012>
- <ADInitParam013>0x0002</ADInitParam013>
- <ADInitParam014>0x0002</ADInitParam014>
- <ADInitParam015>0xFFFF</ADInitParam015>
- <ADInitParam016>0x06</ADInitParam016>
- <ADInitParam017>0x030</ADInitParam017>
- <ADInitParam018>0x012</ADInitParam018>
- <ADInitParam019>0x044</ADInitParam019>
- <ADInitParam020>0xFFFF</ADInitParam020>
- <ADInitParam021>0x80</ADInitParam021>
- <ADInitParam022>0x80</ADInitParam022>
- <ADInitParam023>0x07AE</ADInitParam023>
- <ADInitParam024>0x0800</ADInitParam024>
- <ADInitParam025>0x0333</ADInitParam025>
- <ADInitParam026>0x0800</ADInitParam026>
- <ADInitParam027>0x0333</ADInitParam027>
- <ADInitParam028>0x0006</ADInitParam028>
- <ADInitParam029>0x0222</ADInitParam029>
- <ADInitParam030>0x1000</ADInitParam030>
- <ADInitParam031>0x012C</ADInitParam031>
- <ADInitParam032>0x0BB8</ADInitParam032>
- <ADInitParam033>0x1DB0</ADInitParam033>
- <ADInitParam034>0xFFFF</ADInitParam034>
- <ADInitParam035>0xFFFF</ADInitParam035>
- <ADInitParam036>0x10</ADInitParam036>
- <ADInitParam037>0x00</ADInitParam037>
- <ADInitParam038>0x10</ADInitParam038>
- <ADInitParam039>0x00</ADInitParam039>
- <ADInitParam040>0xFFFF</ADInitParam040>
- <ADInitParam041>0x10</ADInitParam041>
- <ADInitParam042>0x1000</ADInitParam042>
- <ADInitParam043>0x10</ADInitParam043>
- <ADInitParam044>0x0200</ADInitParam044>
- <ADInitParam045>0x0080</ADInitParam045>
- <ADInitParam046>0x0</ADInitParam046>
- <ADInitParam047>0xFF</ADInitParam047>
- <ADInitParam048>0x07</ADInitParam048>
- <ADInitParam049>0xC6</ADInitParam049>
- <ADInitParam050>0x41</ADInitParam050>
- <ADInitParam051>0x3C</ADInitParam051>
- <ADInitParam052>0x80</ADInitParam052>
- <ADInitParam053>0x000</ADInitParam053>
- <ADInitParam054>0x3FF</ADInitParam054>
- <ADInitParam055>0xF0</ADInitParam055>
- <ADInitParam056>0x00</ADInitParam056>
- <ADInitParam057>0x01</ADInitParam057>
- <ADInitParam058>0x2</ADInitParam058>
- <ADInitParam059>0x05</ADInitParam059>
- <ADInitParam060>0x00</ADInitParam060>
- <ADInitParam061>0x00</ADInitParam061>
- <ADInitParam062>0x003</ADInitParam062>
- <ADInitParam063>0x001</ADInitParam063>
- <ADInitParam064>0x001</ADInitParam064>
- <ADInitParam065>0x3FF</ADInitParam065>
- <ADInitParam066>0x08</ADInitParam066>
- <ADInitParam067>0x08</ADInitParam067>
- <ADInitParam068>0x13</ADInitParam068>
- <ADInitParam069>0x0000</ADInitParam069>
- <ADInitParam070>0x001</ADInitParam070>
- <ADInitParam071>0x00C</ADInitParam071>
- <ADInitParam072>0x050</ADInitParam072>
- <ADInitParam073>0x80</ADInitParam073>
- <ADInitParam074>0x040</ADInitParam074>
- <ADInitParam075>0x008</ADInitParam075>
-
- <ADCfgParam001>0x0000</ADCfgParam001>
- <ADCfgParam002>0xFFFF</ADCfgParam002>
- <ADCfgParam003>0x0000</ADCfgParam003>
- <ADCfgParam004>0xFFFF</ADCfgParam004>
- <ADCfgParam005>0x86</ADCfgParam005>
- <ADCfgParam006>0x10</ADCfgParam006>
- <ADCfgParam007>0x80</ADCfgParam007>
- <ADCfgParam008>0x54</ADCfgParam008>
- <ADCfgParam009>0x200</ADCfgParam009>
- <ADCfgParam010>0x500</ADCfgParam010>
- <ADCfgParam011>0x0400</ADCfgParam011>
- <ADCfgParam012>0x0400</ADCfgParam012>
- <ADCfgParam013>0x80</ADCfgParam013>
- <ADCfgParam014>0x5025</ADCfgParam014>
- <ADCfgParam015>0x0000</ADCfgParam015>
- <ADCfgParam016>0x200</ADCfgParam016>
- <ADCfgParam017>0x0020</ADCfgParam017>
- <ADCfgParam018>0x0222</ADCfgParam018>
- <ADCfgParam019>0x0400</ADCfgParam019>
- <ADCfgParam020>0x0400</ADCfgParam020>
- <ADCfgParam021>0x0001</ADCfgParam021>
- <ADCfgParam022>0x0222</ADCfgParam022>
- <ADCfgParam023>0x0400</ADCfgParam023>
- <ADCfgParam024>0x1000</ADCfgParam024>
- <ADCfgParam025>0x0018</ADCfgParam025>
- <ADCfgParam026>0x005F</ADCfgParam026>
- <ADCfgParam027>0x0008</ADCfgParam027>
- <ADCfgParam028>0x0000</ADCfgParam028>
- <ADCfgParam029>0x0000</ADCfgParam029>
- <ADCfgParam030>0x0010</ADCfgParam030>
- <ADCfgParam031>0x080</ADCfgParam031>
- <ADCfgParam032>0x200</ADCfgParam032>
- <ADCfgParam033>0x80</ADCfgParam033>
- <ADCfgParam034>0x0020</ADCfgParam034>
- <ADCfgParam035>0x022</ADCfgParam035>
- <ADCfgParam036>0x600</ADCfgParam036>
- <ADCfgParam037>0x310</ADCfgParam037>
- <ADCfgParam038>0x80</ADCfgParam038>
- <ADCfgParam039>0x30</ADCfgParam039>
- <ADCfgParam040>0x19A</ADCfgParam040>
- <ADCfgParam041>0x03</ADCfgParam041>
- <ADCfgParam042>0x200</ADCfgParam042>
- <ADCfgParam043>0x200</ADCfgParam043>
- <ADCfgParam044>0x80</ADCfgParam044>
- <ADCfgParam045>0x90</ADCfgParam045>
- <ADCfgParam046>0x2000</ADCfgParam046>
- </Group>
-<Group id='Connection Configuration'>
- <Display1Reset1Info>DSI_PANEL_RESET, 0, 30</Display1Reset1Info>
- <Display1Power1Info>DSI_PANEL_MODE_SELECT, 1, 0, 0, 0, TRUE</Display1Power1Info>
-</Group>
-"})
-
-Name (PCF3,
- Buffer() {"<?xml version=\'1.0\' encoding=\'utf-8\'?>
-<PanelName>TFT2P2827-E</PanelName>
-<PanelDescription>Truly Single DSI Video Mode Panel with DSC (1440x2560 24bpp)</PanelDescription>
-<Group id='EDID Configuration'>
- <ManufactureID>0x104D</ManufactureID>
- <ProductCode>850</ProductCode>
- <SerialNumber>0x000001</SerialNumber>
- <WeekofManufacture>0x01</WeekofManufacture>
- <YearofManufacture>0x1B</YearofManufacture>
- <EDIDVersion>1</EDIDVersion>
- <EDIDRevision>3</EDIDRevision>
- <VideoInputDefinition>0x80</VideoInputDefinition>
- <HorizontalScreenSize>0x07</HorizontalScreenSize>
- <VerticalScreenSize>0x0C</VerticalScreenSize>
- <DisplayTransferCharacteristics>0x78</DisplayTransferCharacteristics>
- <FeatureSupport>0x2</FeatureSupport>
- <Red.GreenBits>0xC8</Red.GreenBits>
- <Blue.WhiteBits>0xC0</Blue.WhiteBits>
- <RedX>0xA6</RedX>
- <RedY>0x51</RedY>
- <GreenX>0x4B</GreenX>
- <GreenY>0x9E</GreenY>
- <BlueX>0x25</BlueX>
- <BlueY>0x0E</BlueY>
- <WhiteX>0x48</WhiteX>
- <WhiteY>0x4B</WhiteY>
- <EstablishedTimingsI>0x0</EstablishedTimingsI>
- <EstablishedTimingsII>0x0</EstablishedTimingsII>
- <ManufacturesTiming>0x0</ManufacturesTiming>
- <StandardTimings1/>
- <StandardTimings2/>
- <StandardTimings3/>
- <StandardTimings4/>
- <StandardTimings5/>
- <StandardTimings6/>
- <StandardTimings7/>
- <SignalTimingInterface/>
-</Group>
-<Group id='Detailed Timing'>
- <HorizontalScreenSizeMM>0x44</HorizontalScreenSizeMM>
- <VerticalScreenSizeMM>0x78</VerticalScreenSizeMM>
- <HorizontalVerticalScreenSizeMM>0x00</HorizontalVerticalScreenSizeMM>
-</Group>
-<Group id='Active Timing'>
- <HorizontalActive>1440</HorizontalActive>
- <HorizontalFrontPorch>100</HorizontalFrontPorch>
- <HorizontalBackPorch>32</HorizontalBackPorch>
- <HorizontalSyncPulse>16</HorizontalSyncPulse>
- <HorizontalSyncSkew>0</HorizontalSyncSkew>
- <HorizontalLeftBorder>0</HorizontalLeftBorder>
- <HorizontalRightBorder>0</HorizontalRightBorder>
- <VerticalActive>2560</VerticalActive>
- <VerticalFrontPorch>8</VerticalFrontPorch>
- <VerticalBackPorch>7</VerticalBackPorch>
- <VerticalSyncPulse>1</VerticalSyncPulse>
- <VerticalSyncSkew>0</VerticalSyncSkew>
- <VerticalTopBorder>0</VerticalTopBorder>
- <VerticalBottomBorder>0</VerticalBottomBorder>
- <InvertDataPolarity>False</InvertDataPolarity>
- <InvertVsyncPolairty>False</InvertVsyncPolairty>
- <InvertHsyncPolarity>False</InvertHsyncPolarity>
- <BorderColor>0x0</BorderColor>
-</Group>
-<Group id='Display Interface'>
- <InterfaceType>8</InterfaceType>
- <InterfaceColorFormat>3</InterfaceColorFormat>
-</Group>
-<Group id='DSI Interface'>
- <DSIChannelId>1</DSIChannelId>
- <DSIVirtualId>0</DSIVirtualId>
- <DSIColorFormat>36</DSIColorFormat>
- <DSITrafficMode>1</DSITrafficMode>
- <DSIDSCEnable>True</DSIDSCEnable>
- <DSIDSCMajorVersion>1</DSIDSCMajorVersion>
- <DSIDSCMinorVersion>1</DSIDSCMinorVersion>
- <DSIDSCScr>0</DSIDSCScr>
- <DSIDSCProfileID>7</DSIDSCProfileID>
- <DSIDSCSliceWidth>720</DSIDSCSliceWidth>
- <DSIDSCSliceHeight>16</DSIDSCSliceHeight>
- <DSILanes>4</DSILanes>
- <DSIHsaHseAfterVsVe>False</DSIHsaHseAfterVsVe>
- <DSILowPowerModeInHFP>False</DSILowPowerModeInHFP>
- <DSILowPowerModeInHBP>False</DSILowPowerModeInHBP>
- <DSILowPowerModeInHSA>False</DSILowPowerModeInHSA>
- <DSILowPowerModeInBLLPEOF>True</DSILowPowerModeInBLLPEOF>
- <DSILowPowerModeInBLLP>True</DSILowPowerModeInBLLP>
- <DSIRefreshRate>0x3C0000</DSIRefreshRate>
- <DSIPhyDCDCMode>True</DSIPhyDCDCMode>
- <DSIInitMasterTime>32</DSIInitMasterTime>
- <DSIControllerMapping>
- 01
- </DSIControllerMapping>
-</Group>
-<DSIInitSequence>
- FF 20
- 15 FF 20
- 15 FB 01
- 15 00 01
- 15 01 55
- 15 02 45
- 15 05 40
- 15 06 19
- 15 07 1E
- 15 0B 73
- 15 0C 73
- 15 0E B0
- 15 0F AE
- 15 11 B8
- 15 13 00
- 15 58 80
- 15 59 01
- 15 5A 00
- 15 5B 01
- 15 5C 80
- 15 5D 81
- 15 5E 00
- 15 5F 01
- 15 72 31
- 15 68 03
- 15 FF 24
- 15 FB 01
- 15 00 1C
- 15 01 0B
- 15 02 0C
- 15 03 01
- 15 04 0F
- 15 05 10
- 15 06 10
- 15 07 10
- 15 08 89
- 15 09 8A
- 15 0A 13
- 15 0B 13
- 15 0C 15
- 15 0D 15
- 15 0E 17
- 15 0F 17
- 15 10 1C
- 15 11 0B
- 15 12 0C
- 15 13 01
- 15 14 0F
- 15 15 10
- 15 16 10
- 15 17 10
- 15 18 89
- 15 19 8A
- 15 1A 13
- 15 1B 13
- 15 1C 15
- 15 1D 15
- 15 1E 17
- 15 1F 17
- 15 20 40
- 15 21 01
- 15 22 00
- 15 23 40
- 15 24 40
- 15 25 6D
- 15 26 40
- 15 27 40
- 15 E0 00
- 15 DC 21
- 15 DD 22
- 15 DE 07
- 15 DF 07
- 15 E3 6D
- 15 E1 07
- 15 E2 07
- 15 29 D8
- 15 2A 2A
- 15 4B 03
- 15 4C 11
- 15 4D 10
- 15 4E 01
- 15 4F 01
- 15 50 10
- 15 51 00
- 15 52 80
- 15 53 00
- 15 56 00
- 15 54 07
- 15 58 07
- 15 55 25
- 15 5B 43
- 15 5C 00
- 15 5F 73
- 15 60 73
- 15 63 22
- 15 64 00
- 15 67 08
- 15 68 04
- 15 72 02
- 15 7A 80
- 15 7B 91
- 15 7C D8
- 15 7D 60
- 15 7F 15
- 15 75 15
- 15 B3 C0
- 15 B4 00
- 15 B5 00
- 15 78 00
- 15 79 00
- 15 80 00
- 15 83 00
- 15 93 0A
- 15 94 0A
- 15 8A 00
- 15 9B FF
- 15 9D B0
- 15 9F 63
- 15 98 10
- 15 EC 00
- 15 FF 10
- 15 fb 01
- 15 ba 03
- 15 e5 01
- 15 b0 03
- 39 3B 03 08 08 2e 64
- 15 FF 28
- 15 7a 02
- 15 fb 01
- 15 FF 10
- 15 fb 01
- 15 c0 03
- 15 bb 03
- 15 FF e0
- 15 fb 01
- 15 6b 3d
- 15 6c 3d
- 15 6d 3d
- 15 6e 3d
- 15 6f 3d
- 15 35 02
- 15 36 72
- 15 37 10
- 15 08 c0
- 15 FF 10
- 05 11 00
- ff 64
- 05 29
- ff 28
- 07 01
-</DSIInitSequence>
-<DSITermSequence>
- 05 28 00
- FF 20
- 05 10 00
- FF 80
-</DSITermSequence>
-<TLMMGPIODefaultHigh>34</TLMMGPIODefaultHigh>
-<Group id='Backlight Configuration'>
- <BacklightType>1</BacklightType>
- <BacklightPmicControlType>2</BacklightPmicControlType>
- <BacklightPMICBankSelect>3</BacklightPMICBankSelect>
- <BacklightPMICPWMFrequency>800000</BacklightPMICPWMFrequency>
- <BacklightSteps>100</BacklightSteps>
- <BacklightDefault>80</BacklightDefault>
- <BacklightLowPower>40</BacklightLowPower>
- <PMIPowerPmicNum>1</PMIPowerPmicNum>
- <PMIPowerPmicModel>21</PMIPowerPmicModel>
- <PMIPowerConfig>1</PMIPowerConfig>
- <AdaptiveBrightnessFeature>1</AdaptiveBrightnessFeature>
- <CABLEnable>True</CABLEnable>
- <BrightnessMinLuminance>200</BrightnessMinLuminance>
- <BrightnessMaxLuminance>319970</BrightnessMaxLuminance>
-</Group>
-<Group id='AD Configuration'>
- <ADMaxIterations>30</ADMaxIterations>
- <ADInitParam001>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam001>
- <ADInitParam002>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam002>
- <ADInitParam003>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam003>
- <ADInitParam004>0x0000 0x0800 0x1000 0x1801 0x1D61 0x22F2 0x26A2 0x2993 0x2C23 0x2E94 0x3114 0x33A5 0x3685 0x39C6 0x3D66 0x4177 0x45E7 0x4AE8 0x5058 0x5669 0x5D29 0x648A 0x6CAA 0x759B 0x7F7B 0x8A5C 0x965C 0xA3AD 0xB25D 0xC2BE 0xD4EE 0xE93F 0xFFFF </ADInitParam004>
- <ADInitParam005>0x0001 0x0032 0x0064 0x0096 0x00FA 0x015E 0x0190 0x0384 0x04E2 0x0708 0x08FC 0x0BB8 0x1770 0x2EE0 0x5DC0 0xC350 0x04B0 0x2125 0x2EE0 0x3969 0x4A1E 0x57B2 0x5DC0 0x8CA0 0xA5BA 0xC6E0 0xE0CE 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF </ADInitParam005>
- <ADInitParam006>0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF 0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF </ADInitParam006>
- <ADInitParam007>0x0000 0x0095 0x0128 0x01B9 0x0249 0x02D8 0x0365 0x03F1 0x047B 0x0504 0x058C 0x0612 0x0697 0x071A 0x079D 0x081E 0x089E 0x091C 0x099A 0x0A16 0x0A91 0x0B0B 0x0B83 0x0BFB 0x0C71 0x0CE7 0x0D5B 0x0DCE 0x0E41 0x0EB2 0x0F22 0x0F91 0x0FFF </ADInitParam007>
- <ADInitParam008>0x00FF 0x0116 0x012E 0x0146 0x015E 0x0176 0x018E 0x01A6 0x01BE 0x01D6 0x01EE 0x0205 0x021D 0x0235 0x024D 0x0265 0x027D 0x0295 0x02AC 0x02C4 0x02DC 0x02F3 0x030B 0x0323 0x033A 0x0352 0x036A 0x0381 0x0399 0x03B1 0x03C8 0x03E0 0x03F8 </ADInitParam008>
- <ADInitParam009>0x03</ADInitParam009>
- <ADInitParam010>0x3F</ADInitParam010>
- <ADInitParam011>0x0780</ADInitParam011>
- <ADInitParam012>0x0438</ADInitParam012>
- <ADInitParam013>0x0002</ADInitParam013>
- <ADInitParam014>0x0002</ADInitParam014>
- <ADInitParam015>0xFFFF</ADInitParam015>
- <ADInitParam016>0x06</ADInitParam016>
- <ADInitParam017>0x030</ADInitParam017>
- <ADInitParam018>0x012</ADInitParam018>
- <ADInitParam019>0x044</ADInitParam019>
- <ADInitParam020>0xFFFF</ADInitParam020>
- <ADInitParam021>0x80</ADInitParam021>
- <ADInitParam022>0x80</ADInitParam022>
- <ADInitParam023>0x07AE</ADInitParam023>
- <ADInitParam024>0x0800</ADInitParam024>
- <ADInitParam025>0x0333</ADInitParam025>
- <ADInitParam026>0x0800</ADInitParam026>
- <ADInitParam027>0x0333</ADInitParam027>
- <ADInitParam028>0x0006</ADInitParam028>
- <ADInitParam029>0x0222</ADInitParam029>
- <ADInitParam030>0x1000</ADInitParam030>
- <ADInitParam031>0x012C</ADInitParam031>
- <ADInitParam032>0x0BB8</ADInitParam032>
- <ADInitParam033>0x1DB0</ADInitParam033>
- <ADInitParam034>0xFFFF</ADInitParam034>
- <ADInitParam035>0xFFFF</ADInitParam035>
- <ADInitParam036>0x10</ADInitParam036>
- <ADInitParam037>0x00</ADInitParam037>
- <ADInitParam038>0x10</ADInitParam038>
- <ADInitParam039>0x00</ADInitParam039>
- <ADInitParam040>0xFFFF</ADInitParam040>
- <ADInitParam041>0x10</ADInitParam041>
- <ADInitParam042>0x1000</ADInitParam042>
- <ADInitParam043>0x10</ADInitParam043>
- <ADInitParam044>0x0200</ADInitParam044>
- <ADInitParam045>0x0080</ADInitParam045>
- <ADInitParam046>0x0</ADInitParam046>
- <ADInitParam047>0xFF</ADInitParam047>
- <ADInitParam048>0x07</ADInitParam048>
- <ADInitParam049>0xC6</ADInitParam049>
- <ADInitParam050>0x41</ADInitParam050>
- <ADInitParam051>0x3C</ADInitParam051>
- <ADInitParam052>0x80</ADInitParam052>
- <ADInitParam053>0x000</ADInitParam053>
- <ADInitParam054>0x3FF</ADInitParam054>
- <ADInitParam055>0xF0</ADInitParam055>
- <ADInitParam056>0x00</ADInitParam056>
- <ADInitParam057>0x01</ADInitParam057>
- <ADInitParam058>0x2</ADInitParam058>
- <ADInitParam059>0x05</ADInitParam059>
- <ADInitParam060>0x00</ADInitParam060>
- <ADInitParam061>0x00</ADInitParam061>
- <ADInitParam062>0x003</ADInitParam062>
- <ADInitParam063>0x001</ADInitParam063>
- <ADInitParam064>0x001</ADInitParam064>
- <ADInitParam065>0x3FF</ADInitParam065>
- <ADInitParam066>0x08</ADInitParam066>
- <ADInitParam067>0x08</ADInitParam067>
- <ADInitParam068>0x13</ADInitParam068>
- <ADInitParam069>0x0000</ADInitParam069>
- <ADInitParam070>0x001</ADInitParam070>
- <ADInitParam071>0x00C</ADInitParam071>
- <ADInitParam072>0x050</ADInitParam072>
- <ADInitParam073>0x80</ADInitParam073>
- <ADInitParam074>0x040</ADInitParam074>
- <ADInitParam075>0x008</ADInitParam075>
-
- <ADCfgParam001>0x0000</ADCfgParam001>
- <ADCfgParam002>0xFFFF</ADCfgParam002>
- <ADCfgParam003>0x0000</ADCfgParam003>
- <ADCfgParam004>0xFFFF</ADCfgParam004>
- <ADCfgParam005>0x86</ADCfgParam005>
- <ADCfgParam006>0x10</ADCfgParam006>
- <ADCfgParam007>0x80</ADCfgParam007>
- <ADCfgParam008>0x54</ADCfgParam008>
- <ADCfgParam009>0x200</ADCfgParam009>
- <ADCfgParam010>0x500</ADCfgParam010>
- <ADCfgParam011>0x0400</ADCfgParam011>
- <ADCfgParam012>0x0400</ADCfgParam012>
- <ADCfgParam013>0x80</ADCfgParam013>
- <ADCfgParam014>0x5025</ADCfgParam014>
- <ADCfgParam015>0x0000</ADCfgParam015>
- <ADCfgParam016>0x200</ADCfgParam016>
- <ADCfgParam017>0x0020</ADCfgParam017>
- <ADCfgParam018>0x0222</ADCfgParam018>
- <ADCfgParam019>0x0400</ADCfgParam019>
- <ADCfgParam020>0x0400</ADCfgParam020>
- <ADCfgParam021>0x0001</ADCfgParam021>
- <ADCfgParam022>0x0222</ADCfgParam022>
- <ADCfgParam023>0x0400</ADCfgParam023>
- <ADCfgParam024>0x1000</ADCfgParam024>
- <ADCfgParam025>0x0018</ADCfgParam025>
- <ADCfgParam026>0x005F</ADCfgParam026>
- <ADCfgParam027>0x0008</ADCfgParam027>
- <ADCfgParam028>0x0000</ADCfgParam028>
- <ADCfgParam029>0x0000</ADCfgParam029>
- <ADCfgParam030>0x0010</ADCfgParam030>
- <ADCfgParam031>0x080</ADCfgParam031>
- <ADCfgParam032>0x200</ADCfgParam032>
- <ADCfgParam033>0x80</ADCfgParam033>
- <ADCfgParam034>0x0020</ADCfgParam034>
- <ADCfgParam035>0x022</ADCfgParam035>
- <ADCfgParam036>0x600</ADCfgParam036>
- <ADCfgParam037>0x310</ADCfgParam037>
- <ADCfgParam038>0x80</ADCfgParam038>
- <ADCfgParam039>0x30</ADCfgParam039>
- <ADCfgParam040>0x19A</ADCfgParam040>
- <ADCfgParam041>0x03</ADCfgParam041>
- <ADCfgParam042>0x200</ADCfgParam042>
- <ADCfgParam043>0x200</ADCfgParam043>
- <ADCfgParam044>0x80</ADCfgParam044>
- <ADCfgParam045>0x90</ADCfgParam045>
- <ADCfgParam046>0x2000</ADCfgParam046>
-</Group>
-<Group id='Connection Configuration'>
- <Display1Reset1Info>DSI_PANEL_RESET, 0, 30</Display1Reset1Info>
- <Display1Power1Info>DSI_PANEL_MODE_SELECT, 1, 0, 0, 0, TRUE</Display1Power1Info>
-</Group>
-"})
-
-Name (PCF4,
- Buffer() {"<?xml version='1.0' encoding='utf-8'?>
-<PanelName>LS060R1SX03</PanelName>
-<PanelDescription>Sharp Dual DSI Command Mode DSC Panel (2160x3840 24bpp)</PanelDescription>
-<Group id='EDID Configuration'>
- <ManufactureID>0x104D</ManufactureID>
- <ProductCode>850</ProductCode>
- <SerialNumber>0x000001</SerialNumber>
- <WeekofManufacture>0x01</WeekofManufacture>
- <YearofManufacture>0x1B</YearofManufacture>
- <EDIDVersion>1</EDIDVersion>
- <EDIDRevision>3</EDIDRevision>
- <VideoInputDefinition>0x80</VideoInputDefinition>
- <HorizontalScreenSize>0x07</HorizontalScreenSize>
- <VerticalScreenSize>0x0C</VerticalScreenSize>
- <DisplayTransferCharacteristics>0x78</DisplayTransferCharacteristics>
- <FeatureSupport>0x2</FeatureSupport>
- <Red.GreenBits>0xA5</Red.GreenBits>
- <Blue.WhiteBits>0x58</Blue.WhiteBits>
- <RedX>0xA6</RedX>
- <RedY>0x54</RedY>
- <GreenX>0x33</GreenX>
- <GreenY>0xB3</GreenY>
- <BlueX>0x26</BlueX>
- <BlueY>0x12</BlueY>
- <WhiteX>0x4F</WhiteX>
- <WhiteY>0x54</WhiteY>
- <EstablishedTimingsI>0x0</EstablishedTimingsI>
- <EstablishedTimingsII>0x0</EstablishedTimingsII>
- <ManufacturesTiming>0x0</ManufacturesTiming>
- <StandardTimings1/>
- <StandardTimings2/>
- <StandardTimings3/>
- <StandardTimings4/>
- <StandardTimings5/>
- <StandardTimings6/>
- <StandardTimings7/>
- <SignalTimingInterface/>
-</Group>
-<Group id='Detailed Timing'>
- <HorizontalScreenSizeMM>0x44</HorizontalScreenSizeMM>
- <VerticalScreenSizeMM>0x78</VerticalScreenSizeMM>
- <HorizontalVerticalScreenSizeMM>0x00</HorizontalVerticalScreenSizeMM>
-</Group>
-<Group id='Active Timing'>
- <HorizontalActive>2160</HorizontalActive>
- <HorizontalFrontPorch>30</HorizontalFrontPorch>
- <HorizontalBackPorch>100</HorizontalBackPorch>
- <HorizontalSyncPulse>4</HorizontalSyncPulse>
- <HorizontalSyncSkew>0</HorizontalSyncSkew>
- <HorizontalLeftBorder>0</HorizontalLeftBorder>
- <HorizontalRightBorder>0</HorizontalRightBorder>
- <VerticalActive>3840</VerticalActive>
- <VerticalFrontPorch>8</VerticalFrontPorch>
- <VerticalBackPorch>7</VerticalBackPorch>
- <VerticalSyncPulse>1</VerticalSyncPulse>
- <VerticalSyncSkew>0</VerticalSyncSkew>
- <VerticalTopBorder>0</VerticalTopBorder>
- <VerticalBottomBorder>0</VerticalBottomBorder>
- <InvertDataPolarity>False</InvertDataPolarity>
- <InvertVsyncPolairty>False</InvertVsyncPolairty>
- <InvertHsyncPolarity>False</InvertHsyncPolarity>
- <BorderColor>0x0</BorderColor>
-</Group>
-<Group id='Display Interface'>
- <InterfaceType>9</InterfaceType>
- <InterfaceColorFormat>3</InterfaceColorFormat>
-</Group>
-<Group id='DSI Interface'>
- <DSIChannelId>2</DSIChannelId>
- <DSIVirtualId>0</DSIVirtualId>
- <DSIColorFormat>36</DSIColorFormat>
- <DSITrafficMode>1</DSITrafficMode>
- <DSILanes>4</DSILanes>
- <DSIRefreshRate>0x3C0000</DSIRefreshRate>
- <DSICmdSwapInterface>False</DSICmdSwapInterface>
- <DSICmdUsingTrigger>False</DSICmdUsingTrigger>
- <DSITECheckEnable>False</DSITECheckEnable>
- <DSITEUsingDedicatedTEPin>True</DSITEUsingDedicatedTEPin>
- <DSITEvSyncInitVal>0</DSITEvSyncInitVal>
- <DSITEvSyncRdPtrIrqLine>3600</DSITEvSyncRdPtrIrqLine>
- <DSIDSCEnable>True</DSIDSCEnable>
- <DSIDSCMajorVersion>1</DSIDSCMajorVersion>
- <DSIDSCMinorVersion>1</DSIDSCMinorVersion>
- <DSIDSCScr>0</DSIDSCScr>
- <DSIDSCProfileID>4</DSIDSCProfileID>
- <DSIDSCSliceWidth>1080</DSIDSCSliceWidth>
- <DSIDSCSliceHeight>32</DSIDSCSliceHeight>
- <DSIInitMasterTime>128</DSIInitMasterTime>
- <DSIControllerMapping>
- 00 01
- </DSIControllerMapping>
-</Group>
-<DSIInitSequence>
- 39 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97
- 39 92 10 f0
- 15 90 03
- 15 03 01
- 39 f0 55 aa 52 08 04
- 15 c0 03
- 39 f0 55 aa 52 08 07
- 15 ef 01
- 39 f0 55 aa 52 08 00
- 15 b4 01
- 15 35 00
- 39 f0 55 aa 52 08 01
- 39 ff aa 55 a5 80
- 15 6f 01
- 15 f3 10
- 39 ff aa 55 a5 00
- 05 11
- ff 78
- 05 29
- ff 78
-</DSIInitSequence>
-<DSITermSequence>
- 05 28 00
- FF 20
- 05 10 00
- FF 80
-</DSITermSequence>
-<Group id='Connection Configuration'>
- <Display1Reset1Info>DSI_PANEL_RESET, 0, 30</Display1Reset1Info>
- <Display1Power1Info>DSI_PANEL_MODE_SELECT, 0, 0, 0, 0, TRUE</Display1Power1Info>
-</Group>
-<Group id='Backlight Configuration'>
- <BacklightType>1</BacklightType>
- <BacklightPmicControlType>2</BacklightPmicControlType>
- <BacklightSteps>100</BacklightSteps>
- <BacklightPMICBankSelect>3</BacklightPMICBankSelect>
- <BacklightPMICPWMFrequency>800000</BacklightPMICPWMFrequency>
- <BacklightSteps>100</BacklightSteps>
- <BacklightDefault>80</BacklightDefault>
- <BacklightLowPower>40</BacklightLowPower>
- <PMIPowerPmicNum>1</PMIPowerPmicNum>
- <PMIPowerPmicModel>21</PMIPowerPmicModel>
- <PMIPowerConfig>1</PMIPowerConfig>
- <AdaptiveBrightnessFeature>1</AdaptiveBrightnessFeature>
- <CABLEnable>True</CABLEnable>
- <BrightnessMinLuminance>200</BrightnessMinLuminance>
- <BrightnessMaxLuminance>319970</BrightnessMaxLuminance>
-</Group>
-<Group id='AD Configuration'>
- <ADMaxIterations>30</ADMaxIterations>
- <ADInitParam001>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam001>
- <ADInitParam002>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam002>
- <ADInitParam003>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam003>
- <ADInitParam004>0x0000 0x0800 0x1000 0x1801 0x1D61 0x22F2 0x26A2 0x2993 0x2C23 0x2E94 0x3114 0x33A5 0x3685 0x39C6 0x3D66 0x4177 0x45E7 0x4AE8 0x5058 0x5669 0x5D29 0x648A 0x6CAA 0x759B 0x7F7B 0x8A5C 0x965C 0xA3AD 0xB25D 0xC2BE 0xD4EE 0xE93F 0xFFFF </ADInitParam004>
- <ADInitParam005>0x0001 0x0032 0x0064 0x0096 0x00FA 0x015E 0x0190 0x0384 0x04E2 0x0708 0x08FC 0x0BB8 0x1770 0x2EE0 0x5DC0 0xC350 0x04B0 0x2125 0x2EE0 0x3969 0x4A1E 0x57B2 0x5DC0 0x8CA0 0xA5BA 0xC6E0 0xE0CE 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF </ADInitParam005>
- <ADInitParam006>0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF 0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF </ADInitParam006>
- <ADInitParam007>0x0000 0x0095 0x0128 0x01B9 0x0249 0x02D8 0x0365 0x03F1 0x047B 0x0504 0x058C 0x0612 0x0697 0x071A 0x079D 0x081E 0x089E 0x091C 0x099A 0x0A16 0x0A91 0x0B0B 0x0B83 0x0BFB 0x0C71 0x0CE7 0x0D5B 0x0DCE 0x0E41 0x0EB2 0x0F22 0x0F91 0x0FFF </ADInitParam007>
- <ADInitParam008>0x00FF 0x0116 0x012E 0x0146 0x015E 0x0176 0x018E 0x01A6 0x01BE 0x01D6 0x01EE 0x0205 0x021D 0x0235 0x024D 0x0265 0x027D 0x0295 0x02AC 0x02C4 0x02DC 0x02F3 0x030B 0x0323 0x033A 0x0352 0x036A 0x0381 0x0399 0x03B1 0x03C8 0x03E0 0x03F8 </ADInitParam008>
- <ADInitParam009>0x03</ADInitParam009>
- <ADInitParam010>0x3F</ADInitParam010>
- <ADInitParam011>0x0780</ADInitParam011>
- <ADInitParam012>0x0438</ADInitParam012>
- <ADInitParam013>0x0002</ADInitParam013>
- <ADInitParam014>0x0002</ADInitParam014>
- <ADInitParam015>0xFFFF</ADInitParam015>
- <ADInitParam016>0x06</ADInitParam016>
- <ADInitParam017>0x030</ADInitParam017>
- <ADInitParam018>0x012</ADInitParam018>
- <ADInitParam019>0x044</ADInitParam019>
- <ADInitParam020>0xFFFF</ADInitParam020>
- <ADInitParam021>0x80</ADInitParam021>
- <ADInitParam022>0x80</ADInitParam022>
- <ADInitParam023>0x07AE</ADInitParam023>
- <ADInitParam024>0x0800</ADInitParam024>
- <ADInitParam025>0x0333</ADInitParam025>
- <ADInitParam026>0x0800</ADInitParam026>
- <ADInitParam027>0x0333</ADInitParam027>
- <ADInitParam028>0x0006</ADInitParam028>
- <ADInitParam029>0x0222</ADInitParam029>
- <ADInitParam030>0x1000</ADInitParam030>
- <ADInitParam031>0x012C</ADInitParam031>
- <ADInitParam032>0x0BB8</ADInitParam032>
- <ADInitParam033>0x1DB0</ADInitParam033>
- <ADInitParam034>0xFFFF</ADInitParam034>
- <ADInitParam035>0xFFFF</ADInitParam035>
- <ADInitParam036>0x10</ADInitParam036>
- <ADInitParam037>0x00</ADInitParam037>
- <ADInitParam038>0x10</ADInitParam038>
- <ADInitParam039>0x00</ADInitParam039>
- <ADInitParam040>0xFFFF</ADInitParam040>
- <ADInitParam041>0x10</ADInitParam041>
- <ADInitParam042>0x1000</ADInitParam042>
- <ADInitParam043>0x10</ADInitParam043>
- <ADInitParam044>0x0200</ADInitParam044>
- <ADInitParam045>0x0080</ADInitParam045>
- <ADInitParam046>0x0</ADInitParam046>
- <ADInitParam047>0xFF</ADInitParam047>
- <ADInitParam048>0x07</ADInitParam048>
- <ADInitParam049>0xC6</ADInitParam049>
- <ADInitParam050>0x41</ADInitParam050>
- <ADInitParam051>0x3C</ADInitParam051>
- <ADInitParam052>0x80</ADInitParam052>
- <ADInitParam053>0x000</ADInitParam053>
- <ADInitParam054>0x3FF</ADInitParam054>
- <ADInitParam055>0xF0</ADInitParam055>
- <ADInitParam056>0x00</ADInitParam056>
- <ADInitParam057>0x01</ADInitParam057>
- <ADInitParam058>0x2</ADInitParam058>
- <ADInitParam059>0x05</ADInitParam059>
- <ADInitParam060>0x00</ADInitParam060>
- <ADInitParam061>0x00</ADInitParam061>
- <ADInitParam062>0x003</ADInitParam062>
- <ADInitParam063>0x001</ADInitParam063>
- <ADInitParam064>0x001</ADInitParam064>
- <ADInitParam065>0x3FF</ADInitParam065>
- <ADInitParam066>0x08</ADInitParam066>
- <ADInitParam067>0x08</ADInitParam067>
- <ADInitParam068>0x13</ADInitParam068>
- <ADInitParam069>0x0000</ADInitParam069>
- <ADInitParam070>0x001</ADInitParam070>
- <ADInitParam071>0x00C</ADInitParam071>
- <ADInitParam072>0x050</ADInitParam072>
- <ADInitParam073>0x80</ADInitParam073>
- <ADInitParam074>0x040</ADInitParam074>
- <ADInitParam075>0x008</ADInitParam075>
-
- <ADCfgParam001>0x0000</ADCfgParam001>
- <ADCfgParam002>0xFFFF</ADCfgParam002>
- <ADCfgParam003>0x0000</ADCfgParam003>
- <ADCfgParam004>0xFFFF</ADCfgParam004>
- <ADCfgParam005>0x86</ADCfgParam005>
- <ADCfgParam006>0x10</ADCfgParam006>
- <ADCfgParam007>0x80</ADCfgParam007>
- <ADCfgParam008>0x54</ADCfgParam008>
- <ADCfgParam009>0x200</ADCfgParam009>
- <ADCfgParam010>0x500</ADCfgParam010>
- <ADCfgParam011>0x0400</ADCfgParam011>
- <ADCfgParam012>0x0400</ADCfgParam012>
- <ADCfgParam013>0x80</ADCfgParam013>
- <ADCfgParam014>0x5025</ADCfgParam014>
- <ADCfgParam015>0x0000</ADCfgParam015>
- <ADCfgParam016>0x200</ADCfgParam016>
- <ADCfgParam017>0x0020</ADCfgParam017>
- <ADCfgParam018>0x0222</ADCfgParam018>
- <ADCfgParam019>0x0400</ADCfgParam019>
- <ADCfgParam020>0x0400</ADCfgParam020>
- <ADCfgParam021>0x0001</ADCfgParam021>
- <ADCfgParam022>0x0222</ADCfgParam022>
- <ADCfgParam023>0x0400</ADCfgParam023>
- <ADCfgParam024>0x1000</ADCfgParam024>
- <ADCfgParam025>0x0018</ADCfgParam025>
- <ADCfgParam026>0x005F</ADCfgParam026>
- <ADCfgParam027>0x0008</ADCfgParam027>
- <ADCfgParam028>0x0000</ADCfgParam028>
- <ADCfgParam029>0x0000</ADCfgParam029>
- <ADCfgParam030>0x0010</ADCfgParam030>
- <ADCfgParam031>0x080</ADCfgParam031>
- <ADCfgParam032>0x200</ADCfgParam032>
- <ADCfgParam033>0x80</ADCfgParam033>
- <ADCfgParam034>0x0020</ADCfgParam034>
- <ADCfgParam035>0x022</ADCfgParam035>
- <ADCfgParam036>0x600</ADCfgParam036>
- <ADCfgParam037>0x310</ADCfgParam037>
- <ADCfgParam038>0x80</ADCfgParam038>
- <ADCfgParam039>0x30</ADCfgParam039>
- <ADCfgParam040>0x19A</ADCfgParam040>
- <ADCfgParam041>0x03</ADCfgParam041>
- <ADCfgParam042>0x200</ADCfgParam042>
- <ADCfgParam043>0x200</ADCfgParam043>
- <ADCfgParam044>0x80</ADCfgParam044>
- <ADCfgParam045>0x90</ADCfgParam045>
- <ADCfgParam046>0x2000</ADCfgParam046>
-</Group>
-"})
-
-Name (PCF5,
- Buffer() {"<?xml version='1.0' encoding='utf-8'?>
-<PanelName>LS060R1SX03</PanelName>
-<PanelDescription>Sharp Dual DSI Video Mode Panel with DSC (2160x3840 24bpp)</PanelDescription>
-<Group id='EDID Configuration'>
- <ManufactureID>0x104D</ManufactureID>
- <ProductCode>850</ProductCode>
- <SerialNumber>0x000001</SerialNumber>
- <WeekofManufacture>0x01</WeekofManufacture>
- <YearofManufacture>0x1B</YearofManufacture>
- <EDIDVersion>1</EDIDVersion>
- <EDIDRevision>3</EDIDRevision>
- <VideoInputDefinition>0x80</VideoInputDefinition>
- <HorizontalScreenSize>0x07</HorizontalScreenSize>
- <VerticalScreenSize>0x0C</VerticalScreenSize>
- <DisplayTransferCharacteristics>0x78</DisplayTransferCharacteristics>
- <FeatureSupport>0x2</FeatureSupport>
- <Red.GreenBits>0xA5</Red.GreenBits>
- <Blue.WhiteBits>0x58</Blue.WhiteBits>
- <RedX>0xA6</RedX>
- <RedY>0x54</RedY>
- <GreenX>0x33</GreenX>
- <GreenY>0xB3</GreenY>
- <BlueX>0x26</BlueX>
- <BlueY>0x12</BlueY>
- <WhiteX>0x4F</WhiteX>
- <WhiteY>0x54</WhiteY>
- <EstablishedTimingsI>0x0</EstablishedTimingsI>
- <EstablishedTimingsII>0x0</EstablishedTimingsII>
- <ManufacturesTiming>0x0</ManufacturesTiming>
- <StandardTimings1/>
- <StandardTimings2/>
- <StandardTimings3/>
- <StandardTimings4/>
- <StandardTimings5/>
- <StandardTimings6/>
- <StandardTimings7/>
- <SignalTimingInterface/>
-</Group>
-<Group id='Detailed Timing'>
- <HorizontalScreenSizeMM>0x44</HorizontalScreenSizeMM>
- <VerticalScreenSizeMM>0x78</VerticalScreenSizeMM>
- <HorizontalVerticalScreenSizeMM>0x00</HorizontalVerticalScreenSizeMM>
-</Group>
-<Group id='Active Timing'>
- <HorizontalActive>2160</HorizontalActive>
- <HorizontalFrontPorch>30</HorizontalFrontPorch>
- <HorizontalBackPorch>100</HorizontalBackPorch>
- <HorizontalSyncPulse>4</HorizontalSyncPulse>
- <HorizontalSyncSkew>0</HorizontalSyncSkew>
- <HorizontalLeftBorder>0</HorizontalLeftBorder>
- <HorizontalRightBorder>0</HorizontalRightBorder>
- <VerticalActive>3840</VerticalActive>
- <VerticalFrontPorch>8</VerticalFrontPorch>
- <VerticalBackPorch>7</VerticalBackPorch>
- <VerticalSyncPulse>1</VerticalSyncPulse>
- <VerticalSyncSkew>0</VerticalSyncSkew>
- <VerticalTopBorder>0</VerticalTopBorder>
- <VerticalBottomBorder>0</VerticalBottomBorder>
- <InvertDataPolarity>False</InvertDataPolarity>
- <InvertVsyncPolairty>False</InvertVsyncPolairty>
- <InvertHsyncPolarity>False</InvertHsyncPolarity>
- <BorderColor>0x0</BorderColor>
-</Group>
-<Group id='Display Interface'>
- <InterfaceType>8</InterfaceType>
- <InterfaceColorFormat>3</InterfaceColorFormat>
-</Group>
-<Group id='DSI Interface'>
- <DSIChannelId>1</DSIChannelId>
- <DSIVirtualId>0</DSIVirtualId>
- <DSIColorFormat>36</DSIColorFormat>
- <DSITrafficMode>1</DSITrafficMode>
- <DSIDSCEnable>True</DSIDSCEnable>
- <DSIDSCMajorVersion>1</DSIDSCMajorVersion>
- <DSIDSCMinorVersion>1</DSIDSCMinorVersion>
- <DSIDSCScr>0</DSIDSCScr>
- <DSIDSCProfileID>4</DSIDSCProfileID>
- <DSIDSCSliceWidth>1080</DSIDSCSliceWidth>
- <DSIDSCSliceHeight>32</DSIDSCSliceHeight>
- <DSILanes>4</DSILanes>
- <DSIHsaHseAfterVsVe>False</DSIHsaHseAfterVsVe>
- <DSILowPowerModeInHFP>False</DSILowPowerModeInHFP>
- <DSILowPowerModeInHBP>False</DSILowPowerModeInHBP>
- <DSILowPowerModeInHSA>False</DSILowPowerModeInHSA>
- <DSILowPowerModeInBLLPEOF>True</DSILowPowerModeInBLLPEOF>
- <DSILowPowerModeInBLLP>True</DSILowPowerModeInBLLP>
- <DSIRefreshRate>0x3C0000</DSIRefreshRate>
- <DSIPhyDCDCMode>True</DSIPhyDCDCMode>
- <DSIInitMasterTime>128</DSIInitMasterTime>
- <DSIControllerMapping>
- 00 01
- </DSIControllerMapping>
-</Group>
-<DSIInitSequence>
- 39 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97
- 39 92 10 f0
- 15 90 03
- 15 03 01
- 39 f0 55 aa 52 08 04
- 15 c0 03
- 39 f0 55 aa 52 08 07
- 15 ef 01
- 39 f0 55 aa 52 08 00
- 15 b4 10
- 15 35 00
- 39 f0 55 aa 52 08 01
- 39 ff aa 55 a5 80
- 15 6f 01
- 15 f3 10
- 39 ff aa 55 a5 00
- 05 11
- ff 78
- 05 29
- ff 78
-</DSIInitSequence>
-<DSITermSequence>
- 05 28 00
- FF 20
- 05 10 00
- FF 80
-</DSITermSequence>
-<Group id='Connection Configuration'>
- <Display1Reset1Info>DSI_PANEL_RESET, 0, 30</Display1Reset1Info>
- <Display1Power1Info>DSI_PANEL_MODE_SELECT, 0, 0, 0, 0, TRUE</Display1Power1Info>
-</Group>
-<Group id='Backlight Configuration'>
- <BacklightType>1</BacklightType>
- <BacklightPmicControlType>2</BacklightPmicControlType>
- <BacklightSteps>100</BacklightSteps>
- <BacklightPMICBankSelect>3</BacklightPMICBankSelect>
- <BacklightPMICPWMFrequency>800000</BacklightPMICPWMFrequency>
- <BacklightSteps>100</BacklightSteps>
- <BacklightDefault>80</BacklightDefault>
- <BacklightLowPower>40</BacklightLowPower>
- <PMIPowerPmicNum>1</PMIPowerPmicNum>
- <PMIPowerPmicModel>21</PMIPowerPmicModel>
- <PMIPowerConfig>1</PMIPowerConfig>
- <AdaptiveBrightnessFeature>1</AdaptiveBrightnessFeature>
- <CABLEnable>True</CABLEnable>
- <BrightnessMinLuminance>200</BrightnessMinLuminance>
- <BrightnessMaxLuminance>319970</BrightnessMaxLuminance>
-</Group>
-<Group id='AD Configuration'>
- <ADMaxIterations>30</ADMaxIterations>
- <ADInitParam001>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam001>
- <ADInitParam002>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam002>
- <ADInitParam003>0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x87FF 0x8FFF 0x97FF 0x9FFF 0xA7FF 0xAFFF 0xB7FF 0xBFFF 0xC7FF 0xCFFF 0xD7FF 0xDFFF 0xE7FF 0xEFFF 0xF7FF 0xFFFF </ADInitParam003>
- <ADInitParam004>0x0000 0x0800 0x1000 0x1801 0x1D61 0x22F2 0x26A2 0x2993 0x2C23 0x2E94 0x3114 0x33A5 0x3685 0x39C6 0x3D66 0x4177 0x45E7 0x4AE8 0x5058 0x5669 0x5D29 0x648A 0x6CAA 0x759B 0x7F7B 0x8A5C 0x965C 0xA3AD 0xB25D 0xC2BE 0xD4EE 0xE93F 0xFFFF </ADInitParam004>
- <ADInitParam005>0x0001 0x0032 0x0064 0x0096 0x00FA 0x015E 0x0190 0x0384 0x04E2 0x0708 0x08FC 0x0BB8 0x1770 0x2EE0 0x5DC0 0xC350 0x04B0 0x2125 0x2EE0 0x3969 0x4A1E 0x57B2 0x5DC0 0x8CA0 0xA5BA 0xC6E0 0xE0CE 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF </ADInitParam005>
- <ADInitParam006>0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF 0x0000 0x000A 0x0019 0x0032 0x0064 0x00C8 0x0190 0x02BC 0x03E8 0x05DC 0x09C4 0x0FA0 0x1F40 0x3A98 0x7530 0xFFFF </ADInitParam006>
- <ADInitParam007>0x0000 0x0095 0x0128 0x01B9 0x0249 0x02D8 0x0365 0x03F1 0x047B 0x0504 0x058C 0x0612 0x0697 0x071A 0x079D 0x081E 0x089E 0x091C 0x099A 0x0A16 0x0A91 0x0B0B 0x0B83 0x0BFB 0x0C71 0x0CE7 0x0D5B 0x0DCE 0x0E41 0x0EB2 0x0F22 0x0F91 0x0FFF </ADInitParam007>
- <ADInitParam008>0x00FF 0x0116 0x012E 0x0146 0x015E 0x0176 0x018E 0x01A6 0x01BE 0x01D6 0x01EE 0x0205 0x021D 0x0235 0x024D 0x0265 0x027D 0x0295 0x02AC 0x02C4 0x02DC 0x02F3 0x030B 0x0323 0x033A 0x0352 0x036A 0x0381 0x0399 0x03B1 0x03C8 0x03E0 0x03F8 </ADInitParam008>
- <ADInitParam009>0x03</ADInitParam009>
- <ADInitParam010>0x3F</ADInitParam010>
- <ADInitParam011>0x0780</ADInitParam011>
- <ADInitParam012>0x0438</ADInitParam012>
- <ADInitParam013>0x0002</ADInitParam013>
- <ADInitParam014>0x0002</ADInitParam014>
- <ADInitParam015>0xFFFF</ADInitParam015>
- <ADInitParam016>0x06</ADInitParam016>
- <ADInitParam017>0x030</ADInitParam017>
- <ADInitParam018>0x012</ADInitParam018>
- <ADInitParam019>0x044</ADInitParam019>
- <ADInitParam020>0xFFFF</ADInitParam020>
- <ADInitParam021>0x80</ADInitParam021>
- <ADInitParam022>0x80</ADInitParam022>
- <ADInitParam023>0x07AE</ADInitParam023>
- <ADInitParam024>0x0800</ADInitParam024>
- <ADInitParam025>0x0333</ADInitParam025>
- <ADInitParam026>0x0800</ADInitParam026>
- <ADInitParam027>0x0333</ADInitParam027>
- <ADInitParam028>0x0006</ADInitParam028>
- <ADInitParam029>0x0222</ADInitParam029>
- <ADInitParam030>0x1000</ADInitParam030>
- <ADInitParam031>0x012C</ADInitParam031>
- <ADInitParam032>0x0BB8</ADInitParam032>
- <ADInitParam033>0x1DB0</ADInitParam033>
- <ADInitParam034>0xFFFF</ADInitParam034>
- <ADInitParam035>0xFFFF</ADInitParam035>
- <ADInitParam036>0x10</ADInitParam036>
- <ADInitParam037>0x00</ADInitParam037>
- <ADInitParam038>0x10</ADInitParam038>
- <ADInitParam039>0x00</ADInitParam039>
- <ADInitParam040>0xFFFF</ADInitParam040>
- <ADInitParam041>0x10</ADInitParam041>
- <ADInitParam042>0x1000</ADInitParam042>
- <ADInitParam043>0x10</ADInitParam043>
- <ADInitParam044>0x0200</ADInitParam044>
- <ADInitParam045>0x0080</ADInitParam045>
- <ADInitParam046>0x0</ADInitParam046>
- <ADInitParam047>0xFF</ADInitParam047>
- <ADInitParam048>0x07</ADInitParam048>
- <ADInitParam049>0xC6</ADInitParam049>
- <ADInitParam050>0x41</ADInitParam050>
- <ADInitParam051>0x3C</ADInitParam051>
- <ADInitParam052>0x80</ADInitParam052>
- <ADInitParam053>0x000</ADInitParam053>
- <ADInitParam054>0x3FF</ADInitParam054>
- <ADInitParam055>0xF0</ADInitParam055>
- <ADInitParam056>0x00</ADInitParam056>
- <ADInitParam057>0x01</ADInitParam057>
- <ADInitParam058>0x2</ADInitParam058>
- <ADInitParam059>0x05</ADInitParam059>
- <ADInitParam060>0x00</ADInitParam060>
- <ADInitParam061>0x00</ADInitParam061>
- <ADInitParam062>0x003</ADInitParam062>
- <ADInitParam063>0x001</ADInitParam063>
- <ADInitParam064>0x001</ADInitParam064>
- <ADInitParam065>0x3FF</ADInitParam065>
- <ADInitParam066>0x08</ADInitParam066>
- <ADInitParam067>0x08</ADInitParam067>
- <ADInitParam068>0x13</ADInitParam068>
- <ADInitParam069>0x0000</ADInitParam069>
- <ADInitParam070>0x001</ADInitParam070>
- <ADInitParam071>0x00C</ADInitParam071>
- <ADInitParam072>0x050</ADInitParam072>
- <ADInitParam073>0x80</ADInitParam073>
- <ADInitParam074>0x040</ADInitParam074>
- <ADInitParam075>0x008</ADInitParam075>
-
- <ADCfgParam001>0x0000</ADCfgParam001>
- <ADCfgParam002>0xFFFF</ADCfgParam002>
- <ADCfgParam003>0x0000</ADCfgParam003>
- <ADCfgParam004>0xFFFF</ADCfgParam004>
- <ADCfgParam005>0x86</ADCfgParam005>
- <ADCfgParam006>0x10</ADCfgParam006>
- <ADCfgParam007>0x80</ADCfgParam007>
- <ADCfgParam008>0x54</ADCfgParam008>
- <ADCfgParam009>0x200</ADCfgParam009>
- <ADCfgParam010>0x500</ADCfgParam010>
- <ADCfgParam011>0x0400</ADCfgParam011>
- <ADCfgParam012>0x0400</ADCfgParam012>
- <ADCfgParam013>0x80</ADCfgParam013>
- <ADCfgParam014>0x5025</ADCfgParam014>
- <ADCfgParam015>0x0000</ADCfgParam015>
- <ADCfgParam016>0x200</ADCfgParam016>
- <ADCfgParam017>0x0020</ADCfgParam017>
- <ADCfgParam018>0x0222</ADCfgParam018>
- <ADCfgParam019>0x0400</ADCfgParam019>
- <ADCfgParam020>0x0400</ADCfgParam020>
- <ADCfgParam021>0x0001</ADCfgParam021>
- <ADCfgParam022>0x0222</ADCfgParam022>
- <ADCfgParam023>0x0400</ADCfgParam023>
- <ADCfgParam024>0x1000</ADCfgParam024>
- <ADCfgParam025>0x0018</ADCfgParam025>
- <ADCfgParam026>0x005F</ADCfgParam026>
- <ADCfgParam027>0x0008</ADCfgParam027>
- <ADCfgParam028>0x0000</ADCfgParam028>
- <ADCfgParam029>0x0000</ADCfgParam029>
- <ADCfgParam030>0x0010</ADCfgParam030>
- <ADCfgParam031>0x080</ADCfgParam031>
- <ADCfgParam032>0x200</ADCfgParam032>
- <ADCfgParam033>0x80</ADCfgParam033>
- <ADCfgParam034>0x0020</ADCfgParam034>
- <ADCfgParam035>0x022</ADCfgParam035>
- <ADCfgParam036>0x600</ADCfgParam036>
- <ADCfgParam037>0x310</ADCfgParam037>
- <ADCfgParam038>0x80</ADCfgParam038>
- <ADCfgParam039>0x30</ADCfgParam039>
- <ADCfgParam040>0x19A</ADCfgParam040>
- <ADCfgParam041>0x03</ADCfgParam041>
- <ADCfgParam042>0x200</ADCfgParam042>
- <ADCfgParam043>0x200</ADCfgParam043>
- <ADCfgParam044>0x80</ADCfgParam044>
- <ADCfgParam045>0x90</ADCfgParam045>
- <ADCfgParam046>0x2000</ADCfgParam046>
-</Group>"})
+++ /dev/null
-//
-// This file contains the Power Management IC (PMIC)
-// ACPI device definitions, configuration and look-up tables.
-//
-
-Include("cust_pmic_batt.asl")
-
- // PMIC EIC (Might be external charging chip on i2c)
- //Device (PEIC)
- //{
- // Name (_HID, "QCOM02D3")
- // Alias(\_SB.PSUB, _SUB)
- // Method (_CRS, 0x0, NotSerialized) {
- // Name (RBUF, ResourceTemplate () {
- // // SMB1380
- // I2CSerialBus( 0x08, , 400000,AddressingMode7Bit, "\\_SB.IC11",,,,)
- // })
- // Return (RBUF)
- // }
- // Method (PMCF) {
- // Name (CFG0,
- // Package(){
- // //Charger Info
- // 0, // I2c Index - Resource Index
- // 2, // Charger IC Type - PLAT_CONFIG_CHG_IC_SMB1380
- // })
- // Return (CFG0)
- // }
- //
- // Method (_STA) {
- // Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager
- // }
- //}
-
- //
- // PMIC Battery Manger Driver
- //
- Device (PMBT) {
- Name (_HID, "QCOM0264")
- Alias(\_SB.PSUB, _SUB)
- Name (_DEP, Package(0x2) {
- \_SB_.PMIC,
- \_SB_.ADC1,
- //\_SB_.PEIC
- })
-
- Method (_STA) {
- Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager
- }
-
- Method (_CRS, 0x0, NotSerialized) {
- Name (RBUF, ResourceTemplate ()
- {
- //GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,) {208} // 0x80 - PM_INT__SCHG_CHGR__CHGR_ERROR_RT_STS - Charger Error Interrupt
- //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {336} // 0x210 - PM_INT__FG_BCL__IBT_HI - IBAT greater than threshold Interrupt.
- //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {337} // 0x211 - PM_INT__FG_BCL__IBT_THI - VBatt less than threshold Interrupt
- //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {352} // 0x220 - PM_INT__FG_MEM_IF__IMA_RDY - MEMIF access Interrupt
- //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {215} // 0x87 - PM_INT__SCHG_CHGR__CHGR_7 - Termination Current Interrupt
- //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {209} // 0x81 - PM_INT__SCHG_CHGR__CHARGING_STATE_CHANGE - Charger Inhibit Interrupt
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {329} // 0x209 - PM_INT__FG_BATT_INFO__VBT_LOW - VBAT_LOW Interrupt
- //GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,) {240} // 0xA0 - PM_INT__SCHG_DC__DCIN_COLLAPSE - Qi Wireless Charger Interrupt
- GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {331} // 0x20B - PM_INT__FG_BATT_INFO__BT_MISS - BATT_MISSING Interrupt
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {237} // 0x9D - PM_INT__SCHG_USB__USBIN_SOURCE_CHANGE - AICL_DONE IRQ (Rising Only)
- //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {232} // 0x98 - PM_INT__SCHG_USB__USBIN_COLLAPSE - USB_UV IRQ (Rising Only)
- //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {322} // 0x202 - PM_INT__FG_BATT_SOC__BSOC_DELTA - FULL_SOC Interrupt
- //GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {323} // 0x203 - PM_INT__FG_BATT_SOC__MSOC_DELTA - EMPTY_SOC Interrupt
- // GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {213} // 0x85 - PM_INT__SCHG_CHGR__FG_FVCAL_QUALIFIED - FVCAL_QUALIFIED IRQ
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {224} // 0x90 - PM_INT__SCHG_BATIF__BAT_TEMP - Jeita limit interrupt
-
- })
- Return (RBUF)
- }
-
- //ACPI methods for Battery Manager Device
- Method (BMNR) {
- Name (CFG0,
- Package(){
- 1, //* 0: Select Platform: 0- No HW, 1- SMChg+FGGge, 2- SMB3pChg+SMB3pGge, 3- LBChg+VMBMS
- 0, //* 1: Error State Handling: 0- Don�t Shutdown, 1- Shutdown
- 1, //* 2: Listen to BatteryClass: 0- No 1- Yes
- 0, //* 3: Test Mode Power Flag: 0- Discharging, 1- PowerOnline+Charging
- "CUST_PMIC" //* 4: cust_pmic config identifier
- })
- Store(CUST, Index(CFG0, 4))
- Return (CFG0)
- }
-
- //ACPI methods for Timer
- Method (BTIM) {
- Name (CFG0,
- Package(){
- 30000, // Charging Heartbeat Timer
- 10000, // Charging Tolerable Delay
- 300000, // Discharging Heartbeat Timer
- 120000, // Discharging Tolerable Delay
- 0, // Poll Timer , 0=Timer not used.
- 0, // Poll Tolerable Delay
- 28080000, // Charging Timeout (TDone) Timer
- 0, // Charging Timeout(TDone) Tolerable Delay
- })
- Return (CFG0)
- }
-
-
- //ACPI methods for Battery Info
- Method (BBAT) {
- Name (CFG0,
- Package(){
- 1, //* 0: Battery Technology
- 0x4C494F4E, //* 1: Battery Chemistry: hex(LION)
- 0xFFFFFFFF, //* 2: BFCC: (mWh), Design Capacity
- 0xFFFFFFFF, //* 3: BFCC: (mWh), Full Charge Capacity
- 0xFFFFFFFF, //* 4: PCT1: (% of FCC), Default Alert 1
- 0xFFFFFFFF, //* 5: PCT2: (% of FCC), Default Alert 2
- "QCOMBATT01", //* 6: Device Name
- "Qualcomm", //* 7: Manufacture Name
- "QCOMBAT01_07012011", //* 8: Battery Unique ID
- "07012011", //* 9: Battery Serial Number
- 19, //* 10: Battery Manufacture Date
- 04, //* 11: Battery Manufacture Month
- 2014 //* 12: Battery Manufacture Year
- })
- //Local2 = Default Alert1 = PCT1 * BFCC / 100
- Multiply(PCT1,BFCC,Local0)
- Divide(Local0, 100, Local1, Local2)
- //Local3 = Default Alert2 = PCT2 * BFCC / 100
- Multiply(PCT2,BFCC,Local0)
- Divide(Local0, 100, Local1, Local3)
- Store(BFCC, Index(CFG0, 2))
- Store(BFCC, Index(CFG0, 3))
- Store(Local2, Index(CFG0, 4))
- Store(Local3, Index(CFG0, 5))
- Return (CFG0)
- }
-
- //ACPI methods for Proprietary chargers
- Method (BPCH) {
- Name (CFG0,
- Package(){
- 3000, // QC2.0 charger current = 3000mA
- 3000, // QC3.0 charger current = 3000mA
- 1500 // Invalid Wall charger current = 1500mA
- })
- Return (CFG0)
- }
-
- //ACPI methods for foldback chargers
- Method (BFCH) {
- Name (CFG0,
- Package(){
- 1, // Feature enable/disable
- 5, // No of consecutive times charger attach/detach
- 5000, // msecs, Time elapsed between attach/detach
- 900, // mA, Current setting for foldback charger
- })
- Return (CFG0)
- }
-
- //ACPI methods for coin cell charger
- Method (BCCC) {
- Name (CFG0,
- Package(){
- 1, //Enable coin cell charger; 1 = enable, 0 = disable
- 0, // RSET, 0=2K1, 1=1K7, 2=1K2, 3 = 0K8
- 0 // VSET, 0=2V5, 1=3V2, 2=3V1, 3=3V0
- })
- Return (CFG0)
- }
-
- //ACPI methods for Recharge/Maintenance Mode
- Method (BRCH) {
- Name (CFG0,
- Package(){
- 100, // Delta V Recharge threshold = 100mV
- 0 // Delta V Recharge Reduction below Normal= 0mV
- })
- Return (CFG0)
- }
-
- //ACPI methods for Qi Charging
- Method (_BQI) {
- Name (CFG0,
- Package(){
- 0,
- })
- Return (CFG0)
- }
-
- //ACPI methods for Interrupt Name
- Method (BIRQ) {
- Name (CFG0,
- Package(){
- //"ChgError", // Charger Error
- //"BclIrq1", // IBAT greater than threshold IRQ
- //"BclIrq2", // VBAT less than threshold IRQ
- //"MEMIFaccess", // MEMIF access granted IRQ
- //"TccReached", // Termination Current IRQ
- //"ChargerInhibit" // Charger Inhibit IRQ
- "VbatLow", // VBAT LOW IRQ
- //"QiWlcDet", // Qi charging
- "BattMissing", // BATT_MISSING IRQ
- "AiclDone", // AICL Done
- //"UsbUv", // USB UV
- //"SOCFull", // SOC Full IRQ
- //"SOCEmpty", // SOC Empty IRQ
- //"FvCal", // FVCAl IRQ
- "JeitaLimit" // JEITA limit IRQ
- })
- Return (CFG0)
- }
- //ACPI methods for Platform File
- Method (BPLT) {
- Name (CFG0,
- Package(){
- 1024, //* 0: ACPI Version
- 0xFFFFFFFF, //* 1: VNOM: (mV), Nominal Battery Voltage
- 0xFFFFFFFF, //* 2: VLOW: (mV), Low Battery Voltage
- 0xFFFFFFFF, //* 3: EMPT: (mV), VcutOff
- 0xFFFFFFFF, //* 4: DCMA: (mA), DC Current
- 1, //* 5: ChargePath Priority: Select 0 for DC, 1 for USB
- 50, //* 6: RSLOW for maxFlashCurrentPrediction
- 50, //* 7: RPARA for maxFlashCurrentPrediction
- 5000, //* 8: VINFLASH for maxFlashCurrentPrediction
- 8, //* 9: FlashParam for maxFlashCurrentPrediction
- 1, //* 10: AFP Mode Supported
- 80, //* 11: AFP Trigger Max Battery Temp (+80 deg C)
- 0xFFFFFFEC, //* 12: AFP Trigger Min Battery Temp (-20 deg C)
- 72, //* 13: Watchdog timer in secs
- 100, //* 14: Charger iterm 100 mA for now
- 30, //* 15: SRAM logging timer
- 5, //* 16: VBATT average Window Size
- 6, //* 17: Emergency Shutdown Initial SOC
- 500, //* 18: SoC convergent point
- 126, //* 19: LM_Threshold
- 400, //* 20: MH_Threshold
- 0xFFFFFFFF, //* 21: BOCP: (mA), OCP current used in BCL
- 750, //* 22: soc (75%) below which no soc linearization even in CV charging
- 1, //* 23: BMD - Battery Missing Detection Source when source is attached: BATT_ID (1=BATT_ID, 4=HW Misssing Algorithm)
- 2, //* 24: ibat src sensing : 0 for batfet and 1 for external sensing
- 50, //* 25: IFGD: (mA), FG Iterm delta; (iterm + this value) determines when FG report 100%
- 10, //* 26: VFGD: (mV), CC to CV Vdelta; (Vfloat - this value) determine when FG report 100%
- 1, //* 27: 0 - disable SOC linearization; 1 (nonzero): enable SOC linearization
- 0xFFFFFFEC, //* 28: (Celcius), Temperature threshold do have different SOC slope limiter
- 10, //* 29: (milli%) - SOC slope limiter when charging and at lower temperature than threshold
- 10, //* 30: (milli%) - SOC slope limiter when charging and at higher temperature than threshold
- 10, //* 31: (milli%) - SOC slope limiter when discharging and at lower temperature than threshold
- 10, //* 32: (milli%) - SOC slope limiter when discharging and at higher temperature than threshold
- 1, //* 33: 0 - disable FCC learning; 1 (nonzero): enable FCC leearning
- 150, //* 34: maximum starting SOC (in tenth percent)at which FCC learning would be turned on during charging
- 100, //* 35: maximum allowable decrement (in tenth percent) of battery capacity in FCC learning
- 5, //* 36: maximum allowable increment (in tenth percent) of battery capacity in FCC learning
- 10, //* 37: battery temperature in degree C below which switch to low temp ESR update steps
- 0x02, //* 38: ESR update step tight, (2 * 0.001953 = 0.0039 = 0.4% max change each update)
- 0x33, //* 39: ESR update step broad, (51* 0.001953 = 0.099603 = 10% max change each update)
- 0x02, //* 40: ESR update step tight at low temp (below 10 degree, 0.4% max change each update)
- 0x0A, //* 41: ESR update step broad at low temp (below 10 degree, 2% max change each update)
- 0, //* 42: mOhm, RConn
- 0, //* 43: Type C Thermal Mitigation Enable
- 70, //* 44: Temperature to arm mitigation (degree C)
- 50, //* 45: ICL adjustment (percent)
- 60 //* 46: Temperature to disarm mitigation (degree C)
- })
- Store(VNOM, Index(CFG0, 1))
- Store(VLOW, Index(CFG0, 2))
- Store(EMPT, Index(CFG0, 3))
- Store(DCMA, Index(CFG0, 4))
- Store(BOCP, Index(CFG0, 21))
- Store(IFGD, Index(CFG0, 25))
- Store(VFGD, Index(CFG0, 26))
- Return (CFG0)
- }
-
- //ACPI methods for Platform File
- Method (BPTM) {
- Name (CFG0,
- Package(){
- 15000, // Emergency Timer
- 0, // Emergency Tolerable Delay
- })
- Return (CFG0)
- }
-
- //*****************************************************
- // Battery Charge Table 1 (BCT1)
- // Notes: used in Method(BJTA) & Method (BAT1)
- //*****************************************************
- Name (BCT1, Package(){
- 4350, //* 0: VDD1: (mV), Float Voltage (FV)
- 2100, //* 1: FCC1: (mA), Full Charge Current (FCC)
- 0, //* 2: HCLI: (C) hard cold limit - at which temperature charging will be disabled
- 10, //* 3: SCLI: (C) soft cold limit - at which temperature charge current/float voltage will be reduced to JEITA compensated value
- 45, //* 4: SHLI: (C) soft hot limit - at which temperature float voltage/charge current will be reduced to JEITA compensated value
- 55, //* 5: HHLI: (C) hard hot limit - at which temperature charging will be disabled
- 105, //* 6: FVC1: (mV) Float Voltage compensation (amount of FV reduction) when in battery hot-soft limit
- 0, //* 7: (mV) Float Voltage compensation (amount of FV reduction) when in battery cold-soft limit
- //* notes: put 0 value to disable
- //* These values (10 vs 11) should be the same when HW JEITA is enabled
- 0, //* 8: (mA) Charge Current compensation (amount of CC reduction) when in battery hot-soft limit
- 1000, //* 9: CCC1: (mA) Charge Current compensation (amount of CC reduction) when in battery cold-soft limit
- //* notes: put 0 value to disable
- //* These values (12 vs 13) should be the same when HW JEITA is enabled
- })
-
- //ACPI methods for JEITA
- Method (BJTA) {
- Name (CFG0,
- Package(){
- 2, //* 0: Select JEITA Configuration: 0- No JEITA, 1- SW JEITA, 2- HW JEITA
- 2, //* 1: Temperature Hysteresis (in deg C)
- Package(0xa){0,0,0,0,0,0,0,0,0,0}
- //* 2: Structure for default charge table
- })
- Store(VDD1, Index(\_SB_.PMBT.BCT1, 0))
- Store(FCC1, Index(\_SB_.PMBT.BCT1, 1))
- Store(HCLI, Index(\_SB_.PMBT.BCT1, 2))
- Store(SCLI, Index(\_SB_.PMBT.BCT1, 3))
- Store(SHLI, Index(\_SB_.PMBT.BCT1, 4))
- Store(HHLI, Index(\_SB_.PMBT.BCT1, 5))
- Store(FVC1, Index(\_SB_.PMBT.BCT1, 6))
- Store(CCC1, Index(\_SB_.PMBT.BCT1, 9))
-
- //Use BCT1 as the Default Charge Table
- Store(\_SB_.PMBT.BCT1, Index(CFG0, 2))
- Return (CFG0)
- }
-
- //ACPI methods for Battery-1 (Ascent 860-82209-0000 3450mAh)
- Method (BAT1)
- {
- Name (CFG0,
- Package(){
- 0, //* 0: Battery Category: 0-NORMAL, 1-SMART
- 0xFFFFFFEC, //* 1: min operating battery temp (-20 deg C)
- 65, //* 2: max operating battery temp (+65 deg C)
- Package(4){0,0,0,0}, //* 3: 128-bit battery info for future expansion
- Package(0xa){0,0,0,0,0,0,0,0,0,0}
- //* 4: Structure for charge table
- })
-
- //assign Charge Table to BCT1
- //Notes: 1) If the default charge table and desire charge table are different,
- // Create another table (ex: BCT2) with the same structure as BCT1 and modify BCT1 below with the new table name
- // 2) Method(BJTA) is parsed before this(BAT1) method in Battmngr module
- // Method(BJTA) may be updating BCT1 parameters using configuration from cust_pmic_batt.asl (refer to BJTA method details)
- // If BAT1 desires different value to be used (than what used in BJTA), pls change/update relevant parameter(s) here.
- Store(\_SB_.PMBT.BCT1, Index(CFG0, 4))
-
- Return (CFG0)
- }
-
- //ACPI methods for Battery Error Handling
- Method (BEHC)
- {
- //Actions for Battery Error Handling
- // 0x0 - Do Nothing
- // 0x1 - Reload Charge Table
- // 0x2 - Error Shutdown
- // 0x4 - Emergency Shutdown
- // 0x8 - Enter Test Mode
- Name (CFG0,
- Package(){
- 1, // 1-Feature Enable, 0-Feature Disable
- 0x8, //Action(s) for DEBUG state -> Enter Test Mode
- 0x1, //Action(s) for NORMAL state -> Reload Charge Table
- 0x0, //Action(s) for SMART_AUTHENTICATED state -> Do nothing
- 0x0, //Action(s) for UNKNOWN state -> Do nothing
- 0x2, //Action(s) for NOT_PRESENT state -> Error Shutdown
- 0x2, //Action(s) for INVALID state -> Error Shutdown
- 0x4 //Action(s) for OUT_OP_RANGE state -> AFP for out of operational range
- })
- Return (CFG0)
- }
-
- //ACPI methods for Charge Table Management Configuration
- Method (CTMC)
- {
- Name (CFG0,
- Package(){
- 2000, //* 0: min RID for DEBUG category: 2K
- 14000, //* 1: max RID for DEBUG category: 14K
- 0xFFFFFFFF, //* 2: RID2: min RID for NORMAL category: 15K
- 0xFFFFFFFF, //* 3: RID3: max RID for NORMAL category: 140K
- 240000, //* 4: min RID for SMART category: 240K
- 450000, //* 5: max RID for SMART category: 450K
- 1, //* 6: Number of charging table
- })
- Store(RID2, Index(CFG0, 2))
- Store(RID3, Index(CFG0, 3))
- Return (CFG0)
- }
-
- //ACPI methods for Parallel Charging
- Method (BMPC) {
- Name (CFG0,
- Package(){
- 0, //* 0: Feaature Enable. 1: Enabled, 0: Disable
- 1, //* 1: Input Power Disctribution (HW) configuration: 0: MID-MID, 1: USBIN-USBIN
- 7000, //* 2: (mW) Input Power Threshold to decide if parallel charging to be enabled or not
- //* Note: Not applicable for MID-MID configuration
- 1000, //* 3: (mA) Charge Current Threshold to decide if parallel charging to be enabled or not
- 50, //* 4: (%) Slave Charger Initial Power Distribution
- 60, //* 5: (mV) Slave Charger Float Voltage Headroom
- 500, //* 6: (mA) Slave Charger Charge Current Done Threshold
- 90, //* 7: Slave Charger Minimum Efficiency
- 0, //* 8: Slave Charger HW ID. 0: SMB1380/1
- 70, //* 9: (%)Slave Charger Max Power Distribution: 70%
- 0, //* 10: (%)Slave Charger Min Power Distribution: 0%
- Package(0x4)//* 11: Thermal Balancing Configuration
- {
- 5, //11.1: (C)Temperature Difference to trigger thermal balancing. 0 to disable the feature
- 5, //11.2: (%)Step to redistrubute the power
- 120, //11.3: (Sec)Minimum Wait Time for each redistribution attempt
- 5, //11.4: (C)Temperature Margin for Master Charger
- }
- })
- Return (CFG0)
- }
- }
-
- //
- // PMIC Battery Miniclass Driver
- //
- Device (PMBM) {
- Name (_HID, "QCOM0263")
- Alias(\_SB.PSUB, _SUB)
- Name (_DEP, Package(0x1)
- {
- \_SB_.PMBT
- })
-
- Method (_CRS, 0x0, NotSerialized) {
- Name (RBUF, ResourceTemplate () {
- })
- Return (RBUF)
- }
-
- Method (_STA) {
- Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager
- }
- }
-
-//
-//FGBCL Driver
-//
-Device (BCL1) {
- Name (_HID, "QCOM02D6")
- Alias(\_SB.PSUB, _SUB)
- Name (_DEP, Package(0x1)
- {
- \_SB_.PMIC
- })
-
- Method (_STA) {
- Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager
- }
-
- Method (_CRS, 0x0, NotSerialized) {
- Name (RBUF, ResourceTemplate () {
- GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {64} // 0x1E8 - PM_INT__BCL_COMP__VCOMP_LOW0 - VCOMP_LOW0 IRQ
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {65} // 0x1E9 - PM_INT__BCL_COMP__VCOMP_LOW1 - VCOMP_LOW1 IRQ
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {66} // 0x1EA - PM_INT__BCL_COMP__VCOMP_LOW2 - VCOMP_LOW2 IRQ
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {67} // 0x1EB - PM_INT__BCL_COMP__VCOMP_HI - VCOMP_HI IRQ
- //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {68} // 0x1EC - PM_INT__BCL_COMP__SYS_OK - SYS_OK IRQ
- //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {72} // 0x1F0 - PM_INT__BCL_PLM__VCOMP_LVL0_PLM - LVL0_PLM IRQ
- //GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {74} // 0x1F2 -PM_INT__BCL_PLM__VCOMP_LVL2_PLM - LVL2_PLM IRQ
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {75} // 0x1F3 - PM_INT__BCL_PLM__VCOMP_BA - BAN alarm IRQ
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {336} // 0x210 - PM_INT__FG_BCL__IBT_HI - ibatt high IRQ
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {337} // 0x211 - PM_INT__FG_BCL__IBT_THI - ibatt too high IRQ
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {339} // 0x213 - PM_INT__FG_BCL__VBT_LO_CMP - vbatt low irq
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {340} // 0x214 - PM_INT__FG_BCL__VBT_TLO_CMP - vbatt too low irq
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {324} // 0x204 - PM_INT__FG_BATT_SOC__MSOC_LOW - MSOC_Low Interrupt
- GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {326} // 0x206 - PM_INT__FG_BATT_SOC__MSOC_HIGH - MSOC_HI Interrupt
- GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {344} // 0x218 - PM_INT__FG_LMH__LMH_LVL0 - LMH_LVL0 IRQ
- GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {345} // 0x219 - PM_INT__FG_LMH__LMH_LVL1 - LMH_LVL1 IRQ
- GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {346} // 0x21A - PM_INT__FG_LMH__LMH_LVL2 - LMH_LVL2 IRQ
-
- })
- Return (RBUF)
- }
- //ACPI methods for FGBCL device
- Method (BCLS) {
- Name (CFG0,
- Package(){
- 3, //* FGBCL ACPI revision
- 7, //* 0: BCL disabled, 1: vph_pwr bcl enabled, 2: fg vbatt enabled, 4: fg ibatt enabled
- 5000, //* battery ocp current
- 80, //* ibatt high threshold is set to 80 for 80% of OCP
- 90, //* ibatt too high is set to 90 for 90% of OCP
- 2800, //* vbatt low is set to 2800 mV
- 2600, //* vbatt too low is set to 2600 mV
- 3200, //* vcomp_low0 threshold is 3200 mv
- 2750, //* vcomp_low1 threshold is 2750 mv
- 2500, //* vcomp_low2 threshold is 2500 mV
- 10, //* poll timer for battery soc polling.
- 1, //* 1- enable battery percent notification. 0-disable battery percent notification
- 2000, //* debug board Min battery ID in Ohm
- 14000 //* debug board Max battery ID in Ohm
- })
- Return (CFG0)
- }
- //ACPI methods for Interrupt Name
- Method (BCLQ) {
- Name (CFG0,
- Package(){
- "VCOMP_LOW0", // vcomp_low0 IRQ
- "VCOMP_LOW1", // vcomp_low1 IRQ
- "VCOMP_LOW2", // vcomp_low2 IRQ
- "VCOMP_HI", // vcomp_hi IRQ
- //"SYS_OK", // sys_ok irq
- //"LVL0_PLM", // LVL0_PLM IRQ
- //"LVL1_PLM" // LVL1_PLM IRQ
- //"LVL2_PLM", // LVL2_PLM IRQ
- "BAN_ALARM", // BAN_ALARM IRQ
- "IBATT_HI", // IBATT HIGH IRQ
- "IBATT_THI", // IBATT TOO HIGH IRQ
- "VBATT_LOW", // VBATT_LOW IRQ
- "VBATT_TLOW", // VBATT TOO LOW IRQ
- "MSOC_LOW", // monotonic soc low IRQ
- "MSOC_HI", // monotonic soc high IRQ
- "LMH_LVL0", // LMH_LVL0 IRQ
- "LMH_LVL1", // LMH_LVL1 IRQ
- "LMH_LVL2", // LMH_LVL2 IRQ
- })
- Return (CFG0)
- }
-}
-
-//
-//PMIC Type-C Controler Driver (PMICTCC) Driver
-//
-Device(PTCC)
-{
- Name (_HID, "QCOM02E6")
- Alias(\_SB.PSUB, _SUB)
- Name (_DEP, Package(0x1) {\_SB_.PMIC})
- Method (_CRS, 0x0, NotSerialized) {
- Name (RBUF, ResourceTemplate () {
- GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {239} // 0x9F - PM_INT__SCHG_USB__TYPE_C_OR_RID_DETECTION_CHANGE - CC State Changed IRQ
- GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {270} // 0xBE - PM_INT__USB_PD__MESSAGE_RX_DISCARDED - Message RX Discarded IRQ
- GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {269} // 0xBD - PM_INT__USB_PD__MESSAGE_TX_DISCARDED - Message TX Discarded IRQ
- GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {268} // 0xBC - PM_INT__USB_PD__MESSAGE_TX_FAILED - Message TX Failed IRQ
- GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {267} // 0xBB - PM_INT__USB_PD__MESSAGE_RECEIVED - Message Received IRQ
- GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {266} // 0xBA - PM_INT__USB_PD__MESSAGE_SENT - Message Sent IRQ
- GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {265} // 0xB9 - PM_INT__USB_PD__SIGNAL_RECEIVED - Singal Received IRQ
- GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {264} // 0xB8 - PM_INT__USB_PD__SIGNAL_SENT - Signal Sent IRQ
- GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {217} // 0x89 - PM_INT__SCHG_OTG__OTG_OVERCURRENT - OTG_OC_IRQ
- GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {263} // 0xB7 - PM_INT__SCHG_MISC__SWITCHER_POWER_OK - SWITCHER_POWER_OK (CHG_MISC)
- GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {235} // 0x9B - PM_INT__SCHG_USB__USBIN_OV - USBIN_OV (CHG_USB)
- // GpioIo (Exclusive, PullUp, 0, 0, , "\\_SB.PM01", , , , ) {493} // 0x668 - PM_INT__PM2_GPIO14__GPIO_IN_STS - GPIO14B � For Type-C Debug Accessory Mode
- })
- Return (RBUF)
- }
-}
+++ /dev/null
-/*
- * Intel ACPI Component Architecture
- * AML/ASL+ Disassembler version 20210604 (32-bit version)
- * Copyright (c) 2000 - 2021 Intel Corporation
- *
- * Disassembling to symbolic ASL+ operators
- *
- * Disassembly of H:/EDK/iasl20210604/xiaomi.aml, Mon Jul 26 23:03:46 2021
- *
- * Original Table Header:
- * Signature "DSDT"
- * Length 0x0003B9D8 (244184)
- * Revision 0x02
- * Checksum 0x33
- * OEM ID "QCOMM "
- * OEM Table ID "SDM850 "
- * OEM Revision 0x00000003 (3)
- * Compiler ID "INTL"
- * Compiler Version 0x20210604 (539035140)
- */
-DefinitionBlock ("", "DSDT", 2, "QCOMM ", "SDM850 ", 0x00000003)
-{
- External (_SB_.TZ98, UnknownObj)
- External (_SB_.TZ98._PSV, IntObj)
- External (_SB_.TZ98._TC1, IntObj)
- External (_SB_.TZ98._TC2, IntObj)
- External (_SB_.TZ98._TSP, IntObj)
- External (_SB_.TZ98.TPSV, UnknownObj)
- External (_SB_.TZ98.TTC1, UnknownObj)
- External (_SB_.TZ98.TTC2, UnknownObj)
- External (_SB_.TZ98.TTSP, UnknownObj)
- External (DPON, UnknownObj)
- External (TRUE, UnknownObj)
-
- Scope (_SB)
- {
- Name (PSUB, "RENEGA0E")
- Name (SOID, 0x015C)
- Name (SIDS, "SDM850")
- Name (SIDV, 0x00020001)
- Name (SVMJ, 0x02)
- Name (SVMI, One)
- Name (SDFE, 0x4F)
- Name (SFES, "899800000000000")
- Name (SIDM, 0x0000000FFFFF00FF)
- Name (SOSN, 0x000003F48D126594)
- Name (RMTB, 0x85D00000)
- Name (RMTX, 0x00200000)
- Name (RFMB, Zero)
- Name (RFMS, Zero)
- Name (RFAB, Zero)
- Name (RFAS, Zero)
- Name (TCMA, 0x8AB00000)
- Name (TCML, 0x01400000)
- Name (PRSI, Buffer (0x0E)
- {
- /* 0000 */ 0x53, 0x4F, 0x53, 0x49, 0x0E, 0x10, 0x72, 0x00, // SOSI..r.
- /* 0008 */ 0x86, 0x00, 0x00, 0x00, 0x00, 0x0B // ......
- })
- Name (MDID, 0x03)
- Device (UFS0)
- {
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PEP0
- })
- Name (_HID, "QCOM24A5") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_CID, "ACPIQCOM24A5") // _CID: Compatible ID
- Name (_UID, Zero) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x01D84000, // Address Base
- 0x00014000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000129,
- }
- })
- Return (RBUF) /* \_SB_.UFS0._CRS.RBUF */
- }
-
- Device (DEV0)
- {
- Method (_ADR, 0, NotSerialized) // _ADR: Address
- {
- Return (0x08)
- }
-
- Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
- {
- Return (Zero)
- }
- }
- }
-
- Device (SDC2)
- {
- Name (_DEP, Package (0x02) // _DEP: Dependencies
- {
- PEP0,
- GIO0
- })
- Name (_HID, "QCOM2466") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_CID, "ACPIQCOM2466") // _CID: Compatible ID
- Name (_UID, One) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x08804000, // Address Base
- 0x00001000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000000EC,
- }
- GpioInt (Edge, ActiveBoth, SharedAndWake, PullUp, 0x7530,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x00C0
- }
- GpioIo (Shared, PullUp, 0x0000, 0x0000, IoRestrictionNone,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x007E
- }
- })
- Return (RBUF) /* \_SB_.SDC2._CRS.RBUF */
- }
-
- Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
- {
- }
-
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
- }
-
- Device (ABD)
- {
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PEP0
- })
- Name (_HID, "QCOM0242") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0B)
- }
-
- OperationRegion (ROP1, GenericSerialBus, Zero, 0x0100)
- Name (AVBL, Zero)
- Method (_REG, 2, NotSerialized) // _REG: Region Availability
- {
- If ((Arg0 == 0x09))
- {
- AVBL = Arg1
- }
- }
- }
-
- Name (ESNL, 0x14)
- Name (DBFL, 0x17)
- Device (PMIC)
- {
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- SPMI
- })
- Name (_HID, "QCOM0266") // _HID: Hardware ID
- Name (_CID, "PNP0CA3") // _CID: Compatible ID
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0B)
- }
-
- Method (PMCF, 0, NotSerialized)
- {
- Name (CFG0, Package (0x04)
- {
- 0x03,
- Package (0x02)
- {
- Zero,
- One
- },
-
- Package (0x02)
- {
- 0x02,
- 0x03
- },
-
- Package (0x02)
- {
- 0x04,
- 0x05
- }
- })
- Return (CFG0) /* \_SB_.PMIC.PMCF.CFG0 */
- }
- }
-
- Device (PM01)
- {
- Name (_HID, "QCOM0269") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, One) // _UID: Unique ID
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PMIC
- })
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0B)
- }
-
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
- {
- 0x00000201,
- }
- })
- Return (RBUF) /* \_SB_.PM01._CRS.RBUF */
- }
-
- Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
- {
- While (One)
- {
- Name (_T_0, Buffer (One) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- {
- 0x00 // .
- })
- CopyObject (ToBuffer (Arg0), _T_0) /* \_SB_.PM01._DSM._T_0 */
- If ((_T_0 == ToUUID ("4f248f40-d5e2-499f-834c-27758ea1cd3f") /* GPIO Controller */))
- {
- While (One)
- {
- Name (_T_1, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_1 = ToInteger (Arg2)
- If ((_T_1 == Zero))
- {
- Return (Buffer (One)
- {
- 0x03 // .
- })
- }
- ElseIf ((_T_1 == One))
- {
- Return (Package (0x02)
- {
- Zero,
- One
- })
- }
- Else
- {
- }
-
- Break
- }
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
-
- Break
- }
- }
- }
-
- Device (PMAP)
- {
- Name (_HID, "QCOM0268") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_DEP, Package (0x03) // _DEP: Dependencies
- {
- PMIC,
- ABD,
- SCM0
- })
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0B)
- }
-
- Method (GEPT, 0, NotSerialized)
- {
- Name (BUFF, Buffer (0x04){})
- CreateByteField (BUFF, Zero, STAT)
- CreateWordField (BUFF, 0x02, DATA)
- DATA = 0x02
- Return (DATA) /* \_SB_.PMAP.GEPT.DATA */
- }
-
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, Buffer (0x02)
- {
- 0x79, 0x00 // y.
- })
- Return (RBUF) /* \_SB_.PMAP._CRS.RBUF */
- }
- }
-
- Device (PRTC)
- {
- Name (_HID, "ACPI000E" /* Time and Alarm Device */) // _HID: Hardware ID
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PMAP
- })
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0B)
- }
-
- Method (_GCP, 0, NotSerialized) // _GCP: Get Capabilities
- {
- Return (0x04)
- }
-
- Field (^ABD.ROP1, BufferAcc, NoLock, Preserve)
- {
- Connection (
- I2cSerialBusV2 (0x0002, ControllerInitiated, 0x00000000,
- AddressingMode7Bit, "\\_SB.ABD",
- 0x00, ResourceConsumer, , Exclusive,
- )
- ),
- AccessAs (BufferAcc, AttribRawBytes (0x18)),
- FLD0, 192
- }
-
- Method (_GRT, 0, NotSerialized) // _GRT: Get Real Time
- {
- Name (BUFF, Buffer (0x1A){})
- CreateField (BUFF, 0x10, 0x80, TME1)
- CreateField (BUFF, 0x90, 0x20, ACT1)
- CreateField (BUFF, 0xB0, 0x20, ACW1)
- BUFF = FLD0 /* \_SB_.PRTC.FLD0 */
- Return (TME1) /* \_SB_.PRTC._GRT.TME1 */
- }
-
- Method (_SRT, 1, NotSerialized) // _SRT: Set Real Time
- {
- Name (BUFF, Buffer (0x32){})
- CreateByteField (BUFF, Zero, STAT)
- CreateField (BUFF, 0x10, 0x80, TME1)
- CreateField (BUFF, 0x90, 0x20, ACT1)
- CreateField (BUFF, 0xB0, 0x20, ACW1)
- ACT1 = Zero
- TME1 = Arg0
- ACW1 = Zero
- BUFF = FLD0 = BUFF /* \_SB_.PRTC._SRT.BUFF */
- If ((STAT != Zero))
- {
- Return (One)
- }
-
- Return (Zero)
- }
- }
-
- Include("pmic_batt.asl")
-
- Device (PEP0)
- {
- Name (_HID, "QCOM0237") // _HID: Hardware ID
- Name (_CID, "PNP0D80" /* Windows-compatible System Power Management Controller */) // _CID: Compatible ID
- Include("thz.asl")
-
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Return (ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, ,, )
- {
- 0x0000021A,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, ,, )
- {
- 0x0000021C,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, ,, )
- {
- 0x0000021B,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, ,, )
- {
- 0x0000021D,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000025,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000000A1,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000001A5,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000040,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000041,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000265,
- }
- })
- }
-
- Field (^ABD.ROP1, BufferAcc, NoLock, Preserve)
- {
- Connection (
- I2cSerialBusV2 (0x0001, ControllerInitiated, 0x00000000,
- AddressingMode7Bit, "\\_SB.ABD",
- 0x00, ResourceConsumer, , Exclusive,
- )
- ),
- AccessAs (BufferAcc, AttribRawBytes (0x15)),
- FLD0, 168
- }
-
- Method (GEPT, 0, NotSerialized)
- {
- Name (BUFF, Buffer (0x04){})
- CreateByteField (BUFF, Zero, STAT)
- CreateWordField (BUFF, 0x02, DATA)
- DATA = One
- Return (DATA) /* \_SB_.PEP0.GEPT.DATA */
- }
-
- Name (ROST, Zero)
- Method (NPUR, 1, NotSerialized)
- {
- ^^AGR0._PUR [One] = Arg0
- Notify (AGR0, 0x80) // Status Change
- }
-
- Method (INTR, 0, NotSerialized)
- {
- Name (RBUF, Package (0x18)
- {
- 0x02,
- One,
- 0x03,
- One,
- 0x06,
- 0x17911008,
- One,
- Zero,
- 0x86000000,
- 0x00200000,
- Zero,
- Zero,
- 0x0C300000,
- 0x1000,
- Zero,
- Zero,
- 0x01FD4000,
- 0x08,
- Zero,
- Zero,
- 0x1799000C,
- Zero,
- Zero,
- Zero
- })
- Return (RBUF) /* \_SB_.PEP0.INTR.RBUF */
- }
-
- Method (CRTC, 0, NotSerialized)
- {
- Return (CTRX) /* \_SB_.PEP0.CTRX */
- }
-
- Name (CTRX, Package (0x0B)
- {
- "NSTC",
- "HLCB",
- "MMVD",
- "DSGP",
- "CCGP",
- "MTPS",
- "CPGP",
- "DMPP",
- "VRDL",
- "GBDL",
- "SRDL"
- })
- Method (STND, 0, NotSerialized)
- {
- Return (STNX) /* \_SB_.PEP0.STNX */
- }
-
- Name (STNX, Package (0x19)
- {
- "DMPO",
- "DMSB",
- "DMQP",
- "DMMS",
- "DMPA",
- "DMPC",
- "DMPB",
- "DM0G",
- "DM1G",
- "DM2G",
- "DM3G",
- "DM4G",
- "DM5G",
- "DM6G",
- "DM7G",
- "DM8G",
- "DM9G",
- "DMPS",
- "DMPL",
- "DMDQ",
- "DMPI",
- "DMWE",
- "XMPC",
- "XMPL",
- "DMEP"
- })
- Method (CTPM, 0, NotSerialized)
- {
- Name (CTPN, Package (0x02)
- {
- "CORE_TOPOLOGY",
- 0x08
- })
- Return (CTPN) /* \_SB_.PEP0.CTPM.CTPN */
- }
-
- Name (CCFG, Package (0x08)
- {
- Package (0x02)
- {
- "\\_SB.SYSM.CLUS.CPU0",
- 0x10
- },
-
- Package (0x02)
- {
- "\\_SB.SYSM.CLUS.CPU1",
- 0x11
- },
-
- Package (0x02)
- {
- "\\_SB.SYSM.CLUS.CPU2",
- 0x12
- },
-
- Package (0x02)
- {
- "\\_SB.SYSM.CLUS.CPU3",
- 0x13
- },
-
- Package (0x02)
- {
- "\\_SB.SYSM.CLUS.CPU4",
- 0x14
- },
-
- Package (0x02)
- {
- "\\_SB.SYSM.CLUS.CPU5",
- 0x15
- },
-
- Package (0x02)
- {
- "\\_SB.SYSM.CLUS.CPU6",
- 0x16
- },
-
- Package (0x02)
- {
- "\\_SB.SYSM.CLUS.CPU7",
- 0x17
- }
- })
- Method (PGCC, 0, NotSerialized)
- {
- Return (CCFG) /* \_SB_.PEP0.CCFG */
- }
-
- Name (DRVC, Package (0x02)
- {
- Package (0x03)
- {
- "HLOS_DRV",
- 0x02,
- "/icb/arbiter"
- },
-
- Package (0x03)
- {
- "DISPLAY_DRV",
- 0x09,
- "/icb/arbiter/display"
- }
- })
- Method (LDRV, 0, NotSerialized)
- {
- Return (DRVC) /* \_SB_.PEP0.DRVC */
- }
-
- Name (DCVS, Zero)
- Method (PGDS, 0, NotSerialized)
- {
- Return (DCVS) /* \_SB_.PEP0.DCVS */
- }
-
- Name (PPPP, Package (0x32)
- {
- Package (0x03)
- {
- "PPP_RESOURCE_ID_SMPS1_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_SMPS2_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_SMPS3_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_SMPS4_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_SMPS5_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_SMPS6_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_SMPS7_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_SMPS9_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_SMPS1_C",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_SMPS2_C",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_SMPS3_C",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO1_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO2_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO3_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO4_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO5_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO6_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO7_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO8_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO9_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO10_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO11_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO12_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO13_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO14_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO15_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO16_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO17_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO18_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO19_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO20_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO21_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO22_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO23_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO24_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO25_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO26_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO27_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LDO28_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LVS1_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_LVS2_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK2_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK3_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK1_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK2_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK3_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK1_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK2_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK3_A",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- },
-
- Package (0x03)
- {
- "PPP_RESOURCE_ID_BUCK_BOOST1_B",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH",
- "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF"
- }
- })
- Method (PPPM, 0, NotSerialized)
- {
- Return (PPPP) /* \_SB_.PEP0.PPPP */
- }
-
- Name (PRRP, Package (0x12)
- {
- "PPP_RESOURCE_RANGE_INFO_SMPS_A",
- "PPP_RESOURCE_ID_SMPS1_A",
- "PPP_RESOURCE_ID_SMPS13_A",
- "PPP_RESOURCE_RANGE_INFO_SMPS_C",
- "PPP_RESOURCE_ID_SMPS1_C",
- "PPP_RESOURCE_ID_SMPS4_C",
- "PPP_RESOURCE_RANGE_INFO_LDO_A",
- "PPP_RESOURCE_ID_LDO1_A",
- "PPP_RESOURCE_ID_LDO28_A",
- "PPP_RESOURCE_RANGE_INFO_LVS_A",
- "PPP_RESOURCE_ID_LVS1_A",
- "PPP_RESOURCE_ID_LVS2_A",
- "PPP_RESOURCE_RANGE_INFO_CXO_BUFFERS_A",
- "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK2_A",
- "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK3_A",
- "PPP_RESOURCE_RANGE_INFO_BUCK_BOOST_B",
- "PPP_RESOURCE_ID_BUCK_BOOST1_B",
- "PPP_RESOURCE_ID_BUCK_BOOST1_B"
- })
- Method (PPRR, 0, NotSerialized)
- {
- Return (PRRP) /* \_SB_.PEP0.PRRP */
- }
-
- Method (PGSD, 0, NotSerialized)
- {
- Return (SDFR) /* \_SB_.PEP0.SDFR */
- }
-
- Name (FPDP, Zero)
- Method (FPMD, 0, NotSerialized)
- {
- Return (FPDP) /* \_SB_.PEP0.FPDP */
- }
-
- Name (PPPC, Zero)
- Method (PGPC, 0, NotSerialized)
- {
- Return (PPPC) /* \_SB_.PEP0.PPPC */
- }
-
- Method (DPRF, 0, NotSerialized)
- {
- Return (DPP0) /* \_SB_.DPP0 */
- }
-
- Method (DMRF, 0, NotSerialized)
- {
- Return (DPP1) /* \_SB_.DPP1 */
- }
- }
-
- Scope (PEP0)
- {
- Method (LPDC, 0, NotSerialized)
- {
- Return (NPDC) /* \_SB_.PEP0.NPDC */
- }
-
- Name (NPDC, Package (0x01)
- {
- Package (0x02)
- {
- "INTERRUPT_CONFIG",
- Package (0x0D)
- {
- Package (0x04)
- {
- Zero,
- 0x021A,
- Zero,
- One
- },
-
- Package (0x04)
- {
- One,
- 0x021B,
- Zero,
- One
- },
-
- Package (0x04)
- {
- 0x02,
- 0x021C,
- Zero,
- One
- },
-
- Package (0x04)
- {
- 0x03,
- 0x021D,
- Zero,
- One
- },
-
- Package (0x04)
- {
- 0x04,
- 0x0218,
- Zero,
- One
- },
-
- Package (0x04)
- {
- 0x05,
- 0x0219,
- Zero,
- One
- },
-
- Package (0x04)
- {
- 0x06,
- 0x0206,
- Zero,
- One
- },
-
- Package (0x04)
- {
- 0x07,
- 0x0207,
- Zero,
- One
- },
-
- Package (0x05)
- {
- 0x08,
- 0x0208,
- Zero,
- One,
- 0x08
- },
-
- Package (0x05)
- {
- 0x09,
- 0x0209,
- Zero,
- One,
- 0x08
- },
-
- Package (0x05)
- {
- 0x0A,
- 0x020A,
- Zero,
- One,
- 0x08
- },
-
- Package (0x05)
- {
- 0x0B,
- 0x020B,
- Zero,
- One,
- 0x08
- },
-
- Package (0x04)
- {
- 0x0C,
- 0x0201,
- Zero,
- 0x04
- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (LPCU, 0, NotSerialized)
- {
- Return (NPCU) /* \_SB_.PEP0.NPCU */
- }
-
- Name (NPCU, Package (0x05)
- {
- "PCU_CONFIG",
- 0x09,
- One,
- Package (0x02)
- {
- "PCU_CLUSTER_CONFIG",
- 0x09
- },
-
- Package (0x0A)
- {
- "PCU_PHYS_CONFIG",
- 0x17E00040,
- 0x17E10040,
- 0x17E20040,
- 0x17E30040,
- 0x17E40040,
- 0x17E50040,
- 0x17E60040,
- 0x17E70040,
- 0x17810104
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (LVDD, 0, NotSerialized)
- {
- Return (NVDD) /* \_SB_.PEP0.NVDD */
- }
-
- Name (NVDD, Package (0x06)
- {
- Package (0x02)
- {
- "/arc/client/rail_cx",
- "RAIL_VOLTAGE_LEVEL_NOMINAL"
- },
-
- Package (0x02)
- {
- "/arc/client/display/rail_cx",
- "RAIL_VOLTAGE_LEVEL_OFF"
- },
-
- Package (0x02)
- {
- "/arc/client/rail_mx",
- "RAIL_VOLTAGE_LEVEL_NOMINAL"
- },
-
- Package (0x02)
- {
- "/arc/client/display/rail_mx",
- "RAIL_VOLTAGE_LEVEL_OFF"
- },
-
- Package (0x02)
- {
- "/arc/client/rail_xo",
- "XO_LEVEL_ON"
- },
-
- Package (0x02)
- {
- "/arc/client/display/rail_xo",
- "XO_LEVEL_CRYSTAL_OFF"
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (LLMH, 0, NotSerialized)
- {
- Return (NLMH) /* \_SB_.PEP0.NLMH */
- }
-
- Name (NLMH, Package (0x01)
- {
- Package (0x03)
- {
- "PEP_LMH_CFG",
- Package (0x06)
- {
- Zero,
- Zero,
- 0x002DB400,
- 0x0D02,
- 0x0DF7,
- 0x0DFC
- },
-
- Package (0x06)
- {
- One,
- Zero,
- 0x002DB400,
- 0x0D02,
- 0x0DF7,
- 0x0DFC
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Name (DVMP, Package (0x02)
- {
- Package (0x04)
- {
- "PPP_RESOURCE_ID_PMIC_GPIO_DV1",
- "PPP_RESOURCE_TYPE_DISCRETE_PMIC_GPIO",
- Package (0x02)
- {
- "PM_DISCRETE_VREG_STATE_ON",
- Package (0x0A)
- {
- Zero,
- 0x08,
- Zero,
- Zero,
- One,
- Zero,
- One,
- Zero,
- One,
- 0x05
- }
- },
-
- Package (0x02)
- {
- "PM_DISCRETE_VREG_STATE_OFF",
- Package (0x0A)
- {
- Zero,
- 0x08,
- Zero,
- Zero,
- Zero,
- Zero,
- One,
- Zero,
- One,
- 0x05
- }
- }
- },
-
- Package (0x04)
- {
- "PPP_RESOURCE_ID_PMIC_MPP_DV1",
- "PPP_RESOURCE_TYPE_DISCRETE_PMIC_MPP",
- Package (0x02)
- {
- "PM_DISCRETE_VREG_STATE_ON",
- Package (0x06)
- {
- Zero,
- 0x03,
- Zero,
- 0x02,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PM_DISCRETE_VREG_STATE_OFF",
- Package (0x06)
- {
- Zero,
- 0x03,
- Zero,
- 0x02,
- Zero,
- Zero
- }
- }
- }
- })
- Method (DVMM, 0, NotSerialized)
- {
- Return (DVMP) /* \_SB_.PEP0.DVMP */
- }
- }
-
- Scope (PEP0)
- {
- Method (LDBG, 0, NotSerialized)
- {
- Return (NDBG) /* \_SB_.PEP0.NDBG */
- }
-
- Name (NDBG, Package (0x04)
- {
- "DEBUGGERS",
- Package (0x05)
- {
- "TYPE",
- "SERIAL",
- Package (0x02)
- {
- "INSTANCES",
- "\\_SB.UARD"
- },
-
- Package (0x0C)
- {
- "DEBUG_ON",
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_s1_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x07)
- {
- 0x03,
- "ICBID_MASTER_BLSP_2",
- "ICBID_SLAVE_EBI1",
- 0x00989680,
- 0x0682,
- "HLOS_DRV",
- "SUPPRESSIBLE"
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x07)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_2",
- 0x00989680,
- 0x004C4B40,
- "HLOS_DRV",
- "SUPPRESSIBLE"
- }
- }
- },
-
- Package (0x01)
- {
- "DEBUG_OFF"
- }
- },
-
- Package (0x05)
- {
- "TYPE",
- "USB2.0",
- Package (0x02)
- {
- "INSTANCES",
- "\\_SB.USB1"
- },
-
- Package (0x1E)
- {
- "DEBUG_ON",
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO12_A",
- One,
- 0x001B7740,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO24_A",
- One,
- 0x002EEBB8,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO26_A",
- One,
- 0x00124F80,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO1_A",
- One,
- 0x000D6D80,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "usb30_sec_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb30_sec_sleep_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb30_sec_sleep_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_usb30_sec_sleep_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb3_sec_phy_pipe_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb3_sec_phy_pipe_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_usb3_sec_phy_pipe_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_aggre_usb3_sec_axi_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_aggre_usb3_sec_axi_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_aggre_usb3_sec_axi_clk",
- 0x08,
- 0x78,
- 0x09
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_cfg_noc_usb3_sec_axi_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_cfg_noc_usb3_sec_axi_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_cfg_noc_usb3_sec_axi_clk",
- 0x08,
- 0x78,
- 0x09
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb30_sec_master_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb30_sec_master_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_usb30_sec_master_clk",
- 0x08,
- 0x78,
- 0x09
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb3_sec_phy_aux_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb3_sec_phy_aux_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_usb3_sec_phy_aux_clk",
- 0x08,
- 0x04B0,
- 0x07
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb_phy_cfg_ahb2phy_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb_phy_cfg_ahb2phy_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_usb_phy_cfg_ahb2phy_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x07)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_USB3_1",
- 0x17D78400,
- Zero,
- "HLOS_DRV",
- "SUPPRESSIBLE"
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x07)
- {
- 0x03,
- "ICBID_MASTER_USB3_1",
- "ICBID_SLAVE_EBI1",
- 0x28000000,
- 0x28000000,
- "HLOS_DRV",
- "SUPPRESSIBLE"
- }
- },
-
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x04)
- {
- One,
- "/arc/client/rail_cx",
- 0x0100,
- "SUPPRESSIBLE"
- }
- }
- },
-
- Package (0x01)
- {
- "DEBUG_OFF"
- }
- },
-
- Package (0x05)
- {
- "TYPE",
- "USB3.0",
- Package (0x02)
- {
- "INSTANCES",
- "\\_SB.URS0"
- },
-
- Package (0x1E)
- {
- "DEBUG_ON",
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO12_A",
- One,
- 0x001B7740,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO24_A",
- One,
- 0x002EEBB8,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO26_A",
- One,
- 0x00124F80,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO1_A",
- One,
- 0x000D6D80,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "usb30_prim_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_usb30_prim_sleep_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb30_prim_sleep_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb30_prim_sleep_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_usb3_prim_phy_pipe_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb3_prim_phy_pipe_clk",
- 0x09,
- 0x08
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "gcc_usb3_prim_phy_pipe_clk",
- 0x09,
- 0x0C
- }
- },
-
- Package (0x02)
- {
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- },
-
- Package (0x02)
- {
- "CLOCK",
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- {
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- 0x09,
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- },
-
- Package (0x02)
- {
- "CLOCK",
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- 0x08,
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- }
- },
-
- Package (0x02)
- {
- "CLOCK",
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- },
-
- Package (0x02)
- {
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-
- Package (0x02)
- {
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- 0x09
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- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
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- 0x08
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- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
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- 0x0C
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-
- Package (0x02)
- {
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- Package (0x04)
- {
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- 0x78,
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- },
-
- Package (0x02)
- {
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- {
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- 0x08
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-
- Package (0x02)
- {
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- {
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- },
-
- Package (0x02)
- {
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- {
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- },
-
- Package (0x02)
- {
- "CLOCK",
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- {
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- 0x08
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- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
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-
- Package (0x02)
- {
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- Package (0x02)
- {
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- },
-
- Package (0x02)
- {
- "BUSARB",
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- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_USB3_0",
- 0x17D78400,
- Zero,
- "HLOS_DRV",
- "SUPPRESSIBLE"
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
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- {
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- 0x28000000,
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-
- Package (0x02)
- {
- "NPARESOURCE",
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- {
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-
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- {
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- }
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-
- Scope (PEP0)
- {
- Method (LDRS, 0, NotSerialized)
- {
- Return (NDRS) /* \_SB_.PEP0.NDRS */
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-
- Name (NDRS, Package (0x03)
- {
- "DEFAULT_RESOURCES",
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- {
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- {
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- {
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-
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- {
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- {
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- {
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- Zero
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-
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- {
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-
- Package (0x02)
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-
- Package (0x02)
- {
- "CLOCK",
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- {
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- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (UIDL, 0, NotSerialized)
- {
- Return (NIDL) /* \_SB_.PEP0.NIDL */
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-
- Name (NIDL, Package (0x0E)
- {
- "MICROPEP_IDLE",
- One,
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- {
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- Zero,
- Zero,
- Package (0x07)
- {
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- Zero,
- Zero,
- Zero,
- Zero,
- Zero
- },
-
- Package (0x07)
- {
- "MODE",
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- 0x03E8,
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- Zero,
- Zero,
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-
- Package (0x07)
- {
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- 0x0BB8,
- 0x1194,
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- Zero,
- 0x40000003
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-
- Package (0x07)
- {
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-
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- {
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- One,
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- Zero,
- Zero,
- Zero,
- Zero
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-
- Package (0x07)
- {
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- 0x03E8,
- 0x0FA0,
- Zero,
- Zero,
- 0x02
- },
-
- Package (0x07)
- {
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- 0x0BB8,
- 0x1194,
- 0x03,
- Zero,
- 0x40000003
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-
- Package (0x07)
- {
- "MODE",
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- 0x0BB8,
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- Zero,
- 0x40000004
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-
- Package (0x08)
- {
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- 0x02,
- Zero,
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- {
- "MODE",
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- Zero,
- Zero,
- Zero,
- Zero,
- Zero
- },
-
- Package (0x07)
- {
- "MODE",
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- 0x03E8,
- 0x0FA0,
- Zero,
- Zero,
- 0x02
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-
- Package (0x07)
- {
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- 0x0BB8,
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- Zero,
- 0x40000003
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-
- Package (0x07)
- {
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-
- Package (0x08)
- {
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- {
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- Zero,
- Zero
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-
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- {
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-
- Package (0x07)
- {
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- Zero,
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-
- Package (0x07)
- {
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- Zero,
- Zero,
- Zero,
- Zero,
- Zero
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- Package (0x07)
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- Zero,
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- Package (0x07)
- {
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-
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- {
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- Zero,
- Zero,
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- Package (0x07)
- {
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- 0x40000003
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-
- Package (0x07)
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- Package (0x08)
- {
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- Zero,
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- Zero,
- Zero
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- Package (0x07)
- {
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-
- Package (0x07)
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- Package (0x08)
- {
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- {
- "MODE",
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- Zero,
- Zero,
- Zero,
- Zero,
- Zero
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-
- Package (0x07)
- {
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- Package (0x07)
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-
- Package (0x07)
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-
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-
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-
- Package (0x04)
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-
- Package (0x05)
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-
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- Package (0x04)
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-
- Package (0x04)
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-
- Package (0x05)
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-
- Package (0x04)
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-
- Package (0x04)
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-
- Package (0x04)
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-
- Package (0x05)
- {
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- Package (0x04)
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-
- Package (0x04)
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- Package (0x0B)
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- {
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- Package (0x04)
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- Package (0x03)
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-
- Package (0x04)
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-
- Package (0x03)
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-
- Package (0x04)
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-
- Package (0x03)
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-
- Package (0x04)
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-
- Package (0x0B)
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- {
- "DEPENDENCY_CONTAINER",
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-
- Package (0x04)
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-
- Package (0x03)
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-
- Package (0x04)
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-
- Package (0x03)
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-
- Package (0x04)
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-
- Package (0x03)
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- Package (0x04)
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-
- Package (0x07)
- {
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- Package (0x0B)
- {
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- Zero,
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-
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- Package (0x04)
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-
- Package (0x04)
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-
- Package (0x05)
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- Package (0x04)
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- Package (0x04)
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-
- Package (0x04)
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-
- Package (0x05)
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-
- Package (0x04)
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-
- Package (0x04)
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-
- Package (0x04)
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-
- Package (0x05)
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-
- Package (0x04)
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-
- Package (0x04)
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- Package (0x04)
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-
- Package (0x0B)
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- Package (0x03)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold0",
- "C3",
- 0x07
- },
-
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold0",
- "C3_NI",
- 0x07
- }
- },
-
- Package (0x03)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold1",
- "C3",
- 0x07
- },
-
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold1",
- "C3_NI",
- 0x07
- }
- },
-
- Package (0x03)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold2",
- "C3",
- 0x07
- },
-
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold2",
- "C3_NI",
- 0x07
- }
- },
-
- Package (0x03)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold3",
- "C3",
- 0x07
- },
-
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold3",
- "C3_NI",
- 0x07
- }
- }
- },
-
- Package (0x0B)
- {
- "MODE",
- "D4",
- 0x2EE0,
- 0xEA60,
- 0x10,
- Zero,
- 0x40,
- Package (0x03)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold0",
- "C3",
- 0x07
- },
-
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold0",
- "C3_NI",
- 0x07
- }
- },
-
- Package (0x03)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold1",
- "C3",
- 0x07
- },
-
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold1",
- "C3_NI",
- 0x07
- }
- },
-
- Package (0x03)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold2",
- "C3",
- 0x07
- },
-
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold2",
- "C3_NI",
- 0x07
- }
- },
-
- Package (0x03)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold3",
- "C3",
- 0x07
- },
-
- Package (0x04)
- {
- "DEPENDENCY",
- "KryoGold3",
- "C3_NI",
- 0x07
- }
- }
- }
- },
-
- Package (0x07)
- {
- "LPR",
- "CCI",
- 0xFFFFFFFF,
- 0x02000000,
- Package (0x09)
- {
- "MODE",
- "E1",
- 0x1388,
- 0x6590,
- 0x10,
- Zero,
- 0x0100,
- Package (0x03)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "L2_Silver",
- "D2e",
- 0x07
- },
-
- Package (0x04)
- {
- "DEPENDENCY",
- "L2_Silver",
- "D4",
- 0x07
- }
- },
-
- Package (0x03)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "L2_Gold",
- "D2e",
- 0x07
- },
-
- Package (0x04)
- {
- "DEPENDENCY",
- "L2_Gold",
- "D4",
- 0x07
- }
- }
- },
-
- Package (0x09)
- {
- "MODE",
- "E3",
- 0x2AF8,
- 0x7530,
- 0x10,
- Zero,
- 0x0400,
- Package (0x02)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "L2_Silver",
- "D4",
- 0x07
- }
- },
-
- Package (0x02)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "L2_Gold",
- "D4",
- 0x07
- }
- }
- },
-
- Package (0x09)
- {
- "MODE",
- "E3+RPM",
- 0x2CEC,
- 0x88B8,
- 0x10,
- Zero,
- 0x0500,
- Package (0x02)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "L2_Silver",
- "D4",
- 0x07
- }
- },
-
- Package (0x02)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "L2_Gold",
- "D4",
- 0x07
- }
- }
- }
- },
-
- Package (0x05)
- {
- "LPR",
- "platform",
- 0xFFFFFFFF,
- Zero,
- Package (0x08)
- {
- "MODE",
- "xo",
- 0x1388,
- 0x00050910,
- 0x20,
- 0x10,
- 0xFFFFFE00,
- Package (0x02)
- {
- "DEPENDENCY_CONTAINER",
- Package (0x04)
- {
- "DEPENDENCY",
- "CCI",
- "E3+RPM",
- 0x07
- }
- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (CPRZ, 0, NotSerialized)
- {
- Return (CPRH) /* \_SB_.PEP0.CPRH */
- }
-
- Name (CPRH, Package (0x06)
- {
- "CPRH_SW_SETTING",
- Zero,
- Package (0x05)
- {
- "CPRH_CHIP_INFO",
- 0x0141,
- One,
- Package (0x36)
- {
- "CPRH_SW_CONTROLLER_SETTING",
- Zero,
- "APC0",
- 0x17DC0000,
- 0x4000,
- Zero,
- 0x14,
- 0x0F,
- 0x0C,
- 0x0B,
- One,
- 0x08,
- 0xF0,
- Zero,
- Zero,
- 0x00017700,
- 0x0190,
- 0x04,
- 0x04,
- 0x05,
- Zero,
- One,
- 0x05,
- One,
- One,
- One,
- One,
- 0x17,
- 0x4B00,
- Zero,
- 0x04,
- One,
- 0x04,
- One,
- Zero,
- Zero,
- "",
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- 0x17840800,
- 0x0400,
- One,
- One,
- Zero,
- One,
- One,
- One,
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- Zero,
- "L3",
- 0x02,
- 0x02,
- Zero,
- Zero
- },
-
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- One,
- "Silver",
- 0x02,
- 0x02,
- Zero,
- Zero
- }
- },
-
- Package (0x35)
- {
- "CPRH_SW_CONTROLLER_SETTING",
- One,
- "APC1",
- 0x17DB0000,
- 0x4000,
- Zero,
- 0x14,
- 0x0F,
- 0x0E,
- 0x09,
- One,
- 0x0E,
- Zero,
- Zero,
- Zero,
- 0x00017700,
- 0x0190,
- 0x04,
- 0x04,
- 0x05,
- Zero,
- 0x06,
- 0x0A,
- One,
- One,
- Zero,
- Zero,
- 0x17,
- 0x4B00,
- Zero,
- 0x04,
- One,
- 0x04,
- One,
- Zero,
- Zero,
- "",
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- 0x17830800,
- 0x0400,
- One,
- One,
- Zero,
- One,
- One,
- One,
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- Zero,
- "Gold",
- 0x02,
- 0x02,
- Zero,
- 0x02
- }
- }
- },
-
- Package (0x05)
- {
- "CPRH_CHIP_INFO",
- 0x0141,
- 0x02,
- Package (0x36)
- {
- "CPRH_SW_CONTROLLER_SETTING",
- Zero,
- "APC0",
- 0x17DC0000,
- 0x4000,
- Zero,
- 0x14,
- 0x0F,
- 0x0C,
- 0x0B,
- One,
- 0x08,
- 0xF0,
- Zero,
- Zero,
- 0x00017700,
- 0x0190,
- 0x04,
- 0x04,
- 0x05,
- Zero,
- One,
- 0x05,
- One,
- One,
- One,
- One,
- 0x17,
- 0x4B00,
- Zero,
- 0x04,
- One,
- 0x04,
- One,
- Zero,
- Zero,
- "",
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- 0x17840800,
- 0x0400,
- One,
- One,
- Zero,
- One,
- One,
- One,
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- Zero,
- "L3",
- 0x02,
- 0x02,
- Zero,
- Zero
- },
-
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- One,
- "Silver",
- 0x02,
- 0x02,
- Zero,
- Zero
- }
- },
-
- Package (0x35)
- {
- "CPRH_SW_CONTROLLER_SETTING",
- One,
- "APC1",
- 0x17DB0000,
- 0x4000,
- Zero,
- 0x14,
- 0x0F,
- 0x0E,
- 0x09,
- One,
- 0x0E,
- Zero,
- Zero,
- Zero,
- 0x00017700,
- 0x0190,
- 0x04,
- 0x04,
- 0x05,
- Zero,
- 0x06,
- 0x0A,
- One,
- One,
- Zero,
- Zero,
- 0x17,
- 0x4B00,
- Zero,
- 0x04,
- One,
- 0x04,
- One,
- Zero,
- Zero,
- "",
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- 0x17830800,
- 0x0400,
- One,
- One,
- Zero,
- One,
- One,
- One,
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- Zero,
- "Gold",
- 0x02,
- 0x02,
- Zero,
- 0x02
- }
- }
- },
-
- Package (0x05)
- {
- "CPRH_CHIP_INFO",
- 0x0155,
- One,
- Package (0x36)
- {
- "CPRH_SW_CONTROLLER_SETTING",
- Zero,
- "APC0",
- 0x17DC0000,
- 0x4000,
- Zero,
- 0x14,
- 0x0F,
- 0x0C,
- 0x0B,
- One,
- 0x08,
- 0xF0,
- Zero,
- Zero,
- 0x00017700,
- 0x0190,
- 0x04,
- 0x04,
- 0x05,
- Zero,
- One,
- 0x05,
- One,
- One,
- One,
- One,
- 0x17,
- 0x4B00,
- Zero,
- 0x04,
- One,
- 0x04,
- One,
- Zero,
- Zero,
- "",
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- 0x17840800,
- 0x0400,
- One,
- One,
- Zero,
- One,
- One,
- One,
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- Zero,
- "Silver",
- 0x02,
- 0x02,
- Zero,
- Zero
- },
-
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- One,
- "L3",
- 0x02,
- 0x02,
- Zero,
- Zero
- }
- },
-
- Package (0x35)
- {
- "CPRH_SW_CONTROLLER_SETTING",
- One,
- "APC1",
- 0x17DB0000,
- 0x4000,
- Zero,
- 0x14,
- 0x0F,
- 0x0E,
- 0x09,
- One,
- 0x0E,
- Zero,
- Zero,
- Zero,
- 0x00017700,
- 0x0190,
- 0x04,
- 0x04,
- 0x05,
- Zero,
- 0x06,
- 0x0A,
- One,
- One,
- Zero,
- Zero,
- 0x17,
- 0x4B00,
- Zero,
- 0x04,
- One,
- 0x04,
- One,
- Zero,
- Zero,
- "",
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- 0x17830800,
- 0x0400,
- One,
- One,
- Zero,
- One,
- One,
- One,
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- Zero,
- "Gold",
- 0x02,
- 0x02,
- Zero,
- 0x02
- }
- }
- },
-
- Package (0x05)
- {
- "CPRH_CHIP_INFO",
- 0x0155,
- 0x02,
- Package (0x36)
- {
- "CPRH_SW_CONTROLLER_SETTING",
- Zero,
- "APC0",
- 0x17DC0000,
- 0x4000,
- Zero,
- 0x14,
- 0x0F,
- 0x0C,
- 0x0B,
- One,
- 0x08,
- 0xF0,
- Zero,
- Zero,
- 0x00017700,
- 0x0190,
- 0x04,
- 0x04,
- 0x05,
- Zero,
- One,
- 0x05,
- One,
- One,
- One,
- One,
- 0x17,
- 0x4B00,
- Zero,
- 0x04,
- One,
- 0x04,
- One,
- Zero,
- Zero,
- "",
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- 0x17840800,
- 0x0400,
- One,
- One,
- Zero,
- One,
- One,
- One,
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- Zero,
- "Silver",
- 0x02,
- 0x02,
- Zero,
- Zero
- },
-
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- One,
- "L3",
- 0x02,
- 0x02,
- Zero,
- Zero
- }
- },
-
- Package (0x35)
- {
- "CPRH_SW_CONTROLLER_SETTING",
- One,
- "APC1",
- 0x17DB0000,
- 0x4000,
- Zero,
- 0x14,
- 0x0F,
- 0x0E,
- 0x09,
- One,
- 0x0E,
- Zero,
- Zero,
- Zero,
- 0x00017700,
- 0x0190,
- 0x04,
- 0x04,
- 0x05,
- Zero,
- 0x06,
- 0x0A,
- One,
- One,
- Zero,
- Zero,
- 0x17,
- 0x4B00,
- Zero,
- 0x04,
- One,
- 0x04,
- One,
- Zero,
- Zero,
- "",
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero,
- 0x17830800,
- 0x0400,
- One,
- One,
- Zero,
- One,
- One,
- One,
- Package (0x07)
- {
- "CPRH_SW_THREAD_SETTING",
- Zero,
- "Gold",
- 0x02,
- 0x02,
- Zero,
- 0x02
- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Name (NDCV, Package (0x05)
- {
- Package (0x08)
- {
- "CHIP_INFO",
- 0x0141,
- One,
- Zero,
- 0x02,
- Package (0x06)
- {
- "BIG",
- 0x04,
- "apcs_gold_sysleaf_clk",
- Package (0x03)
- {
- 0x012C,
- 0x040D,
- 0x0626
- },
-
- 0x03,
- Package (0x03)
- {
- Zero,
- 0x09,
- 0x10
- }
- },
-
- Package (0x06)
- {
- "LITTLE",
- 0x04,
- "apcs_silver_sysleaf_clk",
- Package (0x03)
- {
- 0x012C,
- 0x04BA,
- 0x063A
- },
-
- 0x03,
- Package (0x03)
- {
- Zero,
- 0x0B,
- 0x10
- }
- },
-
- Package (0x02)
- {
- "L3_CACHE",
- "apcs_l3_sysleaf_clk"
- }
- },
-
- Package (0x08)
- {
- "CHIP_INFO",
- 0x0141,
- 0x02,
- Zero,
- 0x02,
- Package (0x06)
- {
- "BIG",
- 0x04,
- "apcs_gold_sysleaf_clk",
- Package (0x03)
- {
- 0x033A,
- 0x0553,
- 0x05B4
- },
-
- 0x03,
- Package (0x03)
- {
- Zero,
- 0x07,
- 0x0F
- }
- },
-
- Package (0x06)
- {
- "LITTLE",
- 0x04,
- "apcs_silver_sysleaf_clk",
- Package (0x03)
- {
- 0x012C,
- 0x04CD,
- 0x052D
- },
-
- 0x03,
- Package (0x03)
- {
- Zero,
- 0x0B,
- 0x0F
- }
- },
-
- Package (0x02)
- {
- "L3_CACHE",
- "apcs_l3_sysleaf_clk"
- }
- },
-
- Package (0x08)
- {
- "CHIP_INFO",
- 0x0155,
- One,
- Zero,
- 0x02,
- Package (0x06)
- {
- "BIG",
- 0x04,
- "apcs_gold_sysleaf_clk",
- Package (0x03)
- {
- 0x012C,
- 0x040D,
- 0x0626
- },
-
- 0x03,
- Package (0x03)
- {
- Zero,
- 0x09,
- 0x10
- }
- },
-
- Package (0x06)
- {
- "LITTLE",
- 0x04,
- "apcs_silver_sysleaf_clk",
- Package (0x03)
- {
- 0x012C,
- 0x04BA,
- 0x063A
- },
-
- 0x03,
- Package (0x03)
- {
- Zero,
- 0x0B,
- 0x10
- }
- },
-
- Package (0x02)
- {
- "L3_CACHE",
- "apcs_l3_sysleaf_clk"
- }
- },
-
- Package (0x08)
- {
- "CHIP_INFO",
- 0x0155,
- 0x02,
- Zero,
- 0x02,
- Package (0x06)
- {
- "BIG",
- 0x04,
- "apcs_gold_sysleaf_clk",
- Package (0x03)
- {
- 0x033A,
- 0x0553,
- 0x05B4
- },
-
- 0x03,
- Package (0x03)
- {
- Zero,
- 0x07,
- 0x0F
- }
- },
-
- Package (0x06)
- {
- "LITTLE",
- 0x04,
- "apcs_silver_sysleaf_clk",
- Package (0x03)
- {
- 0x012C,
- 0x04CD,
- 0x052D
- },
-
- 0x03,
- Package (0x03)
- {
- Zero,
- 0x0B,
- 0x0F
- }
- },
-
- Package (0x02)
- {
- "L3_CACHE",
- "apcs_l3_sysleaf_clk"
- }
- },
-
- Package (0x08)
- {
- "CHIP_INFO",
- 0x015C,
- 0x02,
- Zero,
- 0x02,
- Package (0x06)
- {
- "BIG",
- 0x04,
- "apcs_gold_sysleaf_clk",
- Package (0x03)
- {
- 0x033A,
- 0x0553,
- 0x05B4
- },
-
- 0x03,
- Package (0x03)
- {
- Zero,
- 0x07,
- 0x0F
- }
- },
-
- Package (0x06)
- {
- "LITTLE",
- 0x04,
- "apcs_silver_sysleaf_clk",
- Package (0x03)
- {
- 0x012C,
- 0x04CD,
- 0x052D
- },
-
- 0x03,
- Package (0x03)
- {
- Zero,
- 0x0B,
- 0x0F
- }
- },
-
- Package (0x02)
- {
- "L3_CACHE",
- "apcs_l3_sysleaf_clk"
- }
- }
- })
- Method (LDCV, 0, NotSerialized)
- {
- Return (NDCV) /* \_SB_.PEP0.NDCV */
- }
- }
-
- Scope (PEP0)
- {
- Method (CTSN, 0, NotSerialized)
- {
- Return (THSD) /* \_SB_.PEP0.THSD */
- }
-
- Method (PEPH, 0, NotSerialized)
- {
- Return (Package (0x01)
- {
- "ACPI\\VEN_QCOM&DEV_0237"
- })
- }
-
- Method (BCLH, 0, NotSerialized)
- {
- Return (Package (0x01)
- {
- "ACPI\\VEN_QCOM&DEV_0294"
- })
- }
-
- Name (THSD, Package (0x07)
- {
- Package (0x16)
- {
- 0x15,
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_027F",
- Zero
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_0280",
- One
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_0281",
- 0x02
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_0282",
- 0x03
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_0283",
- 0x04
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_0284",
- 0x05
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_0285",
- 0x06
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_0286",
- 0x07
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_0287",
- 0x08
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_0288",
- 0x09
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_0289",
- 0x0A
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_02AB",
- 0x0B
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_02AC",
- 0x0C
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_02AD",
- 0x0D
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_02AE",
- 0x0E
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_02AF",
- 0x0F
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_02C8",
- 0x10
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_02C9",
- 0x11
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_02CA",
- 0x12
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_02CB",
- 0x13
- },
-
- Package (0x02)
- {
- "ACPI\\VEN_QCOM&DEV_02CC",
- 0x14
- }
- },
-
- Package (0x04)
- {
- 0x03,
- Package (0x04)
- {
- "ACPI\\VEN_QCOM&DEV_02B0",
- 0x15,
- 0x05,
- Package (0x05)
- {
- One,
- 0x02,
- 0x03,
- 0x04,
- 0x05
- }
- },
-
- Package (0x04)
- {
- "ACPI\\VEN_QCOM&DEV_02B1",
- 0x16,
- 0x05,
- Package (0x05)
- {
- 0x06,
- 0x07,
- 0x08,
- 0x09,
- 0x0A
- }
- },
-
- Package (0x04)
- {
- "ACPI\\VEN_QCOM&DEV_02B2",
- 0x17,
- 0x15,
- Package (0x15)
- {
- Zero,
- One,
- 0x02,
- 0x03,
- 0x04,
- 0x05,
- 0x06,
- 0x07,
- 0x08,
- 0x09,
- 0x0A,
- 0x0B,
- 0x0C,
- 0x0D,
- 0x0E,
- 0x0F,
- 0x10,
- 0x11,
- 0x12,
- 0x13,
- 0x14
- }
- }
- },
-
- Package (0x09)
- {
- 0x08,
- Package (0x04)
- {
- "SYS_THERM1",
- "ACPI\\VEN_QCOM&DEV_0299",
- Zero,
- Zero
- },
-
- Package (0x04)
- {
- "SYS_THERM2",
- "ACPI\\VEN_QCOM&DEV_029A",
- One,
- Zero
- },
-
- Package (0x04)
- {
- "PA_THERM",
- "ACPI\\VEN_QCOM&DEV_029B",
- 0x02,
- Zero
- },
-
- Package (0x04)
- {
- "PA_THERM1",
- "ACPI\\VEN_QCOM&DEV_029C",
- 0x03,
- Zero
- },
-
- Package (0x04)
- {
- "SYS_THERM3",
- "ACPI\\VEN_QCOM&DEV_029D",
- 0x04,
- Zero
- },
-
- Package (0x04)
- {
- "PMIC_THERM",
- "ACPI\\VEN_QCOM&DEV_029E",
- 0x05,
- Zero
- },
-
- Package (0x04)
- {
- "BAT_THERM",
- "ACPI\\VEN_QCOM&DEV_029F",
- 0x06,
- Zero
- },
-
- Package (0x04)
- {
- "RF_THERM",
- "ACPI\\VEN_QCOM&DEV_02A0",
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- One,
- Package (0x05)
- {
- 0x02,
- 0x0ADC,
- 0x0B0E,
- 0x02,
- One
- }
- },
-
- Package (0x05)
- {
- 0x04,
- Package (0x03)
- {
- "cpuv_restriction_cold",
- One,
- Zero
- },
-
- Package (0x03)
- {
- "cpuv_restriction_cold",
- One,
- One
- },
-
- Package (0x03)
- {
- "cpuv_restriction_cold",
- One,
- 0x43
- },
-
- Package (0x03)
- {
- "cpuv_restriction_cold",
- One,
- 0x53
- }
- },
-
- Package (0x01)
- {
- Zero
- },
-
- Package (0x08)
- {
- 0x07,
- Package (0x03)
- {
- Zero,
- Zero,
- Zero
- },
-
- Package (0x03)
- {
- One,
- 0x03,
- Zero
- },
-
- Package (0x03)
- {
- 0x03,
- 0x02,
- Zero
- },
-
- Package (0x03)
- {
- 0x04,
- 0x02,
- One
- },
-
- Package (0x03)
- {
- 0x06,
- 0x02,
- 0x02
- },
-
- Package (0x03)
- {
- 0x08,
- 0x02,
- 0x03
- },
-
- Package (0x03)
- {
- 0x02,
- 0x04,
- Zero
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (APMD, 0, NotSerialized)
- {
- Return (APCC) /* \_SB_.PEP0.APCC */
- }
-
- Name (APCC, Package (0x02)
- {
- Package (0x1A)
- {
- "DEVICE",
- "\\_SB.ADSP.SLM1.ADCM.AUDD",
- Package (0x05)
- {
- "COMPONENT",
- Zero,
- Package (0x03)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x03)
- {
- "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK2_A",
- 0x06,
- One
- }
- }
- },
-
- Package (0x03)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x03)
- {
- "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK2_A",
- 0x06,
- Zero
- }
- }
- },
-
- Package (0x06)
- {
- "PSTATE_SET",
- Zero,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS4_A",
- 0x02,
- 0x001B7740,
- One,
- Zero,
- Zero
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS4_A",
- 0x02,
- 0x001B7740,
- Zero,
- Zero,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- One
- }
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- One,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x02,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x03,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x04,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x05,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x06,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x07,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x08,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x09,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x0A,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x0B,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x0C,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x0D,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x0E,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x0F,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x10,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x11,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x12,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x13,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x14,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x15,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x16,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x17,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- }
- },
-
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.ADSP.SLM1.ADCM.AUDD.MBHC",
- Package (0x04)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (GPMD, 0, NotSerialized)
- {
- Name (LIST, Package (0x0B)
- {
- "METHOD_LIST",
- "DM0G",
- "DM1G",
- "DM2G",
- "DM3G",
- "DM4G",
- "DM5G",
- "DM6G",
- "DM7G",
- "DM8G",
- "DM9G"
- })
- Return (LIST) /* \_SB_.PEP0.GPMD.LIST */
- }
-
- Method (G0MD, 0, NotSerialized)
- {
- Name (GPCC, Package (0x01)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.GPU0",
- Package (0x0C)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x04)
- {
- "FSTATE",
- One,
- Package (0x12)
- {
- "ENTER",
- Package (0x01)
- {
- "PSTATE_SAVE"
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x03,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x04,
- 0x2A
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x02,
- 0x04
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "mdss_core_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_xo_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "phy_refgen_south",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x08)
- {
- "PPP_RESOURCE_ID_LDO1_A",
- One,
- Zero,
- Zero,
- Zero,
- Zero,
- "HLOS_DRV",
- "REQUIRED"
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x08)
- {
- "PPP_RESOURCE_ID_LDO26_A",
- One,
- Zero,
- Zero,
- Zero,
- Zero,
- "HLOS_DRV",
- "REQUIRED"
- }
- },
-
- Package (0x02)
- {
- "PMICGPIO",
- Package (0x08)
- {
- "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT",
- Zero,
- 0x11,
- Zero,
- One,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x60,
- Zero,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x7B,
- Zero,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x08)
- {
- "PPP_RESOURCE_ID_LDO14_A",
- One,
- Zero,
- Zero,
- Zero,
- Zero,
- "HLOS_DRV",
- "REQUIRED"
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x08)
- {
- "PPP_RESOURCE_ID_SMPS6_A",
- 0x02,
- Zero,
- Zero,
- Zero,
- Zero,
- "HLOS_DRV",
- "REQUIRED"
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x03)
- {
- "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK3_A",
- 0x06,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x80,
- Zero,
- Zero,
- One,
- Zero,
- Zero
- }
- }
- },
-
- Package (0x11)
- {
- "EXIT",
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "mdss_core_gdsc",
- One
- }
- },
-
- Package (0x01)
- {
- "PSTATE_RESTORE"
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x08)
- {
- "PPP_RESOURCE_ID_LDO1_A",
- One,
- 0x000D6D80,
- One,
- 0x07,
- Zero,
- "HLOS_DRV",
- "REQUIRED"
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x08)
- {
- "PPP_RESOURCE_ID_LDO26_A",
- One,
- 0x00124F80,
- One,
- 0x07,
- Zero,
- "HLOS_DRV",
- "REQUIRED"
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x08)
- {
- "PPP_RESOURCE_ID_LDO14_A",
- One,
- 0x001CAFC0,
- One,
- 0x07,
- Zero,
- "HLOS_DRV",
- "REQUIRED"
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x08)
- {
- "PPP_RESOURCE_ID_SMPS6_A",
- 0x02,
- 0x000C3500,
- One,
- 0x07,
- Zero,
- "HLOS_DRV",
- "REQUIRED"
- }
- },
-
- Package (0x02)
- {
- "PMICGPIO",
- Package (0x08)
- {
- "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT",
- Zero,
- 0x11,
- Zero,
- Zero,
- One,
- One,
- 0x04
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0x0A
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x7B,
- One,
- Zero,
- One,
- 0x03,
- 0x07
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x80,
- One,
- Zero,
- One,
- 0x03,
- 0x07
- }
- },
-
- Package (0x02)
- {
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-
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- {
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- {
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- {
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-
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- {
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-
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- {
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- {
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-
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- {
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-
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- {
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-
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- {
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- {
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- {
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- 0x047868C0,
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-
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-
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- {
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- {
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- {
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- {
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-
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-
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- {
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-
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- {
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- {
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-
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-
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- {
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-
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- {
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-
- Package (0x02)
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-
- Package (0x02)
- {
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-
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- {
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- {
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-
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- {
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- {
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-
- Package (0x02)
- {
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- {
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-
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- {
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-
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- {
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-
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- {
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-
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-
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- {
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- Package (0x04)
- {
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- Zero,
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- {
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- Package (0x04)
- {
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- 0x19A14780,
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- {
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- {
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- 0x18964020,
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-
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- {
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- {
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- {
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- {
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- {
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- {
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- {
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- Package (0x04)
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- {
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- 0x06,
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- {
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- Package (0x04)
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- {
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- Package (0x04)
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- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0xA6E49C00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x1B,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x00000001AD274800,
- 0x8F0D1800
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x8F0D1800
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x1C,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x0000000165A0BC00,
- 0x77359400
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x77359400
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x1D,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x5F5E1000
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x5F5E1000
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x1E,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x59682F00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x59682F00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x1F,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x53724E00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x53724E00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x20,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x4D7C6D00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x4D7C6D00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x21,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x47868C00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x47868C00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x22,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x4190AB00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x4190AB00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x23,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x3B9ACA00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x3B9ACA00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x24,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x35A4E900
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x35A4E900
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x25,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x2FAF0800
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x2FAF0800
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x26,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x29B92700
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x29B92700
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x27,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x23C34600
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x23C34600
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x28,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x1DCD6500
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x1DCD6500
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x29,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x17D78400
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x17D78400
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x2A,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- 0x1F
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- 0x1F
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- 0x1F
- }
- }
- }
- }
- })
- Return (GPCC) /* \_SB_.PEP0.G0MD.GPCC */
- }
-
- Method (G1MD, 0, NotSerialized)
- {
- Name (GPCC, Package (0x01)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.GPU0",
- Package (0x0B)
- {
- "COMPONENT",
- One,
- Package (0x03)
- {
- "FSTATE",
- Zero,
- Package (0x08)
- {
- "ENTER",
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- One,
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gpu_cc_cxo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gpu_cc_cx_gmu_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_gpu_memnoc_gfx_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gpu_cc_gx_gfx3d_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gpu_cc_cx_gmu_clk",
- 0x03,
- 0x0BEBC200,
- 0x03
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_GFX3D",
- "ICBID_SLAVE_EBI1",
- One,
- Zero
- }
- }
- }
- },
-
- Package (0x03)
- {
- "FSTATE",
- One,
- Package (0x06)
- {
- "ENTER",
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gpu_cc_gx_gfx3d_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_gpu_memnoc_gfx_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gpu_cc_cx_gmu_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gpu_cc_cxo_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- One,
- 0x02
- }
- }
- }
- },
-
- Package (0x03)
- {
- "FSTATE",
- 0x02,
- Package (0x07)
- {
- "ENTER",
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_GFX3D",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gpu_cc_gx_gfx3d_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_gpu_memnoc_gfx_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gpu_cc_cx_gmu_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gpu_cc_cxo_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- One,
- 0x02
- }
- }
- }
- },
-
- Package (0x02)
- {
- "INIT_FSTATE",
- One
- },
-
- Package (0x02)
- {
- "PRELOAD_FSTATE",
- One
- },
-
- Package (0x02)
- {
- "ABANDON_FSTATE",
- One
- },
-
- Package (0x07)
- {
- "PSTATE_SET",
- Zero,
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x05)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- One,
- 0x02
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- One,
- One
- }
- }
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- Zero
- }
- },
-
- Package (0x08)
- {
- "PSTATE_SET",
- One,
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "cx_gdsc",
- One
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "cx_gdsc",
- 0x02
- }
- }
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- Zero
- }
- },
-
- Package (0x07)
- {
- "PSTATE_SET",
- 0x02,
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PSTATE",
- One
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- One
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- One
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- One
- }
- }
- }
- }
- })
- Return (GPCC) /* \_SB_.PEP0.G1MD.GPCC */
- }
-
- Method (G2MD, 0, NotSerialized)
- {
- Name (GPCC, Package (0x01)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.GPU0",
- Package (0x0C)
- {
- "COMPONENT",
- 0x02,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x04)
- {
- "FSTATE",
- One,
- Package (0x0B)
- {
- "ENTER",
- Package (0x01)
- {
- "PSTATE_SAVE"
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x02,
- 0x0C
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x03,
- 0x31
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_vsync_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_vsync_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_mdp_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_DISPLAY_CFG",
- Zero,
- Zero
- }
- }
- },
-
- Package (0x09)
- {
- "EXIT",
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_DISPLAY_CFG",
- 0x047868C0,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_mdp_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_vsync_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_vsync_clk",
- One
- }
- },
-
- Package (0x01)
- {
- "PSTATE_RESTORE"
- }
- }
- },
-
- Package (0x04)
- {
- "FSTATE",
- 0x02,
- Package (0x0F)
- {
- "ENTER",
- Package (0x01)
- {
- "PSTATE_SAVE"
- },
-
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- 0x000000013D744F80
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x15,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x00000001259CCB80,
- 0x00000001259CCB80
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x16,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x000000010DC54780,
- 0x000000010DC54780
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x17,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0xF5EDC380,
- 0xF5EDC380
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x18,
- Package (0x02)
- {
- "BUSARB",
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- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0xDE163F80,
- 0xDE163F80
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x19,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0xC63EBB80,
- 0xC63EBB80
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x1A,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0xAE673780,
- 0xAE673780
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x1B,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x968FB380,
- 0x968FB380
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x1C,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x8F0D1800,
- 0x8F0D1800
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x1D,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x89173700,
- 0x89173700
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x1E,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x83215600,
- 0x83215600
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x1F,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x7D2B7500,
- 0x7D2B7500
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x20,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x77359400,
- 0x77359400
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x21,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x713FB300,
- 0x713FB300
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x22,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x6B49D200,
- 0x6B49D200
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x23,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x6553F100,
- 0x6553F100
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x24,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x5F5E1000,
- 0x5F5E1000
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x25,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x59682F00,
- 0x59682F00
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x26,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x53724E00,
- 0x53724E00
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x27,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x4D7C6D00,
- 0x4D7C6D00
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x28,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x47868C00,
- 0x47868C00
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x29,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x4190AB00,
- 0x4190AB00
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x2A,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x3B9ACA00,
- 0x3B9ACA00
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x2B,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x35A4E900,
- 0x35A4E900
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x2C,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x2FAF0800
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x2D,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x29B92700,
- 0x29B92700
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x2E,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x23C34600,
- 0x23C34600
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x2F,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x1DCD6500,
- 0x1DCD6500
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x30,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- 0x17D78400,
- 0x17D78400
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x31,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- }
- }
- }
- }
- }
- })
- Return (GPCC) /* \_SB_.PEP0.G2MD.GPCC */
- }
-
- Method (G3MD, 0, NotSerialized)
- {
- Name (GPCC, Package (0x01)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.GPU0",
- Package (0x0C)
- {
- "COMPONENT",
- 0x03,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x04)
- {
- "FSTATE",
- One,
- Package (0x0C)
- {
- "ENTER",
- Package (0x01)
- {
- "PSTATE_SAVE"
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x02,
- 0x07
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x03,
- 0x31
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_vsync_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_vsync_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_mdp_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rot_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_DISPLAY_CFG",
- Zero,
- Zero
- }
- }
- },
-
- Package (0x0B)
- {
- "EXIT",
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_DISPLAY_CFG",
- 0x047868C0,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_mdp_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_vsync_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_vsync_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rot_clk",
- One
- }
- },
-
- Package (0x01)
- {
- "PSTATE_RESTORE"
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x02,
- 0x04
- }
- }
- }
- },
-
- Package (0x04)
- {
- "FSTATE",
- 0x02,
- Package (0x10)
- {
- "ENTER",
- Package (0x01)
- {
- "PSTATE_SAVE"
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x02,
- 0x07
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x03,
- 0x31
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_vsync_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_vsync_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_mdp_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rot_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_DISPLAY_CFG",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "mdss_core_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_xo_clk",
- 0x02
- }
- }
- },
-
- Package (0x0F)
- {
- "EXIT",
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "mdss_core_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_DISPLAY_CFG",
- 0x047868C0,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_mdp_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_vsync_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_vsync_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rot_clk",
- One
- }
- },
-
- Package (0x01)
- {
- "PSTATE_RESTORE"
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x02,
- 0x04
- }
- }
- }
- },
-
- Package (0x02)
- {
- "INIT_FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PRELOAD_FSTATE",
- 0x02
- },
-
- Package (0x02)
- {
- "ABANDON_FSTATE",
- 0x02
- },
-
- Package (0x07)
- {
- "PSTATE_SET",
- Zero,
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PSTATE",
- One
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- Zero
- }
- },
-
- Package (0x04)
- {
- "PSTATE_SET",
- One,
- Package (0x05)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "mdss_core_gdsc",
- One
- }
- }
- },
-
- Package (0x05)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "mdss_core_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_xo_clk",
- 0x02
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- Package (0x03)
- {
- "PSTATE",
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- {
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- {
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-
- Package (0x03)
- {
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- {
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- Package (0x03)
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- }
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- Method (G4MD, 0, NotSerialized)
- {
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- {
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- {
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- {
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- {
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-
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- {
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- {
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- {
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- Package (0x02)
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- Package (0x02)
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- {
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- {
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-
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- {
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- Package (0x02)
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-
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-
- Package (0x02)
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-
- Package (0x02)
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- Package (0x02)
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-
- Package (0x02)
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-
- Package (0x02)
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- Package (0x02)
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-
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-
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-
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-
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-
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-
- Package (0x02)
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-
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-
- Package (0x02)
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- {
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-
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-
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-
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-
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-
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-
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-
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- {
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- {
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- {
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-
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- {
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-
- Package (0x02)
- {
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- {
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-
- Package (0x02)
- {
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- {
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-
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- {
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-
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- {
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- {
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-
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-
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-
- Package (0x02)
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- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_VIDEO_P0",
- "ICBID_SLAVE_EBI1",
- 0x23C34600,
- 0x23C34600
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x6C,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_VIDEO_P0",
- "ICBID_SLAVE_EBI1",
- 0x17D78400,
- 0x17D78400
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x6D,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_VIDEO_P0",
- "ICBID_SLAVE_EBI1",
- 0x0BEBC200,
- 0x0BEBC200
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x6E,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_VIDEO_P0",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- 0x6C
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- 0x6C
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- 0x6C
- }
- }
- }
- }
- })
- Return (GPCC) /* \_SB_.PEP0.G4MD.GPCC */
- }
-
- Method (G5MD, 0, NotSerialized)
- {
- Name (GPCC, Package (0x01)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.GPU0",
- Package (0x0A)
- {
- "COMPONENT",
- 0x05,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- },
-
- Package (0x02)
- {
- "INIT_FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PRELOAD_FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "ABANDON_FSTATE",
- Zero
- },
-
- Package (0x07)
- {
- "PSTATE_SET",
- Zero,
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PSTATE",
- One
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- Zero
- }
- },
-
- Package (0x07)
- {
- "PSTATE_SET",
- One,
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PSTATE",
- One
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- One
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- Zero
- }
- },
-
- Package (0x06)
- {
- "PSTATE_SET",
- 0x02,
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- Zero
- }
- }
- }
- }
- })
- Return (GPCC) /* \_SB_.PEP0.G5MD.GPCC */
- }
-
- Method (G6MD, 0, NotSerialized)
- {
- Name (GPCC, Package (0x01)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.GPU0",
- Package (0x0C)
- {
- "COMPONENT",
- 0x06,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x04)
- {
- "FSTATE",
- One,
- Package (0x09)
- {
- "ENTER",
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_ahb_clk",
- 0x02
- }
- }
- },
-
- Package (0x09)
- {
- "EXIT",
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_core_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_core_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_core_clk",
- One
- }
- }
- }
- },
-
- Package (0x04)
- {
- "FSTATE",
- 0x02,
- Package (0x13)
- {
- "ENTER",
- Package (0x01)
- {
- "PSTATE_SAVE"
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x02,
- 0x06
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x03,
- 0x6E
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec1_gdsc",
- 0x04
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec1_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec0_gdsc",
- 0x04
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec0_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "venus_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_xo_clk",
- 0x02
- }
- }
- },
-
- Package (0x18)
- {
- "EXIT",
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "venus_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec0_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec0_gdsc",
- 0x03
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec1_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec1_gdsc",
- 0x03
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_core_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_core_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_core_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "video_cc_vcodec0_core_clk",
- 0x09,
- 0x12
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "video_cc_vcodec1_core_clk",
- 0x09,
- 0x12
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "video_cc_venus_ctl_core_clk",
- 0x09,
- 0x12
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "video_cc_vcodec0_core_clk",
- 0x09,
- 0x14
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "video_cc_vcodec1_core_clk",
- 0x09,
- 0x14
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x03)
- {
- "video_cc_venus_ctl_core_clk",
- 0x09,
- 0x14
- }
- },
-
- Package (0x01)
- {
- "PSTATE_RESTORE"
- }
- }
- },
-
- Package (0x02)
- {
- "INIT_FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PRELOAD_FSTATE",
- 0x02
- },
-
- Package (0x02)
- {
- "ABANDON_FSTATE",
- 0x02
- },
-
- Package (0x07)
- {
- "PSTATE_SET",
- Zero,
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x11)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_core_clk",
- 0x0A
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_axi_clk",
- 0x0A
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_core_clk",
- 0x0A
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_axi_clk",
- 0x0A
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_core_clk",
- 0x0A
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_axi_clk",
- 0x0A
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ahb_clk",
- 0x0A
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ahb_clk",
- 0x0B
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_axi_clk",
- 0x0B
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_venus_ctl_core_clk",
- 0x0B
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_axi_clk",
- 0x0B
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec0_core_clk",
- 0x0B
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_axi_clk",
- 0x0B
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "video_cc_vcodec1_core_clk",
- 0x0B
- }
- }
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- One
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- One
- }
- },
-
- Package (0x07)
- {
- "PSTATE_SET",
- One,
- Package (0x0A)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "venus_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec0_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec0_gdsc",
- 0x03
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec1_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec1_gdsc",
- 0x03
- }
- }
- },
-
- Package (0x0A)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec1_gdsc",
- 0x04
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec1_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec0_gdsc",
- 0x04
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "vcodec0_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "venus_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_video_xo_clk",
- 0x02
- }
- }
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- One
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- One
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- One
- }
- },
-
- Package (0x0C)
- {
- "PSTATE_SET",
- 0x02,
- Package (0x06)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "video_cc_venus_ctl_core_clk",
- 0x03,
- 0x1FC4EF40,
- 0x03
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "video_cc_vcodec0_core_clk",
- 0x03,
- 0x1FC4EF40,
- 0x03
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "video_cc_vcodec1_core_clk",
- 0x03,
- 0x1FC4EF40,
- 0x03
- }
- },
-
- Package (0x02)
- {
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- "PSTATE",
- 0x69,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_VIDEO_P1",
- "ICBID_SLAVE_EBI1",
- 0x3B9ACA00,
- Zero
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x6A,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_VIDEO_P1",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- Zero
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x6B,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_VIDEO_P1",
- "ICBID_SLAVE_EBI1",
- 0x23C34600,
- Zero
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x6C,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_VIDEO_P1",
- "ICBID_SLAVE_EBI1",
- 0x17D78400,
- Zero
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x6D,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_VIDEO_P1",
- "ICBID_SLAVE_EBI1",
- 0x0BEBC200,
- Zero
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x6E,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_VIDEO_P1",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- 0x6C
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- 0x6C
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- 0x6C
- }
- }
- }
- }
- })
- Return (GPCC) /* \_SB_.PEP0.G6MD.GPCC */
- }
-
- Method (G7MD, 0, NotSerialized)
- {
- Name (GPCC, Package (0x01)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.GPU0",
- Package (0x0C)
- {
- "COMPONENT",
- 0x07,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x04)
- {
- "FSTATE",
- One,
- Package (0x09)
- {
- "ENTER",
- Package (0x01)
- {
- "PSTATE_SAVE"
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-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x03,
- 0x0C
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-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x04,
- 0x2A
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- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
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- {
- 0x02,
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-
- Package (0x02)
- {
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- Package (0x02)
- {
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- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_ahb_clk",
- 0x02
- }
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-
- Package (0x02)
- {
- "CLOCK",
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- {
- "gcc_disp_xo_clk",
- 0x02
- }
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-
- Package (0x02)
- {
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- {
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- 0x02
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-
- Package (0x06)
- {
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- {
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- {
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- One
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-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
- }
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-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "mdss_core_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "phy_refgen_south",
- One
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-
- Package (0x01)
- {
- "PSTATE_RESTORE"
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- }
- },
-
- Package (0x02)
- {
- "INIT_FSTATE",
- One
- },
-
- Package (0x02)
- {
- "PRELOAD_FSTATE",
- Zero
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-
- Package (0x02)
- {
- "ABANDON_FSTATE",
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- },
-
- Package (0x07)
- {
- "PSTATE_SET",
- Zero,
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PSTATE",
- One
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-
- Package (0x02)
- {
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-
- Package (0x02)
- {
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-
- Package (0x02)
- {
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- },
-
- Package (0x04)
- {
- "PSTATE_SET",
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- {
- "PSTATE",
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- {
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- {
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- One
- }
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-
- Package (0x02)
- {
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- {
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-
- Package (0x02)
- {
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- {
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-
- Package (0x05)
- {
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- {
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- {
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- 0x02
- }
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-
- Package (0x02)
- {
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- Package (0x02)
- {
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- 0x02
- }
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-
- Package (0x02)
- {
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- {
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- 0x02
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-
- Package (0x0A)
- {
- "PSTATE_SET",
- 0x02,
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- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_DISPLAY_CFG",
- 0x047868C0,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_axi_clk",
- One
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-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_mdp_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_vsync_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
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-
- Package (0x02)
- {
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- {
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-
- Package (0x02)
- {
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- {
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- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte0_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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-
- Package (0x02)
- {
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- {
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- }
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-
- Package (0x02)
- {
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- {
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- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte1_intf_clk",
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- }
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-
- Package (0x12)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
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- 0x047868C0,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- },
-
- Package (0x02)
- {
- "CLOCK",
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- {
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-
- Package (0x02)
- {
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- {
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- },
-
- Package (0x02)
- {
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- Package (0x02)
- {
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- One
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- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
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- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_esc0_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte0_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte0_intf_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_pclk1_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_esc1_clk",
- One
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- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte1_clk",
- One
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- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
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- }
- },
-
- Package (0x12)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_DISPLAY_CFG",
- 0x047868C0,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
- }
- },
-
- Package (0x02)
- {
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- Package (0x02)
- {
- "disp_cc_mdss_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
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- {
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- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_vsync_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_pclk0_clk",
- One
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- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_esc0_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte0_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte0_intf_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_pclk1_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_esc1_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte1_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte1_intf_clk",
- 0x02
- }
- }
- },
-
- Package (0x12)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_DISPLAY_CFG",
- 0x047868C0,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_mdp_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_vsync_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_vsync_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_pclk0_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_esc0_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte0_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte0_intf_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_pclk1_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_esc1_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte1_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte1_intf_clk",
- One
- }
- }
- },
-
- Package (0x12)
- {
- "PSTATE",
- 0x04,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_mdp_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_vsync_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_rscc_vsync_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_pclk0_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_esc0_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte0_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte0_intf_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_pclk1_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_esc1_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte1_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_byte1_intf_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_DISPLAY_CFG",
- Zero,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- Zero
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- Package (0x02)
- {
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-
- Package (0x04)
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-
- Package (0x02)
- {
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-
- Package (0x04)
- {
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-
- Package (0x02)
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-
- Package (0x02)
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- {
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-
- Package (0x04)
- {
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- {
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- {
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- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
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-
- Package (0x02)
- {
- "BUSARB",
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- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
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- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x2A,
- Package (0x02)
- {
- "BUSARB",
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- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
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- },
-
- Package (0x02)
- {
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-
- Package (0x02)
- {
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-
- Package (0x02)
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- "ABANDON_PSTATE",
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- }
- }
- }
- })
- Return (GPCC) /* \_SB_.PEP0.G7MD.GPCC */
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-
- Method (G8MD, 0, NotSerialized)
- {
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- {
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- {
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- Package (0x0B)
- {
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- 0x08,
- Package (0x02)
- {
- "FSTATE",
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-
- Package (0x04)
- {
- "FSTATE",
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- {
- "ENTER",
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- {
- "PMICVREGVOTE",
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- {
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- Zero,
- Zero,
- Zero,
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-
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- {
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- "PPP_RESOURCE_ID_LDO24_A",
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- Zero,
- Zero,
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- Package (0x02)
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- Zero,
- Zero,
- Zero,
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-
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- {
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- }
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-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_axi_clk",
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- }
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-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_mdp_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "disp_cc_mdss_vsync_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
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- {
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- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
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- {
- "disp_cc_mdss_rscc_vsync_clk",
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- }
- },
-
- Package (0x02)
- {
- "CLOCK",
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- {
- "disp_cc_mdss_dp_pixel_clk",
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- }
- },
-
- Package (0x02)
- {
- "CLOCK",
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- {
- "disp_cc_mdss_dp_link_clk",
- 0x02
- }
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-
- Package (0x02)
- {
- "CLOCK",
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- {
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- }
- },
-
- Package (0x02)
- {
- "CLOCK",
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- {
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-
- Package (0x02)
- {
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- {
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- }
- },
-
- Package (0x02)
- {
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- {
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- }
- },
-
- Package (0x02)
- {
- "CLOCK",
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- {
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- }
- },
-
- Package (0x01)
- {
- "PSTATE_SAVE"
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-
- Package (0x02)
- {
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- {
- 0x02,
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-
- Package (0x02)
- {
- "PSTATE_ADJUST",
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- {
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- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
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- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "mdss_core_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_disp_xo_clk",
- 0x02
- }
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-
- Package (0x16)
- {
- "EXIT",
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- {
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- {
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- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
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- }
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-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "mdss_core_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
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- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
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- 0x047868C0,
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-
- Package (0x02)
- {
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- Package (0x02)
- {
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- }
- },
-
- Package (0x02)
- {
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- Package (0x02)
- {
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- },
-
- Package (0x02)
- {
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-
- Package (0x02)
- {
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- Package (0x02)
- {
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-
- Package (0x02)
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- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0x00000001C4FECC00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x00000001C4FECC00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x0F,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0x00000001AD274800
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x00000001AD274800
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x10,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0x00000001954FC400
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x00000001954FC400
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x11,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0x000000017D784000
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x000000017D784000
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x12,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0x0000000165A0BC00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x0000000165A0BC00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x13,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0x000000014DC93800
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x000000014DC93800
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x14,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0x0000000135F1B400
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x0000000135F1B400
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x15,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0x000000011E1A3000
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x000000011E1A3000
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x16,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0x000000010642AC00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x000000010642AC00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x17,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0xEE6B2800
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0xEE6B2800
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x18,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0xD693A400
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0xD693A400
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x19,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000023C346000,
- 0xBEBC2000
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0xBEBC2000
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x1A,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x00000001F4ADD400,
- 0xA6E49C00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0xA6E49C00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x1B,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x00000001AD274800,
- 0x8F0D1800
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x8F0D1800
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x1C,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x0000000165A0BC00,
- 0x77359400
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x77359400
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x1D,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x5F5E1000
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x5F5E1000
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x1E,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x59682F00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x59682F00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x1F,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x53724E00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x53724E00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x20,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x4D7C6D00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x4D7C6D00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x21,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x47868C00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x47868C00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x22,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x4190AB00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x4190AB00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x23,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x3B9ACA00
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x3B9ACA00
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x24,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x35A4E900
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x35A4E900
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x25,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x2FAF0800
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x2FAF0800
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x26,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x29B92700
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x29B92700
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x27,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x23C34600
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x23C34600
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x28,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x1DCD6500
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x1DCD6500
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x29,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- 0x000000011E1A3000,
- 0x17D78400
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- 0x2FAF0800,
- 0x17D78400
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x2A,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MDP0",
- "ICBID_SLAVE_MNOC_HF_MEM_NOC",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_MNOC_HF_MEM_NOC",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "PRELOAD_PSTATE",
- 0x1F
- },
-
- Package (0x02)
- {
- "PREPARE_PSTATE",
- 0x1F
- },
-
- Package (0x02)
- {
- "ABANDON_PSTATE",
- 0x1F
- }
- }
- }
- }
- })
- Return (GPCC) /* \_SB_.PEP0.G8MD.GPCC */
- }
-
- Method (G9MD, 0, NotSerialized)
- {
- Name (GPCC, Package (0x01)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.GPU0",
- Package (0x06)
- {
- "COMPONENT",
- 0x09,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "INIT_FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PRELOAD_FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "ABANDON_FSTATE",
- Zero
- }
- }
- }
- })
- Return (GPCC) /* \_SB_.PEP0.G9MD.GPCC */
- }
- }
-
- Scope (PEP0)
- {
- Method (SMMD, 0, NotSerialized)
- {
- Return (SMMC) /* \_SB_.PEP0.SMMC */
- }
-
- Name (SMMC, Package (0x02)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.MMU0",
- Package (0x04)
- {
- "COMPONENT",
- Zero,
- Package (0x03)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_hlos1_vote_mmu_tcu_clk",
- One
- }
- }
- },
-
- Package (0x03)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_hlos1_vote_mmu_tcu_clk",
- 0x02
- }
- }
- }
- }
- },
-
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.MMU1",
- Package (0x04)
- {
- "COMPONENT",
- Zero,
- Package (0x04)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "gcc_hlos1_vote_gpu_smmu_gds",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_hlos1_vote_gpu_smmu_clk",
- One
- }
- }
- },
-
- Package (0x04)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_hlos1_vote_gpu_smmu_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "gcc_hlos1_vote_gpu_smmu_gds",
- 0x02
- }
- }
- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (OPMD, 0, NotSerialized)
- {
- Return (OPCC) /* \_SB_.PEP0.OPCC */
- }
-
- Name (OPCC, Package (0x04)
- {
- Package (0x04)
- {
- "DEVICE",
- "\\_SB.PEN1",
- Package (0x07)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x77,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO18_A",
- One,
- 0x002D2A80,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0x14
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x15,
- One,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0x78
- }
- }
- },
-
- Package (0x06)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x15,
- Zero,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO18_A",
- One,
- Zero,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0x14
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x77,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero
- }
- }
- }
- },
-
- Package (0x04)
- {
- "DEVICE",
- "\\_SB.ACC1",
- Package (0x04)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x0E,
- One,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0x0A
- }
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x03
- }
- },
-
- Package (0x04)
- {
- "DEVICE",
- "\\_SB.ALS1",
- Package (0x04)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x0E,
- One,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0x0A
- }
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x03
- }
- },
-
- Package (0x04)
- {
- "DEVICE",
- "\\_SB.LED1",
- Package (0x04)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "PMICGPIO",
- Package (0x08)
- {
- "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT",
- Zero,
- One,
- Zero,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0x0A
- }
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x03
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (SPMD, 0, NotSerialized)
- {
- Return (SPCC) /* \_SB_.PEP0.SPCC */
- }
-
- Name (SPCC, Package (0x04)
- {
- Package (0x05)
- {
- "DEVICE",
- "\\_SB.AMSS",
- Package (0x06)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x0D)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_boot_rom_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_mss_cfg_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_mss_q6_memnoc_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_mss_snoc_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_mss_mfab_axis_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_prng_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_mss_axis2_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS2_C",
- 0x02,
- 0x000B7980,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x03)
- {
- One,
- "/arc/client/rail_cx",
- 0x0180
- }
- },
-
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x03)
- {
- One,
- "/arc/client/rail_mx",
- 0x0180
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x06)
- {
- 0x03,
- "ICBID_MASTER_IPA_CORE",
- "ICBID_SLAVE_IPA_CORE",
- 0x9218,
- Zero,
- "HLOS_DRV"
- }
- }
- },
-
- Package (0x07)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_prng_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS2_C",
- 0x02,
- Zero,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x03)
- {
- One,
- "/arc/client/rail_cx",
- Zero
- }
- },
-
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x03)
- {
- One,
- "/arc/client/rail_mx",
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x06)
- {
- 0x03,
- "ICBID_MASTER_IPA_CORE",
- "ICBID_SLAVE_IPA_CORE",
- Zero,
- Zero,
- "HLOS_DRV"
- }
- }
- },
-
- Package (0x05)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_boot_rom_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_prng_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS2_C",
- 0x02,
- Zero,
- Zero,
- Zero,
- Zero
- }
- }
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x03
- }
- },
-
- Package (0x05)
- {
- "DEVICE",
- "\\_SB.ADSP",
- Package (0x05)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PSTATE",
- One
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x03
- }
- },
-
- Package (0x05)
- {
- "DEVICE",
- "\\_SB.SCSS",
- Package (0x06)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x06)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x0E,
- One,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO27_A",
- One,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO4_A",
- One,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_CLK_CTL",
- One,
- One
- }
- }
- },
-
- Package (0x05)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO27_A",
- One,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO4_A",
- One,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_CLK_CTL",
- Zero,
- Zero
- }
- }
- },
-
- Package (0x05)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO27_A",
- One,
- Zero,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO4_A",
- One,
- Zero,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_CLK_CTL",
- Zero,
- Zero
- }
- }
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x03
- }
- },
-
- Package (0x05)
- {
- "DEVICE",
- "\\_SB.CDSP",
- Package (0x05)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PSTATE",
- One
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x03
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (PPMD, 0, NotSerialized)
- {
- Return (PPCC) /* \_SB_.PEP0.PPCC */
- }
-
- Name (PPCC, Package (0x03)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.PRXY",
- Package (0x03)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- }
- }
- },
-
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.STAT",
- Package (0x03)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- }
- }
- },
-
- Package (0x05)
- {
- "DEVICE",
- 0x81,
- "\\_SB.GIO0",
- Package (0x03)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- }
- },
-
- Package (0x03)
- {
- "COMPONENT",
- One,
- Package (0x02)
- {
- "FSTATE",
- Zero
- }
- }
- }
- })
- Name (SDFR, Package (0x01)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.SDFR",
- Package (0x06)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- },
-
- Package (0x02)
- {
- "FSTATE",
- 0x02
- },
-
- Package (0x02)
- {
- "FSTATE",
- 0x03
- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (BPMD, 0, NotSerialized)
- {
- Return (BPCC) /* \_SB_.PEP0.BPCC */
- }
-
- Method (LPMD, 0, NotSerialized)
- {
- Return (LPCC) /* \_SB_.PEP0.LPCC */
- }
-
- Name (BPCC, Package (0x04)
- {
- Package (0x05)
- {
- "DEVICE",
- "\\_SB.UFS0",
- Package (0x07)
- {
- "COMPONENT",
- Zero,
- Package (0x05)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x02,
- Zero
- }
- }
- },
-
- Package (0x05)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x02,
- One
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- One,
- One
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- One
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE_SET",
- Zero,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "ufs_phy_gdsc",
- One
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "ufs_phy_gdsc",
- 0x02
- }
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE_SET",
- One,
- Package (0x0C)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_ufs_phy_axi_clk",
- 0x08,
- 0x0BEBC200,
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_ufs_phy_unipro_core_clk",
- 0x08,
- 0x08F0D180,
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_ufs_phy_ice_core_clk",
- 0x08,
- 0x11E1A300,
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_aggre_ufs_phy_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_phy_aux_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_tx_symbol_0_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_rx_symbol_0_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_rx_symbol_1_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_mem_clkref_en",
- One
- }
- }
- },
-
- Package (0x0C)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_aggre_ufs_phy_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_phy_aux_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_tx_symbol_0_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_rx_symbol_0_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_rx_symbol_1_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_ice_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_unipro_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_phy_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_ufs_mem_clkref_en",
- 0x02
- }
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE_SET",
- 0x02,
- Package (0x04)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_UFS_MEM",
- "ICBID_SLAVE_EBI1",
- 0x35A4E900,
- 0x35A4E900
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
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- "ICBID_MASTER_USB3_1",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x03)
- {
- One,
- "/arc/client/rail_cx",
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO24_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO12_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO26_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO1_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "ABANDON_DSTATE",
- 0x03
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (IPMD, 0, NotSerialized)
- {
- Return (IPSC) /* \_SB_.PEP0.IPSC */
- }
-
- Name (IPSC, Package (0x01)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.IPA",
- Package (0x04)
- {
- "COMPONENT",
- Zero,
- Package (0x03)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x06)
- {
- 0x03,
- "ICBID_MASTER_IPA_CORE",
- "ICBID_SLAVE_IPA_CORE",
- 0x9218,
- Zero,
- "HLOS_DRV"
- }
- }
- },
-
- Package (0x03)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "BUSARB",
- Package (0x06)
- {
- 0x03,
- "ICBID_MASTER_IPA_CORE",
- "ICBID_SLAVE_IPA_CORE",
- Zero,
- Zero,
- "HLOS_DRV"
- }
- }
- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (EWMD, 0, NotSerialized)
- {
- Return (WBRC) /* \_SB_.PEP0.WBRC */
- }
-
- Name (WBRC, Package (0x03)
- {
- Package (0x07)
- {
- "DEVICE",
- "\\_SB.AMSS.QWLN",
- Package (0x03)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- }
- },
-
- Package (0x07)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS7_A",
- 0x02,
- 0x000FAFA0,
- One,
- 0x06,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO5_A",
- One,
- 0x000C3500,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO7_A",
- One,
- 0x001B7740,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO17_A",
- One,
- 0x0013E5C0,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO25_A",
- One,
- 0x002F5D00,
- One,
- 0x07,
- Zero
- }
- }
- },
-
- Package (0x07)
- {
- "DSTATE",
- 0x02,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO25_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO17_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO7_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO5_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS7_A",
- 0x02,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- }
- },
-
- Package (0x07)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO25_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO17_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO7_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO5_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS7_A",
- 0x02,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "ABANDON_DSTATE",
- 0x02
- }
- },
-
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.COEX",
- Package (0x05)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x07)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS7_A",
- 0x02,
- 0x000FAFA0,
- One,
- 0x06,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO5_A",
- One,
- 0x000C3500,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO7_A",
- One,
- 0x001B7740,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO17_A",
- One,
- 0x0013E5C0,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO25_A",
- One,
- 0x002F5D00,
- One,
- 0x07,
- Zero
- }
- }
- },
-
- Package (0x07)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO25_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO17_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO7_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO5_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS7_A",
- 0x02,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- }
- }
- }
- },
-
- Package (0x05)
- {
- "DEVICE",
- "\\_SB.BTH0",
- Package (0x03)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- }
- },
-
- Package (0x07)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS3_A",
- 0x02,
- 0x0014A140,
- One,
- 0x06,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS5_A",
- 0x02,
- 0x001F20C0,
- One,
- 0x06,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO7_A",
- One,
- 0x001B7740,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO17_A",
- One,
- 0x0013E5C0,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO25_A",
- One,
- 0x002F5D00,
- One,
- 0x07,
- Zero
- }
- }
- },
-
- Package (0x07)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO7_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO17_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO25_A",
- One,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS3_A",
- 0x02,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_SMPS5_A",
- 0x02,
- Zero,
- Zero,
- 0x05,
- Zero
- }
- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (QDMD, 0, NotSerialized)
- {
- Return (QDSC) /* \_SB_.PEP0.QDSC */
- }
-
- Name (QDSC, Package (0x01)
- {
- Package (0x03)
- {
- "DEVICE",
- "\\_SB.QDSS",
- Package (0x08)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x03)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- Zero
- }
- }
- },
-
- Package (0x06)
- {
- "PSTATE_SET",
- Zero,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x03)
- {
- One,
- "/clk/qdss",
- Zero
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x03)
- {
- One,
- "/clk/qdss",
- One
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x03)
- {
- One,
- "/clk/qdss",
- 0x02
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x03)
- {
- One,
- "/clk/qdss",
- 0x03
- }
- }
- }
- },
-
- Package (0x06)
- {
- "PSTATE_SET",
- One,
- Package (0x02)
- {
- "PSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "PSTATE",
- One
- },
-
- Package (0x02)
- {
- "PSTATE",
- 0x02
- },
-
- Package (0x02)
- {
- "PSTATE",
- 0x03
- }
- },
-
- Package (0x04)
- {
- "PSTATE_SET",
- 0x02,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x03)
- {
- One,
- "/clk/qdss",
- One
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "NPARESOURCE",
- Package (0x03)
- {
- One,
- "/clk/qdss",
- Zero
- }
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE_SET",
- 0x03,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "TLMMPORT",
- Package (0x03)
- {
- 0x00033000,
- 0x07FF,
- 0x01C8
- }
- }
- }
- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (PEMD, 0, NotSerialized)
- {
- Return (PEMC) /* \_SB_.PEP0.PEMC */
- }
-
- Name (PEMC, Package (0x04)
- {
- Package (0x07)
- {
- "DEVICE",
- "\\_SB.PCI0",
- Package (0x04)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- },
-
- Package (0x10)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO26_A",
- One,
- 0x00124F80,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO1_A",
- One,
- 0x000D6D80,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "pcie_0_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_PCIE_0_CFG",
- 0x047868C0,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_PCIE_0",
- "ICBID_SLAVE_EBI1",
- 0x17D78400,
- 0x0BEBC200
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_aggre_noc_pcie_tbu_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_phy_refgen_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_phy_aux_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_0_pipe_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_0_slv_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_0_slv_q2a_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_0_mstr_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_0_cfg_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_pcie_0_aux_clk",
- 0x08,
- 0x0124F800,
- 0x03
- }
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- One
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x02
- },
-
- Package (0x10)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_0_pipe_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_0_aux_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_0_slv_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_0_slv_q2a_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_0_mstr_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_0_cfg_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_aggre_noc_pcie_tbu_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_phy_refgen_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_pcie_phy_aux_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_PCIE_0_CFG",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
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- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cci_clk",
- One
- }
- }
- },
-
- Package (0x0E)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cci_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- 0x05
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- One,
- 0x05
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x02,
- 0x05
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- 0x03,
- 0x05
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- 0x02
- }
- }
- },
-
- Package (0x08)
- {
- "PSTATE_SET",
- Zero,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- 0x4190AB00,
- 0x4190AB00
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- 0x17D78400,
- 0x17D78400
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- 0x11E1A300,
- 0x11E1A300
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- 0x0BEBC200,
- 0x0BEBC200
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x04,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- 0x05F5E100,
- 0x05F5E100
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x05,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- Zero,
- Zero
- }
- }
- }
- },
-
- Package (0x08)
- {
- "PSTATE_SET",
- One,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0",
- "ICBID_SLAVE_EBI1",
- 0x4190AB00,
- 0x4190AB00
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0",
- "ICBID_SLAVE_EBI1",
- 0x17D78400,
- 0x17D78400
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0",
- "ICBID_SLAVE_EBI1",
- 0x11E1A300,
- 0x11E1A300
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0",
- "ICBID_SLAVE_EBI1",
- 0x0BEBC200,
- 0x0BEBC200
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x04,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0",
- "ICBID_SLAVE_EBI1",
- 0x05F5E100,
- 0x05F5E100
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x05,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_HF0",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- }
- }
- },
-
- Package (0x08)
- {
- "PSTATE_SET",
- 0x02,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- 0x4190AB00,
- 0x4190AB00
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- 0x17D78400,
- 0x17D78400
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- 0x11E1A300,
- 0x11E1A300
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- 0x0BEBC200,
- 0x0BEBC200
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x04,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- 0x05F5E100,
- 0x05F5E100
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x05,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF_UNCOMP",
- "ICBID_SLAVE_CAMNOC_UNCOMP",
- Zero,
- Zero
- }
- }
- }
- },
-
- Package (0x08)
- {
- "PSTATE_SET",
- 0x03,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF",
- "ICBID_SLAVE_EBI1",
- 0x4190AB00,
- 0x4190AB00
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF",
- "ICBID_SLAVE_EBI1",
- 0x17D78400,
- 0x17D78400
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF",
- "ICBID_SLAVE_EBI1",
- 0x11E1A300,
- 0x11E1A300
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF",
- "ICBID_SLAVE_EBI1",
- 0x0BEBC200,
- 0x0BEBC200
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x04,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF",
- "ICBID_SLAVE_EBI1",
- 0x05F5E100,
- 0x05F5E100
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x05,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_CAMNOC_SF",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- }
- }
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- 0x02,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- }
- },
-
- Package (0x04)
- {
- "DEVICE",
- "\\_SB.CAMS",
- Package (0x19)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO16_A",
- One,
- 0x00294280,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x5F,
- One,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0x04
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x5B,
- One,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x04)
- {
- "PPP_RESOURCE_ID_LVS1_A",
- 0x04,
- 0x001B7740,
- One
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x11,
- One,
- One,
- One,
- 0x03,
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x12,
- One,
- One,
- One,
- 0x03,
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO19_A",
- One,
- 0x002F5D00,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x19,
- One,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_mclk0_clk",
- 0x08,
- 0x016E3600,
- 0x03
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x0D,
- One,
- One,
- One,
- Zero,
- One
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- }
- },
-
- Package (0x1A)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x0D,
- Zero,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_mclk0_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO19_A",
- One,
- Zero,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x19,
- Zero,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x04)
- {
- "PPP_RESOURCE_ID_LVS1_A",
- 0x04,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x5B,
- Zero,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x12,
- Zero,
- Zero,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x11,
- Zero,
- Zero,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x5F,
- Zero,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO16_A",
- One,
- Zero,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- 0x02
- }
- }
- }
- },
-
- Package (0x04)
- {
- "DEVICE",
- "\\_SB.CAMF",
- Package (0x17)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO16_A",
- One,
- 0x00294280,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x81,
- One,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x7F,
- One,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x13,
- One,
- One,
- One,
- 0x03,
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x14,
- One,
- One,
- One,
- 0x03,
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x04)
- {
- "PPP_RESOURCE_ID_LVS2_A",
- 0x04,
- 0x001B7740,
- One
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x0C,
- One,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_mclk2_clk",
- 0x08,
- 0x016E3600,
- 0x03
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x0F,
- One,
- One,
- One,
- Zero,
- One
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- }
- },
-
- Package (0x18)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x0F,
- Zero,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_mclk2_clk",
- 0x0C,
- Zero,
- 0x03
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x0C,
- Zero,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x04)
- {
- "PPP_RESOURCE_ID_LVS2_A",
- 0x04,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x7F,
- Zero,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x14,
- Zero,
- Zero,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x13,
- Zero,
- Zero,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x81,
- Zero,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO16_A",
- One,
- Zero,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- 0x02
- }
- }
- }
- },
-
- Package (0x04)
- {
- "DEVICE",
- "\\_SB.CAMI",
- Package (0x15)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "PMICGPIO",
- Package (0x08)
- {
- "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT",
- Zero,
- Zero,
- Zero,
- One,
- One,
- 0x03,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x04)
- {
- "PPP_RESOURCE_ID_LVS1_A",
- 0x04,
- 0x001B7740,
- One
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO22_A",
- One,
- 0x00328980,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x17,
- Zero,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x17,
- One,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_mclk2_clk",
- 0x08,
- 0x016E3600,
- 0x03
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- }
- },
-
- Package (0x12)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_mclk2_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x17,
- One,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x17,
- Zero,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- One
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO22_A",
- One,
- Zero,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x04)
- {
- "PPP_RESOURCE_ID_LVS1_A",
- 0x04,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICGPIO",
- Package (0x08)
- {
- "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT",
- Zero,
- Zero,
- Zero,
- One,
- Zero,
- 0x03,
- Zero
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- 0x02
- }
- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (CPMD, 0, NotSerialized)
- {
- Return (CPCC) /* \_SB_.PEP0.CPCC */
- }
-
- Name (CPCC, Package (0x03)
- {
- Package (0x04)
- {
- "DEVICE",
- "\\_SB.JPGE",
- Package (0x05)
- {
- "COMPONENT",
- Zero,
- Package (0x0B)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_jpeg_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- 0x02
- }
- }
- },
-
- Package (0x0A)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_jpeg_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- 0x02
- }
- }
- },
-
- Package (0x06)
- {
- "PSTATE_SET",
- Zero,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_jpeg_clk",
- 0x03,
- 0x23C34600,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_jpeg_clk",
- 0x03,
- 0x23C34600,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_jpeg_clk",
- 0x03,
- 0x18148D00,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_jpeg_clk",
- 0x03,
- 0x0BEBC200,
- 0x03
- }
- }
- }
- }
- },
-
- Package (0x05)
- {
- "COMPONENT",
- One,
- Package (0x0B)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_jpeg_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- 0x02
- }
- }
- },
-
- Package (0x0A)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_jpeg_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- 0x02
- }
- }
- },
-
- Package (0x05)
- {
- "PSTATE_SET",
- Zero,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_jpeg_clk",
- 0x03,
- 0x23C34600,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_jpeg_clk",
- 0x03,
- 0x23C34600,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_jpeg_clk",
- 0x03,
- 0x0BEBC200,
- 0x03
- }
- }
- }
- }
- }
- },
-
- Package (0x05)
- {
- "DEVICE",
- "\\_SB.MPCS",
- Package (0x04)
- {
- "COMPONENT",
- Zero,
- Package (0x0C)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
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-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- 0x02
- }
- }
- },
-
- Package (0x06)
- {
- "PSTATE_SET",
- Zero,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_ipe_0_clk",
- 0x03,
- 0x23C34600,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_ipe_0_clk",
- 0x03,
- 0x1C9C3800,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_ipe_0_clk",
- 0x03,
- 0x18148D00,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_ipe_0_clk",
- 0x03,
- Zero,
- 0x03
- }
- }
- }
- },
-
- Package (0x06)
- {
- "PSTATE_SET",
- One,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_ipe_1_clk",
- 0x03,
- 0x23C34600,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_ipe_1_clk",
- 0x03,
- 0x1C9C3800,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_ipe_1_clk",
- 0x03,
- 0x18148D00,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_ipe_1_clk",
- 0x03,
- Zero,
- 0x03
- }
- }
- }
- }
- },
-
- Package (0x05)
- {
- "COMPONENT",
- 0x05,
- Package (0x10)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "bps_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_bps_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_bps_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_bps_areg_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_bps_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "bps_gdsc",
- 0x03
- }
- }
- },
-
- Package (0x10)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "bps_gdsc",
- 0x04
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_bps_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_bps_areg_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- 0x04
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_bps_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_bps_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "bps_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- 0x02
- }
- }
- },
-
- Package (0x06)
- {
- "PSTATE_SET",
- Zero,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_bps_clk",
- 0x03,
- 0x23C34600,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_bps_clk",
- 0x03,
- 0x1C9C3800,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_bps_clk",
- 0x03,
- 0x18148D00,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_bps_clk",
- 0x03,
- Zero,
- 0x03
- }
- }
- }
- }
- },
-
- Package (0x05)
- {
- "COMPONENT",
- 0x06,
- Package (0x0B)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_lrme_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- 0x02
- }
- }
- },
-
- Package (0x0B)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- 0x04
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_lrme_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- 0x02
- }
- }
- },
-
- Package (0x06)
- {
- "PSTATE_SET",
- Zero,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_lrme_clk",
- 0x03,
- 0x17D78400,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_lrme_clk",
- 0x03,
- 0x1312D000,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_lrme_clk",
- 0x03,
- 0x10089D40,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_lrme_clk",
- 0x03,
- Zero,
- 0x03
- }
- }
- }
- }
- },
-
- Package (0x05)
- {
- "COMPONENT",
- 0x07,
- Package (0x0B)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_fd_core_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- 0x02
- }
- }
- },
-
- Package (0x0B)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "PSTATE_ADJUST",
- Package (0x02)
- {
- Zero,
- 0x04
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_fd_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_camnoc_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_cpas_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "cam_cc_soc_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_axi_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "FOOTSWITCH",
- Package (0x02)
- {
- "titan_top_gdsc",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_camera_xo_clk",
- 0x02
- }
- }
- },
-
- Package (0x06)
- {
- "PSTATE_SET",
- Zero,
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_fd_core_clk",
- 0x03,
- 0x23C34600,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_fd_core_clk",
- 0x03,
- 0x20113A80,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_fd_core_clk",
- 0x03,
- 0x17D78400,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "cam_cc_fd_core_clk",
- 0x03,
- Zero,
- 0x03
- }
- }
- }
- }
- }
- }
- })
- }
-
- Scope (PEP0)
- {
- Method (LPMX, 0, NotSerialized)
- {
- Return (LPXC) /* \_SB_.PEP0.LPXC */
- }
-
- Name (LPXC, Package (0x01)
- {
- Package (0x04)
- {
- "DEVICE",
- "\\_SB.TSC1",
- Package (0x09)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x7D,
- Zero,
- Zero,
- Zero,
- 0x03,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x63,
- Zero,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO28_A",
- One,
- 0x00325AA0,
- One,
- 0x07,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x17,
- One,
- Zero,
- One,
- 0x03,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0x02
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x63,
- One,
- Zero,
- One,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "DELAY",
- Package (0x01)
- {
- 0xC8
- }
- }
- },
-
- Package (0x06)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "PMICVREGVOTE",
- Package (0x06)
- {
- "PPP_RESOURCE_ID_LDO28_A",
- One,
- Zero,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x17,
- Zero,
- Zero,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x63,
- Zero,
- Zero,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x7D,
- Zero,
- Zero,
- Zero,
- One,
- Zero
- }
- }
- }
- }
- })
- }
-
- Device (BAM1)
- {
- Name (_HID, "QCOM0213") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, One) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x01DC4000, // Address Base
- 0x00024000, // Address Length
- )
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000130,
- }
- })
- Return (RBUF) /* \_SB_.BAM1._CRS.RBUF */
- }
- }
-
- Device (BAM5)
- {
- Name (_HID, "QCOM0213") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, 0x05) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x17184000, // Address Base
- 0x00032000, // Address Length
- )
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000C4,
- }
- })
- Return (RBUF) /* \_SB_.BAM5._CRS.RBUF */
- }
- }
-
- Device (BAM6)
- {
- Name (_HID, "QCOM0213") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, 0x06) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x17204000, // Address Base
- 0x00026000, // Address Length
- )
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000144,
- }
- })
- Return (RBUF) /* \_SB_.BAM6._CRS.RBUF */
- }
- }
-
- Device (BAM7)
- {
- Name (_HID, "QCOM0213") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, 0x07) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x08884000, // Address Base
- 0x00023000, // Address Length
- )
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000009A,
- }
- })
- Return (RBUF) /* \_SB_.BAM7._CRS.RBUF */
- }
- }
-
- Device (BAMD)
- {
- Name (_HID, "QCOM0213") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, 0x0D) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x0A904000, // Address Base
- 0x00017000, // Address Length
- )
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000A9,
- }
- })
- Return (RBUF) /* \_SB_.BAMD._CRS.RBUF */
- }
- }
-
- Device (BAME)
- {
- Name (_HID, "QCOM0213") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, 0x0E) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x06064000, // Address Base
- 0x00015000, // Address Length
- )
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000C7,
- }
- })
- Return (RBUF) /* \_SB_.BAME._CRS.RBUF */
- }
- }
-
- Device (BAMF)
- {
- Name (_HID, "QCOM0213") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, 0x0F) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x0A704000, // Address Base
- 0x00017000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000000A4,
- }
- })
- Return (RBUF) /* \_SB_.BAMF._CRS.RBUF */
- }
- }
-
- Device (UAR7)
- {
- Name (_HID, "QCOM0236") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, 0x07) // _UID: Unique ID
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PEP0
- })
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x00898000, // Address Base
- 0x00004000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x0000027F,
- }
- GpioInt (Edge, ActiveLow, Exclusive, PullDown, 0x0000,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x0030
- }
- })
- Return (RBUF) /* \_SB_.UAR7._CRS.RBUF */
- }
-
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0B)
- }
- }
-
- Device (UARD)
- {
- Name (_HID, "QCOM0236") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, 0x0A) // _UID: Unique ID
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PEP0
- })
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x00A84000, // Address Base
- 0x00004000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000182,
- }
- GpioInt (Edge, ActiveLow, Exclusive, PullDown, 0x0000,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x0005
- }
- })
- Return (RBUF) /* \_SB_.UARD._CRS.RBUF */
- }
- }
-
- Device (IC15)
- {
- Name (_HID, "QCOM0220") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, 0x0F) // _UID: Unique ID
- Name (_DEP, Package (0x02) // _DEP: Dependencies
- {
- PEP0,
- QGP0
- })
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x00A98000, // Address Base
- 0x00004000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000187,
- }
- })
- Return (RBUF) /* \_SB_.IC15._CRS.RBUF */
- }
- }
-
- Device (SPI9)
- {
- Name (_HID, "QCOM021E") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, 0x09) // _UID: Unique ID
- Name (_DEP, Package (0x02) // _DEP: Dependencies
- {
- PEP0,
- QGP1
- })
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x00A80000, // Address Base
- 0x00004000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000181,
- }
- })
- Return (RBUF) /* \_SB_.SPI9._CRS.RBUF */
- }
- }
-
- Scope (PEP0)
- {
- Method (BSMD, 0, NotSerialized)
- {
- Return (BSRC) /* \_SB_.PEP0.BSRC */
- }
-
- Method (PQMD, 0, NotSerialized)
- {
- If ((SIDV < 0x00020000))
- {
- Return (DFS1) /* \_SB_.PEP0.DFS1 */
- }
- Else
- {
- Return (DFS2) /* \_SB_.PEP0.DFS2 */
- }
- }
-
- Name (BSRC, Package (0x0B)
- {
- Package (0x04)
- {
- "DEVICE",
- "\\_SB.UAR7",
- Package (0x12)
- {
- "COMPONENT",
- Zero,
- Package (0x07)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_0_m_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_0_s_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap0_s6_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_1",
- "ICBID_SLAVE_EBI1",
- 0x53724E00,
- 0x0682
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_1",
- 0x08D24D00,
- 0x02FAF080
- }
- }
- },
-
- Package (0x07)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_0_m_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_0_s_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_1",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_1",
- Zero,
- Zero
- }
- }
- },
-
- Package (0x06)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x2D,
- Zero,
- One,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x2E,
- Zero,
- One,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x2F,
- Zero,
- One,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x30,
- Zero,
- One,
- Zero,
- One,
- Zero
- }
- }
- },
-
- Package (0x06)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x2D,
- Zero,
- One,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x2E,
- Zero,
- One,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x2F,
- Zero,
- One,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x30,
- Zero,
- One,
- Zero,
- One,
- Zero
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x00708000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x00E10000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x04,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x01C20000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x05,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x01E84800,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x06,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x02DC6C00,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x07,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x03D09000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x08,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x04C4B400,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x09,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x05B8D800,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x0A,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x061A8000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x0B,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x06ACFC00,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x0C,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x07080000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x0D,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap0_s6_clk",
- 0x03,
- 0x07A12000,
- 0x04
- }
- }
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- One,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- }
- },
-
- Package (0x05)
- {
- "DEVICE",
- 0x02,
- "\\_SB.UARD",
- Package (0x12)
- {
- "COMPONENT",
- Zero,
- Package (0x0A)
- {
- "FSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_2",
- "ICBID_SLAVE_EBI1",
- 0x53724E00,
- 0x0682
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_2",
- 0x08D24D00,
- 0x02FAF080
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x00708000,
- 0x04
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_s1_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_2x_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_clk",
- One
- }
- }
- },
-
- Package (0x09)
- {
- "FSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_2x_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_2",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_2",
- Zero,
- Zero
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x05,
- Zero,
- One,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x04,
- Zero,
- One,
- Zero,
- Zero,
- Zero
- }
- }
- },
-
- Package (0x04)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x05,
- Zero,
- One,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x04,
- Zero,
- One,
- Zero,
- Zero,
- Zero
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x00708000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x00E10000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x04,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x01C20000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x05,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x01E84800,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x06,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x02DC6C00,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x07,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x03D09000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x08,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x04C4B400,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x09,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x05B8D800,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x0A,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x061A8000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x0B,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x06ACFC00,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x0C,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x07080000,
- 0x04
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x0D,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s1_clk",
- 0x03,
- 0x07A12000,
- 0x04
- }
- }
- }
- },
-
- Package (0x04)
- {
- "COMPONENT",
- One,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x02)
- {
- "FSTATE",
- One
- }
- }
- },
-
- Package (0x07)
- {
- "DEVICE",
- "\\_SB.IC15",
- Package (0x03)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- }
- },
-
- Package (0x0B)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_2",
- "ICBID_SLAVE_EBI1",
- 0x53724E00,
- 0x0682
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_2",
- 0x08F0D180,
- 0x02FAF080
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s6_clk",
- 0x08,
- 0x0124F800,
- 0x04
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_2x_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x21,
- One,
- 0x02,
- One,
- 0x03,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x22,
- One,
- 0x02,
- One,
- 0x03,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- One
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x02
- },
-
- Package (0x0B)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_s6_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_2x_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_2",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_2",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x21,
- Zero,
- Zero,
- Zero,
- 0x03,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x22,
- Zero,
- Zero,
- Zero,
- 0x03,
- Zero
- }
- }
- }
- },
-
- Package (0x07)
- {
- "DEVICE",
- "\\_SB.IC16",
- Package (0x03)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- }
- },
-
- Package (0x0B)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_2",
- "ICBID_SLAVE_EBI1",
- 0x53724E00,
- 0x0682
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_2",
- 0x08D24D00,
- 0x02FAF080
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s7_clk",
- 0x08,
- 0x0124F800,
- 0x04
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_2x_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x51,
- One,
- 0x02,
- One,
- 0x03,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x52,
- One,
- 0x02,
- One,
- 0x03,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- One
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x02
- },
-
- Package (0x0B)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_s7_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_2x_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_2",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_2",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x51,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x52,
- Zero,
- Zero,
- Zero,
- Zero,
- Zero
- }
- }
- }
- }
- })
- Name (DFS1, Package (0x01)
- {
- Package (0x07)
- {
- "DEVICE",
- "\\_SB.SPI9",
- Package (0x0A)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x0124F800,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x01E84800,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x0249F000,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x02DC6C00,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x04,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x03D09000,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x05,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x05B8D800,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x06,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x05F5E100,
- 0x03
- }
- }
- }
- },
-
- Package (0x0D)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_2",
- "ICBID_SLAVE_EBI1",
- 0x53724E00,
- 0x0682
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_2",
- 0x08D24D00,
- 0x02FAF080
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_s0_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_2x_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x41,
- One,
- 0x02,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x42,
- One,
- 0x02,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x43,
- One,
- 0x02,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x44,
- One,
- 0x02,
- One,
- One,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- One
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x02
- },
-
- Package (0x0D)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_2x_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_2",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_2",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x41,
- Zero,
- 0x02,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x42,
- Zero,
- 0x02,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x43,
- Zero,
- 0x02,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x44,
- Zero,
- 0x02,
- Zero,
- One,
- Zero
- }
- }
- }
- }
- })
- Name (DFS2, Package (0x01)
- {
- Package (0x07)
- {
- "DEVICE",
- "\\_SB.SPI9",
- Package (0x0A)
- {
- "COMPONENT",
- Zero,
- Package (0x02)
- {
- "FSTATE",
- Zero
- },
-
- Package (0x03)
- {
- "PSTATE",
- Zero,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x0124F800,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- One,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x01E84800,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x02,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x02DC6C00,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x03D09000,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x04,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x05B8D800,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x05,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x05F5E100,
- 0x03
- }
- }
- },
-
- Package (0x03)
- {
- "PSTATE",
- 0x06,
- Package (0x02)
- {
- "CLOCK",
- Package (0x04)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x03,
- 0x07270E00,
- 0x03
- }
- }
- }
- },
-
- Package (0x0D)
- {
- "DSTATE",
- Zero,
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_2",
- "ICBID_SLAVE_EBI1",
- 0x53724E00,
- 0x0682
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_2",
- 0x08D24D00,
- 0x02FAF080
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_s0_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_2x_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_clk",
- One
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x41,
- One,
- 0x02,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x42,
- One,
- 0x02,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x43,
- One,
- 0x02,
- One,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x44,
- One,
- 0x02,
- One,
- One,
- Zero
- }
- }
- },
-
- Package (0x02)
- {
- "DSTATE",
- One
- },
-
- Package (0x02)
- {
- "DSTATE",
- 0x02
- },
-
- Package (0x0D)
- {
- "DSTATE",
- 0x03,
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_m_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap_1_s_ahb_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_s0_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_2x_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "CLOCK",
- Package (0x02)
- {
- "gcc_qupv3_wrap1_core_clk",
- 0x02
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_BLSP_2",
- "ICBID_SLAVE_EBI1",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "BUSARB",
- Package (0x05)
- {
- 0x03,
- "ICBID_MASTER_APPSS_PROC",
- "ICBID_SLAVE_BLSP_2",
- Zero,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x41,
- Zero,
- 0x02,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x42,
- Zero,
- 0x02,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x43,
- Zero,
- 0x02,
- Zero,
- One,
- Zero
- }
- },
-
- Package (0x02)
- {
- "TLMMGPIO",
- Package (0x06)
- {
- 0x44,
- Zero,
- 0x02,
- Zero,
- One,
- Zero
- }
- }
- }
- }
- })
- }
-
- Device (RPEN)
- {
- Name (_HID, "QCOM026D") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- }
-
- Device (PILC)
- {
- Name (_HID, "QCOM023B") // _HID: Hardware ID
- Method (PILX, 0, NotSerialized)
- {
- Return (PILP) /* \_SB_.PILC.PILP */
- }
-
- Name (PILP, Package (0x01)
- {
- "OPCA"
- })
- Method (ACPO, 0, NotSerialized)
- {
- Name (PKGG, Package (0x01)
- {
- Package (0x03)
- {
- Zero,
- Zero,
- ToUUID ("ba58766d-abf2-4402-88d7-90ab243f6c77") /* Unknown UUID */
- }
- })
- DerefOf (PKGG [Zero]) [Zero] = RMTB /* \_SB_.RMTB */
- DerefOf (PKGG [Zero]) [One] = RMTX /* \_SB_.RMTX */
- Return (PKGG) /* \_SB_.PILC.ACPO.PKGG */
- }
- }
-
- Device (CDI)
- {
- Name (_DEP, Package (0x02) // _DEP: Dependencies
- {
- PILC,
- RPEN
- })
- Name (_HID, "QCOM026C") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
- }
-
- Device (SCSS)
- {
- Name (_DEP, Package (0x06) // _DEP: Dependencies
- {
- PEP0,
- PILC,
- GLNK,
- IPC0,
- RPEN,
- SSDD
- })
- Name (_HID, "QCOM02BE") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000199,
- }
- })
- Return (RBUF) /* \_SB_.SCSS._CRS.RBUF */
- }
-
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
- }
-
- Device (ADSP)
- {
- Name (_DEP, Package (0x07) // _DEP: Dependencies
- {
- PEP0,
- PILC,
- GLNK,
- IPC0,
- RPEN,
- SSDD,
- PDSR
- })
- Name (_HID, "QCOM023D") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Method (WDIR, 0, NotSerialized)
- {
- Return (Package (0x04)
- {
- 0x02,
- 0x17A0011C,
- 0x17A0019C,
- 0x17A0021C
- })
- }
-
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000C2,
- }
- })
- Return (RBUF) /* \_SB_.ADSP._CRS.RBUF */
- }
-
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Device (SLM1)
- {
- Name (_ADR, Zero) // _ADR: Address
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Name (_SUB, "RENEGA0E") // _SUB: Subsystem ID
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x171C0000, // Address Base
- 0x0002C000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000000C3,
- }
- })
- Return (RBUF) /* \_SB_.ADSP.SLM1._CRS.RBUF */
- }
-
- Method (CHLD, 0, NotSerialized)
- {
- Return (Package (0x01)
- {
- "SLM1\\QCOM023F"
- })
- }
-
- Device (ADCM)
- {
- Name (_SUB, "RENEGA0E") // _SUB: Subsystem ID
- Name (_ADR, Zero) // _ADR: Address
- Name (_DEP, Package (0x02) // _DEP: Dependencies
- {
- MMU0,
- IMM0
- })
- Method (CHLD, 0, NotSerialized)
- {
- Return (Package (0x01)
- {
- "ADCM\\QCOM0240"
- })
- }
-
- Device (AUDD)
- {
- Name (_ADR, Zero) // _ADR: Address
- Name (_SUB, "RENEGA0E") // _SUB: Subsystem ID
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- SPI9
- })
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- GpioIo (Exclusive, PullNone, 0x0000, 0x0640, IoRestrictionNone,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x0040
- }
- GpioInt (Edge, ActiveHigh, Exclusive, PullDown, 0x0000,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x0100
- }
- SpiSerialBusV2 (0x0000, PolarityLow, FourWireMode, 0x08,
- ControllerInitiated, 0x016E3600, ClockPolarityLow,
- ClockPhaseFirst, "\\_SB.SPI9",
- 0x00, ResourceConsumer, , Exclusive,
- RawDataBuffer (0x07) // Vendor Data
- {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- })
- })
- Return (RBUF) /* \_SB_.ADSP.SLM1.ADCM.AUDD._CRS.RBUF */
- }
-
- Method (CHLD, 0, NotSerialized)
- {
- Name (CH, Package (0x02)
- {
- "AUDD\\SAMM0803",
- "AUDD\\SAMM0801"
- })
- Return (CH) /* \_SB_.ADSP.SLM1.ADCM.AUDD.CHLD.CH__ */
- }
-
- Device (MBHC)
- {
- Name (_ADR, Zero) // _ADR: Address
- Name (_SUB, "RENEGA0E") // _SUB: Subsystem ID
- }
-
- Device (QCRT)
- {
- Name (_ADR, One) // _ADR: Address
- Name (_SUB, "RENEGA0E") // _SUB: Subsystem ID
- }
- }
- }
- }
-
- Device (SLM2)
- {
- Name (_ADR, One) // _ADR: Address
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x17240000, // Address Base
- 0x0002C000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000143,
- }
- })
- Return (RBUF) /* \_SB_.ADSP.SLM2._CRS.RBUF */
- }
- }
- }
-
- Device (AMSS)
- {
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Name (_DEP, Package (0x09) // _DEP: Dependencies
- {
- PEP0,
- IPA,
- GLNK,
- IPC0,
- PILC,
- RFS0,
- RPEN,
- SSDD,
- PDSR
- })
- Name (_HID, "QCOM023E") // _HID: Hardware ID
- Name (WLEN, One)
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000012A,
- }
- })
- Return (RBUF) /* \_SB_.AMSS._CRS.RBUF */
- }
-
- Method (WDIR, 0, NotSerialized)
- {
- Return (Package (0x04)
- {
- Zero,
- 0x17A0013C,
- 0x17A001BC,
- 0x17A002BC
- })
- }
-
- Device (QWLN)
- {
- Name (_ADR, Zero) // _ADR: Address
- Name (_DEP, Package (0x02) // _DEP: Dependencies
- {
- PEP0,
- MMU0
- })
- Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
- {
- Zero,
- Zero
- })
- Name (_S0W, 0x02) // _S0W: S0 Device Wake State
- Name (_S4W, 0x02) // _S4W: S4 Device Wake State
- Name (_PRR, Package (0x01) // _PRR: Power Resource for Reset
- {
- WRST
- })
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x18800000, // Address Base
- 0x00800000, // Address Length
- )
- Memory32Fixed (ReadWrite,
- 0x0C250000, // Address Base
- 0x00000010, // Address Length
- )
- Memory32Fixed (ReadWrite,
- 0x8E300000, // Address Base
- 0x00100000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000001BE,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000001BF,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, ,, )
- {
- 0x000001C0,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000001C1,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000001C2,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000001C3,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000001C4,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000001C5,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000001C6,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000001C7,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000001C8,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000001C9,
- }
- })
- Return (RBUF) /* \_SB_.AMSS.QWLN._CRS.RBUF */
- }
-
- Method (WMSA, 0, NotSerialized)
- {
- Return (Package (0x01)
- {
- 0x00100000
- })
- }
-
- OperationRegion (WOPR, 0x80, Zero, 0x10)
- Field (WOPR, DWordAcc, NoLock, Preserve)
- {
- Offset (0x04),
- WTRG, 32
- }
-
- PowerResource (WRST, 0x05, 0x0000)
- {
- Method (_ON, 0, NotSerialized) // _ON_: Power On
- {
- }
-
- Method (_OFF, 0, NotSerialized) // _OFF: Power Off
- {
- }
-
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Method (_RST, 0, NotSerialized) // _RST: Device Reset
- {
- WTRG = 0xABCD
- }
- }
- }
-
- Scope (\_SB)
- {
- Device (COEX)
- {
- Name (_HID, "QCOM0295") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- }
-
- Device (WSAR)
- {
- Name (_HID, "SAM0609") // _HID: Hardware ID
- Name (_UID, Zero) // _UID: Unique ID
- Name (_SUB, "RENEGA0E") // _SUB: Subsystem ID
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- ^AMSS.QWLN
- })
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
- }
- }
- }
-
- Device (QSM)
- {
- Name (_HID, "QCOM02B9") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_DEP, Package (0x04) // _DEP: Dependencies
- {
- GLNK,
- IPC0,
- PILC,
- RPEN
- })
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x98F00000, // Address Base
- 0x00600000, // Address Length
- )
- })
- Return (RBUF) /* \_SB_.QSM_._CRS.RBUF */
- }
-
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
- }
-
- Device (SSDD)
- {
- Name (_HID, "QCOM02D1") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_DEP, Package (0x02) // _DEP: Dependencies
- {
- GLNK,
- TFTP
- })
- }
-
- Device (PDSR)
- {
- Name (_HID, "QCOM02CE") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_DEP, Package (0x03) // _DEP: Dependencies
- {
- PEP0,
- GLNK,
- IPC0
- })
- }
-
- Device (CDSP)
- {
- Name (_DEP, Package (0x07) // _DEP: Dependencies
- {
- PEP0,
- PILC,
- GLNK,
- IPC0,
- RPEN,
- SSDD,
- PDSR
- })
- Name (_HID, "QCOM02F7") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000262,
- }
- })
- Return (RBUF) /* \_SB_.CDSP._CRS.RBUF */
- }
- }
-
- Device (TFTP)
- {
- Name (_HID, "QCOM02F6") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- IPC0
- })
- }
-
- Scope (PILC)
- {
- Method (_SUB, 0, NotSerialized) // _SUB: Subsystem ID
- {
- If ((SOID == 0x0155))
- {
- Return ("CLSA0850")
- }
- Else
- {
- Return (PSUB) /* \_SB_.PSUB */
- }
- }
- }
-
- Scope (AMSS)
- {
- Method (_SUB, 0, NotSerialized) // _SUB: Subsystem ID
- {
- If ((SOID == 0x0155))
- {
- Return ("CLSA0850")
- }
- Else
- {
- Return (PSUB) /* \_SB_.PSUB */
- }
- }
- }
-
- Device (LLC)
- {
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PEP0
- })
- Name (_HID, "QCOM02F8") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Return (ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x01300000, // Address Base
- 0x00028000, // Address Length
- )
- })
- }
- }
-
- Device (MMU0)
- {
- Name (_HID, "QCOM0212") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- MMU1
- })
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Return (ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x15000000, // Address Base
- 0x0007FFB8, // Address Length
- )
- Memory32Fixed (ReadWrite,
- 0x01F46000, // Address Base
- 0x00000004, // Address Length
- )
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000080,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000081,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000082,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000083,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000084,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000085,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000086,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000087,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000088,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000089,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000008A,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000008B,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000008C,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000008D,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000008E,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000008F,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000090,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000091,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000092,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000093,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000094,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000095,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000096,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000D5,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000D6,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000D7,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000D8,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000D9,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000DA,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000DB,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000DC,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000DD,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000DE,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000DF,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000E0,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000015B,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000015C,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000015D,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000015E,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000015F,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000160,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000161,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000162,
- }
- })
- }
- }
-
- Device (MMU1)
- {
- Name (_HID, "QCOM0212") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, One) // _UID: Unique ID
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PEP0
- })
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Return (ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x05040000, // Address Base
- 0x00010000, // Address Length
- )
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000018C,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000018D,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000018E,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000018F,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000190,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000191,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000192,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000193,
- }
- })
- }
- }
-
- Device (IMM0)
- {
- Name (_HID, "QCOM030B") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- }
-
- Device (IMM1)
- {
- Name (_HID, "QCOM030B") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, One) // _UID: Unique ID
- }
-
- Device (GPU0)
- {
- Name (_HID, "QCOM027E") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_CID, "ACPIQCOM027E") // _CID: Compatible ID
- Name (_UID, Zero) // _UID: Unique ID
- Name (_HRV, 0x7C) // _HRV: Hardware Revision
- Device (MON0)
- {
- Method (_ADR, 0, NotSerialized) // _ADR: Address
- {
- Return (Zero)
- }
- }
-
- Name (_DEP, Package (0x0A) // _DEP: Dependencies
- {
- MMU0,
- MMU1,
- IMM0,
- IMM1,
- PEP0,
- PMIC,
- PILC,
- RPEN,
- TREE,
- SCM0
- })
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x0AE00000, // Address Base
- 0x00140000, // Address Length
- )
- Memory32Fixed (ReadWrite,
- 0x088E0000, // Address Base
- 0x000F4000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000073,
- }
- Memory32Fixed (ReadWrite,
- 0x05000000, // Address Base
- 0x0003F010, // Address Length
- )
- Memory32Fixed (ReadWrite,
- 0x05060000, // Address Base
- 0x0003F000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x0000014C,
- }
- Memory32Fixed (ReadWrite,
- 0x0B280000, // Address Base
- 0x0000FFFF, // Address Length
- )
- Memory32Fixed (ReadWrite,
- 0x0B480000, // Address Base
- 0x00010000, // Address Length
- )
- Memory32Fixed (ReadWrite,
- 0x05090000, // Address Base
- 0x00009000, // Address Length
- )
- Memory32Fixed (ReadWrite,
- 0x0C200000, // Address Base
- 0x0000FFFF, // Address Length
- )
- Memory32Fixed (ReadWrite,
- 0x0AA00000, // Address Base
- 0x00200000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000000CE,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x000000CF,
- }
- GpioIo (Shared, PullUp, 0x0000, 0x0000, IoRestrictionNone,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x0060
- }
- })
- Return (RBUF) /* \_SB_.GPU0._CRS.RBUF */
- }
-
- Method (RESI, 0, NotSerialized)
- {
- Name (RINF, Package (0x10)
- {
- 0x03,
- Zero,
- Package (0x03)
- {
- "RESOURCE",
- "MDP_REGS",
- "DISPLAY"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "DP_PHY_REGS",
- "DISPLAY"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "VSYNC_INTERRUPT",
- "DISPLAY"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "GFX_REGS",
- "GRAPHICS"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "GFX_REG_CONT",
- "GRAPHICS"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "GFX_INTERRUPT",
- "GRAPHICS"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "GPU_PDC_SEQ_MEM",
- "GRAPHICS"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "GPU_PDC_REGS",
- "GRAPHICS"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "GPU_CC",
- "GRAPHICS"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "GPU_RPMH_CPRF",
- "GRAPHICS"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "VIDEO_REGS",
- "VIDEO"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "VIDC_INTERRUPT",
- "VIDEO"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "VIDC_WD_INTERRUPT",
- "VIDEO"
- },
-
- Package (0x03)
- {
- "RESOURCE",
- "DSI_PANEL_RESET",
- "DISPLAY"
- }
- })
- Return (RINF) /* \_SB_.GPU0.RESI.RINF */
- }
-
- Method (ENGS, 0, NotSerialized)
- {
- Name (EBUF, Package (0x06)
- {
- 0x03,
- 0x02,
- 0x003B0014,
- Package (0x07)
- {
- "ENGINES",
- 0x05,
- Package (0x0A)
- {
- "ENGINE",
- "GRAPHICS",
- "Adreno6X",
- One,
- 0x02,
- Zero,
- Package (0x0B)
- {
- "MMUINFO",
- "Miniport",
- "ArmSmmuV2",
- 0x02,
- 0x31,
- "V8L",
- "SMMUID",
- ToUUID ("9833c712-3292-4ffb-b0f4-2bd20e1f7f66") /* Unknown UUID */,
- "SMMUINTERFACEID",
- Buffer (0x10)
- {
- /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
- /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // ........
- },
-
- Package (0x0E)
- {
- "PAGETABLEUSAGE",
- 0x04,
- "GraphicsGlobalPT",
- Zero,
- 0x03030000,
- "GraphicsPerProcessPT",
- Zero,
- 0x03030000,
- "GraphicsSecurePT",
- One,
- 0x030A0000,
- "GraphicsGmuPT",
- 0x03,
- 0x03030002
- }
- },
-
- Package (0x04)
- {
- "PERF_CONTROLS",
- Package (0x01)
- {
- One
- },
-
- Package (0x02)
- {
- 0x03,
- Package (0x02)
- {
- "LimitForPassiveCooling",
- One
- }
- },
-
- Package (0x02)
- {
- 0x04,
- Package (0x02)
- {
- "LimitForPassiveCooling",
- One
- }
- }
- },
-
- Package (0x02)
- {
- "THERMAL_DOMAINS",
- "GPU"
- },
-
- Package (0x05)
- {
- "PROPERTIES",
- 0x03,
- Package (0x02)
- {
- "GmemBaseAddr",
- Zero
- },
-
- Package (0x02)
- {
- "GmemSize",
- 0x00100000
- },
-
- Package (0x02)
- {
- "SMMUCount",
- One
- }
- }
- },
-
- Package (0x09)
- {
- "ENGINE",
- "MDPBLT",
- "MDP5.x",
- 0x02,
- One,
- Zero,
- Package (0x02)
- {
- "SHAREDSMMU",
- "ROTATOR"
- },
-
- Package (0x03)
- {
- "PERF_CONTROLS",
- Package (0x02)
- {
- 0x02,
- Package (0x02)
- {
- "LimitForPassiveCooling",
- One
- }
- },
-
- Package (0x02)
- {
- 0x03,
- Package (0x02)
- {
- "LimitForPassiveCooling",
- One
- }
- }
- },
-
- Package (0x02)
- {
- "THERMAL_DOMAINS",
- "GPU"
- }
- },
-
- Package (0x09)
- {
- "ENGINE",
- "ROTATOR",
- "MDP5.x",
- 0x03,
- One,
- Zero,
- Package (0x0B)
- {
- "MMUINFO",
- "Miniport",
- "ArmSmmuV2",
- 0x02,
- 0x20,
- "V7S",
- "SMMUID",
- ToUUID ("36079ae4-78e8-452d-af50-0cff78b2f1ca") /* Unknown UUID */,
- "SMMUINTERFACEID",
- Buffer (0x10)
- {
- /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
- /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // ........
- },
-
- Package (0x04)
- {
- "PAGETABLEUSAGE",
- 0x02,
- "MdpNonSecurePT",
- "MdpSecurePT"
- }
- },
-
- Package (0x03)
- {
- "PERF_CONTROLS",
- Package (0x02)
- {
- 0x02,
- Package (0x02)
- {
- "LimitForPassiveCooling",
- One
- }
- },
-
- Package (0x02)
- {
- 0x03,
- Package (0x02)
- {
- "LimitForPassiveCooling",
- One
- }
- }
- },
-
- Package (0x02)
- {
- "THERMAL_DOMAINS",
- "GPU"
- }
- },
-
- Package (0x0A)
- {
- "ENGINE",
- "VIDEO",
- "Venus",
- 0x04,
- One,
- Zero,
- Package (0x0B)
- {
- "MMUINFO",
- "Engine",
- "ArmSmmuV2",
- 0x02,
- 0x20,
- "V7S",
- "SMMUID",
- ToUUID ("665e0f8e-add3-49d1-91bc-5540c5f57fba") /* Unknown UUID */,
- "SMMUINTERFACEID",
- ToUUID ("1c3fc0e8-0b11-4ee0-be89-3e21420a865f") /* Unknown UUID */,
- Package (0x07)
- {
- "PAGETABLEUSAGE",
- 0x05,
- "VideoNonSecurePT",
- "VideoSecurePT1",
- "VideoSecurePT2",
- "VideoSecurePT3",
- "VideoSecurePT4"
- }
- },
-
- Package (0x03)
- {
- "PERF_CONTROLS",
- Package (0x01)
- {
- 0x02
- },
-
- Package (0x01)
- {
- 0x03
- }
- },
-
- Package (0x01)
- {
- "THERMAL_DOMAINS"
- },
-
- Package (0x03)
- {
- "PROPERTIES",
- One,
- Package (0x02)
- {
- "DecMaxFps",
- 0x3C
- }
- }
- },
-
- Package (0x08)
- {
- "ENGINE",
- "VIDEO_ENCODER",
- "Venus",
- 0x06,
- One,
- Zero,
- Package (0x03)
- {
- "PERF_CONTROLS",
- Package (0x01)
- {
- 0x02
- },
-
- Package (0x01)
- {
- 0x03
- }
- },
-
- Package (0x01)
- {
- "THERMAL_DOMAINS"
- }
- }
- },
-
- Package (0x07)
- {
- "DISPLAYS",
- "MDP5.x",
- 0x02,
- Package (0x07)
- {
- "DISPLAY",
- "INTERNAL1",
- Zero,
- One,
- Zero,
- Package (0x04)
- {
- "PERF_CONTROLS",
- Package (0x01)
- {
- 0x02
- },
-
- Package (0x01)
- {
- 0x03
- },
-
- Package (0x01)
- {
- 0x04
- }
- },
-
- Package (0x01)
- {
- "THERMAL_DOMAINS"
- }
- },
-
- Package (0x07)
- {
- "DISPLAY",
- "INTERNAL2",
- 0x07,
- One,
- Zero,
- Package (0x04)
- {
- "PERF_CONTROLS",
- Package (0x01)
- {
- 0x02
- },
-
- Package (0x01)
- {
- 0x03
- },
-
- Package (0x01)
- {
- 0x04
- }
- },
-
- Package (0x01)
- {
- "THERMAL_DOMAINS"
- }
- },
-
- Package (0x02)
- {
- "RESOURCES",
- Package (0x0B)
- {
- "MMUINFO",
- "Miniport",
- "ArmSmmuV2",
- 0x02,
- 0x20,
- "V7S",
- "SMMUID",
- ToUUID ("36079ae4-78e8-452d-af50-0cff78b2f1ca") /* Unknown UUID */,
- "SMMUINTERFACEID",
- Buffer (0x10)
- {
- /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
- /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // ........
- },
-
- Package (0x04)
- {
- "PAGETABLEUSAGE",
- 0x02,
- "MdpNonSecurePT",
- "MdpSecurePT"
- }
- }
- },
-
- Package (0x0F)
- {
- "PRIMARY_SOURCE_MODES",
- 0x0D,
- Package (0x02)
- {
- 0x0280,
- 0x01E0
- },
-
- Package (0x02)
- {
- 0x0320,
- 0x0258
- },
-
- Package (0x02)
- {
- 0x0500,
- 0x02D0
- },
-
- Package (0x02)
- {
- 0x0400,
- 0x0300
- },
-
- Package (0x02)
- {
- 0x0480,
- 0x0300
- },
-
- Package (0x02)
- {
- 0x0500,
- 0x0300
- },
-
- Package (0x02)
- {
- 0x0550,
- 0x0300
- },
-
- Package (0x02)
- {
- 0x0556,
- 0x0300
- },
-
- Package (0x02)
- {
- 0x0640,
- 0x0384
- },
-
- Package (0x02)
- {
- 0x0500,
- 0x0400
- },
-
- Package (0x02)
- {
- 0x0780,
- 0x0438
- },
-
- Package (0x02)
- {
- 0x0780,
- 0x04B0
- },
-
- Package (0x02)
- {
- 0x0780,
- 0x0500
- }
- }
- },
-
- Package (0x0F)
- {
- "PAGETABLES",
- 0x0D,
- Package (0x07)
- {
- "GraphicsGlobalPT",
- One,
- Zero,
- One,
- One,
- 0x0000008000000000,
- 0x0000000800000000
- },
-
- Package (0x07)
- {
- "GraphicsPerProcessPT",
- Zero,
- Zero,
- Zero,
- Zero,
- 0x00400000,
- 0x0000007FFFC00000
- },
-
- Package (0x07)
- {
- "GraphicsSecurePT",
- Zero,
- One,
- Zero,
- One,
- 0x0000008800000000,
- 0xC0000000
- },
-
- Package (0x07)
- {
- "GraphicsGmuPT",
- Zero,
- Zero,
- Zero,
- Zero,
- 0x60000000,
- 0x20000000
- },
-
- Package (0x07)
- {
- "MdpNonSecurePT",
- Zero,
- Zero,
- Zero,
- Zero,
- 0x80100000,
- 0x7FF00000
- },
-
- Package (0x07)
- {
- "MdpSecurePT",
- Zero,
- One,
- Zero,
- One,
- 0x80000000,
- 0x80000000
- },
-
- Package (0x09)
- {
- "VideoNonSecurePT",
- Zero,
- Zero,
- Zero,
- One,
- 0x00100000,
- 0xBFF00000,
- 0x1B,
- Zero
- },
-
- Package (0x09)
- {
- "VideoSecurePT1",
- Zero,
- One,
- Zero,
- One,
- 0xC0000000,
- 0x10000000,
- 0x09,
- One
- },
-
- Package (0x09)
- {
- "VideoSecurePT2",
- Zero,
- One,
- Zero,
- One,
- 0xD0000000,
- 0x10000000,
- 0x07,
- 0x02
- },
-
- Package (0x09)
- {
- "VideoSecurePT3",
- Zero,
- One,
- Zero,
- One,
- 0xE0000000,
- 0x10000000,
- 0x02,
- 0x03
- },
-
- Package (0x09)
- {
- "VideoSecurePT4",
- Zero,
- One,
- Zero,
- One,
- 0xF0000000,
- 0x10000000,
- 0x2A,
- 0x04
- },
-
- Package (0x07)
- {
- "CryptoNonSecurePT",
- Zero,
- Zero,
- Zero,
- Zero,
- 0x00100000,
- 0x7FF00000
- },
-
- Package (0x07)
- {
- "CryptoSecurePT",
- Zero,
- One,
- Zero,
- One,
- 0x80000000,
- 0x80000000
- }
- }
- })
- Return (EBUF) /* \_SB_.GPU0.ENGS.EBUF */
- }
-
- Method (TMDT, 0, NotSerialized)
- {
- Name (RBUF, Package (0x03)
- {
- One,
- Zero,
- Package (0x03)
- {
- "THERMAL_DOMAINS",
- One,
- Package (0x03)
- {
- "GPU",
- "GPU0",
- Package (0x03)
- {
- "GRAPHICS",
- "MDPBLT",
- "ROTATOR"
- }
- }
- }
- })
- Return (RBUF) /* \_SB_.GPU0.TMDT.RBUF */
- }
-
- Method (PMCL, 0, NotSerialized)
- {
- Name (RBUF, Package (0x0D)
- {
- 0x03,
- One,
- 0x0A,
- Package (0x0F)
- {
- "COMPONENT",
- Zero,
- ToUUID ("2c135991-4391-4633-90b1-fa96f2e2cc04") /* Unknown UUID */,
- "PRIMDISPLAY_POWER_STATES",
- "HW_BLOCK_MDP",
- Package (0x02)
- {
- "DISPLAY",
- "INTERNAL1"
- },
-
- 0x02,
- 0x05,
- Package (0x06)
- {
- "FSTATE",
- Zero,
- "ALL_ON",
- Zero,
- Zero,
- 0x02
- },
-
- Package (0x06)
- {
- "FSTATE",
- One,
- "PWR_OFF",
- One,
- One,
- One
- },
-
- Package (0x0A)
- {
- "PSTATE_SET",
- Zero,
- "INTERNAL1_RESET",
- "*",
- "RESET",
- 0x02,
- Zero,
- Zero,
- Package (0x04)
- {
- "PSTATE",
- Zero,
- One,
- 0x02
- },
-
- Package (0x04)
- {
- "PSTATE",
- One,
- Zero,
- 0x02
- }
- },
-
- Package (0x0A)
- {
- "PSTATE_SET",
- One,
- "INTERNAL1_FOOTSWITCH_OVERRIDE",
- "*",
- "FOOTSWITCH_OVERRIDE",
- 0x02,
- 0xFFFFFFFF,
- Zero,
- Package (0x04)
- {
- "PSTATE",
- Zero,
- One,
- 0x02
- },
-
- Package (0x04)
- {
- "PSTATE",
- One,
- Zero,
- 0x02
- }
- },
-
- Package (0x0D)
- {
- "PSTATE_SET",
- 0x02,
- "INTERNAL1_SCAN_CONTROL",
- "*",
- "DISPLAY_SOURCE_SCAN_CTRL",
- 0x05,
- Zero,
- Zero,
- Package (0x04)
- {
- "PSTATE",
- Zero,
- 0x04,
- 0x02
- },
-
- Package (0x04)
- {
- "PSTATE",
- One,
- 0x03,
- 0x02
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x02,
- 0x02,
- 0x02
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x03,
- One,
- 0x02
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x04,
- Zero,
- 0x02
- }
- },
-
- Package (0x15)
- {
- "PSTATE_SET",
- 0x03,
- "INTERNAL1_CORE_CLOCK_CONTROL",
- "*",
- "CORE_CLOCK",
- 0x0D,
- 0x04,
- Zero,
- Package (0x04)
- {
- "PSTATE",
- Zero,
- 0x19A14780,
- One
- },
-
- Package (0x04)
- {
- "PSTATE",
- One,
- 0x18964020,
- One
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x02,
- 0x14810600,
- 0x02
- },
-
- Package (0x04)
- {
- "PSTATE",
- 0x03,
- 0x11E1A300,
- 0x02
- },
-
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- Zero
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- {
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- Zero
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- {
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- Zero
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-
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- {
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- Zero
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-
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- {
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- One
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-
- Package (0x04)
- {
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- One
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- {
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- Zero,
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-
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- {
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- ToUUID ("cc4d73fa-c3c2-4c7e-a217-d468f4611bbd") /* Unknown UUID */,
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- {
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-
- 0x02,
- 0x03,
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- {
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- Zero,
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- Zero,
- Zero,
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-
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- {
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- One,
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- Zero,
- One
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-
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- {
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- Zero,
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- 0x02,
- Zero,
- Zero,
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- {
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-
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- {
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- Zero,
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-
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- One,
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- 0x02,
- One,
- Zero,
- Package (0x04)
- {
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- 0x02
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-
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- Zero,
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- {
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- "*",
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- One,
- Zero,
- Zero,
- Package (0x04)
- {
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- Zero,
- Zero
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-
- Package (0x10)
- {
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- ToUUID ("e6be5096-55ec-4891-884b-0760bfc533b6") /* Unknown UUID */,
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-
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- 0x04,
- Package (0x06)
- {
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- Zero,
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- Zero,
- Zero,
- 0x03
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-
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- {
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- Zero,
- 0x02
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-
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- {
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- 0x000186A0,
- Zero,
- One
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- {
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- Zero,
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- 0x02,
- Zero,
- Zero,
- Package (0x04)
- {
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- One,
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-
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- Zero,
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- One,
- Zero,
- Package (0x04)
- {
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- Zero,
- One,
- 0x02
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-
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- {
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- Zero,
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-
- Package (0x0F)
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- 0x02,
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- 0x07,
- 0x04,
- Zero,
- Package (0x04)
- {
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- 0x1FC4EF40,
- Zero
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-
- Package (0x04)
- {
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- One
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- 0x05F5E100,
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- {
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- ToUUID ("818daed2-9e63-49d5-bd12-b0951f7b0f6b") /* Unknown UUID */,
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- {
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-
- 0x02,
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- Zero,
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- One,
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- One
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- })
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- One,
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- 0x03,
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- {
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- Zero,
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- {
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- One,
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- }
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- {
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- 0x02,
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- {
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- },
-
- Package (0x01)
- {
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- }
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-
- Package (0x06)
- {
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- 0x1EFE9200,
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- {
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-
- Package (0x01)
- {
- 0x0100
- }
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-
- Package (0x06)
- {
- "PSTATE",
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- 0x18AD2380,
- 0x04,
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- {
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-
- Package (0x01)
- {
- 0xC0
- }
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-
- Package (0x06)
- {
- "PSTATE",
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- 0x14628180,
- 0x05,
- Package (0x02)
- {
- "GPU",
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- },
-
- Package (0x01)
- {
- 0x80
- }
- },
-
- Package (0x06)
- {
- "PSTATE",
- 0x06,
- 0x0EB8EBC0,
- 0x06,
- Package (0x02)
- {
- "GPU",
- 0x23
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-
- Package (0x01)
- {
- 0x40
- }
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-
- Package (0x06)
- {
- "PSTATE",
- 0x07,
- 0x0ABA9500,
- 0x07,
- Package (0x02)
- {
- "GPU",
- Zero
- },
-
- Package (0x01)
- {
- 0x30
- }
- },
-
- Package (0x06)
- {
- "PSTATE",
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- Zero,
- 0x08,
- Package (0x02)
- {
- "GPU",
- Zero
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-
- Package (0x01)
- {
- Zero
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- }
- })
- Name (P002, Package (0x0B)
- {
- "ENGINE_PSTATE_SET",
- 0x03,
- "GRAPHICS_FREQ_CONTROL",
- "CORE_CLOCK",
- 0x02,
- One,
- "TRUE",
- Zero,
- Zero,
- Package (0x06)
- {
- "PSTATE",
- Zero,
- 0x10B07600,
- Zero,
- Package (0x02)
- {
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- Zero
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-
- Package (0x01)
- {
- 0x80
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-
- Package (0x06)
- {
- "PSTATE",
- One,
- Zero,
- One,
- Package (0x02)
- {
- "GPU",
- Zero
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-
- Package (0x01)
- {
- Zero
- }
- }
- })
- If ((SIDV >= 0x00020000))
- {
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- Else
- {
- DerefOf (RBUF [0x04]) [0x0E] = P002 /* \_SB_.GPU0.PMCL.P002 */
- }
-
- Return (RBUF) /* \_SB_.GPU0.PMCL.RBUF */
- }
-
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- {
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- /* 0118 */ 0x50, 0x6F, 0x72, 0x63, 0x68, 0x3E, 0x0A, 0x20, // Porch>.
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- /* 0158 */ 0x72, 0x69, 0x7A, 0x6F, 0x6E, 0x74, 0x61, 0x6C, // rizontal
- /* 0160 */ 0x53, 0x79, 0x6E, 0x63, 0x50, 0x75, 0x6C, 0x73, // SyncPuls
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- /* 0170 */ 0x72, 0x69, 0x7A, 0x6F, 0x6E, 0x74, 0x61, 0x6C, // rizontal
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- /* 0640 */ 0x3C, 0x44, 0x53, 0x49, 0x4C, 0x6F, 0x77, 0x50, // <DSILowP
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- /* 0668 */ 0x4D, 0x6F, 0x64, 0x65, 0x49, 0x6E, 0x48, 0x53, // ModeInHS
- /* 0670 */ 0x41, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // A>. <
- /* 0678 */ 0x44, 0x53, 0x49, 0x4C, 0x6F, 0x77, 0x50, 0x6F, // DSILowPo
- /* 0680 */ 0x77, 0x65, 0x72, 0x4D, 0x6F, 0x64, 0x65, 0x49, // werModeI
- /* 0688 */ 0x6E, 0x42, 0x4C, 0x4C, 0x50, 0x45, 0x4F, 0x46, // nBLLPEOF
- /* 0690 */ 0x3E, 0x54, 0x72, 0x75, 0x65, 0x3C, 0x2F, 0x44, // >True</D
- /* 0698 */ 0x53, 0x49, 0x4C, 0x6F, 0x77, 0x50, 0x6F, 0x77, // SILowPow
- /* 06A0 */ 0x65, 0x72, 0x4D, 0x6F, 0x64, 0x65, 0x49, 0x6E, // erModeIn
- /* 06A8 */ 0x42, 0x4C, 0x4C, 0x50, 0x45, 0x4F, 0x46, 0x3E, // BLLPEOF>
- /* 06B0 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x44, 0x53, // . <DS
- /* 06B8 */ 0x49, 0x4C, 0x6F, 0x77, 0x50, 0x6F, 0x77, 0x65, // ILowPowe
- /* 06C0 */ 0x72, 0x4D, 0x6F, 0x64, 0x65, 0x49, 0x6E, 0x42, // rModeInB
- /* 06C8 */ 0x4C, 0x4C, 0x50, 0x3E, 0x54, 0x72, 0x75, 0x65, // LLP>True
- /* 06D0 */ 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x4C, 0x6F, 0x77, // </DSILow
- /* 06D8 */ 0x50, 0x6F, 0x77, 0x65, 0x72, 0x4D, 0x6F, 0x64, // PowerMod
- /* 06E0 */ 0x65, 0x49, 0x6E, 0x42, 0x4C, 0x4C, 0x50, 0x3E, // eInBLLP>
- /* 06E8 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x44, 0x53, // . <DS
- /* 06F0 */ 0x49, 0x4C, 0x50, 0x31, 0x31, 0x41, 0x74, 0x49, // ILP11AtI
- /* 06F8 */ 0x6E, 0x69, 0x74, 0x3E, 0x54, 0x72, 0x75, 0x65, // nit>True
- /* 0700 */ 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x4C, 0x50, 0x31, // </DSILP1
- /* 0708 */ 0x31, 0x41, 0x74, 0x49, 0x6E, 0x69, 0x74, 0x3E, // 1AtInit>
- /* 0710 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x44, 0x53, // . <DS
- /* 0718 */ 0x49, 0x43, 0x6F, 0x6E, 0x74, 0x72, 0x6F, 0x6C, // IControl
- /* 0720 */ 0x6C, 0x65, 0x72, 0x4D, 0x61, 0x70, 0x70, 0x69, // lerMappi
- /* 0728 */ 0x6E, 0x67, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, // ng>.
- /* 0730 */ 0x20, 0x20, 0x20, 0x20, 0x30, 0x30, 0x0A, 0x20, // 00.
- /* 0738 */ 0x20, 0x20, 0x20, 0x3C, 0x2F, 0x44, 0x53, 0x49, // </DSI
- /* 0740 */ 0x43, 0x6F, 0x6E, 0x74, 0x72, 0x6F, 0x6C, 0x6C, // Controll
- /* 0748 */ 0x65, 0x72, 0x4D, 0x61, 0x70, 0x70, 0x69, 0x6E, // erMappin
- /* 0750 */ 0x67, 0x3E, 0x0A, 0x3C, 0x2F, 0x47, 0x72, 0x6F, // g>.</Gro
- /* 0758 */ 0x75, 0x70, 0x3E, 0x0A, 0x3C, 0x44, 0x53, 0x49, // up>.<DSI
- /* 0760 */ 0x49, 0x6E, 0x69, 0x74, 0x53, 0x65, 0x71, 0x75, // InitSequ
- /* 0768 */ 0x65, 0x6E, 0x63, 0x65, 0x3E, 0x0A, 0x20, 0x31, // ence>. 1
- /* 0770 */ 0x35, 0x20, 0x46, 0x46, 0x20, 0x32, 0x34, 0x0A, // 5 FF 24.
- /* 0778 */ 0x20, 0x31, 0x35, 0x20, 0x39, 0x44, 0x20, 0x33, // 15 9D 3
- /* 0780 */ 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x46, 0x42, // 4. 15 FB
- /* 0788 */ 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, // 01. 15
- /* 0790 */ 0x43, 0x34, 0x20, 0x32, 0x35, 0x0A, 0x20, 0x31, // C4 25. 1
- /* 0798 */ 0x35, 0x20, 0x44, 0x31, 0x20, 0x30, 0x38, 0x0A, // 5 D1 08.
- /* 07A0 */ 0x20, 0x31, 0x35, 0x20, 0x44, 0x32, 0x20, 0x38, // 15 D2 8
- /* 07A8 */ 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x46, 0x46, // 4. 15 FF
- /* 07B0 */ 0x20, 0x32, 0x36, 0x0A, 0x20, 0x31, 0x35, 0x20, // 26. 15
- /* 07B8 */ 0x46, 0x42, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // FB 01. 1
- /* 07C0 */ 0x35, 0x20, 0x30, 0x33, 0x20, 0x31, 0x43, 0x0A, // 5 03 1C.
- /* 07C8 */ 0x20, 0x31, 0x35, 0x20, 0x33, 0x42, 0x20, 0x30, // 15 3B 0
- /* 07D0 */ 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x36, 0x42, // 8. 15 6B
- /* 07D8 */ 0x20, 0x30, 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, // 08. 15
- /* 07E0 */ 0x39, 0x37, 0x20, 0x30, 0x38, 0x0A, 0x20, 0x31, // 97 08. 1
- /* 07E8 */ 0x35, 0x20, 0x43, 0x35, 0x20, 0x30, 0x38, 0x0A, // 5 C5 08.
- /* 07F0 */ 0x20, 0x31, 0x35, 0x20, 0x46, 0x42, 0x20, 0x30, // 15 FB 0
- /* 07F8 */ 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x46, 0x46, // 1. 15 FF
- /* 0800 */ 0x20, 0x32, 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, // 23. 15
- /* 0808 */ 0x46, 0x42, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // FB 01. 1
- /* 0810 */ 0x35, 0x20, 0x30, 0x31, 0x20, 0x38, 0x34, 0x0A, // 5 01 84.
- /* 0818 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x35, 0x20, 0x32, // 15 05 2
- /* 0820 */ 0x44, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x36, // D. 15 06
- /* 0828 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0830 */ 0x33, 0x32, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 32 00. 1
- /* 0838 */ 0x35, 0x20, 0x31, 0x33, 0x20, 0x46, 0x46, 0x0A, // 5 13 FF.
- /* 0840 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x34, 0x20, 0x46, // 15 14 F
- /* 0848 */ 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x35, // 8. 15 15
- /* 0850 */ 0x20, 0x45, 0x44, 0x0A, 0x20, 0x31, 0x35, 0x20, // ED. 15
- /* 0858 */ 0x31, 0x36, 0x20, 0x45, 0x35, 0x0A, 0x20, 0x31, // 16 E5. 1
- /* 0860 */ 0x35, 0x20, 0x30, 0x39, 0x20, 0x30, 0x31, 0x0A, // 5 09 01.
- /* 0868 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x41, 0x20, 0x30, // 15 0A 0
- /* 0870 */ 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x42, // 1. 15 0B
- /* 0878 */ 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, // 01. 15
- /* 0880 */ 0x30, 0x43, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // 0C 01. 1
- /* 0888 */ 0x35, 0x20, 0x30, 0x44, 0x20, 0x30, 0x31, 0x0A, // 5 0D 01.
- /* 0890 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x45, 0x20, 0x30, // 15 0E 0
- /* 0898 */ 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x46, // 1. 15 0F
- /* 08A0 */ 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, // 01. 15
- /* 08A8 */ 0x31, 0x30, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // 10 01. 1
- /* 08B0 */ 0x35, 0x20, 0x31, 0x31, 0x20, 0x30, 0x31, 0x0A, // 5 11 01.
- /* 08B8 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x32, 0x20, 0x30, // 15 12 0
- /* 08C0 */ 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x37, // 1. 15 17
- /* 08C8 */ 0x20, 0x46, 0x46, 0x0A, 0x20, 0x31, 0x35, 0x20, // FF. 15
- /* 08D0 */ 0x31, 0x38, 0x20, 0x45, 0x45, 0x0A, 0x20, 0x31, // 18 EE. 1
- /* 08D8 */ 0x35, 0x20, 0x31, 0x39, 0x20, 0x44, 0x44, 0x0A, // 5 19 DD.
- /* 08E0 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x41, 0x20, 0x43, // 15 1A C
- /* 08E8 */ 0x37, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x42, // 7. 15 1B
- /* 08F0 */ 0x20, 0x41, 0x46, 0x0A, 0x20, 0x31, 0x35, 0x20, // AF. 15
- /* 08F8 */ 0x31, 0x43, 0x20, 0x39, 0x39, 0x0A, 0x20, 0x31, // 1C 99. 1
- /* 0900 */ 0x35, 0x20, 0x31, 0x44, 0x20, 0x39, 0x39, 0x0A, // 5 1D 99.
- /* 0908 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x45, 0x20, 0x38, // 15 1E 8
- /* 0910 */ 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x46, // 8. 15 1F
- /* 0918 */ 0x20, 0x37, 0x37, 0x0A, 0x20, 0x31, 0x35, 0x20, // 77. 15
- /* 0920 */ 0x32, 0x30, 0x20, 0x36, 0x36, 0x0A, 0x20, 0x31, // 20 66. 1
- /* 0928 */ 0x35, 0x20, 0x33, 0x33, 0x20, 0x30, 0x30, 0x0A, // 5 33 00.
- /* 0930 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x31, 0x20, 0x46, // 15 21 F
- /* 0938 */ 0x46, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x32, // F. 15 22
- /* 0940 */ 0x20, 0x46, 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, // F8. 15
- /* 0948 */ 0x32, 0x33, 0x20, 0x45, 0x46, 0x0A, 0x20, 0x31, // 23 EF. 1
- /* 0950 */ 0x35, 0x20, 0x32, 0x34, 0x20, 0x45, 0x37, 0x0A, // 5 24 E7.
- /* 0958 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x35, 0x20, 0x44, // 15 25 D
- /* 0960 */ 0x45, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x36, // E. 15 26
- /* 0968 */ 0x20, 0x44, 0x37, 0x0A, 0x20, 0x31, 0x35, 0x20, // D7. 15
- /* 0970 */ 0x32, 0x37, 0x20, 0x43, 0x44, 0x0A, 0x20, 0x31, // 27 CD. 1
- /* 0978 */ 0x35, 0x20, 0x32, 0x38, 0x20, 0x43, 0x34, 0x0A, // 5 28 C4.
- /* 0980 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x39, 0x20, 0x42, // 15 29 B
- /* 0988 */ 0x43, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x41, // C. 15 2A
- /* 0990 */ 0x20, 0x42, 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, // B3. 15
- /* 0998 */ 0x46, 0x46, 0x20, 0x32, 0x32, 0x0A, 0x20, 0x31, // FF 22. 1
- /* 09A0 */ 0x35, 0x20, 0x30, 0x30, 0x20, 0x30, 0x41, 0x0A, // 5 00 0A.
- /* 09A8 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x31, 0x20, 0x34, // 15 01 4
- /* 09B0 */ 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x32, // 3. 15 02
- /* 09B8 */ 0x20, 0x35, 0x42, 0x0A, 0x20, 0x31, 0x35, 0x20, // 5B. 15
- /* 09C0 */ 0x30, 0x33, 0x20, 0x36, 0x41, 0x0A, 0x20, 0x31, // 03 6A. 1
- /* 09C8 */ 0x35, 0x20, 0x30, 0x34, 0x20, 0x37, 0x41, 0x0A, // 5 04 7A.
- /* 09D0 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x35, 0x20, 0x38, // 15 05 8
- /* 09D8 */ 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x36, // 2. 15 06
- /* 09E0 */ 0x20, 0x38, 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, // 85. 15
- /* 09E8 */ 0x30, 0x37, 0x20, 0x38, 0x30, 0x0A, 0x20, 0x31, // 07 80. 1
- /* 09F0 */ 0x35, 0x20, 0x30, 0x38, 0x20, 0x37, 0x43, 0x0A, // 5 08 7C.
- /* 09F8 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x39, 0x20, 0x37, // 15 09 7
- /* 0A00 */ 0x43, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x41, // C. 15 0A
- /* 0A08 */ 0x20, 0x37, 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, // 74. 15
- /* 0A10 */ 0x30, 0x42, 0x20, 0x37, 0x31, 0x0A, 0x20, 0x31, // 0B 71. 1
- /* 0A18 */ 0x35, 0x20, 0x30, 0x43, 0x20, 0x36, 0x45, 0x0A, // 5 0C 6E.
- /* 0A20 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x44, 0x20, 0x36, // 15 0D 6
- /* 0A28 */ 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x45, // 8. 15 0E
- /* 0A30 */ 0x20, 0x36, 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, // 65. 15
- /* 0A38 */ 0x30, 0x46, 0x20, 0x35, 0x43, 0x0A, 0x20, 0x31, // 0F 5C. 1
- /* 0A40 */ 0x35, 0x20, 0x31, 0x30, 0x20, 0x33, 0x32, 0x0A, // 5 10 32.
- /* 0A48 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x31, 0x20, 0x31, // 15 11 1
- /* 0A50 */ 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x32, // 8. 15 12
- /* 0A58 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0A60 */ 0x31, 0x33, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 13 00. 1
- /* 0A68 */ 0x35, 0x20, 0x31, 0x41, 0x20, 0x30, 0x30, 0x0A, // 5 1A 00.
- /* 0A70 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x42, 0x20, 0x30, // 15 1B 0
- /* 0A78 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x43, // 0. 15 1C
- /* 0A80 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0A88 */ 0x31, 0x44, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 1D 00. 1
- /* 0A90 */ 0x35, 0x20, 0x31, 0x45, 0x20, 0x30, 0x30, 0x0A, // 5 1E 00.
- /* 0A98 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x46, 0x20, 0x30, // 15 1F 0
- /* 0AA0 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x30, // 0. 15 20
- /* 0AA8 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0AB0 */ 0x32, 0x31, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 21 00. 1
- /* 0AB8 */ 0x35, 0x20, 0x32, 0x32, 0x20, 0x30, 0x30, 0x0A, // 5 22 00.
- /* 0AC0 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x33, 0x20, 0x30, // 15 23 0
- /* 0AC8 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x34, // 0. 15 24
- /* 0AD0 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0AD8 */ 0x32, 0x35, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 25 00. 1
- /* 0AE0 */ 0x35, 0x20, 0x32, 0x36, 0x20, 0x30, 0x30, 0x0A, // 5 26 00.
- /* 0AE8 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x37, 0x20, 0x30, // 15 27 0
- /* 0AF0 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x38, // 0. 15 28
- /* 0AF8 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0B00 */ 0x32, 0x39, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 29 00. 1
- /* 0B08 */ 0x35, 0x20, 0x32, 0x41, 0x20, 0x30, 0x30, 0x0A, // 5 2A 00.
- /* 0B10 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x42, 0x20, 0x30, // 15 2B 0
- /* 0B18 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x46, // 0. 15 2F
- /* 0B20 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0B28 */ 0x33, 0x30, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 30 00. 1
- /* 0B30 */ 0x35, 0x20, 0x33, 0x31, 0x20, 0x30, 0x30, 0x0A, // 5 31 00.
- /* 0B38 */ 0x20, 0x31, 0x35, 0x20, 0x33, 0x32, 0x20, 0x30, // 15 32 0
- /* 0B40 */ 0x43, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x33, 0x33, // C. 15 33
- /* 0B48 */ 0x20, 0x30, 0x43, 0x0A, 0x20, 0x31, 0x35, 0x20, // 0C. 15
- /* 0B50 */ 0x33, 0x34, 0x20, 0x30, 0x43, 0x0A, 0x20, 0x31, // 34 0C. 1
- /* 0B58 */ 0x35, 0x20, 0x33, 0x35, 0x20, 0x30, 0x42, 0x0A, // 5 35 0B.
- /* 0B60 */ 0x20, 0x31, 0x35, 0x20, 0x33, 0x36, 0x20, 0x30, // 15 36 0
- /* 0B68 */ 0x39, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x33, 0x37, // 9. 15 37
- /* 0B70 */ 0x20, 0x30, 0x39, 0x0A, 0x20, 0x31, 0x35, 0x20, // 09. 15
- /* 0B78 */ 0x33, 0x38, 0x20, 0x30, 0x38, 0x0A, 0x20, 0x31, // 38 08. 1
- /* 0B80 */ 0x35, 0x20, 0x33, 0x39, 0x20, 0x30, 0x35, 0x0A, // 5 39 05.
- /* 0B88 */ 0x20, 0x31, 0x35, 0x20, 0x33, 0x41, 0x20, 0x30, // 15 3A 0
- /* 0B90 */ 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x33, 0x42, // 3. 15 3B
- /* 0B98 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0BA0 */ 0x33, 0x46, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 3F 00. 1
- /* 0BA8 */ 0x35, 0x20, 0x34, 0x30, 0x20, 0x30, 0x30, 0x0A, // 5 40 00.
- /* 0BB0 */ 0x20, 0x31, 0x35, 0x20, 0x34, 0x31, 0x20, 0x30, // 15 41 0
- /* 0BB8 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x34, 0x32, // 0. 15 42
- /* 0BC0 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0BC8 */ 0x34, 0x33, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 43 00. 1
- /* 0BD0 */ 0x35, 0x20, 0x34, 0x34, 0x20, 0x30, 0x30, 0x0A, // 5 44 00.
- /* 0BD8 */ 0x20, 0x31, 0x35, 0x20, 0x34, 0x35, 0x20, 0x30, // 15 45 0
- /* 0BE0 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x34, 0x36, // 0. 15 46
- /* 0BE8 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0BF0 */ 0x34, 0x37, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 47 00. 1
- /* 0BF8 */ 0x35, 0x20, 0x34, 0x38, 0x20, 0x30, 0x30, 0x0A, // 5 48 00.
- /* 0C00 */ 0x20, 0x31, 0x35, 0x20, 0x34, 0x39, 0x20, 0x30, // 15 49 0
- /* 0C08 */ 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x34, 0x41, // 3. 15 4A
- /* 0C10 */ 0x20, 0x30, 0x36, 0x0A, 0x20, 0x31, 0x35, 0x20, // 06. 15
- /* 0C18 */ 0x34, 0x42, 0x20, 0x30, 0x37, 0x0A, 0x20, 0x31, // 4B 07. 1
- /* 0C20 */ 0x35, 0x20, 0x34, 0x43, 0x20, 0x30, 0x37, 0x0A, // 5 4C 07.
- /* 0C28 */ 0x20, 0x31, 0x35, 0x20, 0x34, 0x44, 0x20, 0x30, // 15 4D 0
- /* 0C30 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x34, 0x45, // 0. 15 4E
- /* 0C38 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0C40 */ 0x34, 0x46, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 4F 00. 1
- /* 0C48 */ 0x35, 0x20, 0x35, 0x30, 0x20, 0x30, 0x30, 0x0A, // 5 50 00.
- /* 0C50 */ 0x20, 0x31, 0x35, 0x20, 0x35, 0x31, 0x20, 0x30, // 15 51 0
- /* 0C58 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x35, 0x32, // 0. 15 52
- /* 0C60 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0C68 */ 0x35, 0x33, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // 53 01. 1
- /* 0C70 */ 0x35, 0x20, 0x35, 0x34, 0x20, 0x30, 0x31, 0x0A, // 5 54 01.
- /* 0C78 */ 0x20, 0x31, 0x35, 0x20, 0x35, 0x35, 0x20, 0x38, // 15 55 8
- /* 0C80 */ 0x39, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x35, 0x36, // 9. 15 56
- /* 0C88 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0C90 */ 0x35, 0x38, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 58 00. 1
- /* 0C98 */ 0x35, 0x20, 0x36, 0x38, 0x20, 0x30, 0x30, 0x0A, // 5 68 00.
- /* 0CA0 */ 0x20, 0x31, 0x35, 0x20, 0x38, 0x34, 0x20, 0x46, // 15 84 F
- /* 0CA8 */ 0x46, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x38, 0x35, // F. 15 85
- /* 0CB0 */ 0x20, 0x46, 0x46, 0x0A, 0x20, 0x31, 0x35, 0x20, // FF. 15
- /* 0CB8 */ 0x38, 0x36, 0x20, 0x30, 0x33, 0x0A, 0x20, 0x31, // 86 03. 1
- /* 0CC0 */ 0x35, 0x20, 0x38, 0x37, 0x20, 0x30, 0x30, 0x0A, // 5 87 00.
- /* 0CC8 */ 0x20, 0x31, 0x35, 0x20, 0x38, 0x38, 0x20, 0x30, // 15 88 0
- /* 0CD0 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x41, 0x32, // 0. 15 A2
- /* 0CD8 */ 0x20, 0x32, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 20. 15
- /* 0CE0 */ 0x41, 0x39, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // A9 01. 1
- /* 0CE8 */ 0x35, 0x20, 0x41, 0x41, 0x20, 0x31, 0x32, 0x0A, // 5 AA 12.
- /* 0CF0 */ 0x20, 0x31, 0x35, 0x20, 0x41, 0x42, 0x20, 0x31, // 15 AB 1
- /* 0CF8 */ 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x41, 0x43, // 3. 15 AC
- /* 0D00 */ 0x20, 0x30, 0x41, 0x0A, 0x20, 0x31, 0x35, 0x20, // 0A. 15
- /* 0D08 */ 0x41, 0x44, 0x20, 0x37, 0x34, 0x0A, 0x20, 0x31, // AD 74. 1
- /* 0D10 */ 0x35, 0x20, 0x41, 0x46, 0x20, 0x33, 0x33, 0x0A, // 5 AF 33.
- /* 0D18 */ 0x20, 0x31, 0x35, 0x20, 0x42, 0x30, 0x20, 0x30, // 15 B0 0
- /* 0D20 */ 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x42, 0x31, // 3. 15 B1
- /* 0D28 */ 0x20, 0x31, 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, // 14. 15
- /* 0D30 */ 0x42, 0x32, 0x20, 0x34, 0x32, 0x0A, 0x20, 0x31, // B2 42. 1
- /* 0D38 */ 0x35, 0x20, 0x42, 0x33, 0x20, 0x34, 0x30, 0x0A, // 5 B3 40.
- /* 0D40 */ 0x20, 0x31, 0x35, 0x20, 0x42, 0x34, 0x20, 0x41, // 15 B4 A
- /* 0D48 */ 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x42, 0x36, // 5. 15 B6
- /* 0D50 */ 0x20, 0x34, 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, // 44. 15
- /* 0D58 */ 0x42, 0x37, 0x20, 0x30, 0x34, 0x0A, 0x20, 0x31, // B7 04. 1
- /* 0D60 */ 0x35, 0x20, 0x42, 0x38, 0x20, 0x31, 0x34, 0x0A, // 5 B8 14.
- /* 0D68 */ 0x20, 0x31, 0x35, 0x20, 0x42, 0x39, 0x20, 0x34, // 15 B9 4
- /* 0D70 */ 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x42, 0x41, // 2. 15 BA
- /* 0D78 */ 0x20, 0x34, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 40. 15
- /* 0D80 */ 0x42, 0x42, 0x20, 0x41, 0x35, 0x0A, 0x20, 0x31, // BB A5. 1
- /* 0D88 */ 0x35, 0x20, 0x42, 0x44, 0x20, 0x34, 0x34, 0x0A, // 5 BD 44.
- /* 0D90 */ 0x20, 0x31, 0x35, 0x20, 0x42, 0x45, 0x20, 0x30, // 15 BE 0
- /* 0D98 */ 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x42, 0x46, // 4. 15 BF
- /* 0DA0 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0DA8 */ 0x43, 0x30, 0x20, 0x37, 0x35, 0x0A, 0x20, 0x31, // C0 75. 1
- /* 0DB0 */ 0x35, 0x20, 0x43, 0x31, 0x20, 0x36, 0x41, 0x0A, // 5 C1 6A.
- /* 0DB8 */ 0x20, 0x31, 0x35, 0x20, 0x43, 0x32, 0x20, 0x41, // 15 C2 A
- /* 0DC0 */ 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x43, 0x34, // 5. 15 C4
- /* 0DC8 */ 0x20, 0x32, 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, // 22. 15
- /* 0DD0 */ 0x43, 0x35, 0x20, 0x30, 0x32, 0x0A, 0x20, 0x31, // C5 02. 1
- /* 0DD8 */ 0x35, 0x20, 0x43, 0x36, 0x20, 0x30, 0x30, 0x0A, // 5 C6 00.
- /* 0DE0 */ 0x20, 0x31, 0x35, 0x20, 0x43, 0x37, 0x20, 0x39, // 15 C7 9
- /* 0DE8 */ 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x43, 0x38, // 5. 15 C8
- /* 0DF0 */ 0x20, 0x38, 0x41, 0x0A, 0x20, 0x31, 0x35, 0x20, // 8A. 15
- /* 0DF8 */ 0x43, 0x39, 0x20, 0x41, 0x35, 0x0A, 0x20, 0x31, // C9 A5. 1
- /* 0E00 */ 0x35, 0x20, 0x43, 0x42, 0x20, 0x32, 0x32, 0x0A, // 5 CB 22.
- /* 0E08 */ 0x20, 0x31, 0x35, 0x20, 0x43, 0x43, 0x20, 0x30, // 15 CC 0
- /* 0E10 */ 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x43, 0x44, // 2. 15 CD
- /* 0E18 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0E20 */ 0x43, 0x45, 0x20, 0x42, 0x35, 0x0A, 0x20, 0x31, // CE B5. 1
- /* 0E28 */ 0x35, 0x20, 0x43, 0x46, 0x20, 0x41, 0x41, 0x0A, // 5 CF AA.
- /* 0E30 */ 0x20, 0x31, 0x35, 0x20, 0x44, 0x30, 0x20, 0x41, // 15 D0 A
- /* 0E38 */ 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x44, 0x32, // 5. 15 D2
- /* 0E40 */ 0x20, 0x32, 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, // 22. 15
- /* 0E48 */ 0x44, 0x33, 0x20, 0x30, 0x32, 0x0A, 0x20, 0x31, // D3 02. 1
- /* 0E50 */ 0x35, 0x20, 0x46, 0x42, 0x20, 0x30, 0x31, 0x0A, // 5 FB 01.
- /* 0E58 */ 0x20, 0x31, 0x35, 0x20, 0x46, 0x46, 0x20, 0x31, // 15 FF 1
- /* 0E60 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x36, // 0. 15 26
- /* 0E68 */ 0x20, 0x30, 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, // 02. 15
- /* 0E70 */ 0x33, 0x35, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 35 00. 1
- /* 0E78 */ 0x35, 0x20, 0x35, 0x31, 0x20, 0x46, 0x46, 0x0A, // 5 51 FF.
- /* 0E80 */ 0x20, 0x31, 0x35, 0x20, 0x35, 0x33, 0x20, 0x32, // 15 53 2
- /* 0E88 */ 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x35, 0x35, // 4. 15 55
- /* 0E90 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
- /* 0E98 */ 0x42, 0x30, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x30, // B0 00. 0
- /* 0EA0 */ 0x35, 0x20, 0x31, 0x31, 0x0A, 0x20, 0x46, 0x46, // 5 11. FF
- /* 0EA8 */ 0x20, 0x35, 0x30, 0x0A, 0x20, 0x30, 0x35, 0x20, // 50. 05
- /* 0EB0 */ 0x32, 0x39, 0x0A, 0x20, 0x46, 0x46, 0x20, 0x31, // 29. FF 1
- /* 0EB8 */ 0x34, 0x0A, 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x49, // 4.</DSII
- /* 0EC0 */ 0x6E, 0x69, 0x74, 0x53, 0x65, 0x71, 0x75, 0x65, // nitSeque
- /* 0EC8 */ 0x6E, 0x63, 0x65, 0x3E, 0x0A, 0x3C, 0x44, 0x53, // nce>.<DS
- /* 0ED0 */ 0x49, 0x54, 0x65, 0x72, 0x6D, 0x53, 0x65, 0x71, // ITermSeq
- /* 0ED8 */ 0x75, 0x65, 0x6E, 0x63, 0x65, 0x3E, 0x0A, 0x20, // uence>.
- /* 0EE0 */ 0x20, 0x20, 0x20, 0x30, 0x35, 0x20, 0x32, 0x38, // 05 28
- /* 0EE8 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x20, 0x20, 0x20, // 00.
- /* 0EF0 */ 0x46, 0x46, 0x20, 0x32, 0x30, 0x0A, 0x20, 0x20, // FF 20.
- /* 0EF8 */ 0x20, 0x20, 0x30, 0x35, 0x20, 0x31, 0x30, 0x20, // 05 10
- /* 0F00 */ 0x30, 0x30, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x46, // 00. F
- /* 0F08 */ 0x46, 0x20, 0x38, 0x30, 0x0A, 0x3C, 0x2F, 0x44, // F 80.</D
- /* 0F10 */ 0x53, 0x49, 0x54, 0x65, 0x72, 0x6D, 0x53, 0x65, // SITermSe
- /* 0F18 */ 0x71, 0x75, 0x65, 0x6E, 0x63, 0x65, 0x3E, 0x0A, // quence>.
- /* 0F20 */ 0x3C, 0x47, 0x72, 0x6F, 0x75, 0x70, 0x20, 0x69, // <Group i
- /* 0F28 */ 0x64, 0x3D, 0x27, 0x42, 0x61, 0x63, 0x6B, 0x6C, // d='Backl
- /* 0F30 */ 0x69, 0x67, 0x68, 0x74, 0x20, 0x43, 0x6F, 0x6E, // ight Con
- /* 0F38 */ 0x66, 0x69, 0x67, 0x75, 0x72, 0x61, 0x74, 0x69, // figurati
- /* 0F40 */ 0x6F, 0x6E, 0x27, 0x3E, 0x0A, 0x20, 0x20, 0x20, // on'>.
- /* 0F48 */ 0x20, 0x3C, 0x42, 0x61, 0x63, 0x6B, 0x6C, 0x69, // <Backli
- /* 0F50 */ 0x67, 0x68, 0x74, 0x54, 0x79, 0x70, 0x65, 0x3E, // ghtType>
- /* 0F58 */ 0x31, 0x3C, 0x2F, 0x42, 0x61, 0x63, 0x6B, 0x6C, // 1</Backl
- /* 0F60 */ 0x69, 0x67, 0x68, 0x74, 0x54, 0x79, 0x70, 0x65, // ightType
- /* 0F68 */ 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x42, // >. <B
- /* 0F70 */ 0x61, 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, // acklight
- /* 0F78 */ 0x50, 0x6D, 0x69, 0x63, 0x43, 0x6F, 0x6E, 0x74, // PmicCont
- /* 0F80 */ 0x72, 0x6F, 0x6C, 0x54, 0x79, 0x70, 0x65, 0x3E, // rolType>
- /* 0F88 */ 0x32, 0x3C, 0x2F, 0x42, 0x61, 0x63, 0x6B, 0x6C, // 2</Backl
- /* 0F90 */ 0x69, 0x67, 0x68, 0x74, 0x50, 0x6D, 0x69, 0x63, // ightPmic
- /* 0F98 */ 0x43, 0x6F, 0x6E, 0x74, 0x72, 0x6F, 0x6C, 0x54, // ControlT
- /* 0FA0 */ 0x79, 0x70, 0x65, 0x3E, 0x0A, 0x20, 0x20, 0x20, // ype>.
- /* 0FA8 */ 0x20, 0x3C, 0x42, 0x61, 0x63, 0x6B, 0x6C, 0x69, // <Backli
- /* 0FB0 */ 0x67, 0x68, 0x74, 0x53, 0x74, 0x65, 0x70, 0x73, // ghtSteps
- /* 0FB8 */ 0x3E, 0x31, 0x30, 0x30, 0x3C, 0x2F, 0x42, 0x61, // >100</Ba
- /* 0FC0 */ 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, 0x53, // cklightS
- /* 0FC8 */ 0x74, 0x65, 0x70, 0x73, 0x3E, 0x0A, 0x20, 0x20, // teps>.
- /* 0FD0 */ 0x20, 0x20, 0x3C, 0x42, 0x61, 0x63, 0x6B, 0x6C, // <Backl
- /* 0FD8 */ 0x69, 0x67, 0x68, 0x74, 0x50, 0x4D, 0x49, 0x43, // ightPMIC
- /* 0FE0 */ 0x42, 0x61, 0x6E, 0x6B, 0x53, 0x65, 0x6C, 0x65, // BankSele
- /* 0FE8 */ 0x63, 0x74, 0x3E, 0x31, 0x35, 0x3C, 0x2F, 0x42, // ct>15</B
- /* 0FF0 */ 0x61, 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, // acklight
- /* 0FF8 */ 0x50, 0x4D, 0x49, 0x43, 0x42, 0x61, 0x6E, 0x6B, // PMICBank
- /* 1000 */ 0x53, 0x65, 0x6C, 0x65, 0x63, 0x74, 0x3E, 0x0A, // Select>.
- /* 1008 */ 0x20, 0x20, 0x20, 0x20, 0x3C, 0x42, 0x61, 0x63, // <Bac
- /* 1010 */ 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, 0x50, 0x4D, // klightPM
- /* 1018 */ 0x49, 0x43, 0x50, 0x57, 0x4D, 0x46, 0x72, 0x65, // ICPWMFre
- /* 1020 */ 0x71, 0x75, 0x65, 0x6E, 0x63, 0x79, 0x3E, 0x36, // quency>6
- /* 1028 */ 0x30, 0x30, 0x30, 0x30, 0x30, 0x3C, 0x2F, 0x42, // 00000</B
- /* 1030 */ 0x61, 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, // acklight
- /* 1038 */ 0x50, 0x4D, 0x49, 0x43, 0x50, 0x57, 0x4D, 0x46, // PMICPWMF
- /* 1040 */ 0x72, 0x65, 0x71, 0x75, 0x65, 0x6E, 0x63, 0x79, // requency
- /* 1048 */ 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x42, // >. <B
- /* 1050 */ 0x61, 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, // acklight
- /* 1058 */ 0x53, 0x74, 0x65, 0x70, 0x73, 0x3E, 0x31, 0x30, // Steps>10
- /* 1060 */ 0x30, 0x3C, 0x2F, 0x42, 0x61, 0x63, 0x6B, 0x6C, // 0</Backl
- /* 1068 */ 0x69, 0x67, 0x68, 0x74, 0x53, 0x74, 0x65, 0x70, // ightStep
- /* 1070 */ 0x73, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // s>. <
- /* 1078 */ 0x42, 0x61, 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, // Backligh
- /* 1080 */ 0x74, 0x44, 0x65, 0x66, 0x61, 0x75, 0x6C, 0x74, // tDefault
- /* 1088 */ 0x3E, 0x38, 0x30, 0x3C, 0x2F, 0x42, 0x61, 0x63, // >80</Bac
- /* 1090 */ 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, 0x44, 0x65, // klightDe
- /* 1098 */ 0x66, 0x61, 0x75, 0x6C, 0x74, 0x3E, 0x0A, 0x20, // fault>.
- /* 10A0 */ 0x20, 0x20, 0x20, 0x3C, 0x42, 0x61, 0x63, 0x6B, // <Back
- /* 10A8 */ 0x6C, 0x69, 0x67, 0x68, 0x74, 0x4C, 0x6F, 0x77, // lightLow
- /* 10B0 */ 0x50, 0x6F, 0x77, 0x65, 0x72, 0x3E, 0x34, 0x30, // Power>40
- /* 10B8 */ 0x3C, 0x2F, 0x42, 0x61, 0x63, 0x6B, 0x6C, 0x69, // </Backli
- /* 10C0 */ 0x67, 0x68, 0x74, 0x4C, 0x6F, 0x77, 0x50, 0x6F, // ghtLowPo
- /* 10C8 */ 0x77, 0x65, 0x72, 0x3E, 0x0A, 0x20, 0x20, 0x20, // wer>.
- /* 10D0 */ 0x20, 0x3C, 0x50, 0x4D, 0x49, 0x50, 0x6F, 0x77, // <PMIPow
- /* 10D8 */ 0x65, 0x72, 0x50, 0x6D, 0x69, 0x63, 0x4E, 0x75, // erPmicNu
- /* 10E0 */ 0x6D, 0x3E, 0x31, 0x3C, 0x2F, 0x50, 0x4D, 0x49, // m>1</PMI
- /* 10E8 */ 0x50, 0x6F, 0x77, 0x65, 0x72, 0x50, 0x6D, 0x69, // PowerPmi
- /* 10F0 */ 0x63, 0x4E, 0x75, 0x6D, 0x3E, 0x0A, 0x20, 0x20, // cNum>.
- /* 10F8 */ 0x20, 0x20, 0x3C, 0x50, 0x4D, 0x49, 0x50, 0x6F, // <PMIPo
- /* 1100 */ 0x77, 0x65, 0x72, 0x50, 0x6D, 0x69, 0x63, 0x4D, // werPmicM
- /* 1108 */ 0x6F, 0x64, 0x65, 0x6C, 0x3E, 0x32, 0x31, 0x3C, // odel>21<
- /* 1110 */ 0x2F, 0x50, 0x4D, 0x49, 0x50, 0x6F, 0x77, 0x65, // /PMIPowe
- /* 1118 */ 0x72, 0x50, 0x6D, 0x69, 0x63, 0x4D, 0x6F, 0x64, // rPmicMod
- /* 1120 */ 0x65, 0x6C, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, // el>.
- /* 1128 */ 0x3C, 0x50, 0x4D, 0x49, 0x50, 0x6F, 0x77, 0x65, // <PMIPowe
- /* 1130 */ 0x72, 0x43, 0x6F, 0x6E, 0x66, 0x69, 0x67, 0x3E, // rConfig>
- /* 1138 */ 0x31, 0x3C, 0x2F, 0x50, 0x4D, 0x49, 0x50, 0x6F, // 1</PMIPo
- /* 1140 */ 0x77, 0x65, 0x72, 0x43, 0x6F, 0x6E, 0x66, 0x69, // werConfi
- /* 1148 */ 0x67, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // g>. <
- /* 1150 */ 0x41, 0x64, 0x61, 0x70, 0x74, 0x69, 0x76, 0x65, // Adaptive
- /* 1158 */ 0x42, 0x72, 0x69, 0x67, 0x68, 0x74, 0x6E, 0x65, // Brightne
- /* 1160 */ 0x73, 0x73, 0x46, 0x65, 0x61, 0x74, 0x75, 0x72, // ssFeatur
- /* 1168 */ 0x65, 0x3E, 0x31, 0x3C, 0x2F, 0x41, 0x64, 0x61, // e>1</Ada
- /* 1170 */ 0x70, 0x74, 0x69, 0x76, 0x65, 0x42, 0x72, 0x69, // ptiveBri
- /* 1178 */ 0x67, 0x68, 0x74, 0x6E, 0x65, 0x73, 0x73, 0x46, // ghtnessF
- /* 1180 */ 0x65, 0x61, 0x74, 0x75, 0x72, 0x65, 0x3E, 0x0A, // eature>.
- /* 1188 */ 0x20, 0x20, 0x20, 0x20, 0x3C, 0x43, 0x41, 0x42, // <CAB
- /* 1190 */ 0x4C, 0x45, 0x6E, 0x61, 0x62, 0x6C, 0x65, 0x3E, // LEnable>
- /* 1198 */ 0x54, 0x72, 0x75, 0x65, 0x3C, 0x2F, 0x43, 0x41, // True</CA
- /* 11A0 */ 0x42, 0x4C, 0x45, 0x6E, 0x61, 0x62, 0x6C, 0x65, // BLEnable
- /* 11A8 */ 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x42, // >. <B
- /* 11B0 */ 0x72, 0x69, 0x67, 0x68, 0x74, 0x6E, 0x65, 0x73, // rightnes
- /* 11B8 */ 0x73, 0x4D, 0x69, 0x6E, 0x4C, 0x75, 0x6D, 0x69, // sMinLumi
- /* 11C0 */ 0x6E, 0x61, 0x6E, 0x63, 0x65, 0x3E, 0x32, 0x30, // nance>20
- /* 11C8 */ 0x30, 0x3C, 0x2F, 0x42, 0x72, 0x69, 0x67, 0x68, // 0</Brigh
- /* 11D0 */ 0x74, 0x6E, 0x65, 0x73, 0x73, 0x4D, 0x69, 0x6E, // tnessMin
- /* 11D8 */ 0x4C, 0x75, 0x6D, 0x69, 0x6E, 0x61, 0x6E, 0x63, // Luminanc
- /* 11E0 */ 0x65, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // e>. <
- /* 11E8 */ 0x42, 0x72, 0x69, 0x67, 0x68, 0x74, 0x6E, 0x65, // Brightne
- /* 11F0 */ 0x73, 0x73, 0x4D, 0x61, 0x78, 0x4C, 0x75, 0x6D, // ssMaxLum
- /* 11F8 */ 0x69, 0x6E, 0x61, 0x6E, 0x63, 0x65, 0x3E, 0x33, // inance>3
- /* 1200 */ 0x31, 0x39, 0x39, 0x37, 0x30, 0x3C, 0x2F, 0x42, // 19970</B
- /* 1208 */ 0x72, 0x69, 0x67, 0x68, 0x74, 0x6E, 0x65, 0x73, // rightnes
- /* 1210 */ 0x73, 0x4D, 0x61, 0x78, 0x4C, 0x75, 0x6D, 0x69, // sMaxLumi
- /* 1218 */ 0x6E, 0x61, 0x6E, 0x63, 0x65, 0x3E, 0x0A, 0x3C, // nance>.<
- /* 1220 */ 0x2F, 0x47, 0x72, 0x6F, 0x75, 0x70, 0x3E, 0x0A, // /Group>.
- /* 1228 */ 0x00 // .
- })
- Local2 = PCFG /* \_SB_.GPU0._ROM.PCFG */
- If ((Arg0 >= SizeOf (Local2)))
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
- Else
- {
- Local0 = Arg0
- }
-
- If ((Arg1 > 0x1000))
- {
- Local1 = 0x1000
- }
- Else
- {
- Local1 = Arg1
- }
-
- If (((Local0 + Local1) > SizeOf (Local2)))
- {
- Local1 = (SizeOf (Local2) - Local0)
- }
-
- CreateField (Local2, (0x08 * Local0), (0x08 * Local1), RBUF)
- Return (RBUF) /* \_SB_.GPU0._ROM.RBUF */
- }
-
- Method (PIGC, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.PIGC.RBUF */
- }
-
- Method (PPCC, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.PPCC.RBUF */
- }
-
- Method (PGCT, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.PGCT.RBUF */
- }
-
- Method (PLGC, 3, NotSerialized)
- {
- Name (TBUF, Buffer (One)
- {
- 0x00 // .
- })
- If ((Arg1 >= SizeOf (TBUF)))
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
- Else
- {
- Local1 = Arg1
- }
-
- If ((Arg2 > 0x1000))
- {
- Local2 = 0x1000
- }
- Else
- {
- Local2 = Arg2
- }
-
- If (((Local1 + Local2) > SizeOf (TBUF)))
- {
- Local2 = (SizeOf (TBUF) - Local1)
- }
-
- CreateField (TBUF, (0x08 * Local1), (0x08 * Local2), RBUF)
- Return (RBUF) /* \_SB_.GPU0.PLGC.RBUF */
- }
-
- Method (HSIC, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.HSIC.RBUF */
- }
-
- Method (PGMT, 2, NotSerialized)
- {
- Name (TBUF, Buffer (One)
- {
- 0x00 // .
- })
- If ((Arg0 >= SizeOf (TBUF)))
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
- Else
- {
- Local0 = Arg0
- }
-
- If ((Arg1 > 0x1000))
- {
- Local1 = 0x1000
- }
- Else
- {
- Local1 = Arg1
- }
-
- If (((Local0 + Local1) > SizeOf (TBUF)))
- {
- Local1 = (SizeOf (TBUF) - Local0)
- }
-
- CreateField (TBUF, (0x08 * Local0), (0x08 * Local1), RBUF)
- Return (RBUF) /* \_SB_.GPU0.PGMT.RBUF */
- }
-
- Method (PWGM, 2, NotSerialized)
- {
- Name (TBUF, Buffer (One)
- {
- 0x00 // .
- })
- If ((Arg0 >= SizeOf (TBUF)))
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
- Else
- {
- Local0 = Arg0
- }
-
- If ((Arg1 > 0x1000))
- {
- Local1 = 0x1000
- }
- Else
- {
- Local1 = Arg1
- }
-
- If (((Local0 + Local1) > SizeOf (TBUF)))
- {
- Local1 = (SizeOf (TBUF) - Local0)
- }
-
- CreateField (TBUF, (0x08 * Local0), (0x08 * Local1), RBUF)
- Return (RBUF) /* \_SB_.GPU0.PWGM.RBUF */
- }
-
- Method (PGRT, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.PGRT.RBUF */
- }
-
- Method (PBRT, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.PBRT.RBUF */
- }
-
- Method (PBRC, 2, NotSerialized)
- {
- Name (RBUF, Buffer (0x02)
- {
- 0x00, 0x00 // ..
- })
- Return (RBUF) /* \_SB_.GPU0.PBRC.RBUF */
- }
-
- Method (DITH, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.DITH.RBUF */
- }
-
- Method (BLCP, 1, NotSerialized)
- {
- Name (RBUF, Buffer (0x0100){})
- Return (RBUF) /* \_SB_.GPU0.BLCP.RBUF */
- }
-
- Method (ROM2, 3, NotSerialized)
- {
- Name (PCFG, Buffer (One)
- {
- 0x00 // .
- })
- While (One)
- {
- If (One)
- {
- Local2 = PCFG /* \_SB_.GPU0.ROM2.PCFG */
- }
-
- Break
- }
-
- If ((Arg0 >= SizeOf (Local2)))
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
- Else
- {
- Local0 = Arg0
- }
-
- If ((Arg1 > 0x1000))
- {
- Local1 = 0x1000
- }
- Else
- {
- Local1 = Arg1
- }
-
- If (((Local0 + Local1) > SizeOf (Local2)))
- {
- Local1 = (SizeOf (Local2) - Local0)
- }
-
- CreateField (Local2, (0x08 * Local0), (0x08 * Local1), RBUF)
- Return (RBUF) /* \_SB_.GPU0.ROM2.RBUF */
- }
-
- Method (IGC2, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.IGC2.RBUF */
- }
-
- Method (PCC2, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.PCC2.RBUF */
- }
-
- Method (GCT2, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.GCT2.RBUF */
- }
-
- Method (LGC2, 3, NotSerialized)
- {
- Name (TBUF, Buffer (One)
- {
- 0x00 // .
- })
- If ((Arg1 >= SizeOf (TBUF)))
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
- Else
- {
- Local1 = Arg1
- }
-
- If ((Arg2 > 0x1000))
- {
- Local2 = 0x1000
- }
- Else
- {
- Local2 = Arg2
- }
-
- If (((Local1 + Local2) > SizeOf (TBUF)))
- {
- Local2 = (SizeOf (TBUF) - Local1)
- }
-
- CreateField (TBUF, (0x08 * Local1), (0x08 * Local2), RBUF)
- Return (RBUF) /* \_SB_.GPU0.LGC2.RBUF */
- }
-
- Method (HSI2, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.HSI2.RBUF */
- }
-
- Method (GMT2, 2, NotSerialized)
- {
- Name (TBUF, Buffer (One)
- {
- 0x00 // .
- })
- If ((Arg0 >= SizeOf (TBUF)))
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
- Else
- {
- Local0 = Arg0
- }
-
- If ((Arg1 > 0x1000))
- {
- Local1 = 0x1000
- }
- Else
- {
- Local1 = Arg1
- }
-
- If (((Local0 + Local1) > SizeOf (TBUF)))
- {
- Local1 = (SizeOf (TBUF) - Local0)
- }
-
- CreateField (TBUF, (0x08 * Local0), (0x08 * Local1), RBUF)
- Return (RBUF) /* \_SB_.GPU0.GMT2.RBUF */
- }
-
- Method (WGM2, 2, NotSerialized)
- {
- Name (TBUF, Buffer (One)
- {
- 0x00 // .
- })
- If ((Arg0 >= SizeOf (TBUF)))
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
- Else
- {
- Local0 = Arg0
- }
-
- If ((Arg1 > 0x1000))
- {
- Local1 = 0x1000
- }
- Else
- {
- Local1 = Arg1
- }
-
- If (((Local0 + Local1) > SizeOf (TBUF)))
- {
- Local1 = (SizeOf (TBUF) - Local0)
- }
-
- CreateField (TBUF, (0x08 * Local0), (0x08 * Local1), RBUF)
- Return (RBUF) /* \_SB_.GPU0.WGM2.RBUF */
- }
-
- Method (GRT2, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.GRT2.RBUF */
- }
-
- Method (BRT2, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.BRT2.RBUF */
- }
-
- Method (DIT2, 2, NotSerialized)
- {
- Name (RBUF, Buffer (One)
- {
- 0x00 // .
- })
- Return (RBUF) /* \_SB_.GPU0.DIT2.RBUF */
- }
-
- Method (BLC2, 1, NotSerialized)
- {
- Name (RBUF, Buffer (0x0100){})
- Return (RBUF) /* \_SB_.GPU0.BLC2.RBUF */
- }
-
- Method (ROE1, 3, NotSerialized)
- {
- Name (PCFG, Buffer (One)
- {
- 0x00 // .
- })
- Local2 = PCFG /* \_SB_.GPU0.ROE1.PCFG */
- If ((Arg0 >= SizeOf (Local2)))
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
- Else
- {
- Local0 = Arg0
- }
-
- If ((Arg1 > 0x1000))
- {
- Local1 = 0x1000
- }
- Else
- {
- Local1 = Arg1
- }
-
- If (((Local0 + Local1) > SizeOf (Local2)))
- {
- Local1 = (SizeOf (Local2) - Local0)
- }
-
- CreateField (Local2, (0x08 * Local0), (0x08 * Local1), RBUF)
- Return (RBUF) /* \_SB_.GPU0.ROE1.RBUF */
- }
-
- Name (_DOD, Package (0x01) // _DOD: Display Output Devices
- {
- 0x00024321
- })
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Method (CHDV, 0, NotSerialized)
- {
- Name (CHIF, Package (0x02)
- {
- One,
- Package (0x07)
- {
- "CHILDDEV",
- Zero,
- 0x00024321,
- "QCOM_AVStream_850",
- Zero,
- "Qualcomm Camera AVStream Mini Driver",
- Package (0x04)
- {
- "COMPATIBLEIDS",
- 0x02,
- "VEN_QCOM&DEV__AVSTREAM",
- "QCOM_AVSTREAM"
- }
- }
- })
- Return (CHIF) /* \_SB_.GPU0.CHDV.CHIF */
- }
-
- Method (DPCC, 2, NotSerialized)
- {
- Return (CCST) /* \_SB_.CCST */
- }
-
- Method (DPIN, 2, NotSerialized)
- {
- Return (PINA) /* \_SB_.PINA */
- }
-
- Method (REGR, 0, NotSerialized)
- {
- Name (RBUF, Package (0x1B)
- {
- Package (0x02)
- {
- "ForceMaxPerf",
- Zero
- },
-
- Package (0x02)
- {
- "ForceStablePowerSettings",
- Zero
- },
-
- Package (0x02)
- {
- "ForceActive",
- Zero
- },
-
- Package (0x02)
- {
- "DeferForceActive",
- Zero
- },
-
- Package (0x02)
- {
- "PreventPowerCollapse",
- Zero
- },
-
- Package (0x02)
- {
- "DisableThermalMitigation",
- Zero
- },
-
- Package (0x02)
- {
- "DisableTzMDSSRestore",
- One
- },
-
- Package (0x02)
- {
- "UseLowPTForGfxPerProcess",
- One
- },
-
- Package (0x02)
- {
- "DisableCDI",
- One
- },
-
- Package (0x02)
- {
- "GPU64bAddrEnabled",
- One
- },
-
- Package (0x02)
- {
- "MaxPreemptionOffsets",
- 0x80
- },
-
- Package (0x02)
- {
- "MaxRequiredDmaQueueEntry",
- 0x08
- },
-
- Package (0x02)
- {
- "SupportsSecureInAperture",
- One
- },
-
- Package (0x02)
- {
- "ZeroFlagSupportInPTE",
- One
- },
-
- Package (0x02)
- {
- "SupportsCacheCoherency",
- One
- },
-
- Package (0x02)
- {
- "SupportsSHMBridge",
- Zero
- },
-
- Package (0x02)
- {
- "SecureCarveoutSize",
- 0x00200000
- },
-
- Package (0x02)
- {
- "UBWCEnable",
- Zero
- },
-
- Package (0x02)
- {
- "allowDrmAbove1080p",
- One
- },
-
- Package (0x02)
- {
- "ZeroPageLowAddr",
- 0x85F00000
- },
-
- Package (0x02)
- {
- "ZeroPageHighAddr",
- Zero
- },
-
- Package (0x02)
- {
- "KeepUefiBuffer",
- One
- },
-
- Package (0x06)
- {
- "GRAPHICS",
- Package (0x02)
- {
- "ForceActive",
- Zero
- },
-
- Package (0x02)
- {
- "EnableSystemCache",
- One
- },
-
- Package (0x02)
- {
- "EnableSysCacheForGpuhtw",
- One
- },
-
- Package (0x0A)
- {
- "DCVS",
- Package (0x02)
- {
- "Enable",
- One
- },
-
- Package (0x02)
- {
- "IncreaseFilterBw",
- 0x00020000
- },
-
- Package (0x02)
- {
- "DecreaseFilterBw",
- 0x3333
- },
-
- Package (0x02)
- {
- "TargetBusyPct",
- 0x55
- },
-
- Package (0x02)
- {
- "SampleRate",
- 0x3C
- },
-
- Package (0x02)
- {
- "TargetBusyPctOffscreen",
- 0x4B
- },
-
- Package (0x02)
- {
- "SampleRateOffscreen",
- 0x14
- },
-
- Package (0x02)
- {
- "GpuResetValue",
- 0x11490C80
- },
-
- Package (0x02)
- {
- "BusResetValue",
- 0x04B0
- }
- },
-
- Package (0x06)
- {
- "A6x",
- Package (0x02)
- {
- "SleepMode",
- Zero
- },
-
- Package (0x02)
- {
- "DisableICG",
- Zero
- },
-
- Package (0x02)
- {
- "DisableGmuCG",
- Zero
- },
-
- Package (0x02)
- {
- "EnableFallbackToDisableSecureMode",
- Zero
- },
-
- Package (0x02)
- {
- "DisableCPCrashDump",
- Zero
- }
- }
- },
-
- Package (0x04)
- {
- "VIDEO",
- Package (0x02)
- {
- "ForceActive",
- Zero
- },
-
- Package (0x02)
- {
- "PreventPowerCollapse",
- Zero
- },
-
- Package (0x02)
- {
- "EnableSystemCache",
- One
- }
- },
-
- Package (0x02)
- {
- "CRYPTO",
- Package (0x02)
- {
- "EnableCryptoVA",
- One
- }
- },
-
- Package (0x03)
- {
- "VIDEO_ENCODER",
- Package (0x02)
- {
- "ForceActive",
- Zero
- },
-
- Package (0x02)
- {
- "PreventPowerCollapse",
- Zero
- }
- },
-
- Package (0x07)
- {
- "DISPLAY",
- Package (0x02)
- {
- "DisableMiracast",
- Zero
- },
-
- Package (0x02)
- {
- "EnableOEMDriverDependency",
- Zero
- },
-
- Package (0x02)
- {
- "EnableBridgeDriverDependency",
- Zero
- },
-
- Package (0x02)
- {
- "DisableRotator",
- Zero
- },
-
- Package (0x02)
- {
- "DisableMDPBLT",
- One
- },
-
- Package (0x02)
- {
- "DisableExternal",
- 0x03
- }
- }
- })
- Return (RBUF) /* \_SB_.GPU0.REGR.RBUF */
- }
- }
-
- Device (SCM0)
- {
- Name (_HID, "QCOM0214") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- }
-
- Device (TREE)
- {
- Name (_HID, "QCOM02BB") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Method (MCGT, 0, NotSerialized)
- {
- Name (TPKG, Package (0x01)
- {
- Package (0x02)
- {
- Zero,
- Zero
- }
- })
- DerefOf (TPKG [Zero]) [Zero] = TCMA /* \_SB_.TCMA */
- DerefOf (TPKG [Zero]) [One] = TCML /* \_SB_.TCML */
- Return (TPKG) /* \_SB_.TREE.MCGT.TPKG */
- }
- }
-
- Device (SPMI)
- {
- Name (_HID, "QCOM0216") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_CID, "PNP0CA2") // _CID: Compatible ID
- Name (_UID, One) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x0C400000, // Address Base
- 0x02800000, // Address Length
- )
- })
- Return (RBUF) /* \_SB_.SPMI._CRS.RBUF */
- }
-
- Method (CONF, 0, NotSerialized)
- {
- Name (XBUF, Buffer (0x1A)
- {
- /* 0000 */ 0x00, 0x01, 0x01, 0x01, 0xFF, 0x00, 0x02, 0x00, // ........
- /* 0008 */ 0x0A, 0x07, 0x04, 0x07, 0x01, 0xFF, 0x10, 0x01, // ........
- /* 0010 */ 0x00, 0x01, 0x0C, 0x40, 0x00, 0x00, 0x02, 0x80, // ...@....
- /* 0018 */ 0x00, 0x00 // ..
- })
- Return (XBUF) /* \_SB_.SPMI.CONF.XBUF */
- }
- }
-
- Device (GIO0)
- {
- Name (_HID, "QCOM0217") // _HID: Hardware ID
- Alias (\_SB.PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x03400000, // Address Base
- 0x00C00000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
- {
- 0x000000F0,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
- {
- 0x000000F0,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
- {
- 0x000000F0,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, )
- {
- 0x00000288,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, )
- {
- 0x00000238,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, )
- {
- 0x00000286,
- }
- })
- Return (RBUF) /* \_SB_.GIO0._CRS.RBUF */
- }
-
- Method (OFNI, 0, NotSerialized)
- {
- Name (RBUF, Buffer (0x02)
- {
- 0x96, 0x00 // ..
- })
- Return (RBUF) /* \_SB_.GIO0.OFNI.RBUF */
- }
-
- Name (GABL, Zero)
- Method (_REG, 2, NotSerialized) // _REG: Region Availability
- {
- If ((Arg0 == 0x08))
- {
- GABL = Arg1
- }
- }
- }
-
- OperationRegion (CP00, SystemMemory, 0x13000000, 0x24)
- Field (CP00, DWordAcc, NoLock, Preserve)
- {
- MVIO, 32,
- MV01, 32,
- MV02, 32,
- MV03, 32,
- MV04, 32,
- MV11, 32,
- MV12, 32,
- MV13, 32,
- MV14, 32
- }
-
- OperationRegion (CP01, SystemMemory, 0x01C00000, 0x1004)
- Field (CP01, DWordAcc, NoLock, Preserve)
- {
- PSC0, 32,
- Offset (0x20),
- PPC0, 32,
- PPS0, 32,
- Offset (0x1B0),
- PLT0, 32,
- Offset (0x358),
- PSL0, 32,
- Offset (0x360),
- WBL0, 32,
- WBH0, 32,
- WLL0, 32,
- WLH0, 32,
- RBL0, 32,
- RBH0, 32,
- RLL0, 32,
- RLH0, 32,
- PPEB, 32,
- Offset (0x398),
- WBL1, 32,
- WBH1, 32,
- WLL1, 32,
- WLH1, 32,
- RBL1, 32,
- RBH1, 32,
- RLL1, 32,
- RLH1, 32,
- Offset (0x1000),
- PDT0, 32
- }
-
- OperationRegion (CP02, SystemMemory, 0x01C06000, 0x0188)
- Field (CP02, DWordAcc, NoLock, Preserve)
- {
- Offset (0x0C),
- QCB1, 32,
- QSEC, 32,
- QAP1, 32,
- QAP2, 32,
- QSP1, 32,
- QSP2, 32,
- QSS1, 32,
- QSS2, 32,
- Offset (0x34),
- QECE, 32,
- QCE1, 32,
- QSCC, 32,
- QSBE, 32,
- Offset (0x48),
- QCPI, 32,
- Offset (0x5C),
- QCED, 32,
- QCP0, 32,
- Offset (0x68),
- QPR0, 32,
- Offset (0x70),
- QPC0, 32,
- Offset (0x80),
- QSES, 32,
- Offset (0x88),
- QCRC, 32,
- Offset (0x90),
- QCLC, 32,
- Offset (0x98),
- QC1M, 32,
- QC2M, 32,
- QC3M, 32,
- Offset (0xB0),
- QSM0, 32,
- Offset (0xB8),
- QS1M, 32,
- QS2M, 32,
- QS3M, 32,
- Offset (0xD8),
- QIG0, 32,
- QIG1, 32,
- Offset (0xF0),
- QCVT, 32,
- QVT1, 32,
- QVT2, 32,
- Offset (0x11C),
- QTT1, 32,
- QTT2, 32,
- Offset (0x138),
- QCCS, 32,
- QCHS, 32,
- Offset (0x148),
- QCD0, 32,
- Offset (0x154),
- QCCN, 32,
- Offset (0x15C),
- QCCC, 32,
- Offset (0x164),
- QMCS, 32,
- Offset (0x184),
- QCCM, 32
- }
-
- OperationRegion (CP03, SystemMemory, 0x01C06200, 0xA8)
- Field (CP03, DWordAcc, NoLock, Preserve)
- {
- Offset (0x44),
- QTOT, 32,
- Offset (0x60),
- QTDE, 32,
- Offset (0x8C),
- QTM1, 32,
- Offset (0xA4),
- QTL2, 32
- }
-
- OperationRegion (CP04, SystemMemory, 0x01C06400, 0x016C)
- Field (CP04, DWordAcc, NoLock, Preserve)
- {
- Offset (0x0C),
- QRSH, 32,
- Offset (0x14),
- QRSG, 32,
- Offset (0x34),
- QRUS, 32,
- Offset (0x3C),
- QRFL, 32,
- Offset (0x44),
- QRPC, 32,
- Offset (0xD4),
- QRC2, 32,
- QRC3, 32,
- QRC4, 32,
- Offset (0xF8),
- QRA1, 32,
- QRA2, 32,
- QRSE, 32,
- QRSC, 32,
- Offset (0x10C),
- QRDC, 32,
- Offset (0x11C),
- QRIM, 32,
- Offset (0x164),
- QRM0, 32,
- QRM1, 32
- }
-
- OperationRegion (CP05, SystemMemory, 0x01C06600, 0x70)
- Field (CP05, DWordAcc, NoLock, Preserve)
- {
- Offset (0x2C),
- PMDC, 32,
- Offset (0x44),
- PAC1, 32,
- Offset (0x54),
- PMC2, 32,
- PMC3, 32,
- PMC4, 32,
- PMC5, 32
- }
-
- OperationRegion (CP06, SystemMemory, 0x01C06800, 0x0210)
- Field (CP06, DWordAcc, NoLock, Preserve)
- {
- PPSR, 32,
- PPDC, 32,
- PCST, 32,
- Offset (0x54),
- PERD, 32,
- Offset (0x6C),
- PSC4, 32,
- Offset (0xA0),
- PDTA, 32,
- PLTA, 32,
- PLCD, 32,
- Offset (0xC4),
- PFC1, 32,
- PFC2, 32,
- PFVL, 32,
- PFVH, 32,
- PFMC, 32,
- Offset (0x174),
- PPPS, 32,
- Offset (0x1A8),
- PSDM, 32,
- PODA, 32,
- PPSC, 32,
- Offset (0x1D8),
- PRSL, 32,
- PDAL, 32,
- PDAM, 32,
- Offset (0x20C),
- PRC1, 32
- }
-
- OperationRegion (CP07, SystemMemory, 0x60000000, 0x1000)
- Field (CP07, DWordAcc, NoLock, Preserve)
- {
- Offset (0x04),
- SCR0, 32,
- CRI0, 32,
- Offset (0x10),
- R0B0, 32,
- R0B1, 32,
- BNR0, 32,
- Offset (0x7C),
- LCA0, 32,
- LCS0, 32,
- Offset (0x88),
- SLC0, 32,
- Offset (0xA0),
- LC20, 32,
- Offset (0x8BC),
- CSW0, 32,
- Offset (0x900),
- IAV0, 32,
- CR10, 32,
- CR20, 32,
- ILB0, 32,
- IUB0, 32,
- ILR0, 32,
- ILT0, 32,
- IUT0, 32,
- Offset (0xF24),
- ESC0, 32,
- EST0, 32,
- Offset (0xFC4),
- ECS0, 32
- }
-
- Method (PPU0, 0, Serialized)
- {
- Name (TOUT, Zero)
- PDT0 = 0x04
- PPDC = One
- QECE = 0x14
- QCPI = 0x07
- QCLC = One
- QCRC = 0x20
- QCVT = Zero
- QVT2 = One
- QVT1 = 0xC9
- QTT1 = 0xFF
- QTT2 = 0x3F
- QMCS = One
- QCCN = Zero
- QCD0 = 0x0A
- QCED = 0x19
- QCE1 = 0x90
- QSM0 = 0x82
- QS3M = 0x02
- QS2M = 0xEA
- QS1M = 0xAB
- QC3M = Zero
- QC2M = 0x0D
- QC1M = 0x04
- QCHS = Zero
- QCP0 = 0x06
- QPR0 = 0x16
- QPC0 = 0x36
- QCCM = One
- QCCC = 0x16
- QCCS = 0x33
- QSCC = 0x02
- QSBE = 0x07
- QSES = 0x04
- QIG1 = Zero
- QIG0 = 0x3F
- QCB1 = 0x09
- QSEC = One
- QSP1 = 0x40
- QSP2 = One
- QAP1 = 0x02
- QAP2 = Zero
- QSS1 = 0x7E
- QSS2 = 0x15
- QTOT = 0x02
- QTL2 = 0x12
- QTDE = 0x10
- QTM1 = 0x06
- QRSC = 0x03
- QRSE = 0x1C
- QRDC = 0x14
- QRC2 = 0x0E
- QRC3 = 0x04
- QRC4 = 0x1A
- QRUS = 0x4B
- QRSG = 0x04
- QRSH = 0x04
- QRA1 = 0x71
- QRM0 = 0x59
- QRM1 = 0x59
- QRA2 = 0x80
- QRIM = 0x40
- QRPC = 0x71
- QRFL = 0x40
- PERD = 0x04
- PMDC = 0x52
- PMC2 = 0x50
- PMC4 = 0x1A
- PMC5 = 0x06
- PFC2 = 0x83
- PFVL = 0x09
- PFVH = 0xA2
- PFMC = 0x40
- PFC1 = 0x02
- PODA = Zero
- PDTA = One
- PDAM = Zero
- PDAL = 0x20
- PSDM = Zero
- PLTA = One
- PLCD = 0x73
- PRSL = 0xAA
- PPSC = 0x03
- PRC1 = 0x0D
- PSC4 = Zero
- PAC1 = Zero
- If ((SIDV >= 0x00020000)){}
- PPDC = 0x03
- PPSR = Zero
- PCST = 0x03
- Local0 = PPPS /* \_SB_.PPPS */
- While ((Local0 & 0x40))
- {
- Sleep (One)
- TOUT++
- If ((TOUT == 0x0F))
- {
- Break
- }
-
- Local0 = PPPS /* \_SB_.PPPS */
- }
-
- If ((TOUT == 0x0F))
- {
- Return (One)
- }
- Else
- {
- Return (Zero)
- }
- }
-
- Method (LTS0, 0, Serialized)
- {
- Name (TOUT, Zero)
- Local0 = LC20 /* \_SB_.LC20 */
- Local0 |= 0x40
- LC20 = Local0
- PLT0 = 0x0100
- Local0 = EST0 /* \_SB_.EST0 */
- While (((Local0 & 0x0400) != 0x0400))
- {
- Sleep (One)
- TOUT++
- If ((TOUT == 0x96))
- {
- Break
- }
-
- Local0 = EST0 /* \_SB_.EST0 */
- }
-
- If ((TOUT == 0x96))
- {
- Return (One)
- }
- Else
- {
- Return (Zero)
- }
- }
-
- Method (IAT0, 0, Serialized)
- {
- IAV0 = One
- ILB0 = 0x60100000
- IUB0 = Zero
- ILR0 = 0x601FFFFF
- ILT0 = 0x01000000
- IUT0 = Zero
- CR10 = 0x04
- CR20 = 0x80000000
- BNR0 = 0x00010100
- }
-
- Method (REB0, 2, Serialized)
- {
- Local0 = PSC0 /* \_SB_.PSC0 */
- Local0 &= 0xFBFFFFFF
- PSC0 = Local0
- WBL0 = Arg0
- WBH0 = Zero
- WLL0 = Arg1
- WLH0 = Zero
- RBL0 = Arg0
- RBH0 = Zero
- RLL0 = Arg1
- RLH0 = Zero
- Local0 = PSC0 /* \_SB_.PSC0 */
- Local0 |= 0x04000000
- PSC0 = Local0
- }
-
- Method (EEB0, 2, Serialized)
- {
- Local0 = PSC0 /* \_SB_.PSC0 */
- Local0 &= 0xBFFFFFFF
- PSC0 = Local0
- WBL1 = Arg0
- WBH1 = Zero
- WLL1 = Arg1
- WLH1 = Zero
- RBL1 = Arg0
- RBH1 = Zero
- RLL1 = Arg1
- RLH1 = Zero
- Local0 = PSC0 /* \_SB_.PSC0 */
- Local0 |= 0x40000000
- PSC0 = Local0
- }
-
- Name (E0LT, 0x600FFFFF)
- Method (MSC0, 0, Serialized)
- {
- Local0 = SCR0 /* \_SB_.SCR0 */
- Local0 |= 0x02
- SCR0 = Local0
- PSL0 = 0x01000000
- Local0 = PPC0 /* \_SB_.PPC0 */
- Local0 &= 0xFFFFFFDF
- PPC0 = Local0
- CSW0 = One
- Local0 = LCA0 /* \_SB_.LCA0 */
- Local0 |= 0x00400000
- Local0 &= 0xFFFFFBFF
- Local0 |= 0x0800
- LCA0 = Local0
- Local0 = CRI0 /* \_SB_.CRI0 */
- Local0 &= 0xFFFF
- Local0 |= 0x06040000
- CRI0 = Local0
- ECS0 = One
- R0B0 = Zero
- R0B1 = Zero
- ECS0 = Zero
- CSW0 = Zero
- PPEB = 0x60000000
- REB0 (0x60001000, E0LT)
- EEB0 (0x60101000, 0x601FFFFF)
- }
-
- Name (G0D3, Zero)
- OperationRegion (CP08, SystemMemory, 0x01C08000, 0x1004)
- Field (CP08, DWordAcc, NoLock, Preserve)
- {
- PSC1, 32,
- Offset (0x20),
- PPC1, 32,
- PPS1, 32,
- Offset (0x1B0),
- PLT1, 32,
- Offset (0x358),
- PSL1, 32,
- Offset (0x360),
- LBW0, 32,
- HBW0, 32,
- LLW0, 32,
- HLW0, 32,
- LBR0, 32,
- HBR0, 32,
- LLR0, 32,
- HLR0, 32,
- PEB1, 32,
- Offset (0x398),
- LBW1, 32,
- HBW1, 32,
- LLW1, 32,
- HLW1, 32,
- LBR1, 32,
- HBR1, 32,
- LLR1, 32,
- HLR1, 32,
- Offset (0x1000),
- PDT1, 32
- }
-
- OperationRegion (CP09, SystemMemory, 0x01C0A000, 0x026C)
- Field (CP09, DWordAcc, NoLock, Preserve)
- {
- Offset (0x14),
- HSEC, 32,
- HAP1, 32,
- HAP2, 32,
- HSP1, 32,
- HSP2, 32,
- HSS1, 32,
- HSS2, 32,
- Offset (0x34),
- HSM1, 32,
- HSM2, 32,
- Offset (0x54),
- HECE, 32,
- HCE1, 32,
- HSCC, 32,
- HSBE, 32,
- HPLE, 32,
- HCPI, 32,
- C1M0, 32,
- C2M0, 32,
- C3M0, 32,
- C1M1, 32,
- C2M1, 32,
- C3M1, 32,
- Offset (0xB4),
- HCM0, 32,
- HCM1, 32,
- Offset (0xC0),
- HPR0, 32,
- HPR1, 32,
- HPR2, 32,
- HPC0, 32,
- HPC1, 32,
- HPC2, 32,
- Offset (0xDC),
- HSES, 32,
- Offset (0xF0),
- HRC2, 32,
- Offset (0xF8),
- HCLC, 32,
- Offset (0x100),
- HRM0, 32,
- Offset (0x108),
- HRM1, 32,
- Offset (0x11C),
- S1M0, 32,
- S2M0, 32,
- S3M0, 32,
- S1M1, 32,
- S2M1, 32,
- S3M1, 32,
- Offset (0x150),
- G0M0, 32,
- Offset (0x158),
- G0M1, 32,
- Offset (0x178),
- HCVT, 32,
- Offset (0x1CC),
- HCCS, 32,
- HCHS, 32,
- Offset (0x1E0),
- HCDV, 32,
- Offset (0x1E8),
- HCCE, 32,
- Offset (0x1F0),
- HCCC, 32,
- Offset (0x1FC),
- HMCS, 32,
- Offset (0x21C),
- HDM1, 32,
- Offset (0x224),
- HCCM, 32,
- HVD1, 32,
- HVD2, 32
- }
-
- OperationRegion (CP10, SystemMemory, 0x01C0A800, 0x02F0)
- Field (CP10, DWordAcc, NoLock, Preserve)
- {
- Offset (0x0C),
- L0C0, 32,
- L0C1, 32,
- L0C2, 32,
- L0TE, 32,
- Offset (0x60),
- L0BM, 32,
- L0LM, 32,
- Offset (0x7C),
- L0PR, 32,
- Offset (0xC0),
- L0L0, 32,
- L0L1, 32,
- L0L2, 32,
- Offset (0xD0),
- L0R1, 32,
- L0R2, 32,
- L0M0, 32,
- L0M1, 32,
- L0M2, 32,
- Offset (0xFC),
- L0CD, 32,
- L0VD, 32,
- Offset (0x108),
- L0X0, 32,
- Offset (0x114),
- L0TT, 32,
- L0OT, 32,
- L0RT, 32,
- L0ET, 32,
- L0VG, 32,
- L0DG, 32,
- Offset (0x130),
- L0EG, 32,
- L0OG, 32,
- L0PG, 32,
- L0IN, 32,
- Offset (0x154),
- L0EI, 32,
- Offset (0x160),
- L0DI, 32,
- Offset (0x168),
- L0B0, 32,
- L0B1, 32,
- Offset (0x178),
- L0T1, 32,
- Offset (0x180),
- L0RC, 32,
- L0F0, 32,
- L0F1, 32,
- L0F2, 32,
- L0S0, 32,
- L0S1, 32,
- L0S2, 32,
- L0SC, 32,
- Offset (0x1A4),
- L0RB, 32,
- Offset (0x1C0),
- L0P0, 32,
- L0P1, 32,
- L0P2, 32,
- Offset (0x230),
- L0SE, 32,
- L0SN, 32,
- L0SD, 32,
- Offset (0x2A4),
- L0DC, 32,
- L0ST, 32,
- L0RE, 32,
- L0PC, 32,
- Offset (0x2B8),
- L0N0, 32,
- Offset (0x2C0),
- L0ER, 32,
- L0HI, 32,
- Offset (0x2CC),
- L0RR, 32
- }
-
- OperationRegion (CP11, SystemMemory, 0x01C0B000, 0x02F0)
- Field (CP11, DWordAcc, NoLock, Preserve)
- {
- Offset (0x0C),
- L1C0, 32,
- L1C1, 32,
- L1C2, 32,
- L1TE, 32,
- Offset (0x60),
- L1BM, 32,
- L1LM, 32,
- Offset (0x7C),
- L1PR, 32,
- Offset (0xC0),
- L1L0, 32,
- L1L1, 32,
- L1L2, 32,
- Offset (0xD0),
- L1R1, 32,
- L1R2, 32,
- L1M0, 32,
- L1M1, 32,
- L1M2, 32,
- Offset (0xFC),
- L1CD, 32,
- L1VD, 32,
- Offset (0x108),
- L1X0, 32,
- Offset (0x114),
- L1TT, 32,
- L1OT, 32,
- L1RT, 32,
- L1ET, 32,
- L1VG, 32,
- L1DG, 32,
- Offset (0x130),
- L1EG, 32,
- L1OG, 32,
- L1PG, 32,
- L1IN, 32,
- Offset (0x154),
- L1EI, 32,
- Offset (0x160),
- L1DI, 32,
- Offset (0x168),
- L1B0, 32,
- L1B1, 32,
- Offset (0x178),
- L1T1, 32,
- Offset (0x180),
- L1RC, 32,
- L1F0, 32,
- L1F1, 32,
- L1F2, 32,
- L1S0, 32,
- L1S1, 32,
- L1S2, 32,
- L1SC, 32,
- Offset (0x1A4),
- L1RB, 32,
- Offset (0x1C0),
- L1P0, 32,
- L1P1, 32,
- L1P2, 32,
- Offset (0x230),
- L1SE, 32,
- L1SN, 32,
- L1SD, 32,
- Offset (0x2A4),
- L1DC, 32,
- L1ST, 32,
- L1RE, 32,
- L1PC, 32,
- Offset (0x2B8),
- L1N0, 32,
- Offset (0x2C0),
- L1ER, 32,
- L1HI, 32,
- Offset (0x2CC),
- L1RR, 32
- }
-
- OperationRegion (CP12, SystemMemory, 0x01C0B800, 0x02DC)
- Field (CP12, DWordAcc, NoLock, Preserve)
- {
- HPSR, 32,
- HPDC, 32,
- HSTC, 32,
- Offset (0x2C),
- HTM3, 32,
- Offset (0x40),
- HTP3, 32,
- Offset (0x54),
- HTM6, 32,
- Offset (0x68),
- HTP6, 32,
- Offset (0x15C),
- HPSG, 32,
- Offset (0x174),
- HTRC, 32,
- Offset (0x2AC),
- HPST, 32
- }
-
- OperationRegion (CP13, SystemMemory, 0x40000000, 0x1000)
- Field (CP13, DWordAcc, NoLock, Preserve)
- {
- Offset (0x04),
- SCR1, 32,
- CRI1, 32,
- Offset (0x10),
- R1B0, 32,
- R1B1, 32,
- BNR1, 32,
- Offset (0x7C),
- LCA1, 32,
- LCS1, 32,
- SCA1, 32,
- SLC1, 32,
- Offset (0xA0),
- LC21, 32,
- Offset (0x154),
- P1PR, 32,
- Offset (0x710),
- GPLC, 32,
- Offset (0x80C),
- G32C, 32,
- Offset (0x8A8),
- GEQC, 32,
- GMDC, 32,
- Offset (0x8BC),
- CSW1, 32,
- Offset (0x900),
- IAV1, 32,
- CR11, 32,
- CR21, 32,
- ILB1, 32,
- IUB1, 32,
- ILR1, 32,
- ILT1, 32,
- IUT1, 32,
- Offset (0xF24),
- ESC1, 32,
- EST1, 32,
- Offset (0xFC4),
- ECS1, 32
- }
-
- OperationRegion (CP14, SystemMemory, 0x03971000, 0x10)
- Field (CP14, DWordAcc, NoLock, Preserve)
- {
- C113, 32,
- I113, 32,
- N113, 32,
- S113, 32
- }
-
- OperationRegion (CP15, SystemMemory, 0x0016B000, 0x1020)
- Field (CP15, DWordAcc, NoLock, Preserve)
- {
- GP0B, 32,
- Offset (0x101C),
- G0PB, 32
- }
-
- OperationRegion (CP16, SystemMemory, 0x0018D000, 0x1030)
- Field (CP16, DWordAcc, NoLock, Preserve)
- {
- GP1B, 32,
- Offset (0x1014),
- G1LB, 32,
- Offset (0x101C),
- G1PB, 32,
- G1NB, 32
- }
-
- Method (PPU1, 0, Serialized)
- {
- Name (TOUT, Zero)
- PDT1 = 0x04
- HPDC = 0x03
- HSES = 0x27
- HSEC = One
- HSP1 = 0x31
- HSP2 = One
- HSS1 = 0xDE
- HSS2 = 0x07
- HSM1 = 0x4C
- HSM2 = 0x06
- HECE = 0x18
- HCE1 = 0xB0
- C1M0 = 0x8C
- C2M0 = 0x20
- C1M1 = 0x14
- C2M1 = 0x34
- HCM0 = 0x06
- HCM1 = 0x06
- HPR0 = 0x16
- HPR1 = 0x16
- HPC0 = 0x36
- HPC1 = 0x36
- HRC2 = 0x05
- HCLC = 0x42
- HRM0 = 0x82
- HRM1 = 0x68
- S1M0 = 0x55
- S2M0 = 0x55
- S3M0 = 0x03
- S1M1 = 0xAB
- S2M1 = 0xAA
- S3M1 = 0x02
- G0M0 = 0x3F
- G0M1 = 0x3F
- HCVT = 0x10
- HCCS = Zero
- HCHS = 0x30
- HCDV = 0x04
- HCCE = 0x73
- HCCC = 0x1C
- HMCS = 0x15
- HDM1 = 0x04
- HCCM = One
- HVD1 = 0x22
- HVD2 = Zero
- L0C0 = Zero
- L0TE = 0x0D
- L0BM = One
- L0LM = 0x3A
- L0PR = 0x2F
- L0L0 = 0x09
- L0L1 = 0x09
- L0L2 = 0x1A
- L0R1 = One
- L0R2 = 0x07
- L0M0 = 0x31
- L0M1 = 0x31
- L0M2 = 0x03
- L0CD = 0x02
- L0VD = One
- L0X0 = 0x12
- L0TT = 0x25
- L0OT = Zero
- L0RT = 0x05
- L0ET = One
- L0VG = 0x26
- L0DG = 0x12
- L0EG = 0x04
- L0OG = 0x04
- L0PG = 0x09
- L0EI = 0x15
- L0DI = 0x32
- L0B0 = 0x7F
- L0B1 = 0x07
- L0T1 = 0x04
- L0RC = 0x70
- L0F0 = 0x08
- L0F1 = 0x08
- L0F2 = 0x09
- L0S0 = 0x04
- L0S1 = 0x04
- L0S2 = 0x02
- L0SC = 0x0C
- L0RB = 0x02
- L0P0 = 0x5C
- L0P1 = 0x3E
- L0P2 = 0x3F
- L0SE = 0x21
- L0SN = 0xA0
- L0SD = 0x08
- L0DC = One
- L0RE = 0xC3
- L0PC = Zero
- L0N0 = 0x8C
- L0ER = 0x7F
- L0HI = 0x2A
- L0C1 = 0x0C
- L0C2 = Zero
- L0RR = 0x02
- L0IN = 0x20
- L1C0 = Zero
- L1TE = 0x0D
- L1BM = One
- L1LM = 0x3A
- L1PR = 0x2F
- L1L0 = 0x09
- L1L1 = 0x09
- L1L2 = 0x1A
- L1R1 = One
- L1R2 = 0x07
- L1M0 = 0x31
- L1M1 = 0x31
- L1M2 = 0x03
- L1CD = 0x02
- L1VD = One
- L1X0 = 0x12
- L1TT = 0x25
- L1OT = Zero
- L1RT = 0x05
- L1ET = One
- L1VG = 0x26
- L1DG = 0x12
- L1EG = 0x04
- L1OG = 0x04
- L1PG = 0x09
- L1EI = 0x15
- L1DI = 0x32
- L1B0 = 0x7F
- L1B1 = 0x07
- L1T1 = 0x04
- L1RC = 0x70
- L1F0 = 0x08
- L1F1 = 0x08
- L1F2 = 0x09
- L1S0 = 0x04
- L1S1 = 0x04
- L1S2 = 0x02
- L1SC = 0x0C
- L1RB = 0x02
- L1P0 = 0x5C
- L1P1 = 0x3E
- L1P2 = 0x3F
- L1SE = 0x21
- L1SN = 0xA0
- L1SD = 0x08
- L1DC = One
- L1RE = 0xC3
- L1PC = Zero
- L1N0 = 0x8C
- L1ER = 0x7F
- L1HI = 0x2A
- L1C1 = 0x0C
- L1C2 = Zero
- L1RR = 0x02
- L1IN = 0x20
- HPSG = 0x3F
- HTRC = 0x58
- HTM3 = 0x19
- HTP3 = 0x07
- HTM6 = 0x17
- HTP6 = 0x09
- If ((SIDV >= 0x00020000)){}
- HPSR = Zero
- L0ST = One
- L1ST = One
- HSTC = One
- Local0 = HPST /* \_SB_.HPST */
- While ((Local0 & 0x40))
- {
- Sleep (One)
- TOUT++
- If ((TOUT == 0x0F))
- {
- Break
- }
-
- Local0 = HPST /* \_SB_.HPST */
- }
-
- If ((TOUT == 0x0F))
- {
- Return (One)
- }
- Else
- {
- Return (Zero)
- }
- }
-
- Method (LTS1, 0, Serialized)
- {
- Name (TOUT, Zero)
- Local0 = G32C /* \_SB_.G32C */
- Local0 &= 0xFFFFE0FF
- Local0 |= 0x0100
- G32C = Local0
- GMDC = 0x000155A0
- Local0 = GEQC /* \_SB_.GEQC */
- Local0 &= 0xFFFFFFEF
- GEQC = Local0
- CSW1 = One
- P1PR = 0x77777777
- CSW1 = Zero
- Local0 = GPLC /* \_SB_.GPLC */
- Local0 &= 0xFFC0F0FF
- Local0 |= 0x00030300
- GPLC = Local0
- PLT1 = 0x0100
- Local0 = EST1 /* \_SB_.EST1 */
- While (((Local0 & 0x0400) != 0x0400))
- {
- Sleep (One)
- TOUT++
- If ((TOUT == 0x96))
- {
- Break
- }
-
- Local0 = EST1 /* \_SB_.EST1 */
- }
-
- If ((TOUT == 0x96))
- {
- Return (One)
- }
- Else
- {
- Return (Zero)
- }
- }
-
- Method (IAT1, 0, Serialized)
- {
- IAV1 = One
- ILB1 = 0x40100000
- IUB1 = Zero
- ILR1 = 0x401FFFFF
- ILT1 = 0x01000000
- IUT1 = Zero
- CR11 = 0x04
- CR21 = 0x80000000
- BNR1 = 0x00010100
- }
-
- Method (REB1, 2, Serialized)
- {
- Local0 = PSC1 /* \_SB_.PSC1 */
- Local0 &= 0xFBFFFFFF
- PSC1 = Local0
- LBW0 = Arg0
- HBW0 = Zero
- LLW0 = Arg1
- HLW0 = Zero
- LBR0 = Arg0
- HBR0 = Zero
- LLR0 = Arg1
- HLR0 = Zero
- Local0 = PSC1 /* \_SB_.PSC1 */
- Local0 |= 0x04000000
- PSC1 = Local0
- }
-
- Method (EEB1, 2, Serialized)
- {
- Local0 = PSC1 /* \_SB_.PSC1 */
- Local0 &= 0xBFFFFFFF
- PSC1 = Local0
- LBW1 = Arg0
- HBW1 = Zero
- LLW1 = Arg1
- HLW1 = Zero
- LBR1 = Arg0
- HBR1 = Zero
- LLR1 = Arg1
- HLR1 = Zero
- Local0 = PSC1 /* \_SB_.PSC1 */
- Local0 |= 0x40000000
- PSC1 = Local0
- }
-
- Name (E1LT, 0x400FFFFF)
- Method (MSC1, 0, Serialized)
- {
- Local0 = SCR1 /* \_SB_.SCR1 */
- Local0 |= 0x02
- SCR1 = Local0
- PSL1 = 0x20000000
- Local0 = PPC1 /* \_SB_.PPC1 */
- Local0 &= 0xFFFFFFDF
- PPC1 = Local0
- CSW1 = One
- Local0 = LCA1 /* \_SB_.LCA1 */
- Local0 |= 0x00400000
- Local0 |= 0x0C00
- LCA1 = Local0
- Local0 = CRI1 /* \_SB_.CRI1 */
- Local0 &= 0xFFFF
- Local0 |= 0x06040000
- CRI1 = Local0
- Local0 = SCA1 /* \_SB_.SCA1 */
- Local0 &= 0xFFFFFFBF
- SCA1 = Local0
- CSW1 = Zero
- ECS1 = One
- R1B0 = Zero
- R1B1 = Zero
- ECS1 = Zero
- PEB1 = 0x40000000
- REB1 (0x40001000, E1LT)
- EEB1 (0x40101000, 0x401FFFFF)
- }
-
- Name (G1D3, Zero)
- Device (IPC0)
- {
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- GLNK
- })
- Name (_HID, "QCOM021C") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- }
-
- Device (GLNK)
- {
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- RPEN
- })
- Name (_HID, "QCOM02F9") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000001E3,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000BE,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000CC,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000260,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000001E1,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000BC,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000000CA,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x0000025E,
- }
- })
- Return (RBUF) /* \_SB_.GLNK._CRS.RBUF */
- }
- }
-
- Device (ARPC)
- {
- Name (_DEP, Package (0x03) // _DEP: Dependencies
- {
- MMU0,
- GLNK,
- SCM0
- })
- Name (_HID, "QCOM0297") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- }
-
- Device (ARPD)
- {
- Name (_DEP, Package (0x02) // _DEP: Dependencies
- {
- ADSP,
- ARPC
- })
- Name (_HID, "QCOM02F3") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- }
-
- Device (RFS0)
- {
- Name (_DEP, Package (0x02) // _DEP: Dependencies
- {
- IPC0,
- UFS0
- })
- Name (_HID, "QCOM0235") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x88888888, // Address Base
- 0x99999999, // Address Length
- _Y00)
- Memory32Fixed (ReadWrite,
- 0x11111111, // Address Base
- 0x22222222, // Address Length
- _Y01)
- Memory32Fixed (ReadWrite,
- 0x33333333, // Address Base
- 0x44444444, // Address Length
- _Y02)
- })
- CreateDWordField (RBUF, \_SB.RFS0._CRS._Y00._BAS, RMTA) // _BAS: Base Address
- CreateDWordField (RBUF, \_SB.RFS0._CRS._Y00._LEN, RMTL) // _LEN: Length
- CreateDWordField (RBUF, \_SB.RFS0._CRS._Y01._BAS, RFMA) // _BAS: Base Address
- CreateDWordField (RBUF, \_SB.RFS0._CRS._Y01._LEN, RFML) // _LEN: Length
- CreateDWordField (RBUF, \_SB.RFS0._CRS._Y02._BAS, RFAA) // _BAS: Base Address
- CreateDWordField (RBUF, \_SB.RFS0._CRS._Y02._LEN, RFAL) // _LEN: Length
- RMTA = RMTB /* \_SB_.RMTB */
- RMTL = RMTX /* \_SB_.RMTX */
- RFMA = RFMB /* \_SB_.RFMB */
- RFML = RFMS /* \_SB_.RFMS */
- RFAA = RFAB /* \_SB_.RFAB */
- RFAL = RFAS /* \_SB_.RFAS */
- Return (RBUF) /* \_SB_.RFS0._CRS.RBUF */
- }
-
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0B)
- }
- }
-
- Device (IPA)
- {
- Name (_DEP, Package (0x06) // _DEP: Dependencies
- {
- PEP0,
- RPEN,
- PILC,
- MMU0,
- GSI,
- GLNK
- })
- Name (_HID, "QCOM02B3") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Return (ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x01E40000, // Address Base
- 0x0001FFFF, // Address Length
- )
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x00000157,
- }
- })
- }
- }
-
- Device (GSI)
- {
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PEP0
- })
- Name (_HID, "QCOM02E7") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x01E00000, // Address Base
- 0x00030000, // Address Length
- )
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- 0x000001D0,
- }
- })
- Return (RBUF) /* \_SB_.GSI_._CRS.RBUF */
- }
- }
-
- Device (QDIG)
- {
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- GLNK
- })
- Name (_HID, "QCOM0225") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- }
-
- Device (QCDB)
- {
- Name (_HID, "QCOM0298") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- }
-
- Device (SYSM)
- {
- Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
- Name (_UID, 0x00100000) // _UID: Unique ID
- Name (_LPI, Package (0x05) // _LPI: Low Power Idle States
- {
- Zero,
- 0x01000000,
- 0x02,
- Package (0x0A)
- {
- 0x251C,
- 0x1770,
- Zero,
- 0x20,
- Zero,
- Zero,
- 0x3300,
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "platform.F1"
- },
-
- Package (0x0A)
- {
- 0x2710,
- 0x19C8,
- One,
- 0x20,
- Zero,
- Zero,
- 0xC300,
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "platform.F2"
- }
- })
- Device (CLUS)
- {
- Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
- Name (_UID, 0x10) // _UID: Unique ID
- Name (_LPI, Package (0x05) // _LPI: Low Power Idle States
- {
- Zero,
- 0x01000000,
- 0x02,
- Package (0x0A)
- {
- 0x170C,
- 0x0BB8,
- Zero,
- Zero,
- Zero,
- Zero,
- 0x20,
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "L3Cluster.D2"
- },
-
- Package (0x0A)
- {
- 0x1770,
- 0x0CE4,
- One,
- Zero,
- Zero,
- 0x02,
- 0x40,
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "L3Cluster.D4"
- }
- })
- Device (CPU0)
- {
- Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
- Name (_UID, Zero) // _UID: Unique ID
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Name (_LPI, Package (0x07) // _LPI: Low Power Idle States
- {
- Zero,
- Zero,
- 0x04,
- Package (0x0A)
- {
- Zero,
- Zero,
- One,
- Zero,
- Zero,
- Zero,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x00000000FFFFFFFF, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver0.C1"
- },
-
- Package (0x0A)
- {
- 0x0190,
- 0x64,
- Zero,
- Zero,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000002, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver0.C2"
- },
-
- Package (0x0A)
- {
- 0x1388,
- 0x01F4,
- One,
- One,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000003, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver0.C3"
- },
-
- Package (0x0A)
- {
- 0x13EC,
- 0x0226,
- One,
- One,
- Zero,
- 0x02,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000004, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver0.C4"
- }
- })
- }
-
- Device (CPU1)
- {
- Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
- Name (_UID, One) // _UID: Unique ID
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Name (_LPI, Package (0x07) // _LPI: Low Power Idle States
- {
- Zero,
- Zero,
- 0x04,
- Package (0x0A)
- {
- Zero,
- Zero,
- One,
- Zero,
- Zero,
- Zero,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x00000000FFFFFFFF, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver1.C1"
- },
-
- Package (0x0A)
- {
- 0x0190,
- 0x64,
- Zero,
- Zero,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000002, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver1.C2"
- },
-
- Package (0x0A)
- {
- 0x1388,
- 0x01F4,
- One,
- One,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000003, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver1.C3"
- },
-
- Package (0x0A)
- {
- 0x13EC,
- 0x0226,
- One,
- One,
- Zero,
- 0x02,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000004, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver1.C4"
- }
- })
- }
-
- Device (CPU2)
- {
- Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
- Name (_UID, 0x02) // _UID: Unique ID
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Name (_LPI, Package (0x07) // _LPI: Low Power Idle States
- {
- Zero,
- Zero,
- 0x04,
- Package (0x0A)
- {
- Zero,
- Zero,
- One,
- Zero,
- Zero,
- Zero,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x00000000FFFFFFFF, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver2.C1"
- },
-
- Package (0x0A)
- {
- 0x0190,
- 0x64,
- Zero,
- Zero,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000002, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver2.C2"
- },
-
- Package (0x0A)
- {
- 0x1388,
- 0x01F4,
- One,
- One,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000003, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver2.C3"
- },
-
- Package (0x0A)
- {
- 0x13EC,
- 0x0226,
- One,
- One,
- Zero,
- 0x02,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000004, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver2.C4"
- }
- })
- }
-
- Device (CPU3)
- {
- Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
- Name (_UID, 0x03) // _UID: Unique ID
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Name (_LPI, Package (0x07) // _LPI: Low Power Idle States
- {
- Zero,
- Zero,
- 0x04,
- Package (0x0A)
- {
- Zero,
- Zero,
- One,
- Zero,
- Zero,
- Zero,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x00000000FFFFFFFF, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver3.C1"
- },
-
- Package (0x0A)
- {
- 0x0190,
- 0x64,
- Zero,
- Zero,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000002, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver3.C2"
- },
-
- Package (0x0A)
- {
- 0x1388,
- 0x01F4,
- One,
- One,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000003, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver3.C3"
- },
-
- Package (0x0A)
- {
- 0x13EC,
- 0x0226,
- One,
- One,
- Zero,
- 0x02,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000004, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoSilver3.C4"
- }
- })
- }
-
- Device (CPU4)
- {
- Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
- Name (_UID, 0x04) // _UID: Unique ID
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Name (_LPI, Package (0x07) // _LPI: Low Power Idle States
- {
- Zero,
- Zero,
- 0x04,
- Package (0x0A)
- {
- Zero,
- Zero,
- One,
- Zero,
- Zero,
- Zero,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x00000000FFFFFFFF, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold0.C1"
- },
-
- Package (0x0A)
- {
- 0x0190,
- 0x64,
- Zero,
- Zero,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000002, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold0.C2"
- },
-
- Package (0x0A)
- {
- 0x03E8,
- 0x028A,
- One,
- One,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000003, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold0.C3"
- },
-
- Package (0x0A)
- {
- 0x05DC,
- 0x044C,
- One,
- One,
- Zero,
- 0x02,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000004, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold0.C4"
- }
- })
- }
-
- Device (CPU5)
- {
- Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
- Name (_UID, 0x05) // _UID: Unique ID
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Name (_LPI, Package (0x07) // _LPI: Low Power Idle States
- {
- Zero,
- Zero,
- 0x04,
- Package (0x0A)
- {
- Zero,
- Zero,
- One,
- Zero,
- Zero,
- Zero,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x00000000FFFFFFFF, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold1.C1"
- },
-
- Package (0x0A)
- {
- 0x0190,
- 0x64,
- Zero,
- Zero,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000002, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold1.C2"
- },
-
- Package (0x0A)
- {
- 0x03E8,
- 0x028A,
- One,
- One,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000003, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold1.C3"
- },
-
- Package (0x0A)
- {
- 0x05DC,
- 0x044C,
- One,
- One,
- Zero,
- 0x02,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000004, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold1.C4"
- }
- })
- }
-
- Device (CPU6)
- {
- Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
- Name (_UID, 0x06) // _UID: Unique ID
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Name (_LPI, Package (0x07) // _LPI: Low Power Idle States
- {
- Zero,
- Zero,
- 0x04,
- Package (0x0A)
- {
- Zero,
- Zero,
- One,
- Zero,
- Zero,
- Zero,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x00000000FFFFFFFF, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold2.C1"
- },
-
- Package (0x0A)
- {
- 0x0190,
- 0x64,
- Zero,
- Zero,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000002, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold2.C2"
- },
-
- Package (0x0A)
- {
- 0x03E8,
- 0x028A,
- One,
- One,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000003, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold2.C3"
- },
-
- Package (0x0A)
- {
- 0x05DC,
- 0x044C,
- One,
- One,
- Zero,
- 0x02,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000004, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold2.C4"
- }
- })
- }
-
- Device (CPU7)
- {
- Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
- Name (_UID, 0x07) // _UID: Unique ID
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Name (_LPI, Package (0x07) // _LPI: Low Power Idle States
- {
- Zero,
- Zero,
- 0x04,
- Package (0x0A)
- {
- Zero,
- Zero,
- One,
- Zero,
- Zero,
- Zero,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x00000000FFFFFFFF, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold3.C1"
- },
-
- Package (0x0A)
- {
- 0x0190,
- 0x64,
- Zero,
- Zero,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000002, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold3.C2"
- },
-
- Package (0x0A)
- {
- 0x03E8,
- 0x028A,
- One,
- One,
- Zero,
- One,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000003, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold3.C3"
- },
-
- Package (0x0A)
- {
- 0x05DC,
- 0x044C,
- One,
- One,
- Zero,
- 0x02,
- ResourceTemplate ()
- {
- Register (FFixedHW,
- 0x20, // Bit Width
- 0x00, // Bit Offset
- 0x0000000040000004, // Address
- 0x03, // Access Size
- )
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- ResourceTemplate ()
- {
- Register (SystemMemory,
- 0x00, // Bit Width
- 0x00, // Bit Offset
- 0x0000000000000000, // Address
- ,)
- },
-
- "KryoGold3.C4"
- }
- })
- }
- }
- }
-
- Device (QRNG)
- {
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PEP0
- })
- Name (_HID, "QCOM02FE") // _HID: Hardware ID
- Name (_UID, Zero) // _UID: Unique ID
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x00793000, // Address Base
- 0x00001000, // Address Length
- )
- })
- Return (RBUF) /* \_SB_.QRNG._CRS.RBUF */
- }
- }
-
- Device (GPS)
- {
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- GLNK
- })
- Name (_HID, "QCOM02B6") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_CID, "ACPIQCOM24B4") // _CID: Compatible ID
- Name (_UID, Zero) // _UID: Unique ID
- }
-
- Device (QGP0)
- {
- Name (_HID, "QCOM02F4") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x00804000, // Address Base
- 0x00050000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000119,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x0000011B,
- }
- })
- Return (RBUF) /* \_SB_.QGP0._CRS.RBUF */
- }
-
- Method (GPII, 0, Serialized)
- {
- Return (Package (0x02)
- {
- Package (0x03)
- {
- Zero,
- 0x05,
- 0x0119
- },
-
- Package (0x03)
- {
- Zero,
- 0x07,
- 0x011B
- }
- })
- }
- }
-
- Device (QGP1)
- {
- Name (_HID, "QCOM02F4") // _HID: Hardware ID
- Alias (\_SB.PSUB, _SUB)
- Name (_UID, One) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x00A04000, // Address Base
- 0x00050000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000138,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x0000013A,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000145,
- }
- })
- Return (RBUF) /* \_SB_.QGP1._CRS.RBUF */
- }
-
- Method (GPII, 0, Serialized)
- {
- Return (Package (0x03)
- {
- Package (0x03)
- {
- One,
- One,
- 0x0138
- },
-
- Package (0x03)
- {
- One,
- 0x03,
- 0x013A
- },
-
- Package (0x03)
- {
- One,
- 0x06,
- 0x0145
- }
- })
- }
- }
-
- Device (SARM)
- {
- Name (_HID, "QCOM0301") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- }
-
- Scope (\_SB)
- {
- Device (WBDI)
- {
- Name (_HID, "SAM0909") // _HID: Hardware ID
- Name (_UID, Zero) // _UID: Unique ID
- Name (_SUB, "RENEGA0E") // _SUB: Subsystem ID
- Name (_DEP, Package (0x02) // _DEP: Dependencies
- {
- GIO0,
- SCM0
- })
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- GpioIo (Exclusive, PullNone, 0x0000, 0x0000, IoRestrictionNone,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x003E
- }
- GpioIo (Exclusive, PullNone, 0x0000, 0x0000, IoRestrictionNone,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x003B
- }
- GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault, 0x0000,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x003C
- }
- })
- Return (RBUF) /* \_SB_.WBDI._CRS.RBUF */
- }
- }
- }
-
- Scope (\_SB)
- {
- Name (GRST, Zero)
- }
-
- Device (SEN2)
- {
- Name (_DEP, Package (0x03) // _DEP: Dependencies
- {
- IPC0,
- SCSS,
- ARPC
- })
- Name (_HID, "QCOM0308") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_CID, "QCOM02A2") // _CID: Compatible ID
- }
-
- Device (LID0)
- {
- Name (_HID, "PNP0C0D" /* Lid Device */) // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (LIDB, One)
- Method (_LID, 0, NotSerialized) // _LID: Lid Status
- {
- Return (LIDB) /* \_SB_.LID0.LIDB */
- }
- }
-
- Method (ADDR, 0, NotSerialized)
- {
- If ((SVMJ == One))
- {
- Return (0x0390B000)
- }
- ElseIf ((SVMJ == 0x02))
- {
- Return (0x0350B000)
- }
- }
-
- OperationRegion (NM11, SystemMemory, ADDR (), 0x14)
- Field (NM11, DWordAcc, NoLock, Preserve)
- {
- PI1C, 32,
- PIN1, 32,
- PI1N, 32,
- PI1S, 32,
- PI1L, 32
- }
-
- Method (_MID, 0, Serialized)
- {
- Name (NMID, Zero)
- NMID = PIN1 /* \_SB_.PIN1 */
- Return (NMID) /* \_SB_._MID.NMID */
- }
-
- Scope (\_SB)
- {
- Device (AGNT)
- {
- Name (_ADR, Zero) // _ADR: Address
- Name (_HID, "SAM0603") // _HID: Hardware ID
- Name (_CID, "SAM0603") // _CID: Compatible ID
- Name (_SUB, "RENEGA0E") // _SUB: Subsystem ID
- Name (_UID, One) // _UID: Unique ID
- Name (_STA, 0x0F) // _STA: Status
- }
- }
-
- Method (ADBG, 1, Serialized)
- {
- }
-
- Device (UCP0)
- {
- Name (_HID, "QCOM02D0") // _HID: Hardware ID
- Name (_DEP, Package (0x03) // _DEP: Dependencies
- {
- PEP0,
- PTCC,
- URS0
- })
- Device (CON0)
- {
- Name (_ADR, Zero) // _ADR: Address
- Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
- {
- ToPLD (
- PLD_Revision = 0x2,
- PLD_IgnoreColor = 0x1,
- PLD_Red = 0x0,
- PLD_Green = 0x0,
- PLD_Blue = 0x0,
- PLD_Width = 0x0,
- PLD_Height = 0x0,
- PLD_UserVisible = 0x1,
- PLD_Dock = 0x0,
- PLD_Lid = 0x0,
- PLD_Panel = "BACK",
- PLD_VerticalPosition = "CENTER",
- PLD_HorizontalPosition = "LEFT",
- PLD_Shape = "VERTICALRECTANGLE",
- PLD_GroupOrientation = 0x0,
- PLD_GroupToken = 0x0,
- PLD_GroupPosition = 0x1,
- PLD_Bay = 0x0,
- PLD_Ejectable = 0x0,
- PLD_EjectRequired = 0x0,
- PLD_CabinetNumber = 0x0,
- PLD_CardCageNumber = 0x0,
- PLD_Reference = 0x0,
- PLD_Rotation = 0x0,
- PLD_Order = 0x0,
- PLD_VerticalOffset = 0xFFFF,
- PLD_HorizontalOffset = 0xFFFF)
-
- })
- Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
- {
- One,
- 0x09,
- Zero,
- Zero
- })
- Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
- {
- ToUUID ("6b856e62-40f4-4688-bd46-5e888a2260de") /* Unknown UUID */,
- Package (0x0A)
- {
- Package (0x02)
- {
- One,
- 0x04
- },
-
- Package (0x02)
- {
- 0x02,
- 0x03
- },
-
- Package (0x02)
- {
- 0x03,
- Zero
- },
-
- Package (0x02)
- {
- 0x04,
- One
- },
-
- Package (0x02)
- {
- 0x05,
- 0x03
- },
-
- Package (0x02)
- {
- 0x06,
- Package (0x01)
- {
- 0x0001905A
- }
- },
-
- Package (0x02)
- {
- 0x07,
- Package (0x02)
- {
- 0x0001912C,
- 0x0002D0C8
- }
- },
-
- Package (0x02)
- {
- 0x08,
- Package (0x02)
- {
- 0xFF01,
- 0x3C86
- }
- },
-
- Package (0x02)
- {
- 0x09,
- One
- },
-
- Package (0x02)
- {
- 0x0A,
- One
- }
- }
- })
- }
-
- Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
- {
- While (One)
- {
- Name (_T_0, Buffer (One) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- {
- 0x00 // .
- })
- CopyObject (ToBuffer (Arg0), _T_0) /* \_SB_.UCP0._DSM._T_0 */
- If ((_T_0 == ToUUID ("18de299f-9476-4fc9-b43b-8aeb713ed751") /* Unknown UUID */))
- {
- While (One)
- {
- Name (_T_1, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_1 = ToInteger (Arg2)
- If ((_T_1 == Zero))
- {
- While (One)
- {
- Name (_T_2, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_2 = ToInteger (Arg1)
- If ((_T_2 == Zero))
- {
- Return (Buffer (One)
- {
- 0x01 // .
- })
- Break
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x01 // .
- })
- Break
- }
-
- Break
- }
-
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
- ElseIf ((_T_1 == One))
- {
- While (One)
- {
- Name (_T_3, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_3 = ToInteger (Arg3)
- If ((_T_3 == Zero))
- {
- Return (Package (0x01)
- {
- 0x36019050
- })
- Break
- }
- ElseIf ((_T_3 == One))
- {
- Return (Package (0x01)
- {
- 0x3601912C
- })
- Break
- }
- Else
- {
- Return (Package (0x01)
- {
- Zero
- })
- Break
- }
-
- Break
- }
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
-
- Break
- }
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
-
- Break
- }
- }
-
- Method (CCOT, 2, NotSerialized)
- {
- CCST = Arg0
- HSFL = Arg1
- }
-
- Method (CCVL, 0, NotSerialized)
- {
- Return (CCST) /* \_SB_.CCST */
- }
-
- Method (HPDS, 0, NotSerialized)
- {
- Notify (GPU0, 0x94) // Device-Specific
- }
-
- Method (HPDF, 2, NotSerialized)
- {
- HPDB = Arg0
- PINA = Arg1
- Notify (GPU0, HPDB)
- }
-
- Method (HPDV, 0, NotSerialized)
- {
- Return (HPDB) /* \_SB_.HPDB */
- }
-
- Method (PINV, 0, NotSerialized)
- {
- Return (PINA) /* \_SB_.PINA */
- }
- }
-
- Name (QUFN, Zero)
- Name (DPP0, Buffer (One)
- {
- 0x00 // .
- })
- Device (URS0)
- {
- Method (URSI, 0, NotSerialized)
- {
- If ((QUFN == Zero))
- {
- Return ("QCOM0304")
- }
- Else
- {
- Return ("QCOM0305")
- }
- }
-
- Alias (URSI, _HID)
- Name (_CID, "PNP0CA1") // _CID: Compatible ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Name (_CCA, Zero) // _CCA: Cache Coherency Attribute
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PEP0
- })
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- Memory32Fixed (ReadWrite,
- 0x0A600000, // Address Base
- 0x000FFFFF, // Address Length
- )
- })
- Device (USB0)
- {
- Name (_ADR, Zero) // _ADR: Address
- Name (_S0W, 0x03) // _S0W: S0 Device Wake State
- Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
- {
- ToPLD (
- PLD_Revision = 0x2,
- PLD_IgnoreColor = 0x1,
- PLD_Red = 0x0,
- PLD_Green = 0x0,
- PLD_Blue = 0x0,
- PLD_Width = 0x0,
- PLD_Height = 0x0,
- PLD_UserVisible = 0x1,
- PLD_Dock = 0x0,
- PLD_Lid = 0x0,
- PLD_Panel = "BACK",
- PLD_VerticalPosition = "CENTER",
- PLD_HorizontalPosition = "LEFT",
- PLD_Shape = "VERTICALRECTANGLE",
- PLD_GroupOrientation = 0x0,
- PLD_GroupToken = 0x0,
- PLD_GroupPosition = 0x1,
- PLD_Bay = 0x0,
- PLD_Ejectable = 0x0,
- PLD_EjectRequired = 0x0,
- PLD_CabinetNumber = 0x0,
- PLD_CardCageNumber = 0x0,
- PLD_Reference = 0x0,
- PLD_Rotation = 0x0,
- PLD_Order = 0x0,
- PLD_VerticalOffset = 0xFFFF,
- PLD_HorizontalOffset = 0xFFFF)
-
- })
- Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
- {
- One,
- 0x09,
- Zero,
- Zero
- })
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
- {
- 0x000000A5,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, )
- {
- 0x0000017A,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, )
- {
- 0x00000206,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, )
- {
- 0x00000208,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, )
- {
- 0x00000209,
- }
- })
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
-
- Method (DPM0, 1, NotSerialized)
- {
- DPP0 = Arg0
- Notify (PEP0, 0xA0) // Device-Specific
- }
-
- Method (CCVL, 0, NotSerialized)
- {
- Return (CCST) /* \_SB_.CCST */
- }
-
- Method (HSEN, 0, NotSerialized)
- {
- Return (HSFL) /* \_SB_.HSFL */
- }
-
- Name (HSEI, ResourceTemplate ()
- {
- GpioIo (Exclusive, PullNone, 0x0000, 0x0000, IoRestrictionNone,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x002B
- }
- })
- Scope (^^GIO0)
- {
- OperationRegion (HLEN, GeneralPurposeIo, Zero, One)
- }
-
- Field (^^GIO0.HLEN, ByteAcc, NoLock, Preserve)
- {
- Connection (HSEI),
- MOD1, 1
- }
-
- Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
- {
- While (One)
- {
- Name (_T_0, Buffer (One) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- {
- 0x00 // .
- })
- CopyObject (ToBuffer (Arg0), _T_0) /* \_SB_.URS0.USB0._DSM._T_0 */
- If ((_T_0 == ToUUID ("ce2ee385-00e6-48cb-9f05-2edb927c4899") /* USB Controller */))
- {
- While (One)
- {
- Name (_T_1, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_1 = ToInteger (Arg2)
- If ((_T_1 == Zero))
- {
- While (One)
- {
- Name (_T_2, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_2 = ToInteger (Arg1)
- If ((_T_2 == Zero))
- {
- Return (Buffer (One)
- {
- 0x1D // .
- })
- Break
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x01 // .
- })
- Break
- }
-
- Break
- }
-
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
- ElseIf ((_T_1 == 0x02))
- {
- Return (Zero)
- Break
- }
- ElseIf ((_T_1 == 0x03))
- {
- Return (One)
- Break
- }
- ElseIf ((_T_1 == 0x04))
- {
- Return (0x02)
- Break
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
-
- Break
- }
- }
- ElseIf ((_T_0 == ToUUID ("a9a82a56-95a1-4b4a-b014-3be47df1b7d5") /* Unknown UUID */))
- {
- While (One)
- {
- Name (_T_3, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_3 = ToInteger (Arg1)
- If ((_T_3 == One))
- {
- While (One)
- {
- Name (_T_4, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_4 = ToInteger (Arg2)
- If ((_T_4 == One))
- {
- ADBG ("MOD1+")
- MOD1 = One
- Return (Buffer (One)
- {
- 0x01 // .
- })
- }
- ElseIf ((_T_4 == Zero))
- {
- ADBG ("MOD1-")
- MOD1 = Zero
- Return (Buffer (One)
- {
- 0x01 // .
- })
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
-
- Break
- }
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
-
- Break
- }
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
-
- Break
- }
- }
-
- Method (PHYC, 0, NotSerialized)
- {
- Name (CFG0, Package (0x01)
- {
- Package (0x03)
- {
- Zero,
- 0x088E2198,
- 0x20
- }
- })
- Return (CFG0) /* \_SB_.URS0.USB0.PHYC.CFG0 */
- }
-
- Device (RHUB)
- {
- Name (_ADR, Zero) // _ADR: Address
- Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
- {
- While (One)
- {
- Name (_T_0, Buffer (One) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- {
- 0x00 // .
- })
- CopyObject (ToBuffer (Arg0), _T_0) /* \_SB_.URS0.USB0.RHUB._DSM._T_0 */
- If ((_T_0 == ToUUID ("a9a82a56-95a1-4b4a-b014-3be47df1b7d5") /* Unknown UUID */))
- {
- While (One)
- {
- Name (_T_1, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_1 = ToInteger (Arg1)
- If ((_T_1 == One))
- {
- While (One)
- {
- Name (_T_2, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_2 = ToInteger (Arg2)
- If ((_T_2 == One))
- {
- ADBG ("MOD1++")
- MOD1 = One
- Return (Buffer (One)
- {
- 0x01 // .
- })
- }
- ElseIf ((_T_2 == Zero))
- {
- ADBG ("MOD1--")
- MOD1 = Zero
- Return (Buffer (One)
- {
- 0x01 // .
- })
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
-
- Break
- }
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- }
-
- Break
- }
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
-
- Break
- }
- }
- }
- }
-
- Device (UFN0)
- {
- Name (_ADR, One) // _ADR: Address
- Name (_S0W, 0x03) // _S0W: S0 Device Wake State
- Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
- {
- ToPLD (
- PLD_Revision = 0x2,
- PLD_IgnoreColor = 0x1,
- PLD_Red = 0x0,
- PLD_Green = 0x0,
- PLD_Blue = 0x0,
- PLD_Width = 0x0,
- PLD_Height = 0x0,
- PLD_UserVisible = 0x1,
- PLD_Dock = 0x0,
- PLD_Lid = 0x0,
- PLD_Panel = "BACK",
- PLD_VerticalPosition = "CENTER",
- PLD_HorizontalPosition = "LEFT",
- PLD_Shape = "VERTICALRECTANGLE",
- PLD_GroupOrientation = 0x0,
- PLD_GroupToken = 0x0,
- PLD_GroupPosition = 0x1,
- PLD_Bay = 0x0,
- PLD_Ejectable = 0x0,
- PLD_EjectRequired = 0x0,
- PLD_CabinetNumber = 0x0,
- PLD_CardCageNumber = 0x0,
- PLD_Reference = 0x0,
- PLD_Rotation = 0x0,
- PLD_Order = 0x0,
- PLD_VerticalOffset = 0xFFFF,
- PLD_HorizontalOffset = 0xFFFF)
-
- })
- Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
- {
- One,
- 0x09,
- Zero,
- Zero
- })
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
- {
- 0x000000A5,
- }
- Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, )
- {
- 0x000000A2,
- }
- })
- Method (CCVL, 0, NotSerialized)
- {
- Return (CCST) /* \_SB_.CCST */
- }
-
- Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
- {
- While (One)
- {
- Name (_T_0, Buffer (One) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- {
- 0x00 // .
- })
- CopyObject (ToBuffer (Arg0), _T_0) /* \_SB_.URS0.UFN0._DSM._T_0 */
- If ((_T_0 == ToUUID ("fe56cfeb-49d5-4378-a8a2-2978dbe54ad2") /* Unknown UUID */))
- {
- While (One)
- {
- Name (_T_1, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_1 = ToInteger (Arg2)
- If ((_T_1 == Zero))
- {
- While (One)
- {
- Name (_T_2, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_2 = ToInteger (Arg1)
- If ((_T_2 == Zero))
- {
- Return (Buffer (One)
- {
- 0x03 // .
- })
- Break
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x01 // .
- })
- Break
- }
-
- Break
- }
-
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
- ElseIf ((_T_1 == One))
- {
- Return (0x20)
- Break
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
-
- Break
- }
- }
- ElseIf ((_T_0 == ToUUID ("18de299f-9476-4fc9-b43b-8aeb713ed751") /* Unknown UUID */))
- {
- While (One)
- {
- Name (_T_3, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_3 = ToInteger (Arg2)
- If ((_T_3 == Zero))
- {
- While (One)
- {
- Name (_T_4, Zero) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z
- _T_4 = ToInteger (Arg1)
- If ((_T_4 == Zero))
- {
- Return (Buffer (One)
- {
- 0x03 // .
- })
- Break
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x01 // .
- })
- Break
- }
-
- Break
- }
-
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
- ElseIf ((_T_3 == One))
- {
- Return (0x39)
- Break
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
-
- Break
- }
- }
- Else
- {
- Return (Buffer (One)
- {
- 0x00 // .
- })
- Break
- }
-
- Break
- }
- }
-
- Method (PHYC, 0, NotSerialized)
- {
- Name (CFG0, Package (0x12)
- {
- Package (0x03)
- {
- Zero,
- 0x088E2210,
- 0x23
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2004,
- 0x03
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E218C,
- 0x7C
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E202C,
- 0x80
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2184,
- 0x0A
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E20B4,
- 0x19
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2194,
- 0x40
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2198,
- 0x28
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2214,
- 0x21
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2220,
- Zero
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2224,
- 0x58
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2240,
- 0x35
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2244,
- 0x29
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2248,
- 0xCA
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E224C,
- 0x04
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2250,
- 0x03
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E223C,
- Zero
- },
-
- Package (0x03)
- {
- Zero,
- 0x088E2210,
- 0x22
- }
- })
- Return (CFG0) /* \_SB_.URS0.UFN0.PHYC.CFG0 */
- }
- }
- }
-
- Name (HPDB, Zero)
- Name (PINA, Zero)
- Name (CCST, Buffer (One)
- {
- 0x02 // .
- })
- Name (HSFL, Buffer (One)
- {
- 0x00 // .
- })
- Name (HPDS, Zero)
- Name (USBC, Buffer (One)
- {
- 0x0B // .
- })
- Name (DPPN, 0x0D)
- Name (MUXC, Buffer (One)
- {
- 0x00 // .
- })
- Name (DPP1, Buffer (One)
- {
- 0x00 // .
- })
- Name (SKYD, Buffer (One)
- {
- 0x01 // .
- })
-
-Include("cust_thermal_zones.asl")
-
- Name (HWNH, Zero)
- Name (HWNL, Zero)
- Device (HWN1)
- {
- Name (_HID, "QCOM02A9") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- If ((HWNH == Zero))
- {
- Return (Zero)
- }
- Else
- {
- Return (0x0F)
- }
- }
-
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- PMIC
- })
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- GpioInt (Level, ActiveHigh, Exclusive, PullNone, 0x0000,
- "\\_SB.PM01", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x0190
- }
- })
- Return (RBUF) /* \_SB_.HWN1._CRS.RBUF */
- }
-
- Method (HAPI, 0, NotSerialized)
- {
- Name (CFG0, Package (0x03)
- {
- One,
- One,
- One
- })
- Return (CFG0) /* \_SB_.HWN1.HAPI.CFG0 */
- }
-
- Method (HAPC, 0, NotSerialized)
- {
- Name (CFG0, Package (0x16)
- {
- Zero,
- 0x0984,
- Zero,
- One,
- One,
- One,
- One,
- Zero,
- 0x04,
- One,
- 0x03,
- 0x14,
- One,
- 0x03,
- Zero,
- Zero,
- 0x06,
- Zero,
- Zero,
- 0x0535,
- 0x03,
- One
- })
- Return (CFG0) /* \_SB_.HWN1.HAPC.CFG0 */
- }
- }
-
- Device (HWN0)
- {
- Name (_HID, "QCOM02A8") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- If ((^^HWNL == Zero))
- {
- Return (Zero)
- }
- Else
- {
- Return (0x0F)
- }
- }
-
- Method (HWNL, 0, NotSerialized)
- {
- Name (CFG0, Package (0x10)
- {
- One,
- 0x03,
- 0x019B,
- 0x14,
- 0x20,
- 0x02,
- 0x40,
- 0x03,
- 0x80,
- 0x04,
- One,
- One,
- One,
- 0x03,
- One,
- One
- })
- Return (CFG0) /* \_SB_.HWN0.HWNL.CFG0 */
- }
- }
-
- Device (CONT)
- {
- Name (_HID, "CONT1234") // _HID: Hardware ID
- Name (_CID, "PNP0C60" /* Display Sensor Device */) // _CID: Compatible ID
- }
-
- Device (POWR)
- {
- Name (_HID, "POWR1234") // _HID: Hardware ID
- Name (_CID, "PNP0C40" /* Standard Button Controller */) // _CID: Compatible ID
- }
-
- Device (SVBI)
- {
- Name (_HID, "SAMM0901") // _HID: Hardware ID
- Name (_SUB, "RENEGA0E") // _SUB: Subsystem ID
- }
-
- Device (TSC1)
- {
- Name (_HID, "MSHW1003") // _HID: Hardware ID
- Name (_UID, One) // _UID: Unique ID
- Name (_DEP, Package (0x03) // _DEP: Dependencies
- {
- PEP0,
- GIO0,
- IC15
- })
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- I2cSerialBusV2 (0x0020, ControllerInitiated, 0x00061A80,
- AddressingMode7Bit, "\\_SB.IC15",
- 0x00, ResourceConsumer, , Exclusive,
- )
- GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullUp, 0x0000,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x007D
- }
- GpioIo (Exclusive, PullNone, 0x0000, 0x0000, IoRestrictionNone,
- "\\_SB.GIO0", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x0063
- }
- })
- Return (RBUF) /* \_SB_.TSC1._CRS.RBUF */
- }
-
- Name (PGID, Buffer (0x0A)
- {
- "\\_SB.TSC1"
- })
- Name (DBUF, Buffer (DBFL){})
- CreateByteField (DBUF, Zero, STAT)
- CreateByteField (DBUF, 0x02, DVAL)
- CreateField (DBUF, 0x18, 0xA0, DEID)
- Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
- {
- Return (0x03)
- }
-
- Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
- {
- Return (0x03)
- }
-
- Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
- {
- Return (0x03)
- }
-
- Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
- {
- DEID = Buffer (ESNL){}
- DVAL = Zero
- DEID = PGID /* \_SB_.TSC1.PGID */
- If (^^ABD.AVBL)
- {
- ^^PEP0.FLD0 = DBUF /* \_SB_.TSC1.DBUF */
- }
- }
-
- Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
- {
- DEID = Buffer (ESNL){}
- DVAL = 0x03
- DEID = PGID /* \_SB_.TSC1.PGID */
- If (^^ABD.AVBL)
- {
- ^^PEP0.FLD0 = DBUF /* \_SB_.TSC1.DBUF */
- }
- }
- }
-
- Device (BTNS)
- {
- Name (_HID, "ACPI0011" /* Generic Buttons Device */) // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_UID, Zero) // _UID: Unique ID
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- GpioInt (Edge, ActiveBoth, Exclusive, PullDown, 0x0010,
- "\\_SB.PM01", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x0000
- }
- GpioInt (Edge, ActiveBoth, ExclusiveAndWake, PullUp, 0x0000,
- "\\_SB.PM01", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x0085
- }
- GpioInt (Edge, ActiveBoth, ExclusiveAndWake, PullDown, 0x0000,
- "\\_SB.PM01", 0x00, ResourceConsumer, ,
- )
- { // Pin list
- 0x0084
- }
- })
- Return (RBUF) /* \_SB_.BTNS._CRS.RBUF */
- }
-
- Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
- {
- ToUUID ("fa6bd625-9ce8-470d-a2c7-b3ca36c4282e") /* Generic Buttons Device */,
- Package (0x06)
- {
- Package (0x05)
- {
- Zero,
- One,
- Zero,
- One,
- 0x0D
- },
-
- Package (0x05)
- {
- One,
- Zero,
- One,
- One,
- 0x81
- },
-
- Package (0x05)
- {
- One,
- One,
- One,
- 0x0C,
- 0xE9
- },
-
- Package (0x05)
- {
- One,
- 0x02,
- One,
- 0x0C,
- 0xEA
- },
-
- Package (0x05)
- {
- One,
- 0x03,
- One,
- 0x90,
- 0x20
- },
-
- Package (0x05)
- {
- One,
- 0x04,
- One,
- 0x90,
- 0x21
- }
- }
- })
- }
-
- Device (QDCI)
- {
- Name (_DEP, Package (0x01) // _DEP: Dependencies
- {
- GLNK
- })
- Name (_HID, "QCOM0224") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- }
-
- Device (BTH0)
- {
- Name (_HID, "QCOM02B5") // _HID: Hardware ID
- Alias (PSUB, _SUB)
- Name (_DEP, Package (0x03) // _DEP: Dependencies
- {
- PEP0,
- PMIC,
- UAR7
- })
- Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
- {
- Zero,
- Zero
- })
- Name (_S4W, 0x02) // _S4W: S4 Device Wake State
- Name (_S0W, 0x02) // _S0W: S0 Device Wake State
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
- {
- Name (PBUF, ResourceTemplate ()
- {
- UartSerialBusV2 (0x0001C200, DataBitsEight, StopBitsOne,
- 0xC0, LittleEndian, ParityTypeNone, FlowControlHardware,
- 0x0020, 0x0020, "\\_SB.UAR7",
- 0x00, ResourceConsumer, , Exclusive,
- )
- })
- Return (PBUF) /* \_SB_.BTH0._CRS.PBUF */
- }
-
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Return (0x0F)
- }
- }
-
- Include("adc.asl")
- }
-
- Name (WAKP, Package (0x02)
- {
- Zero,
- Zero
- })
-}
-
//
// NOTE: The 3rd parameter (i.e. ComplianceRevision) must be >=2 for 64-bit integer support.
//
-DefinitionBlock("", "DSDT", 0x02, "QCOMM ", "SDM850 ", 3)
+DefinitionBlock("DSDT.AML", "DSDT", 0x02, "QCOMM ", "SDM850 ", 3)
{
Scope(\_SB_) {
- Include("../common/addSub.asl")
+ Include("../Common/addSub.asl")
Include("dsdt_common.asl")
Include("cust_dsdt.asl")
// Thermal Zone devices depend on PEP (included in dsdt_common). Please be CAREFUL on location
Include("cust_thermal_zones.asl")
-
//
// Hardware Notifications
//
//
// Data components
//
- Include("../common/data.asl")
+ Include("../Common/data.asl")
//
//Qualcomm Diagnostic Consumer Interface
//
- Device (QDCI)
- {
- Name (_DEP, Package(0x1)
- {
- \_SB_.GLNK
- })
- Name (_HID, "QCOM0224")
- Alias(\_SB.PSUB, _SUB)
- }
+ Device (QDCI)
+ {
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.GLNK
+ })
+ Name (_HID, "QCOM0224")
+ Alias(\_SB.PSUB, _SUB)
+ }
//
// Bluetooth
//
- Include("../common/wcnss_bt.asl")
+ Include("../Common/wcnss_bt.asl")
//
// ADC driver
//
Include("adc.asl")
- //Include("Bringup_Disable.asl")
}
}
DEPENDENCIES: None
============================================================================*/
+
/*----------------------------------------------------------------------------
* QCADC
* -------------------------------------------------------------------------*/
// This file contains the Audio Drivers
// ACPI device definitions, configuration and look-up tables.
//
-// Currently there's nothing here
//
Device (ADCM)
{
- // HID values are present in Qualcomm.HID.props under <WDKRoot>MSBuild\Qualcomm
- // Parent of ADCM shall defined this ( Refer mproc.asl or slimbus.asl)
- // AMSS in bear family and Slimbus in Badger family makes below entry
- // Name (_HID, "QCOM023F")
Alias(\_SB.PSUB, _SUB)
// Address object for acpi device enumerated device (ADCM) on parent device bus
{
Return (Package()
{
- // Syntax: Name of Parent Device (ADCM)\\HID value (HID_XXX) of AUDD driver
- // HID values are present in Qualcomm.HID.props under <WDKRoot>MSBuild\Qualcomm
-
"ADCM\\QCOM0240"
})
}
Method (CHLD)
{
- // HID values are present in Qualcomm.HID.props under <WDKRoot>MSBuild\Qualcomm
Name(CH, Package()
{
- // Syntax: Name of Parent Device (AUDD)\\HID value (HID_XXX) of MBHC driver
- // QCOM0277 = QCOM2468
"AUDD\\QCOM0277",
- // Syntax: Name of Parent Device (AUDD)\\HID value (HID_XXX) of QCRT driver
- //QCOM0262 = QCOM2451
"AUDD\\QCOM0262",
})
Return(CH)
// Please note that not all the SE engine instances (I2C/SPI/UART) from below asl file can be used directly by icluding in the client ACPI,
// The corresponding Access Control needs to be enabled from TZ side to get the SE/usecase working End 2 End.
//
-//
//
// QUPV3_ID0_SE7 (attached to BT SOC)
//
// I2C4 - "Core I2C Bus"
//
-// Device (I2C4)
-// {
-// Name (_HID, "QCOM0220")
-// Alias(\_SB.PSUB, _SUB)
-// Name (_UID, 4)
-// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
-// Name (_CCA, 0)
-
-// Method (_CRS, 0x0, NotSerialized)
-// {
-// Name (RBUF, ResourceTemplate ()
-// {
-// Memory32Fixed (ReadWrite, 0x0088C000, 0x00004000)
-// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {636}
-// })
-// Return (RBUF)
-// }
-// }
+Device (I2C4)
+{
+ Name (_HID, "QCOM0220")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 4)
+ Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
+ Name (_CCA, 0)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0088C000, 0x00004000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {636}
+ })
+ Return (RBUF)
+ }
+}
//
// I2C5 - "Core I2C Bus"
//
-// Device (I2C6)
-// {
-// Name (_HID, "QCOM0220")
-// Alias(\_SB.PSUB, _SUB)
-// Name (_UID, 6)
-// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
-// Name (_CCA, 0)
-
-// Method (_CRS, 0x0, NotSerialized)
-// {
-// Name (RBUF, ResourceTemplate ()
-// {
-// Memory32Fixed (ReadWrite, 0x894000, 0x00004000)
-// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {638}
-// })
-// Return (RBUF)
-// }
-// }
+Device (I2C6)
+{
+ Name (_HID, "QCOM0220")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 6)
+ Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
+ Name (_CCA, 0)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x894000, 0x00004000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {638}
+ })
+ Return (RBUF)
+ }
+}
//
// I2C11 - "Core I2C Bus"
//
-// Device (IC11)
-// {
-// Name (_HID, "QCOM0220")
-// Alias(\_SB.PSUB, _SUB)
-// Name (_UID, 11)
-// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
-// Name (_CCA, 0)
-
-// Method (_CRS, 0x0, NotSerialized)
-// {
-// Name (RBUF, ResourceTemplate ()
-// {
-// Memory32Fixed (ReadWrite, 0x00A88000, 0x00004000)
-// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {387}
-// })
-// Return (RBUF)
-// }
-// }
+Device (IC11)
+{
+ Name (_HID, "QCOM0220")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 11)
+ Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
+ Name (_CCA, 0)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x00A88000, 0x00004000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {387}
+ })
+ Return (RBUF)
+ }
+}
//
// I2C15 - "Core I2C Bus"
//
-//Device (IC15)
-//{
-// Name (_HID, "QCOM0220")
-// Name (_UID, 15)
-// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
-// Name (_CCA, 0)
-
-// Method (_CRS, 0x0, NotSerialized)
-// {
-// Name (RBUF, ResourceTemplate ()
-// {
-// Memory32Fixed (ReadWrite, 0x00A98000, 0x00004000)
-// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {391}
-// })
-// Return (RBUF)
-// }
-//}
+Device (IC15)
+{
+ Name (_HID, "QCOM0220")
+ Alias(\_SB.PSUB, _SUB)
+ Name (_UID, 15)
+ Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
+ Name (_CCA, 0)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x00A98000, 0x00004000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {391}
+ })
+ Return (RBUF)
+ }
+}
//SPI9 - EPM
},
// "\\_SB.IC15"
- //Package()
- //{
- //"DEVICE",
- //"\\_SB.IC15",
- //Package()
- //{
- //"COMPONENT",
- //0x0, // Component 0.
- //Package()
- //{
- //"FSTATE",
- //0x0, // f0 state
- //},
- //},
- //Package()
- //{
- //"DSTATE",
- //0x0, // D0 state
- //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}},
- //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}},
- //Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",8,19200000, 4}},
- //Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666 }},
- //Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000 }},
+ Package()
+ {
+ "DEVICE",
+ "\\_SB.IC15",
+ Package()
+ {
+ "COMPONENT",
+ 0x0, // Component 0.
+ Package()
+ {
+ "FSTATE",
+ 0x0, // f0 state
+ },
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x0, // D0 state
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",8,19200000, 4}},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666 }},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000 }},
// Configure SDA and then SCL
- //package() {"TLMMGPIO", package() {33, 1, 1, 1, 3, 0}},
- //package() {"TLMMGPIO", package() {34, 1, 1, 1, 3, 0}},
- //},
- //Package()
- //{
- //"DSTATE",
- //0x1, // D1 state
- //},
- //Package()
- //{
- //"DSTATE",
- //0x2, // D2 state
- //},
- //Package()
- //{
- //"DSTATE",
- //0x3, // D3 state
- //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}},
- //Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}},
- //Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",2}},
- //Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0 }},
- //Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0 }},
+ package() {"TLMMGPIO", package() {33, 1, 2, 1, 3, 0}},
+ package() {"TLMMGPIO", package() {34, 1, 2, 1, 3, 0}},
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x1, // D1 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x2, // D2 state
+ },
+ Package()
+ {
+ "DSTATE",
+ 0x3, // D3 state
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}},
+ Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",2}},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0 }},
+ Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0 }},
// Configure SCL and then SDA
- //package() { "TLMMGPIO", package() {33, 0, 0, 0, 3, 0}},
- // package() { "TLMMGPIO", package() {34, 0, 0, 0, 3, 0}},
- //},
- //},
+ package() { "TLMMGPIO", package() {33, 0, 0, 0, 3, 0}},
+ package() { "TLMMGPIO", package() {34, 0, 0, 0, 3, 0}},
+ },
+ },
})
Name(DFS1, Package()
DEPENDENCIES: None
============================================================================*/
+
/*----------------------------------------------------------------------------
* QCADC
* -------------------------------------------------------------------------*/
Device (BTNS)
{
Name(_HID, "ACPI0011")
+
Alias(\_SB.PSUB, _SUB)
+
Name(_UID, 0)
+
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
GpioInt(Edge, ActiveBoth, Exclusive, PullDown, 0, "\\_SB.PM01", ,) {1} // 0x41 - PM_INT__PON__RESIN_ON
// Camera Focus
- GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {135} // 0x638 - PM_INT__PM1_GPIO8__GPIO_IN_STS
+ // GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {135} // 0x638 - PM_INT__PM1_GPIO8__GPIO_IN_STS
//Camera Snapshot
- GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {134} // 0x630 - PM_INT__PM1_GPIO7__GPIO_IN_STS
+ // GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {134} // 0x630 - PM_INT__PM1_GPIO7__GPIO_IN_STS
})
Return (RBUF)
}
Package(5) {1,0,1,0x01,0x81}, // Sleep
Package(5) {1,1,1,0x0C,0xE9}, // Volume Increment
Package(5) {1,2,1,0x0C,0xEA}, // Volume Decrement
- Package(5) {1,3,1,0x90,0x20}, // Camera Auto Focus
- Package(5) {1,4,1,0x90,0x21}, // Camera Shutter
+ // Package(5) {1,3,1,0x90,0x20}, // Camera Auto Focus
+ // Package(5) {1,4,1,0x90,0x21}, // Camera Shutter
},
})
}
// DESCRIPTION
// This file contains resources (such as memory address, GPIOs, etc.) and
// methods needed by camera drivers.
+//
//==============================================================================
Include("cust_camera_exasoc.asl")
//
//===========================================================================
-// Placeholder only, NOT WORKING yet!
-
Scope(\_SB_.PEP0)
{
// Exa-SoC Devices
//
//===========================================================================
-// Placeholder only, NOT WORKING yet!
-
Include("cust_camera_exasoc_resources.asl")
Scope(\_SB_.PEP0)
Name(HWNH, 1)
-Name(HWNL, 1)
+Name(HWNL, 0)
//
// HWN Haptics
Alias(\_SB.PSUB, _SUB)
Name (_CID, "QCOM02A2")
-// Enable below for Dual Sensor Multinode
-//Device (SEN3)
-//{
-// Name (_DEP, Package(0x4)
-// {
-// \_SB_.IPC0, //IPC Router used by QMI
-// \_SB_.SCSS, //SCSS loads the sensors image
-// \_SB_.ARPC, //Dependency on FastRPC
-// \_SB_.SEN2 //Dependency on SEN2
-// })
-// Name (_HID, "QCOM0309")
-// Alias(\_SB.PSUB, _SUB)
-// Name (_CID, "QCOM02A2")
-//}
// Methods used for parsing the sensors configuration (.conf) file.
// HARD corresponds to ":hardware"
// PLAT corresponds to ":platform"
Method(PLAT, 0x0, NotSerialized) {
Return("MTP")
}
- //Disable Sensors for V1s to support new SLPI
- Method(_STA, 0)
+ Method(_STA, 0)
{
-
- If(Lequal(\_SB_.SVMJ, 1))
- {
- return (0x0)
- }
- Else
- {
- return (0xFF)
- }
+ Return (0x0)
}
}
-//
//CPU Aggregator Device -- Required for Thermal Parking
Device(AGR0)
{
// Thermal Zones for Camera TSENS
//---------------------------------------------------------------------
//Thermal zone for TSENS17 to dial back MSM at 95C
- // ThermalZone (TZ32) {
- // Name (_HID, "QCOM02C9")
- // Name (_UID, 0)
- // Name(_TZD, Package (){\_SB.GPU0.AVS0})
- // Name(TPSV, 3680)
- // Method(_PSV) { Return (\_SB.TZ32.TPSV) }
- // Name(TTC1, 1)
- // Method(_TC1) { Return (\_SB.TZ32.TTC1) }
- // // For non-cpu devices, tc2 should be atleast 5, please refer to the
- // // explanation at the top of the file or msdn link for thermal guide.
- // Name(TTC2, 2)
- // Method(_TC2) { Return (\_SB.TZ32.TTC2) }
- // // For non-cpu devices, _tsp should be 20 or 30
- // Name(TTSP, 10)
- // Method(_TSP) { Return (\_SB.TZ32.TTSP) }
- // Name(_TZP, 0)
- // Method(_DEP) {
- // Return (Package() {\_SB.PEP0})
- // }
- // } // end of TZ32
+ ThermalZone (TZ32) {
+ Name (_HID, "QCOM02C9")
+ Name (_UID, 0)
+ Name(_TZD, Package (){\_SB.GPU0.AVS0})
+ Name(TPSV, 3680)
+ Method(_PSV) { Return (\_SB.TZ32.TPSV) }
+ Name(TTC1, 1)
+ Method(_TC1) { Return (\_SB.TZ32.TTC1) }
+ // For non-cpu devices, tc2 should be atleast 5, please refer to the
+ // explanation at the top of the file or msdn link for thermal guide.
+ Name(TTC2, 2)
+ Method(_TC2) { Return (\_SB.TZ32.TTC2) }
+ // For non-cpu devices, _tsp should be 20 or 30
+ Name(TTSP, 10)
+ Method(_TSP) { Return (\_SB.TZ32.TTSP) }
+ Name(_TZP, 0)
+ Method(_DEP) {
+ Return (Package() {\_SB.PEP0})
+ }
+ } // end of TZ32
ThermalZone (TZ33) {
Name (_HID, "QCOM02CB")
--- /dev/null
+//
+// This file contains the touch ACPI device definitions.
+//
+
+Device (TSC1)
+{
+ Name (_HID, "MSHW1003") // _HID: Hardware ID
+ Alias (\_SB.PSUB, _SUB)
+ Name (_DEP, Package (0x03) // _DEP: Dependencies
+ {
+ \_SB.GIO0,
+ \_SB.IC15,
+ \_SB.PEP0
+ })
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ I2cSerialBusV2 (0x0020, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.IC15",
+ 0x00, ResourceConsumer, , Exclusive,
+ )
+ GpioInt (Level, ActiveLow, Exclusive, PullUp, 0x0000,
+ "\\_SB.GIO0", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x007D
+ }
+ })
+ Return (RBUF) /* \_SB_.TSC1._CRS.RBUF */
+ }
+
+ Name (PGID, Buffer (0x0A)
+ {
+ "\\_SB.TSC1"
+ })
+ Name (DBUF, Buffer (DBFL){})
+ CreateByteField (DBUF, Zero, STAT)
+ CreateByteField (DBUF, 0x02, DVAL)
+ CreateField (DBUF, 0x18, 0xA0, DEID)
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (0x03)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (0x03)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (0x03)
+ }
+
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ DEID = Buffer (ESNL){}
+ DVAL = Zero
+ DEID = PGID /* \_SB_.TSC1.PGID */
+ If (\_SB.ABD.AVBL)
+ {
+ \_SB.PEP0.FLD0 = DBUF /* \_SB_.TSC1.DBUF */
+ }
+ }
+
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ DEID = Buffer (ESNL){}
+ DVAL = 0x03
+ DEID = PGID /* \_SB_.TSC1.PGID */
+ If (\_SB.ABD.AVBL)
+ {
+ \_SB.PEP0.FLD0 = DBUF /* \_SB_.TSC1.DBUF */
+ }
+ }
+}
--- /dev/null
+//===========================================================================
+// <cust_touch_resources.asl>
+// DESCRIPTION
+// This file contains the resources needed by touch driver.
+//
+//===========================================================================
+Scope(\_SB_.PEP0)
+{
+
+ Method(LPMX)
+ {
+ Return(LPXC)
+ }
+
+ Name(LPXC,
+ Package(){
+ Package ()
+ {
+ "DEVICE",
+ "\\_SB.TSC1",
+ Package ()
+ {
+ "DSTATE",
+ Zero,
+ Package ()
+ {
+ "PMICVREGVOTE",
+ Package ()
+ {
+ "PPP_RESOURCE_ID_LDO6_A",
+ One,
+ 0x001C5200,
+ One,
+ 0x07,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "PMICVREGVOTE",
+ Package ()
+ {
+ "PPP_RESOURCE_ID_LDO28_A",
+ One,
+ 0x002DE600,
+ One,
+ 0x07,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 0x17,
+ One,
+ Zero,
+ One,
+ 0x03,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 0x7D,
+ Zero,
+ Zero,
+ Zero,
+ 0x03,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 0x63,
+ Zero,
+ Zero,
+ One,
+ Zero,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "DELAY",
+ Package ()
+ {
+ 0x02
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 0x63,
+ One,
+ Zero,
+ One,
+ Zero,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "DELAY",
+ Package ()
+ {
+ 0xC8
+ }
+ }
+ },
+
+ Package ()
+ {
+ "DSTATE",
+ 0x03,
+ Package ()
+ {
+ "PMICVREGVOTE",
+ Package ()
+ {
+ "PPP_RESOURCE_ID_LDO6_A",
+ One,
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "PMICVREGVOTE",
+ Package ()
+ {
+ "PPP_RESOURCE_ID_LDO28_A",
+ One,
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 0x17,
+ Zero,
+ Zero,
+ One,
+ One,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 0x63,
+ Zero,
+ Zero,
+ Zero,
+ One,
+ Zero
+ }
+ },
+
+ Package ()
+ {
+ "TLMMGPIO",
+ Package ()
+ {
+ 0x7D,
+ Zero,
+ Zero,
+ Zero,
+ One,
+ Zero
+ }
+ }
+ }
+ }
+ })
+}
--- /dev/null
+//
+// MPROC Drivers (PIL Driver and Subsystem Drivers)
+//
+
+Scope(\_SB.ADSP)
+{
+
+}
+
+Scope(\_SB.AMSS)
+{
+
+}
+
+Scope(\_SB.SCSS)
+{
+
+}
+
+Scope(\_SB.PILC)
+{
+
+}
+
+Scope(\_SB.CDI)
+{
+
+}
+
+Scope(\_SB.RPEN)
+{
+
+}
// PCFG is buffer name for all default panel configurations
// All other dynamically detected panel configurations must not use this name
//======================================================================================
- Switch ( ToInteger (Arg2) )
- {
- // Truly WQHD Dual DSI Command Mode
- Case (0x008010) {
- Store (PCFG, Local2)
- }
- // Truly WQHD Dual DSI Video Mode
- Case (0x008011) {
- Store (PCF1, Local2)
- }
- // Truly WQHD Single DSI DSC Command Mode
- Case (0x008012) {
- Store (PCF2, Local2)
- }
- // Truly WQHD Single DSI DSC Video Mode
- Case (0x008013) {
- Store (PCF3, Local2)
- }
- // 4k Dual DSC Sharp Command Mode
- Case (0x00008000) {
- Store (PCF4, Local2)
- }
- // 4k Dual DSC Sharp Video Mode
- Case (0x00008056) {
- Store (PCF5, Local2)
- }
- // All others
- Default {
- Store (PCFG, Local2)
- }
- }
+
+ Local2 = PCFG
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
// PCFG is buffer name for all default panel configurations
// All other dynamically detected panel configurations must not use this name
//======================================================================================
- While (One)
- {
- If (One)
- {
- Local2 = PCFG /* \_SB_.GPU0.ROM2.PCFG */
+ Switch ( ToInteger (Arg2) )
+ {
+ // Default case
+ Default {
+ Store (PCFG, Local2)
}
- Break
- }
+ }
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
--- /dev/null
+// To enable SOC revision based run time differentiation, uncomment following line
+// and uncomment SSID method in ABD device. The original string is artificailly set as
+// 16 characters, so there is enough room to hold SOC revision string.
+// To adjust the number, the MAX_SOCID_LEN macro as defined in ABD device.h should be
+// adjusted at the same time.
+
+Name (SOID, 0x0141) // Holds the Chip Id
+Name (SIDS, "SDM845") // Holds the Chip ID translated to a string
+Name (SIDV, 0x00020001) // Holds the Chip Version as (major<<16)|(minor&0xffff)
+Name (SVMJ, 0x02) // Holds the major Chip Version
+Name (SVMI, One) // Holds the minor Chip Version
+Name (SDFE, 0x4F) // Holds the Chip Family enum
+Name (SFES, "899800000000000") // Holds the Chip Family translated to a string
+Name (SIDM, 0x0000000FFFFF00FF) // Holds the Modem Support bit field
+Name (SOSN, 0x000003F48D126594)
+Name (RMTB, 0x85D00000)
+Name (RMTX, 0x00200000)
+Name (RFMB, Zero)
+Name (RFMS, Zero)
+Name (RFAB, Zero)
+Name (RFAS, Zero)
+Name (TPMA, 0x11111111) // Holds whether TPM is seperate app or combined with Winsecapp
+Name (TDTV, 0x6654504D) // Holds TPM type, by default it set to fTPM type
+Name (TCMA, 0x8AB00000) // Holds TrEE Carveout Memory Address
+Name (TCML, 0x01400000) // Holds TrEE Carveout Memory Length
+// Name (SOSI, 0xdeadbeefffffffff) // Holds the base address of the SoCInfo shared memory region used by ChipInfoLib
+
+//Audio Drivers
+Include("audio.asl")
+
+ //
+ // Storage - UFS/SD
+ //
+ Include("../Common/ufs.asl")
+ // Include("../Common/sdc.asl") // No SD support on polaris
+
+ //
+ // ASL Bridge Device
+ //
+ Include("../Common/abd.asl")
+
+ Name (ESNL, 20) // Exsoc name limit 20 characters
+ Name (DBFL, 23) // buffer Length, should be ESNL+3
+
+//
+// PMIC driver
+//
+Include("../Common/pmic_core.asl")
+
+//
+// PMICTCC driver
+//
+Include("pmic_batt.asl")
+
+ Include("pep.asl")
+ Include("../Common/bam.asl")
+ Include("buses.asl")
+ // MPROC Drivers (PIL Driver and Subsystem Drivers)
+ Include("../Common/win_mproc.asl")
+ Include("../Common/syscache.asl")
+ Include("../Common/HoyaSmmu.asl")
+ Include("graphics.asl")
+
+ Include("../Common/SCM.asl");
+
+ //
+ // SPMI driver
+ //
+ Include("../Common/spmi.asl")
+
+ //
+ // TLMM controller.
+ //
+ Include("qcgpio.asl")
+
+ Include("../Common/pcie.asl")
+
+ Include("../Common/cbsp_mproc.asl")
+
+ Include("../Common/adsprpc.asl")
+
+ //
+ // RemoteFS
+ //
+ Include("../Common/rfs.asl")
+
+
+ // Test Drivers
+ Include("testdev.asl")
+ //
+
+ //
+ // Qualcomm IPA
+ Include("../Common/ipa.asl")
+
+ Include("../Common/gsi.asl")
+
+ //
+ //Qualcomm DIAG Service
+ //
+ Device (QDIG)
+ {
+ Name (_DEP, Package(0x1)
+ {
+ \_SB_.GLNK
+ })
+ Name (_HID, "QCOM0225")
+ Alias(\_SB.PSUB, _SUB)
+ }
+ Include("../Common/qcdb.asl")
+ Include("../Common/pep_lpi.asl")
+
+ //
+ // QcRNG Driver (qcsecuremsm)
+ //
+ Device (QRNG)
+ {
+ Name (_DEP, Package(0x1) {
+ \_SB_.PEP0,
+ })
+ Name (_HID, "QCOM02FE")
+ Name (_UID, 0)
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // PRNG_CFG_EE2_EE2_PRNG_SUB register address space
+ Memory32Fixed (ReadWrite, 0x00793000, 0x00001000)
+ })
+ Return (RBUF)
+ }
+ }
+
+ //
+ // QCOM GPS
+ //
+ Include("../Common/gps.asl")
+
+ // QDSS driver
+ Include("../Common/Qdss.asl")
+
+// QUPV3 GPI device node and resources
+//
+Include("../Common/qgpi.asl")
+
+Include("../Common/qwpp.asl")
+//Include("nfc.asl")
+
+Include("../Common/sar_manager.asl")
+//--------------------------------------------------------------------------------------------------
+// GfxXMLToACPI Version 2.3.
+//--------------------------------------------------------------------------------------------------
+
//--------------------------------------------------------------------------------------------------
// This file contains all graphics ACPI Device Configuration Information and Methods
//
Alias(\_SB.PSUB, _SUB)
Name (_CID, "ACPI\QCOM027E")
Name (_UID, 0)
- Name (_CLS, Package(0x3)
- {
- 0x0003000000000000
- })
+ Name (_CLS, 0x0003000000000000)
Name (_HRV, 0x07C)
// Expose the internal monitor device to allow it to be used in a thermal zone
// TLMM GPIO used to select DSI panel mode
//
- GpioIo(Exclusive, PullUp, 0, 0, , "\\_SB.GIO0", ,) {52}
+ // GpioIo(Exclusive, PullUp, 0, 0, , "\\_SB.GIO0", ,) {52}
// TLMM GPIO used to DP AUX polarity select
//
- GpioIo(Shared, PullUp, 0, 0, , "\\_SB.GIO0", ,) {51}
+ // GpioIo(Shared, PullUp, 0, 0, , "\\_SB.GIO0", ,) {51}
})
Return (RBUF)
}
// TLMM GPIO used to select DSI panel mode
//
- Package()
- {
- "RESOURCE",
- "DSI_PANEL_MODE_SELECT", // Resource Name
- "DISPLAY", // Owning Component
- },
+ // Package()
+ // {
+ // "RESOURCE",
+ // "DSI_PANEL_MODE_SELECT", // Resource Name
+ // "DISPLAY", // Owning Component
+ // },
// TLMM GPIO used to DP AUX polarity select
//
- Package()
- {
- "RESOURCE",
- "DP_AUX", // Resource Name
- "DISPLAY", // Owning Component
- },
+ // Package()
+ // {
+ // "RESOURCE",
+ // "DP_AUX", // Resource Name
+ // "DISPLAY", // Owning Component
+ // },
})
Return (RINF)
"BANDWIDTH", // Resource Type
13, // Num P-States in Set
0, // Num CustomData fields in Set
- "TRUE", // Has Thermal Thresholds
+ TRUE, // Has Thermal Thresholds
4, // Initial P-State
3, // Stable Power P-State
"CORE_CLOCK", // Resource Type
9, // Num P-States in Set
1, // Num CustomData fields in Set
- "TRUE", // Has Thermal Thresholds
+ TRUE, // Has Thermal Thresholds
5, // Initial P-State
3, // Stable Power P-State
"CORE_CLOCK", // Resource Type
2, // Num P-States in Set
1, // Num CustomData fields in Set
- "TRUE", // Has Thermal Thresholds
+ TRUE, // Has Thermal Thresholds
0, // Initial P-State
0, // Stable Power P-State
// 0x0B: UFP_D(Upstream Facing Port DP) Pin E
//------------------------------------------------------------------------------
//
- Method (DPIN, 2, NotSerialized)
- {
- // Arg0 - Panel ID
+
+ // Method (DPIN, 2, NotSerialized)
+ // {
+ // // Arg0 - Panel ID
- // Arg1 - Data size
+ // // Arg1 - Data size
- return (\_SB_.PINA)
- }
+ // return (\_SB_.PINA)
+ // }
Method (REGR)
{
Package()
{
"ForceActive",
- 0,
+ 1,
},
Package()
{
Package()
{
"DisableCDI",
- 0,
+ 1,
},
Package()
{
Package()
{
"SupportsSHMBridge", // Supports SHM Bridge registration.
- 1,
+ 0,
},
Package()
{
Package()
{
"DisableExternal", // Disable External Display
- 0,
+ 3,
},
},
})
--- /dev/null
+//
+// NFC entry.
+//
+Device(NFCD)
+{
+ Name(_HID, "NXP1001")
+ Name(_CID, "ACPI\NXP1001")
+ Alias(\_SB.PSUB, _SUB)
+ Name(_CRS, ResourceTemplate()
+ {
+ I2CSerialBus(0x28, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.I2C4", 0, ResourceConsumer, , )
+ GpioInt(Level, ActiveHigh, Exclusive, PullDefault, 0, "\\_SB.GIO0", 0, ResourceConsumer, , ) {63}
+ })
+// ESE SPI GPIO
+ Name(NFCS, ResourceTemplate()
+ {
+ GpioIO(Exclusive, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , ) {116}
+ })
+// NFCC VEN GPIO
+ Name(NFCP, ResourceTemplate()
+ {
+ GpioIO(Exclusive, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , ) {12}
+ })
+ Scope(GIO0)
+ {
+ OperationRegion(NFPO, GeneralPurposeIO, Zero, One)
+ }
+ Field(\_SB_.GIO0.NFPO, ByteAcc, NoLock, Preserve)
+ {
+ Connection(\_SB_.NFCD.NFCP),
+ MGPE, 1
+ }
+ Method(POON, 0x0, NotSerialized)
+ {
+ Store(One, MGPE)
+ }
+ Method(POOF, 0x0, NotSerialized)
+ {
+ Store(Zero, MGPE)
+ }
+//NFCC FW DOWNLOAD GPIO
+ Name(NFCF, ResourceTemplate()
+ {
+ GpioIO(Exclusive, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GIO0", 0, ResourceConsumer, , ) {62} // Download
+ })
+ Scope(GIO0)
+ {
+ OperationRegion(NFFO, GeneralPurposeIO, Zero, One)
+ }
+ Field(\_SB_.GIO0.NFFO, ByteAcc, NoLock, Preserve)
+ {
+ Connection(\_SB_.NFCD.NFCF),
+ MGFE, 1
+ }
+ Method(FWON, 0x0, NotSerialized)
+ {
+ Store(One, MGFE)
+ }
+ Method(FWOF, 0x0, NotSerialized)
+ {
+ Store(Zero, MGFE)
+ }
+ Method(_DSM, 0x4, NotSerialized)
+ {
+ Store("Method NFC _DSM begin", Debug)
+ If(LEqual(Arg0, Buffer(0x10)
+ {
+ 0xc4, 0xf6, 0xe7, 0xa2, 0x38, 0x96, 0x85, 0x44, 0x9f, 0x12, 0x6b, 0x4e,
+ 0x20, 0xb6, 0x0d, 0x63
+ }))
+ {
+ If(LEqual(Arg2, Zero))
+ {
+ Store("Method NFC _DSM QUERY", Debug)
+ If(LEqual(Arg1, One))
+ {
+ \_SB_.NFCD.POOF()
+ Sleep(0x14)
+ Return(Buffer(One)
+ {
+ 0x0f
+ })
+ }
+ }
+ If(LEqual(Arg2, 0x2))
+ {
+ Store("Method NFC _DSM SETPOWERMODE", Debug)
+ If(LEqual(Arg3, One))
+ {
+ \_SB_.NFCD.POON()
+ Sleep(0x14)
+ }
+ If(LEqual(Arg3, Zero))
+ {
+ \_SB_.NFCD.POOF()
+ Sleep(0x14)
+ }
+ }
+ If(LEqual(Arg2, One))
+ {
+ Store("Method NFC _DSM SETFWMODE", Debug)
+//
+// Set the firmware mode to ON.
+//
+ If(LEqual(Arg3, One))
+ {
+ \_SB_.NFCD.FWON()
+//
+// Provide any delay required by the controller before toggling the power GPIO line.
+//
+ Sleep(0x14)
+ \_SB_.NFCD.POOF()
+ Sleep(0x14)
+ \_SB_.NFCD.POON()
+ Sleep(0x14)
+ }
+//
+// Set the firmware mode to OFF.
+//
+ If(LEqual(Arg3, Zero))
+ {
+ \_SB_.NFCD.FWOF()
+ Sleep(0x14)
+ \_SB_.NFCD.POOF()
+ Sleep(0x14)
+ \_SB_.NFCD.POON()
+ Sleep(0x14)
+ }
+ }
+ If(LEqual(Arg2, 0x3))
+ {
+ Store("Method NFC _DSM EEPROM Config", Debug)
+ Return(Buffer(0x13)
+ {
+ 0x9c, 0x1f, 0x38, 0x19, 0xa8, 0xb9, 0x4b, 0xab, 0xa1, 0xba, 0xd0, 0x20,
+ 0x76, 0x88, 0x2a, 0xe0, 0x03, 0x01, 0x11
+ })
+ }
+ }
+ }
+//PEP Proxy Support
+ Name(PGID, Buffer(10) {"\\_SB.NFCD"}) // Device ID buffer - PGID( Pep given ID )
+ Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID( Pep given ID )
+ CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE
+ // HIDDEN 1 BYTE ( SIZE )
+ CreateByteField(DBUF, 2, DVAL ) // Packet value, 1 BYTES Device Status
+ CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES(160 Bits)
+ Method (_S1D, 0) { Return (3) } // S1 => D3
+ Method (_S2D, 0) { Return (3) } // S2 => D3
+ Method (_S3D, 0) { Return (3) } // S3 => D3
+
+ Method(_PS0, 0x0, NotSerialized)
+ {
+ Store(Buffer(ESNL){}, DEID)
+ Store(0, DVAL)
+ Store(PGID, DEID)
+ If(\_SB.ABD.AVBL)
+ {
+ Store(DBUF, \_SB.PEP0.FLD0)
+ }
+ }
+ Method(_PS3, 0x0, NotSerialized)
+ {
+ Store(Buffer(ESNL){}, DEID)
+ Store(3, DVAL)
+ Store(PGID, DEID)
+ If(\_SB.ABD.AVBL)
+ {
+ Store(DBUF, \_SB.PEP0.FLD0)
+ }
+ }
+}
--- /dev/null
+Name (PCFG, Buffer (0x1229)
+{
+ /* 0000 */ 0x3C, 0x3F, 0x78, 0x6D, 0x6C, 0x20, 0x76, 0x65, // <?xml ve
+ /* 0008 */ 0x72, 0x73, 0x69, 0x6F, 0x6E, 0x3D, 0x27, 0x31, // rsion='1
+ /* 0010 */ 0x2E, 0x30, 0x27, 0x20, 0x65, 0x6E, 0x63, 0x6F, // .0' enco
+ /* 0018 */ 0x64, 0x69, 0x6E, 0x67, 0x3D, 0x27, 0x75, 0x74, // ding='ut
+ /* 0020 */ 0x66, 0x2D, 0x38, 0x27, 0x3F, 0x3E, 0x0A, 0x3C, // f-8'?>.<
+ /* 0028 */ 0x50, 0x61, 0x6E, 0x65, 0x6C, 0x4E, 0x61, 0x6D, // PanelNam
+ /* 0030 */ 0x65, 0x3E, 0x4A, 0x44, 0x49, 0x5F, 0x4E, 0x54, // e>JDI_NT
+ /* 0038 */ 0x33, 0x35, 0x35, 0x39, 0x36, 0x53, 0x3C, 0x2F, // 35596S</
+ /* 0040 */ 0x50, 0x61, 0x6E, 0x65, 0x6C, 0x4E, 0x61, 0x6D, // PanelNam
+ /* 0048 */ 0x65, 0x3E, 0x0A, 0x3C, 0x50, 0x61, 0x6E, 0x65, // e>.<Pane
+ /* 0050 */ 0x6C, 0x44, 0x65, 0x73, 0x63, 0x72, 0x69, 0x70, // lDescrip
+ /* 0058 */ 0x74, 0x69, 0x6F, 0x6E, 0x3E, 0x4A, 0x44, 0x49, // tion>JDI
+ /* 0060 */ 0x20, 0x53, 0x69, 0x6E, 0x67, 0x6C, 0x65, 0x20, // Single
+ /* 0068 */ 0x44, 0x53, 0x49, 0x20, 0x56, 0x69, 0x64, 0x65, // DSI Vide
+ /* 0070 */ 0x6F, 0x20, 0x4D, 0x6F, 0x64, 0x65, 0x20, 0x50, // o Mode P
+ /* 0078 */ 0x61, 0x6E, 0x65, 0x6C, 0x20, 0x28, 0x31, 0x30, // anel (10
+ /* 0080 */ 0x38, 0x30, 0x78, 0x32, 0x31, 0x36, 0x30, 0x20, // 80x2160
+ /* 0088 */ 0x32, 0x34, 0x62, 0x70, 0x70, 0x29, 0x3C, 0x2F, // 24bpp)</
+ /* 0090 */ 0x50, 0x61, 0x6E, 0x65, 0x6C, 0x44, 0x65, 0x73, // PanelDes
+ /* 0098 */ 0x63, 0x72, 0x69, 0x70, 0x74, 0x69, 0x6F, 0x6E, // cription
+ /* 00A0 */ 0x3E, 0x0A, 0x3C, 0x47, 0x72, 0x6F, 0x75, 0x70, // >.<Group
+ /* 00A8 */ 0x20, 0x69, 0x64, 0x3D, 0x27, 0x41, 0x63, 0x74, // id='Act
+ /* 00B0 */ 0x69, 0x76, 0x65, 0x20, 0x54, 0x69, 0x6D, 0x69, // ive Timi
+ /* 00B8 */ 0x6E, 0x67, 0x27, 0x3E, 0x0A, 0x20, 0x20, 0x20, // ng'>.
+ /* 00C0 */ 0x20, 0x3C, 0x48, 0x6F, 0x72, 0x69, 0x7A, 0x6F, // <Horizo
+ /* 00C8 */ 0x6E, 0x74, 0x61, 0x6C, 0x41, 0x63, 0x74, 0x69, // ntalActi
+ /* 00D0 */ 0x76, 0x65, 0x3E, 0x31, 0x30, 0x38, 0x30, 0x3C, // ve>1080<
+ /* 00D8 */ 0x2F, 0x48, 0x6F, 0x72, 0x69, 0x7A, 0x6F, 0x6E, // /Horizon
+ /* 00E0 */ 0x74, 0x61, 0x6C, 0x41, 0x63, 0x74, 0x69, 0x76, // talActiv
+ /* 00E8 */ 0x65, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // e>. <
+ /* 00F0 */ 0x48, 0x6F, 0x72, 0x69, 0x7A, 0x6F, 0x6E, 0x74, // Horizont
+ /* 00F8 */ 0x61, 0x6C, 0x46, 0x72, 0x6F, 0x6E, 0x74, 0x50, // alFrontP
+ /* 0100 */ 0x6F, 0x72, 0x63, 0x68, 0x3E, 0x31, 0x36, 0x3C, // orch>16<
+ /* 0108 */ 0x2F, 0x48, 0x6F, 0x72, 0x69, 0x7A, 0x6F, 0x6E, // /Horizon
+ /* 0110 */ 0x74, 0x61, 0x6C, 0x46, 0x72, 0x6F, 0x6E, 0x74, // talFront
+ /* 0118 */ 0x50, 0x6F, 0x72, 0x63, 0x68, 0x3E, 0x0A, 0x20, // Porch>.
+ /* 0120 */ 0x20, 0x20, 0x20, 0x3C, 0x48, 0x6F, 0x72, 0x69, // <Hori
+ /* 0128 */ 0x7A, 0x6F, 0x6E, 0x74, 0x61, 0x6C, 0x42, 0x61, // zontalBa
+ /* 0130 */ 0x63, 0x6B, 0x50, 0x6F, 0x72, 0x63, 0x68, 0x3E, // ckPorch>
+ /* 0138 */ 0x34, 0x30, 0x3C, 0x2F, 0x48, 0x6F, 0x72, 0x69, // 40</Hori
+ /* 0140 */ 0x7A, 0x6F, 0x6E, 0x74, 0x61, 0x6C, 0x42, 0x61, // zontalBa
+ /* 0148 */ 0x63, 0x6B, 0x50, 0x6F, 0x72, 0x63, 0x68, 0x3E, // ckPorch>
+ /* 0150 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x48, 0x6F, // . <Ho
+ /* 0158 */ 0x72, 0x69, 0x7A, 0x6F, 0x6E, 0x74, 0x61, 0x6C, // rizontal
+ /* 0160 */ 0x53, 0x79, 0x6E, 0x63, 0x50, 0x75, 0x6C, 0x73, // SyncPuls
+ /* 0168 */ 0x65, 0x3E, 0x32, 0x38, 0x3C, 0x2F, 0x48, 0x6F, // e>28</Ho
+ /* 0170 */ 0x72, 0x69, 0x7A, 0x6F, 0x6E, 0x74, 0x61, 0x6C, // rizontal
+ /* 0178 */ 0x53, 0x79, 0x6E, 0x63, 0x50, 0x75, 0x6C, 0x73, // SyncPuls
+ /* 0180 */ 0x65, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // e>. <
+ /* 0188 */ 0x48, 0x6F, 0x72, 0x69, 0x7A, 0x6F, 0x6E, 0x74, // Horizont
+ /* 0190 */ 0x61, 0x6C, 0x53, 0x79, 0x6E, 0x63, 0x53, 0x6B, // alSyncSk
+ /* 0198 */ 0x65, 0x77, 0x3E, 0x30, 0x3C, 0x2F, 0x48, 0x6F, // ew>0</Ho
+ /* 01A0 */ 0x72, 0x69, 0x7A, 0x6F, 0x6E, 0x74, 0x61, 0x6C, // rizontal
+ /* 01A8 */ 0x53, 0x79, 0x6E, 0x63, 0x53, 0x6B, 0x65, 0x77, // SyncSkew
+ /* 01B0 */ 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x48, // >. <H
+ /* 01B8 */ 0x6F, 0x72, 0x69, 0x7A, 0x6F, 0x6E, 0x74, 0x61, // orizonta
+ /* 01C0 */ 0x6C, 0x4C, 0x65, 0x66, 0x74, 0x42, 0x6F, 0x72, // lLeftBor
+ /* 01C8 */ 0x64, 0x65, 0x72, 0x3E, 0x30, 0x3C, 0x2F, 0x48, // der>0</H
+ /* 01D0 */ 0x6F, 0x72, 0x69, 0x7A, 0x6F, 0x6E, 0x74, 0x61, // orizonta
+ /* 01D8 */ 0x6C, 0x4C, 0x65, 0x66, 0x74, 0x42, 0x6F, 0x72, // lLeftBor
+ /* 01E0 */ 0x64, 0x65, 0x72, 0x3E, 0x0A, 0x20, 0x20, 0x20, // der>.
+ /* 01E8 */ 0x20, 0x3C, 0x48, 0x6F, 0x72, 0x69, 0x7A, 0x6F, // <Horizo
+ /* 01F0 */ 0x6E, 0x74, 0x61, 0x6C, 0x52, 0x69, 0x67, 0x68, // ntalRigh
+ /* 01F8 */ 0x74, 0x42, 0x6F, 0x72, 0x64, 0x65, 0x72, 0x3E, // tBorder>
+ /* 0200 */ 0x30, 0x3C, 0x2F, 0x48, 0x6F, 0x72, 0x69, 0x7A, // 0</Horiz
+ /* 0208 */ 0x6F, 0x6E, 0x74, 0x61, 0x6C, 0x52, 0x69, 0x67, // ontalRig
+ /* 0210 */ 0x68, 0x74, 0x42, 0x6F, 0x72, 0x64, 0x65, 0x72, // htBorder
+ /* 0218 */ 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x56, // >. <V
+ /* 0220 */ 0x65, 0x72, 0x74, 0x69, 0x63, 0x61, 0x6C, 0x41, // erticalA
+ /* 0228 */ 0x63, 0x74, 0x69, 0x76, 0x65, 0x3E, 0x32, 0x31, // ctive>21
+ /* 0230 */ 0x36, 0x30, 0x3C, 0x2F, 0x56, 0x65, 0x72, 0x74, // 60</Vert
+ /* 0238 */ 0x69, 0x63, 0x61, 0x6C, 0x41, 0x63, 0x74, 0x69, // icalActi
+ /* 0240 */ 0x76, 0x65, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, // ve>.
+ /* 0248 */ 0x3C, 0x56, 0x65, 0x72, 0x74, 0x69, 0x63, 0x61, // <Vertica
+ /* 0250 */ 0x6C, 0x46, 0x72, 0x6F, 0x6E, 0x74, 0x50, 0x6F, // lFrontPo
+ /* 0258 */ 0x72, 0x63, 0x68, 0x3E, 0x37, 0x3C, 0x2F, 0x56, // rch>7</V
+ /* 0260 */ 0x65, 0x72, 0x74, 0x69, 0x63, 0x61, 0x6C, 0x46, // erticalF
+ /* 0268 */ 0x72, 0x6F, 0x6E, 0x74, 0x50, 0x6F, 0x72, 0x63, // rontPorc
+ /* 0270 */ 0x68, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // h>. <
+ /* 0278 */ 0x56, 0x65, 0x72, 0x74, 0x69, 0x63, 0x61, 0x6C, // Vertical
+ /* 0280 */ 0x42, 0x61, 0x63, 0x6B, 0x50, 0x6F, 0x72, 0x63, // BackPorc
+ /* 0288 */ 0x68, 0x3E, 0x32, 0x34, 0x3C, 0x2F, 0x56, 0x65, // h>24</Ve
+ /* 0290 */ 0x72, 0x74, 0x69, 0x63, 0x61, 0x6C, 0x42, 0x61, // rticalBa
+ /* 0298 */ 0x63, 0x6B, 0x50, 0x6F, 0x72, 0x63, 0x68, 0x3E, // ckPorch>
+ /* 02A0 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x56, 0x65, // . <Ve
+ /* 02A8 */ 0x72, 0x74, 0x69, 0x63, 0x61, 0x6C, 0x53, 0x79, // rticalSy
+ /* 02B0 */ 0x6E, 0x63, 0x50, 0x75, 0x6C, 0x73, 0x65, 0x3E, // ncPulse>
+ /* 02B8 */ 0x34, 0x3C, 0x2F, 0x56, 0x65, 0x72, 0x74, 0x69, // 4</Verti
+ /* 02C0 */ 0x63, 0x61, 0x6C, 0x53, 0x79, 0x6E, 0x63, 0x50, // calSyncP
+ /* 02C8 */ 0x75, 0x6C, 0x73, 0x65, 0x3E, 0x0A, 0x20, 0x20, // ulse>.
+ /* 02D0 */ 0x20, 0x20, 0x3C, 0x56, 0x65, 0x72, 0x74, 0x69, // <Verti
+ /* 02D8 */ 0x63, 0x61, 0x6C, 0x53, 0x79, 0x6E, 0x63, 0x53, // calSyncS
+ /* 02E0 */ 0x6B, 0x65, 0x77, 0x3E, 0x30, 0x3C, 0x2F, 0x56, // kew>0</V
+ /* 02E8 */ 0x65, 0x72, 0x74, 0x69, 0x63, 0x61, 0x6C, 0x53, // erticalS
+ /* 02F0 */ 0x79, 0x6E, 0x63, 0x53, 0x6B, 0x65, 0x77, 0x3E, // yncSkew>
+ /* 02F8 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x56, 0x65, // . <Ve
+ /* 0300 */ 0x72, 0x74, 0x69, 0x63, 0x61, 0x6C, 0x54, 0x6F, // rticalTo
+ /* 0308 */ 0x70, 0x42, 0x6F, 0x72, 0x64, 0x65, 0x72, 0x3E, // pBorder>
+ /* 0310 */ 0x30, 0x3C, 0x2F, 0x56, 0x65, 0x72, 0x74, 0x69, // 0</Verti
+ /* 0318 */ 0x63, 0x61, 0x6C, 0x54, 0x6F, 0x70, 0x42, 0x6F, // calTopBo
+ /* 0320 */ 0x72, 0x64, 0x65, 0x72, 0x3E, 0x0A, 0x20, 0x20, // rder>.
+ /* 0328 */ 0x20, 0x20, 0x3C, 0x56, 0x65, 0x72, 0x74, 0x69, // <Verti
+ /* 0330 */ 0x63, 0x61, 0x6C, 0x42, 0x6F, 0x74, 0x74, 0x6F, // calBotto
+ /* 0338 */ 0x6D, 0x42, 0x6F, 0x72, 0x64, 0x65, 0x72, 0x3E, // mBorder>
+ /* 0340 */ 0x30, 0x3C, 0x2F, 0x56, 0x65, 0x72, 0x74, 0x69, // 0</Verti
+ /* 0348 */ 0x63, 0x61, 0x6C, 0x42, 0x6F, 0x74, 0x74, 0x6F, // calBotto
+ /* 0350 */ 0x6D, 0x42, 0x6F, 0x72, 0x64, 0x65, 0x72, 0x3E, // mBorder>
+ /* 0358 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x49, 0x6E, // . <In
+ /* 0360 */ 0x76, 0x65, 0x72, 0x74, 0x44, 0x61, 0x74, 0x61, // vertData
+ /* 0368 */ 0x50, 0x6F, 0x6C, 0x61, 0x72, 0x69, 0x74, 0x79, // Polarity
+ /* 0370 */ 0x3E, 0x46, 0x61, 0x6C, 0x73, 0x65, 0x3C, 0x2F, // >False</
+ /* 0378 */ 0x49, 0x6E, 0x76, 0x65, 0x72, 0x74, 0x44, 0x61, // InvertDa
+ /* 0380 */ 0x74, 0x61, 0x50, 0x6F, 0x6C, 0x61, 0x72, 0x69, // taPolari
+ /* 0388 */ 0x74, 0x79, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, // ty>.
+ /* 0390 */ 0x3C, 0x49, 0x6E, 0x76, 0x65, 0x72, 0x74, 0x56, // <InvertV
+ /* 0398 */ 0x73, 0x79, 0x6E, 0x63, 0x50, 0x6F, 0x6C, 0x61, // syncPola
+ /* 03A0 */ 0x69, 0x72, 0x74, 0x79, 0x3E, 0x46, 0x61, 0x6C, // irty>Fal
+ /* 03A8 */ 0x73, 0x65, 0x3C, 0x2F, 0x49, 0x6E, 0x76, 0x65, // se</Inve
+ /* 03B0 */ 0x72, 0x74, 0x56, 0x73, 0x79, 0x6E, 0x63, 0x50, // rtVsyncP
+ /* 03B8 */ 0x6F, 0x6C, 0x61, 0x69, 0x72, 0x74, 0x79, 0x3E, // olairty>
+ /* 03C0 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x49, 0x6E, // . <In
+ /* 03C8 */ 0x76, 0x65, 0x72, 0x74, 0x48, 0x73, 0x79, 0x6E, // vertHsyn
+ /* 03D0 */ 0x63, 0x50, 0x6F, 0x6C, 0x61, 0x72, 0x69, 0x74, // cPolarit
+ /* 03D8 */ 0x79, 0x3E, 0x46, 0x61, 0x6C, 0x73, 0x65, 0x3C, // y>False<
+ /* 03E0 */ 0x2F, 0x49, 0x6E, 0x76, 0x65, 0x72, 0x74, 0x48, // /InvertH
+ /* 03E8 */ 0x73, 0x79, 0x6E, 0x63, 0x50, 0x6F, 0x6C, 0x61, // syncPola
+ /* 03F0 */ 0x72, 0x69, 0x74, 0x79, 0x3E, 0x0A, 0x20, 0x20, // rity>.
+ /* 03F8 */ 0x20, 0x20, 0x3C, 0x42, 0x6F, 0x72, 0x64, 0x65, // <Borde
+ /* 0400 */ 0x72, 0x43, 0x6F, 0x6C, 0x6F, 0x72, 0x3E, 0x30, // rColor>0
+ /* 0408 */ 0x78, 0x30, 0x3C, 0x2F, 0x42, 0x6F, 0x72, 0x64, // x0</Bord
+ /* 0410 */ 0x65, 0x72, 0x43, 0x6F, 0x6C, 0x6F, 0x72, 0x3E, // erColor>
+ /* 0418 */ 0x0A, 0x3C, 0x2F, 0x47, 0x72, 0x6F, 0x75, 0x70, // .</Group
+ /* 0420 */ 0x3E, 0x0A, 0x3C, 0x47, 0x72, 0x6F, 0x75, 0x70, // >.<Group
+ /* 0428 */ 0x20, 0x69, 0x64, 0x3D, 0x27, 0x44, 0x69, 0x73, // id='Dis
+ /* 0430 */ 0x70, 0x6C, 0x61, 0x79, 0x20, 0x49, 0x6E, 0x74, // play Int
+ /* 0438 */ 0x65, 0x72, 0x66, 0x61, 0x63, 0x65, 0x27, 0x3E, // erface'>
+ /* 0440 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x49, 0x6E, // . <In
+ /* 0448 */ 0x74, 0x65, 0x72, 0x66, 0x61, 0x63, 0x65, 0x54, // terfaceT
+ /* 0450 */ 0x79, 0x70, 0x65, 0x3E, 0x38, 0x3C, 0x2F, 0x49, // ype>8</I
+ /* 0458 */ 0x6E, 0x74, 0x65, 0x72, 0x66, 0x61, 0x63, 0x65, // nterface
+ /* 0460 */ 0x54, 0x79, 0x70, 0x65, 0x3E, 0x0A, 0x20, 0x20, // Type>.
+ /* 0468 */ 0x20, 0x20, 0x3C, 0x49, 0x6E, 0x74, 0x65, 0x72, // <Inter
+ /* 0470 */ 0x66, 0x61, 0x63, 0x65, 0x43, 0x6F, 0x6C, 0x6F, // faceColo
+ /* 0478 */ 0x72, 0x46, 0x6F, 0x72, 0x6D, 0x61, 0x74, 0x3E, // rFormat>
+ /* 0480 */ 0x33, 0x3C, 0x2F, 0x49, 0x6E, 0x74, 0x65, 0x72, // 3</Inter
+ /* 0488 */ 0x66, 0x61, 0x63, 0x65, 0x43, 0x6F, 0x6C, 0x6F, // faceColo
+ /* 0490 */ 0x72, 0x46, 0x6F, 0x72, 0x6D, 0x61, 0x74, 0x3E, // rFormat>
+ /* 0498 */ 0x0A, 0x3C, 0x2F, 0x47, 0x72, 0x6F, 0x75, 0x70, // .</Group
+ /* 04A0 */ 0x3E, 0x0A, 0x3C, 0x47, 0x72, 0x6F, 0x75, 0x70, // >.<Group
+ /* 04A8 */ 0x20, 0x69, 0x64, 0x3D, 0x27, 0x44, 0x53, 0x49, // id='DSI
+ /* 04B0 */ 0x20, 0x49, 0x6E, 0x74, 0x65, 0x72, 0x66, 0x61, // Interfa
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+ /* 04C0 */ 0x20, 0x3C, 0x44, 0x53, 0x49, 0x43, 0x68, 0x61, // <DSICha
+ /* 04C8 */ 0x6E, 0x6E, 0x65, 0x6C, 0x49, 0x64, 0x3E, 0x32, // nnelId>2
+ /* 04D0 */ 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x43, 0x68, 0x61, // </DSICha
+ /* 04D8 */ 0x6E, 0x6E, 0x65, 0x6C, 0x49, 0x64, 0x3E, 0x0A, // nnelId>.
+ /* 04E0 */ 0x20, 0x20, 0x20, 0x20, 0x3C, 0x44, 0x53, 0x49, // <DSI
+ /* 04E8 */ 0x56, 0x69, 0x72, 0x74, 0x75, 0x61, 0x6C, 0x49, // VirtualI
+ /* 04F0 */ 0x64, 0x3E, 0x30, 0x3C, 0x2F, 0x44, 0x53, 0x49, // d>0</DSI
+ /* 04F8 */ 0x56, 0x69, 0x72, 0x74, 0x75, 0x61, 0x6C, 0x49, // VirtualI
+ /* 0500 */ 0x64, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // d>. <
+ /* 0508 */ 0x44, 0x53, 0x49, 0x43, 0x6F, 0x6C, 0x6F, 0x72, // DSIColor
+ /* 0510 */ 0x46, 0x6F, 0x72, 0x6D, 0x61, 0x74, 0x3E, 0x33, // Format>3
+ /* 0518 */ 0x36, 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x43, 0x6F, // 6</DSICo
+ /* 0520 */ 0x6C, 0x6F, 0x72, 0x46, 0x6F, 0x72, 0x6D, 0x61, // lorForma
+ /* 0528 */ 0x74, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // t>. <
+ /* 0530 */ 0x44, 0x53, 0x49, 0x54, 0x72, 0x61, 0x66, 0x66, // DSITraff
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+ /* 0540 */ 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x54, 0x72, 0x61, // </DSITra
+ /* 0548 */ 0x66, 0x66, 0x69, 0x63, 0x4D, 0x6F, 0x64, 0x65, // fficMode
+ /* 0550 */ 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x44, // >. <D
+ /* 0558 */ 0x53, 0x49, 0x4C, 0x61, 0x6E, 0x65, 0x73, 0x3E, // SILanes>
+ /* 0560 */ 0x34, 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x4C, 0x61, // 4</DSILa
+ /* 0568 */ 0x6E, 0x65, 0x73, 0x3E, 0x0A, 0x20, 0x20, 0x20, // nes>.
+ /* 0570 */ 0x20, 0x3C, 0x44, 0x53, 0x49, 0x52, 0x65, 0x66, // <DSIRef
+ /* 0578 */ 0x72, 0x65, 0x73, 0x68, 0x52, 0x61, 0x74, 0x65, // reshRate
+ /* 0580 */ 0x3E, 0x30, 0x78, 0x33, 0x43, 0x30, 0x30, 0x30, // >0x3C000
+ /* 0588 */ 0x30, 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x52, 0x65, // 0</DSIRe
+ /* 0590 */ 0x66, 0x72, 0x65, 0x73, 0x68, 0x52, 0x61, 0x74, // freshRat
+ /* 0598 */ 0x65, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // e>. <
+ /* 05A0 */ 0x44, 0x53, 0x49, 0x48, 0x73, 0x61, 0x48, 0x73, // DSIHsaHs
+ /* 05A8 */ 0x65, 0x41, 0x66, 0x74, 0x65, 0x72, 0x56, 0x73, // eAfterVs
+ /* 05B0 */ 0x56, 0x65, 0x3E, 0x46, 0x61, 0x6C, 0x73, 0x65, // Ve>False
+ /* 05B8 */ 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x48, 0x73, 0x61, // </DSIHsa
+ /* 05C0 */ 0x48, 0x73, 0x65, 0x41, 0x66, 0x74, 0x65, 0x72, // HseAfter
+ /* 05C8 */ 0x56, 0x73, 0x56, 0x65, 0x3E, 0x0A, 0x20, 0x20, // VsVe>.
+ /* 05D0 */ 0x20, 0x20, 0x3C, 0x44, 0x53, 0x49, 0x4C, 0x6F, // <DSILo
+ /* 05D8 */ 0x77, 0x50, 0x6F, 0x77, 0x65, 0x72, 0x4D, 0x6F, // wPowerMo
+ /* 05E0 */ 0x64, 0x65, 0x49, 0x6E, 0x48, 0x46, 0x50, 0x3E, // deInHFP>
+ /* 05E8 */ 0x46, 0x61, 0x6C, 0x73, 0x65, 0x3C, 0x2F, 0x44, // False</D
+ /* 05F0 */ 0x53, 0x49, 0x4C, 0x6F, 0x77, 0x50, 0x6F, 0x77, // SILowPow
+ /* 05F8 */ 0x65, 0x72, 0x4D, 0x6F, 0x64, 0x65, 0x49, 0x6E, // erModeIn
+ /* 0600 */ 0x48, 0x46, 0x50, 0x3E, 0x0A, 0x20, 0x20, 0x20, // HFP>.
+ /* 0608 */ 0x20, 0x3C, 0x44, 0x53, 0x49, 0x4C, 0x6F, 0x77, // <DSILow
+ /* 0610 */ 0x50, 0x6F, 0x77, 0x65, 0x72, 0x4D, 0x6F, 0x64, // PowerMod
+ /* 0618 */ 0x65, 0x49, 0x6E, 0x48, 0x42, 0x50, 0x3E, 0x46, // eInHBP>F
+ /* 0620 */ 0x61, 0x6C, 0x73, 0x65, 0x3C, 0x2F, 0x44, 0x53, // alse</DS
+ /* 0628 */ 0x49, 0x4C, 0x6F, 0x77, 0x50, 0x6F, 0x77, 0x65, // ILowPowe
+ /* 0630 */ 0x72, 0x4D, 0x6F, 0x64, 0x65, 0x49, 0x6E, 0x48, // rModeInH
+ /* 0638 */ 0x42, 0x50, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, // BP>.
+ /* 0640 */ 0x3C, 0x44, 0x53, 0x49, 0x4C, 0x6F, 0x77, 0x50, // <DSILowP
+ /* 0648 */ 0x6F, 0x77, 0x65, 0x72, 0x4D, 0x6F, 0x64, 0x65, // owerMode
+ /* 0650 */ 0x49, 0x6E, 0x48, 0x53, 0x41, 0x3E, 0x46, 0x61, // InHSA>Fa
+ /* 0658 */ 0x6C, 0x73, 0x65, 0x3C, 0x2F, 0x44, 0x53, 0x49, // lse</DSI
+ /* 0660 */ 0x4C, 0x6F, 0x77, 0x50, 0x6F, 0x77, 0x65, 0x72, // LowPower
+ /* 0668 */ 0x4D, 0x6F, 0x64, 0x65, 0x49, 0x6E, 0x48, 0x53, // ModeInHS
+ /* 0670 */ 0x41, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // A>. <
+ /* 0678 */ 0x44, 0x53, 0x49, 0x4C, 0x6F, 0x77, 0x50, 0x6F, // DSILowPo
+ /* 0680 */ 0x77, 0x65, 0x72, 0x4D, 0x6F, 0x64, 0x65, 0x49, // werModeI
+ /* 0688 */ 0x6E, 0x42, 0x4C, 0x4C, 0x50, 0x45, 0x4F, 0x46, // nBLLPEOF
+ /* 0690 */ 0x3E, 0x54, 0x72, 0x75, 0x65, 0x3C, 0x2F, 0x44, // >True</D
+ /* 0698 */ 0x53, 0x49, 0x4C, 0x6F, 0x77, 0x50, 0x6F, 0x77, // SILowPow
+ /* 06A0 */ 0x65, 0x72, 0x4D, 0x6F, 0x64, 0x65, 0x49, 0x6E, // erModeIn
+ /* 06A8 */ 0x42, 0x4C, 0x4C, 0x50, 0x45, 0x4F, 0x46, 0x3E, // BLLPEOF>
+ /* 06B0 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x44, 0x53, // . <DS
+ /* 06B8 */ 0x49, 0x4C, 0x6F, 0x77, 0x50, 0x6F, 0x77, 0x65, // ILowPowe
+ /* 06C0 */ 0x72, 0x4D, 0x6F, 0x64, 0x65, 0x49, 0x6E, 0x42, // rModeInB
+ /* 06C8 */ 0x4C, 0x4C, 0x50, 0x3E, 0x54, 0x72, 0x75, 0x65, // LLP>True
+ /* 06D0 */ 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x4C, 0x6F, 0x77, // </DSILow
+ /* 06D8 */ 0x50, 0x6F, 0x77, 0x65, 0x72, 0x4D, 0x6F, 0x64, // PowerMod
+ /* 06E0 */ 0x65, 0x49, 0x6E, 0x42, 0x4C, 0x4C, 0x50, 0x3E, // eInBLLP>
+ /* 06E8 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x44, 0x53, // . <DS
+ /* 06F0 */ 0x49, 0x4C, 0x50, 0x31, 0x31, 0x41, 0x74, 0x49, // ILP11AtI
+ /* 06F8 */ 0x6E, 0x69, 0x74, 0x3E, 0x54, 0x72, 0x75, 0x65, // nit>True
+ /* 0700 */ 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x4C, 0x50, 0x31, // </DSILP1
+ /* 0708 */ 0x31, 0x41, 0x74, 0x49, 0x6E, 0x69, 0x74, 0x3E, // 1AtInit>
+ /* 0710 */ 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x44, 0x53, // . <DS
+ /* 0718 */ 0x49, 0x43, 0x6F, 0x6E, 0x74, 0x72, 0x6F, 0x6C, // IControl
+ /* 0720 */ 0x6C, 0x65, 0x72, 0x4D, 0x61, 0x70, 0x70, 0x69, // lerMappi
+ /* 0728 */ 0x6E, 0x67, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, // ng>.
+ /* 0730 */ 0x20, 0x20, 0x20, 0x20, 0x30, 0x30, 0x0A, 0x20, // 00.
+ /* 0738 */ 0x20, 0x20, 0x20, 0x3C, 0x2F, 0x44, 0x53, 0x49, // </DSI
+ /* 0740 */ 0x43, 0x6F, 0x6E, 0x74, 0x72, 0x6F, 0x6C, 0x6C, // Controll
+ /* 0748 */ 0x65, 0x72, 0x4D, 0x61, 0x70, 0x70, 0x69, 0x6E, // erMappin
+ /* 0750 */ 0x67, 0x3E, 0x0A, 0x3C, 0x2F, 0x47, 0x72, 0x6F, // g>.</Gro
+ /* 0758 */ 0x75, 0x70, 0x3E, 0x0A, 0x3C, 0x44, 0x53, 0x49, // up>.<DSI
+ /* 0760 */ 0x49, 0x6E, 0x69, 0x74, 0x53, 0x65, 0x71, 0x75, // InitSequ
+ /* 0768 */ 0x65, 0x6E, 0x63, 0x65, 0x3E, 0x0A, 0x20, 0x31, // ence>. 1
+ /* 0770 */ 0x35, 0x20, 0x46, 0x46, 0x20, 0x32, 0x34, 0x0A, // 5 FF 24.
+ /* 0778 */ 0x20, 0x31, 0x35, 0x20, 0x39, 0x44, 0x20, 0x33, // 15 9D 3
+ /* 0780 */ 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x46, 0x42, // 4. 15 FB
+ /* 0788 */ 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, // 01. 15
+ /* 0790 */ 0x43, 0x34, 0x20, 0x32, 0x35, 0x0A, 0x20, 0x31, // C4 25. 1
+ /* 0798 */ 0x35, 0x20, 0x44, 0x31, 0x20, 0x30, 0x38, 0x0A, // 5 D1 08.
+ /* 07A0 */ 0x20, 0x31, 0x35, 0x20, 0x44, 0x32, 0x20, 0x38, // 15 D2 8
+ /* 07A8 */ 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x46, 0x46, // 4. 15 FF
+ /* 07B0 */ 0x20, 0x32, 0x36, 0x0A, 0x20, 0x31, 0x35, 0x20, // 26. 15
+ /* 07B8 */ 0x46, 0x42, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // FB 01. 1
+ /* 07C0 */ 0x35, 0x20, 0x30, 0x33, 0x20, 0x31, 0x43, 0x0A, // 5 03 1C.
+ /* 07C8 */ 0x20, 0x31, 0x35, 0x20, 0x33, 0x42, 0x20, 0x30, // 15 3B 0
+ /* 07D0 */ 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x36, 0x42, // 8. 15 6B
+ /* 07D8 */ 0x20, 0x30, 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, // 08. 15
+ /* 07E0 */ 0x39, 0x37, 0x20, 0x30, 0x38, 0x0A, 0x20, 0x31, // 97 08. 1
+ /* 07E8 */ 0x35, 0x20, 0x43, 0x35, 0x20, 0x30, 0x38, 0x0A, // 5 C5 08.
+ /* 07F0 */ 0x20, 0x31, 0x35, 0x20, 0x46, 0x42, 0x20, 0x30, // 15 FB 0
+ /* 07F8 */ 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x46, 0x46, // 1. 15 FF
+ /* 0800 */ 0x20, 0x32, 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, // 23. 15
+ /* 0808 */ 0x46, 0x42, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // FB 01. 1
+ /* 0810 */ 0x35, 0x20, 0x30, 0x31, 0x20, 0x38, 0x34, 0x0A, // 5 01 84.
+ /* 0818 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x35, 0x20, 0x32, // 15 05 2
+ /* 0820 */ 0x44, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x36, // D. 15 06
+ /* 0828 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0830 */ 0x33, 0x32, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 32 00. 1
+ /* 0838 */ 0x35, 0x20, 0x31, 0x33, 0x20, 0x46, 0x46, 0x0A, // 5 13 FF.
+ /* 0840 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x34, 0x20, 0x46, // 15 14 F
+ /* 0848 */ 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x35, // 8. 15 15
+ /* 0850 */ 0x20, 0x45, 0x44, 0x0A, 0x20, 0x31, 0x35, 0x20, // ED. 15
+ /* 0858 */ 0x31, 0x36, 0x20, 0x45, 0x35, 0x0A, 0x20, 0x31, // 16 E5. 1
+ /* 0860 */ 0x35, 0x20, 0x30, 0x39, 0x20, 0x30, 0x31, 0x0A, // 5 09 01.
+ /* 0868 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x41, 0x20, 0x30, // 15 0A 0
+ /* 0870 */ 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x42, // 1. 15 0B
+ /* 0878 */ 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, // 01. 15
+ /* 0880 */ 0x30, 0x43, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // 0C 01. 1
+ /* 0888 */ 0x35, 0x20, 0x30, 0x44, 0x20, 0x30, 0x31, 0x0A, // 5 0D 01.
+ /* 0890 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x45, 0x20, 0x30, // 15 0E 0
+ /* 0898 */ 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x46, // 1. 15 0F
+ /* 08A0 */ 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, // 01. 15
+ /* 08A8 */ 0x31, 0x30, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // 10 01. 1
+ /* 08B0 */ 0x35, 0x20, 0x31, 0x31, 0x20, 0x30, 0x31, 0x0A, // 5 11 01.
+ /* 08B8 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x32, 0x20, 0x30, // 15 12 0
+ /* 08C0 */ 0x31, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x37, // 1. 15 17
+ /* 08C8 */ 0x20, 0x46, 0x46, 0x0A, 0x20, 0x31, 0x35, 0x20, // FF. 15
+ /* 08D0 */ 0x31, 0x38, 0x20, 0x45, 0x45, 0x0A, 0x20, 0x31, // 18 EE. 1
+ /* 08D8 */ 0x35, 0x20, 0x31, 0x39, 0x20, 0x44, 0x44, 0x0A, // 5 19 DD.
+ /* 08E0 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x41, 0x20, 0x43, // 15 1A C
+ /* 08E8 */ 0x37, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x42, // 7. 15 1B
+ /* 08F0 */ 0x20, 0x41, 0x46, 0x0A, 0x20, 0x31, 0x35, 0x20, // AF. 15
+ /* 08F8 */ 0x31, 0x43, 0x20, 0x39, 0x39, 0x0A, 0x20, 0x31, // 1C 99. 1
+ /* 0900 */ 0x35, 0x20, 0x31, 0x44, 0x20, 0x39, 0x39, 0x0A, // 5 1D 99.
+ /* 0908 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x45, 0x20, 0x38, // 15 1E 8
+ /* 0910 */ 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x46, // 8. 15 1F
+ /* 0918 */ 0x20, 0x37, 0x37, 0x0A, 0x20, 0x31, 0x35, 0x20, // 77. 15
+ /* 0920 */ 0x32, 0x30, 0x20, 0x36, 0x36, 0x0A, 0x20, 0x31, // 20 66. 1
+ /* 0928 */ 0x35, 0x20, 0x33, 0x33, 0x20, 0x30, 0x30, 0x0A, // 5 33 00.
+ /* 0930 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x31, 0x20, 0x46, // 15 21 F
+ /* 0938 */ 0x46, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x32, // F. 15 22
+ /* 0940 */ 0x20, 0x46, 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, // F8. 15
+ /* 0948 */ 0x32, 0x33, 0x20, 0x45, 0x46, 0x0A, 0x20, 0x31, // 23 EF. 1
+ /* 0950 */ 0x35, 0x20, 0x32, 0x34, 0x20, 0x45, 0x37, 0x0A, // 5 24 E7.
+ /* 0958 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x35, 0x20, 0x44, // 15 25 D
+ /* 0960 */ 0x45, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x36, // E. 15 26
+ /* 0968 */ 0x20, 0x44, 0x37, 0x0A, 0x20, 0x31, 0x35, 0x20, // D7. 15
+ /* 0970 */ 0x32, 0x37, 0x20, 0x43, 0x44, 0x0A, 0x20, 0x31, // 27 CD. 1
+ /* 0978 */ 0x35, 0x20, 0x32, 0x38, 0x20, 0x43, 0x34, 0x0A, // 5 28 C4.
+ /* 0980 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x39, 0x20, 0x42, // 15 29 B
+ /* 0988 */ 0x43, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x41, // C. 15 2A
+ /* 0990 */ 0x20, 0x42, 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, // B3. 15
+ /* 0998 */ 0x46, 0x46, 0x20, 0x32, 0x32, 0x0A, 0x20, 0x31, // FF 22. 1
+ /* 09A0 */ 0x35, 0x20, 0x30, 0x30, 0x20, 0x30, 0x41, 0x0A, // 5 00 0A.
+ /* 09A8 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x31, 0x20, 0x34, // 15 01 4
+ /* 09B0 */ 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x32, // 3. 15 02
+ /* 09B8 */ 0x20, 0x35, 0x42, 0x0A, 0x20, 0x31, 0x35, 0x20, // 5B. 15
+ /* 09C0 */ 0x30, 0x33, 0x20, 0x36, 0x41, 0x0A, 0x20, 0x31, // 03 6A. 1
+ /* 09C8 */ 0x35, 0x20, 0x30, 0x34, 0x20, 0x37, 0x41, 0x0A, // 5 04 7A.
+ /* 09D0 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x35, 0x20, 0x38, // 15 05 8
+ /* 09D8 */ 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x36, // 2. 15 06
+ /* 09E0 */ 0x20, 0x38, 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, // 85. 15
+ /* 09E8 */ 0x30, 0x37, 0x20, 0x38, 0x30, 0x0A, 0x20, 0x31, // 07 80. 1
+ /* 09F0 */ 0x35, 0x20, 0x30, 0x38, 0x20, 0x37, 0x43, 0x0A, // 5 08 7C.
+ /* 09F8 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x39, 0x20, 0x37, // 15 09 7
+ /* 0A00 */ 0x43, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x41, // C. 15 0A
+ /* 0A08 */ 0x20, 0x37, 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, // 74. 15
+ /* 0A10 */ 0x30, 0x42, 0x20, 0x37, 0x31, 0x0A, 0x20, 0x31, // 0B 71. 1
+ /* 0A18 */ 0x35, 0x20, 0x30, 0x43, 0x20, 0x36, 0x45, 0x0A, // 5 0C 6E.
+ /* 0A20 */ 0x20, 0x31, 0x35, 0x20, 0x30, 0x44, 0x20, 0x36, // 15 0D 6
+ /* 0A28 */ 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x30, 0x45, // 8. 15 0E
+ /* 0A30 */ 0x20, 0x36, 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, // 65. 15
+ /* 0A38 */ 0x30, 0x46, 0x20, 0x35, 0x43, 0x0A, 0x20, 0x31, // 0F 5C. 1
+ /* 0A40 */ 0x35, 0x20, 0x31, 0x30, 0x20, 0x33, 0x32, 0x0A, // 5 10 32.
+ /* 0A48 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x31, 0x20, 0x31, // 15 11 1
+ /* 0A50 */ 0x38, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x32, // 8. 15 12
+ /* 0A58 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0A60 */ 0x31, 0x33, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 13 00. 1
+ /* 0A68 */ 0x35, 0x20, 0x31, 0x41, 0x20, 0x30, 0x30, 0x0A, // 5 1A 00.
+ /* 0A70 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x42, 0x20, 0x30, // 15 1B 0
+ /* 0A78 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x31, 0x43, // 0. 15 1C
+ /* 0A80 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0A88 */ 0x31, 0x44, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 1D 00. 1
+ /* 0A90 */ 0x35, 0x20, 0x31, 0x45, 0x20, 0x30, 0x30, 0x0A, // 5 1E 00.
+ /* 0A98 */ 0x20, 0x31, 0x35, 0x20, 0x31, 0x46, 0x20, 0x30, // 15 1F 0
+ /* 0AA0 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x30, // 0. 15 20
+ /* 0AA8 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0AB0 */ 0x32, 0x31, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 21 00. 1
+ /* 0AB8 */ 0x35, 0x20, 0x32, 0x32, 0x20, 0x30, 0x30, 0x0A, // 5 22 00.
+ /* 0AC0 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x33, 0x20, 0x30, // 15 23 0
+ /* 0AC8 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x34, // 0. 15 24
+ /* 0AD0 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0AD8 */ 0x32, 0x35, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 25 00. 1
+ /* 0AE0 */ 0x35, 0x20, 0x32, 0x36, 0x20, 0x30, 0x30, 0x0A, // 5 26 00.
+ /* 0AE8 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x37, 0x20, 0x30, // 15 27 0
+ /* 0AF0 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x38, // 0. 15 28
+ /* 0AF8 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0B00 */ 0x32, 0x39, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 29 00. 1
+ /* 0B08 */ 0x35, 0x20, 0x32, 0x41, 0x20, 0x30, 0x30, 0x0A, // 5 2A 00.
+ /* 0B10 */ 0x20, 0x31, 0x35, 0x20, 0x32, 0x42, 0x20, 0x30, // 15 2B 0
+ /* 0B18 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x46, // 0. 15 2F
+ /* 0B20 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0B28 */ 0x33, 0x30, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 30 00. 1
+ /* 0B30 */ 0x35, 0x20, 0x33, 0x31, 0x20, 0x30, 0x30, 0x0A, // 5 31 00.
+ /* 0B38 */ 0x20, 0x31, 0x35, 0x20, 0x33, 0x32, 0x20, 0x30, // 15 32 0
+ /* 0B40 */ 0x43, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x33, 0x33, // C. 15 33
+ /* 0B48 */ 0x20, 0x30, 0x43, 0x0A, 0x20, 0x31, 0x35, 0x20, // 0C. 15
+ /* 0B50 */ 0x33, 0x34, 0x20, 0x30, 0x43, 0x0A, 0x20, 0x31, // 34 0C. 1
+ /* 0B58 */ 0x35, 0x20, 0x33, 0x35, 0x20, 0x30, 0x42, 0x0A, // 5 35 0B.
+ /* 0B60 */ 0x20, 0x31, 0x35, 0x20, 0x33, 0x36, 0x20, 0x30, // 15 36 0
+ /* 0B68 */ 0x39, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x33, 0x37, // 9. 15 37
+ /* 0B70 */ 0x20, 0x30, 0x39, 0x0A, 0x20, 0x31, 0x35, 0x20, // 09. 15
+ /* 0B78 */ 0x33, 0x38, 0x20, 0x30, 0x38, 0x0A, 0x20, 0x31, // 38 08. 1
+ /* 0B80 */ 0x35, 0x20, 0x33, 0x39, 0x20, 0x30, 0x35, 0x0A, // 5 39 05.
+ /* 0B88 */ 0x20, 0x31, 0x35, 0x20, 0x33, 0x41, 0x20, 0x30, // 15 3A 0
+ /* 0B90 */ 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x33, 0x42, // 3. 15 3B
+ /* 0B98 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0BA0 */ 0x33, 0x46, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 3F 00. 1
+ /* 0BA8 */ 0x35, 0x20, 0x34, 0x30, 0x20, 0x30, 0x30, 0x0A, // 5 40 00.
+ /* 0BB0 */ 0x20, 0x31, 0x35, 0x20, 0x34, 0x31, 0x20, 0x30, // 15 41 0
+ /* 0BB8 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x34, 0x32, // 0. 15 42
+ /* 0BC0 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0BC8 */ 0x34, 0x33, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 43 00. 1
+ /* 0BD0 */ 0x35, 0x20, 0x34, 0x34, 0x20, 0x30, 0x30, 0x0A, // 5 44 00.
+ /* 0BD8 */ 0x20, 0x31, 0x35, 0x20, 0x34, 0x35, 0x20, 0x30, // 15 45 0
+ /* 0BE0 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x34, 0x36, // 0. 15 46
+ /* 0BE8 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0BF0 */ 0x34, 0x37, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 47 00. 1
+ /* 0BF8 */ 0x35, 0x20, 0x34, 0x38, 0x20, 0x30, 0x30, 0x0A, // 5 48 00.
+ /* 0C00 */ 0x20, 0x31, 0x35, 0x20, 0x34, 0x39, 0x20, 0x30, // 15 49 0
+ /* 0C08 */ 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x34, 0x41, // 3. 15 4A
+ /* 0C10 */ 0x20, 0x30, 0x36, 0x0A, 0x20, 0x31, 0x35, 0x20, // 06. 15
+ /* 0C18 */ 0x34, 0x42, 0x20, 0x30, 0x37, 0x0A, 0x20, 0x31, // 4B 07. 1
+ /* 0C20 */ 0x35, 0x20, 0x34, 0x43, 0x20, 0x30, 0x37, 0x0A, // 5 4C 07.
+ /* 0C28 */ 0x20, 0x31, 0x35, 0x20, 0x34, 0x44, 0x20, 0x30, // 15 4D 0
+ /* 0C30 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x34, 0x45, // 0. 15 4E
+ /* 0C38 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0C40 */ 0x34, 0x46, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 4F 00. 1
+ /* 0C48 */ 0x35, 0x20, 0x35, 0x30, 0x20, 0x30, 0x30, 0x0A, // 5 50 00.
+ /* 0C50 */ 0x20, 0x31, 0x35, 0x20, 0x35, 0x31, 0x20, 0x30, // 15 51 0
+ /* 0C58 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x35, 0x32, // 0. 15 52
+ /* 0C60 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0C68 */ 0x35, 0x33, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // 53 01. 1
+ /* 0C70 */ 0x35, 0x20, 0x35, 0x34, 0x20, 0x30, 0x31, 0x0A, // 5 54 01.
+ /* 0C78 */ 0x20, 0x31, 0x35, 0x20, 0x35, 0x35, 0x20, 0x38, // 15 55 8
+ /* 0C80 */ 0x39, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x35, 0x36, // 9. 15 56
+ /* 0C88 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0C90 */ 0x35, 0x38, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 58 00. 1
+ /* 0C98 */ 0x35, 0x20, 0x36, 0x38, 0x20, 0x30, 0x30, 0x0A, // 5 68 00.
+ /* 0CA0 */ 0x20, 0x31, 0x35, 0x20, 0x38, 0x34, 0x20, 0x46, // 15 84 F
+ /* 0CA8 */ 0x46, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x38, 0x35, // F. 15 85
+ /* 0CB0 */ 0x20, 0x46, 0x46, 0x0A, 0x20, 0x31, 0x35, 0x20, // FF. 15
+ /* 0CB8 */ 0x38, 0x36, 0x20, 0x30, 0x33, 0x0A, 0x20, 0x31, // 86 03. 1
+ /* 0CC0 */ 0x35, 0x20, 0x38, 0x37, 0x20, 0x30, 0x30, 0x0A, // 5 87 00.
+ /* 0CC8 */ 0x20, 0x31, 0x35, 0x20, 0x38, 0x38, 0x20, 0x30, // 15 88 0
+ /* 0CD0 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x41, 0x32, // 0. 15 A2
+ /* 0CD8 */ 0x20, 0x32, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 20. 15
+ /* 0CE0 */ 0x41, 0x39, 0x20, 0x30, 0x31, 0x0A, 0x20, 0x31, // A9 01. 1
+ /* 0CE8 */ 0x35, 0x20, 0x41, 0x41, 0x20, 0x31, 0x32, 0x0A, // 5 AA 12.
+ /* 0CF0 */ 0x20, 0x31, 0x35, 0x20, 0x41, 0x42, 0x20, 0x31, // 15 AB 1
+ /* 0CF8 */ 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x41, 0x43, // 3. 15 AC
+ /* 0D00 */ 0x20, 0x30, 0x41, 0x0A, 0x20, 0x31, 0x35, 0x20, // 0A. 15
+ /* 0D08 */ 0x41, 0x44, 0x20, 0x37, 0x34, 0x0A, 0x20, 0x31, // AD 74. 1
+ /* 0D10 */ 0x35, 0x20, 0x41, 0x46, 0x20, 0x33, 0x33, 0x0A, // 5 AF 33.
+ /* 0D18 */ 0x20, 0x31, 0x35, 0x20, 0x42, 0x30, 0x20, 0x30, // 15 B0 0
+ /* 0D20 */ 0x33, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x42, 0x31, // 3. 15 B1
+ /* 0D28 */ 0x20, 0x31, 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, // 14. 15
+ /* 0D30 */ 0x42, 0x32, 0x20, 0x34, 0x32, 0x0A, 0x20, 0x31, // B2 42. 1
+ /* 0D38 */ 0x35, 0x20, 0x42, 0x33, 0x20, 0x34, 0x30, 0x0A, // 5 B3 40.
+ /* 0D40 */ 0x20, 0x31, 0x35, 0x20, 0x42, 0x34, 0x20, 0x41, // 15 B4 A
+ /* 0D48 */ 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x42, 0x36, // 5. 15 B6
+ /* 0D50 */ 0x20, 0x34, 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, // 44. 15
+ /* 0D58 */ 0x42, 0x37, 0x20, 0x30, 0x34, 0x0A, 0x20, 0x31, // B7 04. 1
+ /* 0D60 */ 0x35, 0x20, 0x42, 0x38, 0x20, 0x31, 0x34, 0x0A, // 5 B8 14.
+ /* 0D68 */ 0x20, 0x31, 0x35, 0x20, 0x42, 0x39, 0x20, 0x34, // 15 B9 4
+ /* 0D70 */ 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x42, 0x41, // 2. 15 BA
+ /* 0D78 */ 0x20, 0x34, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 40. 15
+ /* 0D80 */ 0x42, 0x42, 0x20, 0x41, 0x35, 0x0A, 0x20, 0x31, // BB A5. 1
+ /* 0D88 */ 0x35, 0x20, 0x42, 0x44, 0x20, 0x34, 0x34, 0x0A, // 5 BD 44.
+ /* 0D90 */ 0x20, 0x31, 0x35, 0x20, 0x42, 0x45, 0x20, 0x30, // 15 BE 0
+ /* 0D98 */ 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x42, 0x46, // 4. 15 BF
+ /* 0DA0 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0DA8 */ 0x43, 0x30, 0x20, 0x37, 0x35, 0x0A, 0x20, 0x31, // C0 75. 1
+ /* 0DB0 */ 0x35, 0x20, 0x43, 0x31, 0x20, 0x36, 0x41, 0x0A, // 5 C1 6A.
+ /* 0DB8 */ 0x20, 0x31, 0x35, 0x20, 0x43, 0x32, 0x20, 0x41, // 15 C2 A
+ /* 0DC0 */ 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x43, 0x34, // 5. 15 C4
+ /* 0DC8 */ 0x20, 0x32, 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, // 22. 15
+ /* 0DD0 */ 0x43, 0x35, 0x20, 0x30, 0x32, 0x0A, 0x20, 0x31, // C5 02. 1
+ /* 0DD8 */ 0x35, 0x20, 0x43, 0x36, 0x20, 0x30, 0x30, 0x0A, // 5 C6 00.
+ /* 0DE0 */ 0x20, 0x31, 0x35, 0x20, 0x43, 0x37, 0x20, 0x39, // 15 C7 9
+ /* 0DE8 */ 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x43, 0x38, // 5. 15 C8
+ /* 0DF0 */ 0x20, 0x38, 0x41, 0x0A, 0x20, 0x31, 0x35, 0x20, // 8A. 15
+ /* 0DF8 */ 0x43, 0x39, 0x20, 0x41, 0x35, 0x0A, 0x20, 0x31, // C9 A5. 1
+ /* 0E00 */ 0x35, 0x20, 0x43, 0x42, 0x20, 0x32, 0x32, 0x0A, // 5 CB 22.
+ /* 0E08 */ 0x20, 0x31, 0x35, 0x20, 0x43, 0x43, 0x20, 0x30, // 15 CC 0
+ /* 0E10 */ 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x43, 0x44, // 2. 15 CD
+ /* 0E18 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0E20 */ 0x43, 0x45, 0x20, 0x42, 0x35, 0x0A, 0x20, 0x31, // CE B5. 1
+ /* 0E28 */ 0x35, 0x20, 0x43, 0x46, 0x20, 0x41, 0x41, 0x0A, // 5 CF AA.
+ /* 0E30 */ 0x20, 0x31, 0x35, 0x20, 0x44, 0x30, 0x20, 0x41, // 15 D0 A
+ /* 0E38 */ 0x35, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x44, 0x32, // 5. 15 D2
+ /* 0E40 */ 0x20, 0x32, 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, // 22. 15
+ /* 0E48 */ 0x44, 0x33, 0x20, 0x30, 0x32, 0x0A, 0x20, 0x31, // D3 02. 1
+ /* 0E50 */ 0x35, 0x20, 0x46, 0x42, 0x20, 0x30, 0x31, 0x0A, // 5 FB 01.
+ /* 0E58 */ 0x20, 0x31, 0x35, 0x20, 0x46, 0x46, 0x20, 0x31, // 15 FF 1
+ /* 0E60 */ 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x32, 0x36, // 0. 15 26
+ /* 0E68 */ 0x20, 0x30, 0x32, 0x0A, 0x20, 0x31, 0x35, 0x20, // 02. 15
+ /* 0E70 */ 0x33, 0x35, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, // 35 00. 1
+ /* 0E78 */ 0x35, 0x20, 0x35, 0x31, 0x20, 0x46, 0x46, 0x0A, // 5 51 FF.
+ /* 0E80 */ 0x20, 0x31, 0x35, 0x20, 0x35, 0x33, 0x20, 0x32, // 15 53 2
+ /* 0E88 */ 0x34, 0x0A, 0x20, 0x31, 0x35, 0x20, 0x35, 0x35, // 4. 15 55
+ /* 0E90 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x31, 0x35, 0x20, // 00. 15
+ /* 0E98 */ 0x42, 0x30, 0x20, 0x30, 0x30, 0x0A, 0x20, 0x30, // B0 00. 0
+ /* 0EA0 */ 0x35, 0x20, 0x31, 0x31, 0x0A, 0x20, 0x46, 0x46, // 5 11. FF
+ /* 0EA8 */ 0x20, 0x35, 0x30, 0x0A, 0x20, 0x30, 0x35, 0x20, // 50. 05
+ /* 0EB0 */ 0x32, 0x39, 0x0A, 0x20, 0x46, 0x46, 0x20, 0x31, // 29. FF 1
+ /* 0EB8 */ 0x34, 0x0A, 0x3C, 0x2F, 0x44, 0x53, 0x49, 0x49, // 4.</DSII
+ /* 0EC0 */ 0x6E, 0x69, 0x74, 0x53, 0x65, 0x71, 0x75, 0x65, // nitSeque
+ /* 0EC8 */ 0x6E, 0x63, 0x65, 0x3E, 0x0A, 0x3C, 0x44, 0x53, // nce>.<DS
+ /* 0ED0 */ 0x49, 0x54, 0x65, 0x72, 0x6D, 0x53, 0x65, 0x71, // ITermSeq
+ /* 0ED8 */ 0x75, 0x65, 0x6E, 0x63, 0x65, 0x3E, 0x0A, 0x20, // uence>.
+ /* 0EE0 */ 0x20, 0x20, 0x20, 0x30, 0x35, 0x20, 0x32, 0x38, // 05 28
+ /* 0EE8 */ 0x20, 0x30, 0x30, 0x0A, 0x20, 0x20, 0x20, 0x20, // 00.
+ /* 0EF0 */ 0x46, 0x46, 0x20, 0x32, 0x30, 0x0A, 0x20, 0x20, // FF 20.
+ /* 0EF8 */ 0x20, 0x20, 0x30, 0x35, 0x20, 0x31, 0x30, 0x20, // 05 10
+ /* 0F00 */ 0x30, 0x30, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x46, // 00. F
+ /* 0F08 */ 0x46, 0x20, 0x38, 0x30, 0x0A, 0x3C, 0x2F, 0x44, // F 80.</D
+ /* 0F10 */ 0x53, 0x49, 0x54, 0x65, 0x72, 0x6D, 0x53, 0x65, // SITermSe
+ /* 0F18 */ 0x71, 0x75, 0x65, 0x6E, 0x63, 0x65, 0x3E, 0x0A, // quence>.
+ /* 0F20 */ 0x3C, 0x47, 0x72, 0x6F, 0x75, 0x70, 0x20, 0x69, // <Group i
+ /* 0F28 */ 0x64, 0x3D, 0x27, 0x42, 0x61, 0x63, 0x6B, 0x6C, // d='Backl
+ /* 0F30 */ 0x69, 0x67, 0x68, 0x74, 0x20, 0x43, 0x6F, 0x6E, // ight Con
+ /* 0F38 */ 0x66, 0x69, 0x67, 0x75, 0x72, 0x61, 0x74, 0x69, // figurati
+ /* 0F40 */ 0x6F, 0x6E, 0x27, 0x3E, 0x0A, 0x20, 0x20, 0x20, // on'>.
+ /* 0F48 */ 0x20, 0x3C, 0x42, 0x61, 0x63, 0x6B, 0x6C, 0x69, // <Backli
+ /* 0F50 */ 0x67, 0x68, 0x74, 0x54, 0x79, 0x70, 0x65, 0x3E, // ghtType>
+ /* 0F58 */ 0x31, 0x3C, 0x2F, 0x42, 0x61, 0x63, 0x6B, 0x6C, // 1</Backl
+ /* 0F60 */ 0x69, 0x67, 0x68, 0x74, 0x54, 0x79, 0x70, 0x65, // ightType
+ /* 0F68 */ 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x42, // >. <B
+ /* 0F70 */ 0x61, 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, // acklight
+ /* 0F78 */ 0x50, 0x6D, 0x69, 0x63, 0x43, 0x6F, 0x6E, 0x74, // PmicCont
+ /* 0F80 */ 0x72, 0x6F, 0x6C, 0x54, 0x79, 0x70, 0x65, 0x3E, // rolType>
+ /* 0F88 */ 0x32, 0x3C, 0x2F, 0x42, 0x61, 0x63, 0x6B, 0x6C, // 2</Backl
+ /* 0F90 */ 0x69, 0x67, 0x68, 0x74, 0x50, 0x6D, 0x69, 0x63, // ightPmic
+ /* 0F98 */ 0x43, 0x6F, 0x6E, 0x74, 0x72, 0x6F, 0x6C, 0x54, // ControlT
+ /* 0FA0 */ 0x79, 0x70, 0x65, 0x3E, 0x0A, 0x20, 0x20, 0x20, // ype>.
+ /* 0FA8 */ 0x20, 0x3C, 0x42, 0x61, 0x63, 0x6B, 0x6C, 0x69, // <Backli
+ /* 0FB0 */ 0x67, 0x68, 0x74, 0x53, 0x74, 0x65, 0x70, 0x73, // ghtSteps
+ /* 0FB8 */ 0x3E, 0x31, 0x30, 0x30, 0x3C, 0x2F, 0x42, 0x61, // >100</Ba
+ /* 0FC0 */ 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, 0x53, // cklightS
+ /* 0FC8 */ 0x74, 0x65, 0x70, 0x73, 0x3E, 0x0A, 0x20, 0x20, // teps>.
+ /* 0FD0 */ 0x20, 0x20, 0x3C, 0x42, 0x61, 0x63, 0x6B, 0x6C, // <Backl
+ /* 0FD8 */ 0x69, 0x67, 0x68, 0x74, 0x50, 0x4D, 0x49, 0x43, // ightPMIC
+ /* 0FE0 */ 0x42, 0x61, 0x6E, 0x6B, 0x53, 0x65, 0x6C, 0x65, // BankSele
+ /* 0FE8 */ 0x63, 0x74, 0x3E, 0x31, 0x35, 0x3C, 0x2F, 0x42, // ct>15</B
+ /* 0FF0 */ 0x61, 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, // acklight
+ /* 0FF8 */ 0x50, 0x4D, 0x49, 0x43, 0x42, 0x61, 0x6E, 0x6B, // PMICBank
+ /* 1000 */ 0x53, 0x65, 0x6C, 0x65, 0x63, 0x74, 0x3E, 0x0A, // Select>.
+ /* 1008 */ 0x20, 0x20, 0x20, 0x20, 0x3C, 0x42, 0x61, 0x63, // <Bac
+ /* 1010 */ 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, 0x50, 0x4D, // klightPM
+ /* 1018 */ 0x49, 0x43, 0x50, 0x57, 0x4D, 0x46, 0x72, 0x65, // ICPWMFre
+ /* 1020 */ 0x71, 0x75, 0x65, 0x6E, 0x63, 0x79, 0x3E, 0x36, // quency>6
+ /* 1028 */ 0x30, 0x30, 0x30, 0x30, 0x30, 0x3C, 0x2F, 0x42, // 00000</B
+ /* 1030 */ 0x61, 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, // acklight
+ /* 1038 */ 0x50, 0x4D, 0x49, 0x43, 0x50, 0x57, 0x4D, 0x46, // PMICPWMF
+ /* 1040 */ 0x72, 0x65, 0x71, 0x75, 0x65, 0x6E, 0x63, 0x79, // requency
+ /* 1048 */ 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x42, // >. <B
+ /* 1050 */ 0x61, 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, // acklight
+ /* 1058 */ 0x53, 0x74, 0x65, 0x70, 0x73, 0x3E, 0x31, 0x30, // Steps>10
+ /* 1060 */ 0x30, 0x3C, 0x2F, 0x42, 0x61, 0x63, 0x6B, 0x6C, // 0</Backl
+ /* 1068 */ 0x69, 0x67, 0x68, 0x74, 0x53, 0x74, 0x65, 0x70, // ightStep
+ /* 1070 */ 0x73, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // s>. <
+ /* 1078 */ 0x42, 0x61, 0x63, 0x6B, 0x6C, 0x69, 0x67, 0x68, // Backligh
+ /* 1080 */ 0x74, 0x44, 0x65, 0x66, 0x61, 0x75, 0x6C, 0x74, // tDefault
+ /* 1088 */ 0x3E, 0x38, 0x30, 0x3C, 0x2F, 0x42, 0x61, 0x63, // >80</Bac
+ /* 1090 */ 0x6B, 0x6C, 0x69, 0x67, 0x68, 0x74, 0x44, 0x65, // klightDe
+ /* 1098 */ 0x66, 0x61, 0x75, 0x6C, 0x74, 0x3E, 0x0A, 0x20, // fault>.
+ /* 10A0 */ 0x20, 0x20, 0x20, 0x3C, 0x42, 0x61, 0x63, 0x6B, // <Back
+ /* 10A8 */ 0x6C, 0x69, 0x67, 0x68, 0x74, 0x4C, 0x6F, 0x77, // lightLow
+ /* 10B0 */ 0x50, 0x6F, 0x77, 0x65, 0x72, 0x3E, 0x34, 0x30, // Power>40
+ /* 10B8 */ 0x3C, 0x2F, 0x42, 0x61, 0x63, 0x6B, 0x6C, 0x69, // </Backli
+ /* 10C0 */ 0x67, 0x68, 0x74, 0x4C, 0x6F, 0x77, 0x50, 0x6F, // ghtLowPo
+ /* 10C8 */ 0x77, 0x65, 0x72, 0x3E, 0x0A, 0x20, 0x20, 0x20, // wer>.
+ /* 10D0 */ 0x20, 0x3C, 0x50, 0x4D, 0x49, 0x50, 0x6F, 0x77, // <PMIPow
+ /* 10D8 */ 0x65, 0x72, 0x50, 0x6D, 0x69, 0x63, 0x4E, 0x75, // erPmicNu
+ /* 10E0 */ 0x6D, 0x3E, 0x31, 0x3C, 0x2F, 0x50, 0x4D, 0x49, // m>1</PMI
+ /* 10E8 */ 0x50, 0x6F, 0x77, 0x65, 0x72, 0x50, 0x6D, 0x69, // PowerPmi
+ /* 10F0 */ 0x63, 0x4E, 0x75, 0x6D, 0x3E, 0x0A, 0x20, 0x20, // cNum>.
+ /* 10F8 */ 0x20, 0x20, 0x3C, 0x50, 0x4D, 0x49, 0x50, 0x6F, // <PMIPo
+ /* 1100 */ 0x77, 0x65, 0x72, 0x50, 0x6D, 0x69, 0x63, 0x4D, // werPmicM
+ /* 1108 */ 0x6F, 0x64, 0x65, 0x6C, 0x3E, 0x32, 0x31, 0x3C, // odel>21<
+ /* 1110 */ 0x2F, 0x50, 0x4D, 0x49, 0x50, 0x6F, 0x77, 0x65, // /PMIPowe
+ /* 1118 */ 0x72, 0x50, 0x6D, 0x69, 0x63, 0x4D, 0x6F, 0x64, // rPmicMod
+ /* 1120 */ 0x65, 0x6C, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, // el>.
+ /* 1128 */ 0x3C, 0x50, 0x4D, 0x49, 0x50, 0x6F, 0x77, 0x65, // <PMIPowe
+ /* 1130 */ 0x72, 0x43, 0x6F, 0x6E, 0x66, 0x69, 0x67, 0x3E, // rConfig>
+ /* 1138 */ 0x31, 0x3C, 0x2F, 0x50, 0x4D, 0x49, 0x50, 0x6F, // 1</PMIPo
+ /* 1140 */ 0x77, 0x65, 0x72, 0x43, 0x6F, 0x6E, 0x66, 0x69, // werConfi
+ /* 1148 */ 0x67, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // g>. <
+ /* 1150 */ 0x41, 0x64, 0x61, 0x70, 0x74, 0x69, 0x76, 0x65, // Adaptive
+ /* 1158 */ 0x42, 0x72, 0x69, 0x67, 0x68, 0x74, 0x6E, 0x65, // Brightne
+ /* 1160 */ 0x73, 0x73, 0x46, 0x65, 0x61, 0x74, 0x75, 0x72, // ssFeatur
+ /* 1168 */ 0x65, 0x3E, 0x31, 0x3C, 0x2F, 0x41, 0x64, 0x61, // e>1</Ada
+ /* 1170 */ 0x70, 0x74, 0x69, 0x76, 0x65, 0x42, 0x72, 0x69, // ptiveBri
+ /* 1178 */ 0x67, 0x68, 0x74, 0x6E, 0x65, 0x73, 0x73, 0x46, // ghtnessF
+ /* 1180 */ 0x65, 0x61, 0x74, 0x75, 0x72, 0x65, 0x3E, 0x0A, // eature>.
+ /* 1188 */ 0x20, 0x20, 0x20, 0x20, 0x3C, 0x43, 0x41, 0x42, // <CAB
+ /* 1190 */ 0x4C, 0x45, 0x6E, 0x61, 0x62, 0x6C, 0x65, 0x3E, // LEnable>
+ /* 1198 */ 0x54, 0x72, 0x75, 0x65, 0x3C, 0x2F, 0x43, 0x41, // True</CA
+ /* 11A0 */ 0x42, 0x4C, 0x45, 0x6E, 0x61, 0x62, 0x6C, 0x65, // BLEnable
+ /* 11A8 */ 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, 0x42, // >. <B
+ /* 11B0 */ 0x72, 0x69, 0x67, 0x68, 0x74, 0x6E, 0x65, 0x73, // rightnes
+ /* 11B8 */ 0x73, 0x4D, 0x69, 0x6E, 0x4C, 0x75, 0x6D, 0x69, // sMinLumi
+ /* 11C0 */ 0x6E, 0x61, 0x6E, 0x63, 0x65, 0x3E, 0x32, 0x30, // nance>20
+ /* 11C8 */ 0x30, 0x3C, 0x2F, 0x42, 0x72, 0x69, 0x67, 0x68, // 0</Brigh
+ /* 11D0 */ 0x74, 0x6E, 0x65, 0x73, 0x73, 0x4D, 0x69, 0x6E, // tnessMin
+ /* 11D8 */ 0x4C, 0x75, 0x6D, 0x69, 0x6E, 0x61, 0x6E, 0x63, // Luminanc
+ /* 11E0 */ 0x65, 0x3E, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x3C, // e>. <
+ /* 11E8 */ 0x42, 0x72, 0x69, 0x67, 0x68, 0x74, 0x6E, 0x65, // Brightne
+ /* 11F0 */ 0x73, 0x73, 0x4D, 0x61, 0x78, 0x4C, 0x75, 0x6D, // ssMaxLum
+ /* 11F8 */ 0x69, 0x6E, 0x61, 0x6E, 0x63, 0x65, 0x3E, 0x33, // inance>3
+ /* 1200 */ 0x31, 0x39, 0x39, 0x37, 0x30, 0x3C, 0x2F, 0x42, // 19970</B
+ /* 1208 */ 0x72, 0x69, 0x67, 0x68, 0x74, 0x6E, 0x65, 0x73, // rightnes
+ /* 1210 */ 0x73, 0x4D, 0x61, 0x78, 0x4C, 0x75, 0x6D, 0x69, // sMaxLumi
+ /* 1218 */ 0x6E, 0x61, 0x6E, 0x63, 0x65, 0x3E, 0x0A, 0x3C, // nance>.<
+ /* 1220 */ 0x2F, 0x47, 0x72, 0x6F, 0x75, 0x70, 0x3E, 0x0A, // /Group>.
+ /* 1228 */ 0x00 // .
+})
--- /dev/null
+//===========================================================================
+// <pep.asl>
+// DESCRIPTION
+// The PEP Device & Driver Related Configuration
+//
+//===========================================================================
+
+// Resources by area
+Include("../Common/pep_common.asl")
+Include("cust_camera_resources.asl")
+//Include("nfc_resources.asl") //NFC
+Include("cust_touch_resources.asl")
--- /dev/null
+Scope(\_SB.PILC)
+{
+ Method (_SUB) {
+ return(\_SB.PSUB)
+ }
+}
+
+Scope(\_SB.AMSS)
+{
+ Method (_SUB) {
+ return(\_SB.PSUB)
+ }
+}
+
+//Disabling SCSS
+Scope(\_SB.SCSS)
+{
+ Method(_STA, 0)
+ {
+ Return (Zero)
+ }
+}
+
+Scope(\_SB.CDSP)
+{
+ Method(_STA, 0)
+ {
+ Return (0x0F)
+ }
+}
+
+Scope(\_SB.ADSP)
+{
+ Method(_STA, 0)
+ {
+ Return (0x0F)
+ }
+}
-//
// This file contains the Power Management IC (PMIC)
// ACPI device definitions, configuration and look-up tables.
//
Include("cust_pmic_batt.asl")
+ // PMIC EIC
+ //Device (PEIC)
+ //{
+ // Name (_HID, "QCOM02D3")
+ // Alias(\_SB.PSUB, _SUB)
+ // Method (_CRS, 0x0, NotSerialized) {
+ // Name (RBUF, ResourceTemplate () {
+ // // SMB1380
+ // I2CSerialBus( 0x08, , 400000,AddressingMode7Bit, "\\_SB.IC11",,,,)
+ // })
+ // Return (RBUF)
+ // }
+ // Method (PMCF) {
+ // Name (CFG0,
+ // Package(){
+ // //Charger Info
+ // 0, // I2c Index - Resource Index
+ // 2, // Charger IC Type - PLAT_CONFIG_CHG_IC_SMB1380
+ // })
+ // Return (CFG0)
+ // }
+ //
+ // Method (_STA) {
+ // Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager
+ // }
+ //}
+
//
// PMIC Battery Manger Driver
//
Device (PMBT) {
Name (_HID, "QCOM0264")
- Name (_SUB, "RENEGA0E")
+ Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x2) {
\_SB_.PMIC,
\_SB_.ADC1,
0, //* 1: Error State Handling: 0- Don�t Shutdown, 1- Shutdown
1, //* 2: Listen to BatteryClass: 0- No 1- Yes
0, //* 3: Test Mode Power Flag: 0- Discharging, 1- PowerOnline+Charging
- "CUST_PMIC" //* 4: cust_pmic config identifier
+ "CUST_PMIC" //* 4: cust_pmic config identifier
})
- Store(CUST, Index(CFG0, 4))
+ Store(CUST, Index(CFG0, 4))
Return (CFG0)
}
Method (BTIM) {
Name (CFG0,
Package(){
- 30000, // Charging Heartbeat Timer
- 10000, // Charging Tolerable Delay
- 300000, // Discharging Heartbeat Timer
- 120000, // Discharging Tolerable Delay
- 0, // Poll Timer , 0=Timer not used.
- 0, // Poll Tolerable Delay
- 28080000, // Charging Timeout (TDone) Timer
- 0, // Charging Timeout(TDone) Tolerable Delay
+ 30000, // Charging Heartbeat Timer
+ 10000, // Charging Tolerable Delay
+ 300000, // Discharging Heartbeat Timer
+ 120000, // Discharging Tolerable Delay
+ 0, // Poll Timer , 0=Timer not used.
+ 0, // Poll Tolerable Delay
+ 28080000, //Charging Timeout (TDone) Timer
+ 0, //Charging Timeout(TDone) Tolerable Delay
})
Return (CFG0)
}
- //ACPI methods for Battery Info
+ //ACPI methods for Battery Info
Method (BBAT) {
Name (CFG0,
Package(){
- 1, //* 0: Battery Technology
- 0x4C494F4E, //* 1: Battery Chemistry: hex(LION)
+ 1, //* 0: Battery Technology
+ 0x4C494F4E, //* 1: Battery Chemistry: hex(LION)
0xFFFFFFFF, //* 2: BFCC: (mWh), Design Capacity
0xFFFFFFFF, //* 3: BFCC: (mWh), Full Charge Capacity
- 0xFFFFFFFF, //* 4: PCT1: (% of FCC), Default Alert 1
- 0xFFFFFFFF, //* 5: PCT2: (% of FCC), Default Alert 2
+ 0xFFFFFFFF, //* 4: PCT1: (% of FCC), Default Alert 1
+ 0xFFFFFFFF, //* 5: PCT2: (% of FCC), Default Alert 2
"QCOMBATT01", //* 6: Device Name
"Qualcomm", //* 7: Manufacture Name
"QCOMBAT01_07012011", //* 8: Battery Unique ID
- "07012011", //* 9: Battery Serial Number
+ "07012011", //* 9: Battery Serial Number
19, //* 10: Battery Manufacture Date
- 04, //* 11: Battery Manufacture Month
+ 04, //* 11: Battery Manufacture Month
2014 //* 12: Battery Manufacture Year
})
//Local2 = Default Alert1 = PCT1 * BFCC / 100
Return (CFG0)
}
- //ACPI methods for Proprietary chargers
+ //ACPI methods for Proprietary chargers
Method (BPCH) {
Name (CFG0,
Package(){
3000, // QC2.0 charger current = 3000mA
3000, // QC3.0 charger current = 3000mA
- 1500 // Invalid Wall charger current = 1500mA
+ 1500 // Invalid Wall charger current = 1500mA
})
Return (CFG0)
}
- //ACPI methods for foldback chargers
+ //ACPI methods for foldback chargers
Method (BFCH) {
Name (CFG0,
Package(){
Method (BCCC) {
Name (CFG0,
Package(){
- 1, //Enable coin cell charger; 1 = enable, 0 = disable
+ 1, //Enable coin cell charger; 1 = enable, 0 = disable
0, // RSET, 0=2K1, 1=1K7, 2=1K2, 3 = 0K8
0 // VSET, 0=2V5, 1=3V2, 2=3V1, 3=3V0
})
Return (CFG0)
}
- //ACPI methods for Recharge/Maintenance Mode
+ //ACPI methods for Recharge/Maintenance Mode
Method (BRCH) {
Name (CFG0,
Package(){
- 100, // Delta V Recharge threshold = 100mV
- 0 // Delta V Recharge Reduction below Normal= 0mV
+ 100, // Delta V Recharge threshold = 100mV
+ 0 // Delta V Recharge Reduction below Normal= 0mV
})
Return (CFG0)
}
- //ACPI methods for Qi Charging
+ //ACPI methods for Qi Charging
Method (_BQI) {
Name (CFG0,
Package(){
Method (BIRQ) {
Name (CFG0,
Package(){
- //"ChgError", // Charger Error
- //"BclIrq1", // IBAT greater than threshold IRQ
- //"BclIrq2", // VBAT less than threshold IRQ
- //"MEMIFaccess", // MEMIF access granted IRQ
- //"TccReached", // Termination Current IRQ
- //"ChargerInhibit" // Charger Inhibit IRQ
- "VbatLow", // VBAT LOW IRQ
- //"QiWlcDet", // Qi charging
- "BattMissing", // BATT_MISSING IRQ
- "AiclDone", // AICL Done
- //"UsbUv", // USB UV
- //"SOCFull", // SOC Full IRQ
- //"SOCEmpty", // SOC Empty IRQ
- //"FvCal", // FVCAl IRQ
- "JeitaLimit" // JEITA limit IRQ
+ //"ChgError", //Charger Error
+ //"BclIrq1", //IBAT greater than threshold IRQ
+ //"BclIrq2", // VBAT less than threshold IRQ
+ //"MEMIFaccess", //MEMIF access granted IRQ
+ //"TccReached", // Termination Current IRQ
+ // "ChargerInhibit" // Charger Inhibit IRQ
+ "VbatLow", // VBAT LOW IRQ
+ //"QiWlcDet", // Qi charging
+ "BattMissing", // BATT_MISSING IRQ
+ "AiclDone", // AICL Done
+ // "UsbUv", //USB UV
+ //"SOCFull", //SOC Full IRQ
+ //"SOCEmpty", //SOC Empty IRQ
+ //"FvCal", //FVCAl IRQ
+ "JeitaLimit" //JEITA limit IRQ
})
Return (CFG0)
}
0xFFFFFFFF, //* 2: VLOW: (mV), Low Battery Voltage
0xFFFFFFFF, //* 3: EMPT: (mV), VcutOff
0xFFFFFFFF, //* 4: DCMA: (mA), DC Current
- 1, //* 5: ChargePath Priority: Select 0 for DC, 1 for USB
+ 1, //* 5: ChargePath Priority: Select 0 for DC, 1 for USB
50, //* 6: RSLOW for maxFlashCurrentPrediction
50, //* 7: RPARA for maxFlashCurrentPrediction
5000, //* 8: VINFLASH for maxFlashCurrentPrediction
8, //* 9: FlashParam for maxFlashCurrentPrediction
- 1, //* 10: AFP Mode Supported
- 80, //* 11: AFP Trigger Max Battery Temp (+80 deg C)
- 0xFFFFFFEC, //* 12: AFP Trigger Min Battery Temp (-20 deg C)
+ 1, //* 10: AFP Mode Supported
+ 80, //* 11: AFP Trigger Max Battery Temp (+80 deg C)
+ 0xFFFFFFEC, //* 12: AFP Trigger Min Battery Temp (-20 deg C)
72, //* 13: Watchdog timer in secs
100, //* 14: Charger iterm 100 mA for now
- 30, //* 15: SRAM logging timer
- 5, //* 16: VBATT average Window Size
+ 30, //* 15: SRAM logging timer
+ 5, //* 16: VBATT average Window Size
6, //* 17: Emergency Shutdown Initial SOC
500, //* 18: SoC convergent point
126, //* 19: LM_Threshold
750, //* 22: soc (75%) below which no soc linearization even in CV charging
1, //* 23: BMD - Battery Missing Detection Source when source is attached: BATT_ID (1=BATT_ID, 4=HW Misssing Algorithm)
2, //* 24: ibat src sensing : 0 for batfet and 1 for external sensing
- 50, //* 25: IFGD: (mA), FG Iterm delta; (iterm + this value) determines when FG report 100%
- 10, //* 26: VFGD: (mV), CC to CV Vdelta; (Vfloat - this value) determine when FG report 100%
- 1, //* 27: 0 - disable SOC linearization; 1 (nonzero): enable SOC linearization
- 0xFFFFFFEC, //* 28: (Celcius), Temperature threshold do have different SOC slope limiter
- 10, //* 29: (milli%) - SOC slope limiter when charging and at lower temperature than threshold
- 10, //* 30: (milli%) - SOC slope limiter when charging and at higher temperature than threshold
- 10, //* 31: (milli%) - SOC slope limiter when discharging and at lower temperature than threshold
- 10, //* 32: (milli%) - SOC slope limiter when discharging and at higher temperature than threshold
+ 50, //* 25: IFGD: (mA), FG Iterm delta; (iterm + this value) determines when FG report 100%
+ 10, //* 26: VFGD: (mV), CC to CV Vdelta; (Vfloat - this value) determine when FG report 100%
+ 1, //* 27: 0 - disable SOC linearization; 1 (nonzero): enable SOC linearization
+ 0xFFFFFFEC, //* 28: (Celcius), Temperature threshold do have different SOC slope limiter
+ 10, //* 29: (milli%) - SOC slope limiter when charging and at lower temperature than threshold
+ 10, //* 30: (milli%) - SOC slope limiter when charging and at higher temperature than threshold
+ 10, //* 31: (milli%) - SOC slope limiter when discharging and at lower temperature than threshold
+ 10, //* 32: (milli%) - SOC slope limiter when discharging and at higher temperature than threshold
1, //* 33: 0 - disable FCC learning; 1 (nonzero): enable FCC leearning
150, //* 34: maximum starting SOC (in tenth percent)at which FCC learning would be turned on during charging
100, //* 35: maximum allowable decrement (in tenth percent) of battery capacity in FCC learning
// Notes: used in Method(BJTA) & Method (BAT1)
//*****************************************************
Name (BCT1, Package(){
- 4350, //* 0: VDD1: (mV), Float Voltage (FV)
- 2100, //* 1: FCC1: (mA), Full Charge Current (FCC)
- 0, //* 2: HCLI: (C) hard cold limit - at which temperature charging will be disabled
- 10, //* 3: SCLI: (C) soft cold limit - at which temperature charge current/float voltage will be reduced to JEITA compensated value
- 45, //* 4: SHLI: (C) soft hot limit - at which temperature float voltage/charge current will be reduced to JEITA compensated value
- 55, //* 5: HHLI: (C) hard hot limit - at which temperature charging will be disabled
- 105, //* 6: FVC1: (mV) Float Voltage compensation (amount of FV reduction) when in battery hot-soft limit
- 0, //* 7: (mV) Float Voltage compensation (amount of FV reduction) when in battery cold-soft limit
- //* notes: put 0 value to disable
- //* These values (10 vs 11) should be the same when HW JEITA is enabled
- 0, //* 8: (mA) Charge Current compensation (amount of CC reduction) when in battery hot-soft limit
- 1000, //* 9: CCC1: (mA) Charge Current compensation (amount of CC reduction) when in battery cold-soft limit
- //* notes: put 0 value to disable
- //* These values (12 vs 13) should be the same when HW JEITA is enabled
- })
+ 4350, //* 0: VDD1: (mV), Float Voltage (FV)
+ 2100, //* 1: FCC1: (mA), Full Charge Current (FCC)
+ 0, //* 2: HCLI: (C) hard cold limit - at which temperature charging will be disabled
+ 10, //* 3: SCLI: (C) soft cold limit - at which temperature charge current/float voltage will be reduced to JEITA compensated value
+ 45, //* 4: SHLI: (C) soft hot limit - at which temperature float voltage/charge current will be reduced to JEITA compensated value
+ 55, //* 5: HHLI: (C) hard hot limit - at which temperature charging will be disabled
+ 105, //* 6: FVC1: (mV) Float Voltage compensation (amount of FV reduction) when in battery hot-soft limit
+ 0, //* 7: (mV) Float Voltage compensation (amount of FV reduction) when in battery cold-soft limit
+ //* notes: put 0 value to disable
+ //* These values (10 vs 11) should be the same when HW JEITA is enabled
+ 0, //* 8: (mA) Charge Current compensation (amount of CC reduction) when in battery hot-soft limit
+ 1000, //* 9: CCC1: (mA) Charge Current compensation (amount of CC reduction) when in battery cold-soft limit
+ //* notes: put 0 value to disable
+ //* These values (12 vs 13) should be the same when HW JEITA is enabled
+ })
//ACPI methods for JEITA
Method (BJTA) {
Name (CFG0,
Package(){
- 2, //* 0: Select JEITA Configuration: 0- No JEITA, 1- SW JEITA, 2- HW JEITA
- 2, //* 1: Temperature Hysteresis (in deg C)
- Package(0xa){0,0,0,0,0,0,0,0,0,0}
- //* 2: Structure for default charge table
- })
+ 2, //* 0: Select JEITA Configuration: 0- No JEITA, 1- SW JEITA, 2- HW JEITA
+ 2, //* 1: Temperature Hysteresis (in deg C)
+ Package(0xa){0,0,0,0,0,0,0,0,0,0}
+ //* 2: Structure for default charge table
+ })
Store(VDD1, Index(\_SB_.PMBT.BCT1, 0))
Store(FCC1, Index(\_SB_.PMBT.BCT1, 1))
Store(HCLI, Index(\_SB_.PMBT.BCT1, 2))
{
Name (CFG0,
Package(){
- 0, //* 0: Battery Category: 0-NORMAL, 1-SMART
- 0xFFFFFFEC, //* 1: min operating battery temp (-20 deg C)
- 65, //* 2: max operating battery temp (+65 deg C)
+ 0, //* 0: Battery Category: 0-NORMAL, 1-SMART
+ 0xFFFFFFEC, //* 1: min operating battery temp (-20 deg C)
+ 65, //* 2: max operating battery temp (+65 deg C)
Package(4){0,0,0,0}, //* 3: 128-bit battery info for future expansion
Package(0xa){0,0,0,0,0,0,0,0,0,0}
//* 4: Structure for charge table
})
//assign Charge Table to BCT1
- //Notes: 1) If the default charge table and desire charge table are different,
- // Create another table (ex: BCT2) with the same structure as BCT1 and modify BCT1 below with the new table name
+ //Notes: 1) If the default charge table and desire charge table are different,
+ // Create another table (ex: BCT2) with the same structure as BCT1 and modify BCT1 below with the new table name
// 2) Method(BJTA) is parsed before this(BAT1) method in Battmngr module
// Method(BJTA) may be updating BCT1 parameters using configuration from cust_pmic_batt.asl (refer to BJTA method details)
// If BAT1 desires different value to be used (than what used in BJTA), pls change/update relevant parameter(s) here.
{
//Actions for Battery Error Handling
// 0x0 - Do Nothing
- // 0x1 - Reload Charge Table
+ // 0x1 - Reload Charge Table
// 0x2 - Error Shutdown
// 0x4 - Emergency Shutdown
// 0x8 - Enter Test Mode
Name (CFG0,
Package(){
- 1, // 1-Feature Enable, 0-Feature Disable
+ 1, //1-Feature Enable, 0-Feature Disable
0x8, //Action(s) for DEBUG state -> Enter Test Mode
0x1, //Action(s) for NORMAL state -> Reload Charge Table
0x0, //Action(s) for SMART_AUTHENTICATED state -> Do nothing
{
Name (CFG0,
Package(){
- 2000, //* 0: min RID for DEBUG category: 2K
- 14000, //* 1: max RID for DEBUG category: 14K
- 0xFFFFFFFF, //* 2: RID2: min RID for NORMAL category: 15K
- 0xFFFFFFFF, //* 3: RID3: max RID for NORMAL category: 140K
- 240000, //* 4: min RID for SMART category: 240K
- 450000, //* 5: max RID for SMART category: 450K
- 1, //* 6: Number of charging table
+ 2000, //* 0: min RID for DEBUG category: 2K
+ 14000, //* 1: max RID for DEBUG category: 14K
+ 0xFFFFFFFF, //* 2: RID2: min RID for NORMAL category: 15K
+ 0xFFFFFFFF, //* 3: RID3: max RID for NORMAL category: 140K
+ 240000, //* 4: min RID for SMART category: 240K
+ 450000, //* 5: max RID for SMART category: 450K
+ 1, //* 6: Number of charging table
})
Store(RID2, Index(CFG0, 2))
Store(RID3, Index(CFG0, 3))
50, //* 4: (%) Slave Charger Initial Power Distribution
60, //* 5: (mV) Slave Charger Float Voltage Headroom
500, //* 6: (mA) Slave Charger Charge Current Done Threshold
- 90, //* 7: Slave Charger Minimum Efficiency
+ 90, //* 7: Slave Charger Minimum Efficiency
0, //* 8: Slave Charger HW ID. 0: SMB1380/1
70, //* 9: (%)Slave Charger Max Power Distribution: 70%
0, //* 10: (%)Slave Charger Min Power Distribution: 0%
Package(0x4)//* 11: Thermal Balancing Configuration
{
- 5, //11.1: (C)Temperature Difference to trigger thermal balancing. 0 to disable the feature
- 5, //11.2: (%)Step to redistrubute the power
- 120, //11.3: (Sec)Minimum Wait Time for each redistribution attempt
- 5, //11.4: (C)Temperature Margin for Master Charger
+ 5, //11.1: (C)Temperature Difference to trigger thermal balancing. 0 to disable the feature
+ 5, //11.2: (%)Step to redistrubute the power
+ 120, //11.3: (Sec)Minimum Wait Time for each redistribution attempt
+ 5, //11.4: (C)Temperature Margin for Master Charger
}
})
Return (CFG0)
//
Device (PMBM) {
Name (_HID, "QCOM0263")
- Name (_SUB, "RENEGA0E")
+ Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x1)
{
\_SB_.PMBT
Return (RBUF)
}
- Method (_STA) {
+ Method (_STA) {
Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager
}
}
//
Device (BCL1) {
Name (_HID, "QCOM02D6")
- Name (_SUB, "RENEGA0E")
+ Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x1)
{
\_SB_.PMIC
Name (CFG0,
Package(){
3, //* FGBCL ACPI revision
- 7, //* 0: BCL disabled, 1: vph_pwr bcl enabled, 2: fg vbatt enabled, 4: fg ibatt enabled
+ 7, //* 0: BCL disabled, 1: vph_pwr bcl enabled, 2: fg vbatt enabled, 4: fg ibatt enabled
5000, //* battery ocp current
80, //* ibatt high threshold is set to 80 for 80% of OCP
90, //* ibatt too high is set to 90 for 90% of OCP
3200, //* vcomp_low0 threshold is 3200 mv
2750, //* vcomp_low1 threshold is 2750 mv
2500, //* vcomp_low2 threshold is 2500 mV
- 10, //* poll timer for battery soc polling.
+ 10, //* poll timer for battery soc polling.
1, //* 1- enable battery percent notification. 0-disable battery percent notification
2000, //* debug board Min battery ID in Ohm
14000 //* debug board Max battery ID in Ohm
Method (BCLQ) {
Name (CFG0,
Package(){
- "VCOMP_LOW0", // vcomp_low0 IRQ
- "VCOMP_LOW1", // vcomp_low1 IRQ
- "VCOMP_LOW2", // vcomp_low2 IRQ
- "VCOMP_HI", // vcomp_hi IRQ
- //"SYS_OK", // sys_ok irq
- //"LVL0_PLM", // LVL0_PLM IRQ
- //"LVL1_PLM" // LVL1_PLM IRQ
- //"LVL2_PLM", // LVL2_PLM IRQ
- "BAN_ALARM", // BAN_ALARM IRQ
- "IBATT_HI", // IBATT HIGH IRQ
- "IBATT_THI", // IBATT TOO HIGH IRQ
- "VBATT_LOW", // VBATT_LOW IRQ
- "VBATT_TLOW", // VBATT TOO LOW IRQ
- "MSOC_LOW", // monotonic soc low IRQ
- "MSOC_HI", // monotonic soc high IRQ
- "LMH_LVL0", // LMH_LVL0 IRQ
- "LMH_LVL1", // LMH_LVL1 IRQ
- "LMH_LVL2", // LMH_LVL2 IRQ
+ "VCOMP_LOW0", //vcomp_low0 IRQ
+ "VCOMP_LOW1", //vcomp_low1 IRQ
+ "VCOMP_LOW2", //vcomp_low2 IRQ
+ "VCOMP_HI", //vcomp_hi IRQ
+ //"SYS_OK", // sys_ok irq
+ //"LVL0_PLM", // LVL0_PLM IRQ
+ //"LVL1_PLM" // LVL1_PLM IRQ
+ //"LVL2_PLM", //LVL2_PLM IRQ
+ "BAN_ALARM", // BAN_ALARM IRQ
+ "IBATT_HI", // IBATT HIGH IRQ
+ "IBATT_THI", // IBATT TOO HIGH IRQ
+ "VBATT_LOW", // VBATT_LOW IRQ
+ "VBATT_TLOW", // VBATT TOO LOW IRQ
+ "MSOC_LOW", //monotonic soc low IRQ
+ "MSOC_HI", //monotonic soc high IRQ
+ "LMH_LVL0", //LMH_LVL0 IRQ
+ "LMH_LVL1", //LMH_LVL1 IRQ
+ "LMH_LVL2", //LMH_LVL2 IRQ
})
Return (CFG0)
}
Device(PTCC)
{
Name (_HID, "QCOM02E6")
- Name (_SUB, "RENEGA0E")
+ Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x1) {\_SB_.PMIC})
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate () {
--- /dev/null
+\r
+ // SPI1 - EPM\r
+ //\r
+ Device (SPI1)\r
+ {\r
+ Name (_HID, "QCOM021E")\r
+ Alias(\_SB.PSUB, _SUB)\r
+ Name (_UID, 1)\r
+ Name (_DEP, Package(){\_SB_.PEP0, \_SB_.BAM3})\r
+ Name (_CCA, 0)\r
+\r
+ Method (_CRS)\r
+ {\r
+ Name (RBUF, ResourceTemplate()\r
+ {\r
+\r
+ Memory32Fixed(ReadWrite, 0xf9923000, 0x00000800)\r
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {127}\r
+ })\r
+ Return (RBUF)\r
+ }\r
+ Method (FNOC)\r
+ {\r
+ Name(RBUF, Buffer()\r
+ {\r
+ 0x01, // Controller Number\r
+ 0x00, // BamBaseAddress\r
+ 0x40, // BamBaseAddress\r
+ 0x90, // BamBaseAddress\r
+ 0xf9, // BamBaseAddress\r
+ 0x0d, // Input Pipe\r
+ 0x0c, // Output Pipe\r
+ 0x00, // Threshold\r
+ 0x01 // Threshold\r
+ })\r
+ Return (RBUF)\r
+ }\r
+ }\r
} // UCP0
//Dummy device to allow KDNET on 2ndary port debugger registration
-Device (USB1)
-{
- Name (_DEP, Package(0x1)
- {
- \_SB_.PEP0
- })
- Name (_HID, "QCOM02BA") // QCOM02BA
- Name (_UID, 1)
+// Device (USB1)
+// {
+// Name (_DEP, Package(0x1)
+// {
+// \_SB_.PEP0
+// })
+// Name (_HID, "QCOM02BA") // QCOM02BA
+// Name (_UID, 1)
- //set device status as not present, disabled, not shown in UI, not functioning properly
- Name(STVL, 0x0)
+// //set device status as not present, disabled, not shown in UI, not functioning properly
+// Name(STVL, 0x0)
- Method (_STA) {
- Return (STVL) // return the current device status
- }
-} // USB1
+// Method (_STA) {
+// Return (STVL) // return the current device status
+// }
+// } // USB1
//
// USB Type-C Audio Driver
//
-Device (USBA)
-{
- Name (_DEP, Package(0x1)
- {
- \_SB_.IMM0
- })
- Name (_HID, "QCOM0300")
- Alias(\_SB.PSUB, _SUB)
-}
+// Device (USBA)
+// {
+// Name (_DEP, Package(0x1)
+// {
+// \_SB_.IMM0
+// })
+// Name (_HID, "QCOM0300")
+// Alias(\_SB.PSUB, _SUB)
+// }
-Name(DPP1, Buffer(){0x0})
//URS1 specific
/*
// Shared memory
Memory32Fixed (ReadWrite, 0x18800000, 0x800000) //CE registers
Memory32Fixed (ReadWrite, 0xC250000, 0x10) //WCSSAON registers
- Memory32Fixed (ReadWrite, 0x8C400000, 0x100000) //MSA image address
+ Memory32Fixed (ReadWrite, 0x8E300000, 0x100000) //MSA image address
// CE interrupts
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {446} //CE0 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {447} //CE1 interrupt
})
}
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ }
+
+ Method (_PS2, 0, NotSerialized) // _PS2: Power State 2
+ {
+ }
+
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ }
+
+ OperationRegion (WOPR, 0x80, Zero, 0x10)
+ Field (WOPR, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ WTRG, 32
+ }
+
PowerResource(WRST, 0x5, 0x0)
{
//
}
Method(_RST, 0x0, NotSerialized)
{
+ WTRG = 0xABCD
}
}
}
--- /dev/null
+//WLAN_11ad driver ACPI Enumeration
+
+Method(_STA, 0)
+{
+ Return (0xF)
+}
+++ /dev/null
-/*============================================================================
- FILE: adc.asl
-
- OVERVIEW: This file contains the board-specific configuration info for
- ADC1 - qcadc analog-to-digital converter (ADC): ACPI device
- definitions, common settings, etc.
-
- DEPENDENCIES: None
-
-============================================================================*/
-/*----------------------------------------------------------------------------
- * QCADC
- * -------------------------------------------------------------------------*/
-
-Device(ADC1)
-{
- /*----------------------------------------------------------------------------
- * Dependencies
- * -------------------------------------------------------------------------*/
- Name(_DEP, Package(0x2)
- {
- \_SB_.SPMI,
- \_SB_.PMIC
- })
-
- /*----------------------------------------------------------------------------
- * HID
- * -------------------------------------------------------------------------*/
- Name(_HID, "QCOM0221")
- Alias(\_SB.PSUB, _SUB)
- Name(_UID, 0)
-
- /*----------------------------------------------------------------------------
- * ADC Resources
- * -------------------------------------------------------------------------*/
- Method(_CRS)
- {
- /*
- * Interrupts
- */
- Name (INTB, ResourceTemplate()
- {
- // VAdc - EOC
- // ID = {slave id}{perph id}{int} = {0}{0011 0001}{000} = 0x188
- GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {32} // 0x188 - PM_INT__VADC_HC1_USR__EOC
-
- // VAdc TM - All interrupts
- // ID = {slave id}{perph id}{int} = {0}{0011 0100}{000} = 0x1A0
- GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {40} // 0x1A0 - PM_INT__VADC_HC7_BTM__THR
-
- // FgAdc - All interrupts
- // ID = {slave id}{perph id}{int} = {10}{0100 0101}{000} = 0x1228
- GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {360} // 0x1228 - PM_INT__FG_ADC__BT_ID
- })
-
- /*
- * SPMI peripherals
- */
- Name(NAM, Buffer() {"\\_SB.SPMI"})
-
- // VAdc
- Name(VUSR, Buffer()
- {
- 0x8E, // SPB Descriptor
- 0x13, 0x00, // Length including NAM above
- 0x01, // +0x00 SPB Descriptor Revision
- 0x00, // +0x01 Resource Source Index
- 0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff
- 0x02, // +0x03 Consumer + controller initiated
- 0x00, 0x31, // +0x04 Type specific flags . Slave id, Upper8 bit address
- 0x01, // +0x06 Type specific revision
- 0x00, 0x00 // +0x07 type specific data length
- // +0x09 - 0xd bytes for NULL-terminated NAM
- // Length = 0x13
- })
-
- // VAdc TM
- Name(VBTM, Buffer()
- {
- 0x8E, // SPB Descriptor
- 0x13, 0x00, // Length including NAM above
- 0x01, // +0x00 SPB Descriptor Revision
- 0x00, // +0x01 Resource Source Index
- 0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff
- 0x02, // +0x03 Consumer + controller initiated
- 0x00, 0x34, // +0x04 Type specific flags . Slave id, Upper8 bit address
- 0x01, // +0x06 Type specific revision
- 0x00, 0x00 // +0x07 type specific data length
- // +0x09 - 0xd bytes for NULL-terminated NAM
- // Length = 0x13
- })
-
- // FgAdc
- Name(FGRR, Buffer()
- {
- 0x8E, // SPB Descriptor
- 0x13, 0x00, // Length including NAM above
- 0x01, // +0x00 SPB Descriptor Revision
- 0x00, // +0x01 Resource Source Index
- 0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff
- 0x02, // +0x03 Consumer + controller initiated
- 0x02, 0x45, // +0x04 Type specific flags . Slave id, Upper8 bit address
- 0x01, // +0x06 Type specific revision
- 0x00, 0x00 // +0x07 type specific data length
- // +0x09 - 0xd bytes for NULL-terminated NAM
- // Length = 0x13
- })
-
- // Name(END, Buffer() {0x79, 0x00})
-
- // {VUSR, NAM, VBTM, NAM, FGRR, NAM, INTB}
- // {Local1, Local2, Local3, INTB}
- // {Local4, Local5}
- // {Local0}
- Concatenate(VUSR, NAM, Local1)
- Concatenate(VBTM, NAM, Local2)
- Concatenate(FGRR, NAM, Local3)
- Concatenate(Local1, Local2, Local4)
- Concatenate(Local3, INTB, Local5)
- Concatenate(Local4, Local5, Local0)
-
- Return(Local0)
- }
-
- /*----------------------------------------------------------------------------
- * Device configuration
- * -------------------------------------------------------------------------*/
- /*
- * General ADC properties
- *
- * bHasVAdc:
- * Whether or not TM is supported.
- * 0 - Not supported
- * 1 - Supported
- *
- * bHasTM:
- * Whether or not TM is supported.
- * 0 - Not supported
- * 1 - Supported
- *
- * bHasFgAdc:
- * Whether or not FGADC is supported.
- * 0 - Not supported
- * 1 - Supported
- *
- */
- Method (ADDV)
- {
- Return (Package()
- {
- /* .bHasVAdc = */ 1,
- /* .bHasTM = */ 1,
- /* .bHasFgAdc = */ 1,
- })
- }
-
- /*----------------------------------------------------------------------------
- * Voltage ADC (VADC) Configuration
- * -------------------------------------------------------------------------*/
- /*
- * General VADC properties
- *
- * bUsesInterrupts:
- * End-of-conversion interrupt mode.
- * 0 - Polling mode
- * 1 - Interrupt mode
- *
- * uFullScale_code:
- * Full-scale ADC code.
- *
- * uFullScale_uV:
- * Full-scale ADC voltage in uV.
- *
- * uReadTimeout_us:
- * Timeout for reading ADC channels in us.
- *
- * uLDOSettlingTime_us:
- * LDO settling time in us.
- *
- * ucMasterID:
- * Master ID to send the interrupt to.
- *
- * ucPmicDevice:
- * PMIC which has the VAdc.
- *
- * usMinDigRev:
- * Minimum digital version <major> <minor>
- *
- * usMinAnaRev:
- * Minimum analog version <major> <minor>
- *
- * ucPerphType:
- * ADC peripheral type.
- *
- */
- Method (GENP)
- {
- Return (Package()
- {
- /* .bUsesInterrupts = */ 0,
- /* .uFullScale_code = */ 0x4000,
- /* .uFullScale_uV = */ 1875000,
- /* .uReadTimeout_us = */ 500000,
- /* .uLDOSettlingTime_us = */ 17,
- /* .ucMasterID = */ 0,
- /* .ucPmicDevice = */ 0,
- /* .usMinDigRev = */ 0x300,
- /* .usMinAnaRev = */ 0x100,
- /* .ucPerphType = */ 0x8,
- })
- }
-
- /*===========================================================================
-
- FUNCTION PTCF
-
- DESCRIPTION Scales the ADC result from millivolts to 0.001 degrees
- Celsius using the PMIC thermistor conversion equation.
-
- DEPENDENCIES None
-
- PARAMETERS Arg0 [in] ADC result data (uMicroVolts)
-
- RETURN VALUE Scaled result in mDegC
-
- SIDE EFFECTS None
-
- ===========================================================================*/
- Method (PTCF, 1)
- {
- /*
- * Divide by two to convert from microvolt reading to micro-Kelvin.
- *
- * Subtract 273160 to convert the temperature from Kelvin to
- * 0.001 degrees Celsius.
- */
- ShiftRight (Arg0, 1, Local0)
- Subtract (Local0, 273160, Local0)
- Return (Local0)
- }
-
- /*===========================================================================
-
- FUNCTION PTCI
-
- DESCRIPTION Inverse of PTCF - scaled PMIC temperature to microvolts.
-
- DEPENDENCIES None
-
- PARAMETERS Arg0 [in] temperature in mDegC
-
- RETURN VALUE ADC result data (uMicroVolts)
-
- SIDE EFFECTS None
-
- ===========================================================================*/
- Method (PTCI, 1)
- {
- Add (Arg0, 273160, Local0)
- ShiftLeft (Local0, 1, Local0)
- Return (Local0)
- }
-
- /*
- * VADC channel to GPIO mapping
- *
- */
- Method (VGIO)
- {
- Return (Package()
- {
- Package()
- {
- /* .GPIO = */ 8,
- /* .aucChannels = */ Buffer(){0x12, 0x32, 0x52, 0x72},
- },
-
- Package()
- {
- /* .GPIO = */ 9,
- /* .aucChannels = */ Buffer(){0x13, 0x33, 0x53, 0x73},
- },
-
- Package()
- {
- /* .GPIO = */ 10,
- /* .aucChannels = */ Buffer(){0x14, 0x34, 0x54, 0x74},
- },
-
- Package()
- {
- /* .GPIO = */ 11,
- /* .aucChannels = */ Buffer(){0x15, 0x35, 0x55, 0x75},
- },
-
- Package()
- {
- /* .GPIO = */ 12,
- /* .aucChannels = */ Buffer(){0x16, 0x36, 0x56, 0x76},
- },
-
- Package()
- {
- /* .GPIO = */ 21,
- /* .aucChannels = */ Buffer(){0x17, 0x37, 0x57, 0x77, 0x97},
- },
-
- Package()
- {
- /* .GPIO = */ 22,
- /* .aucChannels = */ Buffer(){0x18, 0x38, 0x58, 0x78, 0x98},
- },
-
- Package()
- {
- /* .GPIO = */ 23,
- /* .aucChannels = */ Buffer(){0x19, 0x39, 0x59, 0x79, 0x99},
- },
- })
- }
-
- /*----------------------------------------------------------------------------
- * Voltage ADC Threshold Monitor (VADCTM) Configuration
- * -------------------------------------------------------------------------*/
- /*
- * General VADCTM properties
- *
- * eAverageMode:
- * Obtains N ADC readings and averages them together.
- * 0 - VADCTM_AVERAGE_1_SAMPLE
- * 1 - VADCTM_AVERAGE_2_SAMPLES
- * 2 - VADCTM_AVERAGE_4_SAMPLES
- * 3 - VADCTM_AVERAGE_8_SAMPLES
- * 4 - VADCTM_AVERAGE_16_SAMPLES
- *
- * eDecimationRatio:
- * The decimation ratio.
- * 0 - VADCTM_DECIMATION_RATIO_256
- * 1 - VADCTM_DECIMATION_RATIO_512
- * 2 - VADCTM_DECIMATION_RATIO_1024
- *
- * uFullScale_code:
- * Full-scale ADC code.
- *
- * uFullScale_uV:
- * Full-scale ADC voltage in uV.
- *
- * ucMasterID:
- * Master ID to send the interrupt to.
- *
- * ucPmicDevice:
- * PMIC which has the VAdc.
- *
- * usMinDigRev:
- * Minimum digital version <major> <minor>
- *
- * usMinAnaRev:
- * Minimum analog version <major> <minor>
- *
- * ucPerphType:
- * ADC peripheral type.
- *
- */
- Method (VTGN)
- {
- Return (Package()
- {
- /* .eAverageMode = */ 2,
- /* .eDecimationRatio = */ 2,
- /* .uFullScale_code = */ 0x4000,
- /* .uFullScale_uV = */ 1875000,
- /* .ucMasterID = */ 0,
- /* .ucPmicDevice = */ 0,
- /* .usMinDigRev = */ 0x300,
- /* .usMinAnaRev = */ 0x100,
- /* .ucPerphType = */ 0x8,
- })
- }
-
- /*----------------------------------------------------------------------------
- * Fuel Gauge ADC (FGADC) Configuration
- * -------------------------------------------------------------------------*/
- /*
- * General FGADC properties
- *
- * skinTempThreshRange:
- * Range for skin temperature thresholds
- *
- * chgTempThreshRange:
- * Range for charger temperature thresholds
- *
- * uFullScale_code:
- * Full scale ADC value in code.
- *
- * uFullScale_uV:
- * Full scale ADC value in microvolts.
- *
- * uMicroVoltsPerMilliAmps:
- * Microvolts per milliamp scaling factor.
- *
- * uCodePerKelvin:
- * Code per Kelvin scaling factor.
- *
- * uBattIdClipThresh:
- * Max code for a BATT ID channel.
- *
- * uMaxWaitTimeus:
- * Maximum time to wait for a reading to complete in microseconds.
- *
- * uSlaveId:
- * PMIC slave ID.
- *
- * ucPmicDevice:
- * PMIC which has the VAdc.
- *
- * ucPerphType:
- * ADC peripheral type.
- *
- */
- Method (GENF)
- {
- Return (Package()
- {
- /* .skinTempThreshRange.nMin = */ 0xFFFFFFE2, // -30
- /* .skinTempThreshRange.nMax = */ 97,
- /* .chgTempThreshRange.nMin = */ 0xFFFFFFCE, // -50
- /* .chgTempThreshRange.nMax = */ 160,
- /* .uFullScale_code = */ 0x3ff,
- /* .uFullScale_uV = */ 2500000,
- /* .uMicroVoltsPerMilliAmps = */ 500,
- /* .uCodePerKelvin = */ 4,
- /* .uBattIdClipThresh = */ 820,
- /* .uMaxWaitTimeUs = */ 5000000,
- /* .uSlaveId = */ 2,
- /* .ucPmicDevice = */ 1,
- /* .ucPerphType = */ 0xD,
- })
- }
-
- /*
- * FGADC Channel Configuration Table
- *
- * The following table is the list of channels the FGADC can read. Below is
- * a description of each field:
- *
- * sName:
- * Appropriate string name for the channel from AdcInputs.h.
- *
- * eChannel:
- * Which channel.
- * 0 - FGADC_CHAN_SKIN_TEMP
- * 1 - FGADC_CHAN_BATT_ID
- * 2 - FGADC_CHAN_BATT_ID_FRESH
- * 3 - FGADC_CHAN_BATT_ID_5
- * 4 - FGADC_CHAN_BATT_ID_15
- * 5 - FGADC_CHAN_BATT_ID_150
- * 6 - FGADC_CHAN_BATT_THERM
- * 7 - FGADC_CHAN_AUX_THERM
- * 8 - FGADC_CHAN_USB_IN_V
- * 9 - FGADC_CHAN_USB_IN_I
- * 10 - FGADC_CHAN_DC_IN_V
- * 11 - FGADC_CHAN_DC_IN_I
- * 12 - FGADC_CHAN_DIE_TEMP
- * 13 - FGADC_CHAN_CHARGER_TEMP
- * 14 - FGADC_CHAN_GPIO
- *
- * eEnable:
- * Whether or not to enable the channel.
- * 0 - FGADC_DISABLE
- * 1 - FGADC_ENABLE
- *
- * ucTriggers:
- * Mask of triggers. Use 0x0 for default trigger configuration.
- *
- * scalingFactor.num:
- * Numerator of the channel scaling
- *
- * scalingFactor.den:
- * Denominator of the channel scaling
- *
- * eScaling:
- * The scaling method to use.
- * 0 - FGADC_SCALE_TO_MILLIVOLTS
- * 1 - FGADC_SCALE_BATT_ID_TO_OHMS
- * 2 - FGADC_SCALE_INTERPOLATE_FROM_MILLIVOLTS (requires uInterpolationTableName)
- * 3 - FGADC_SCALE_THERMISTOR
- * 4 - FGADC_SCALE_CURRENT_TO_MILLIAMPS
- *
- * uInterpolationTableName:
- * The name of the lookup table in ACPI that will be interpolated to obtain
- * a physical value. Note that the physical value (which has default units
- * of millivolts unless custom scaling function is used) is passed as the
- * input. This value corresponds to the first column of the table. The
- * scaled output appears in the physical adc result.
- * 0 - No interpolation table
- * WXYZ - Where 'WXYZ' is the interpolation table name
- *
- */
- Method (FCHN)
- {
- Return (Package()
- {
- /* BATT_ID_OHMS (BATT_ID pin) */
- Package()
- {
- /* .sName = */ "BATT_ID_OHMS",
- /* .eChannel = */ 1,
- /* .eEnable = */ 1,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScaling = */ 1,
- /* .uInterpolationTableName = */ 0,
- },
-
- /* BATT_ID_OHMS_FRESH (BATT_ID pin) */
- Package()
- {
- /* .sName = */ "BATT_ID_OHMS_FRESH",
- /* .eChannel = */ 2,
- /* .eEnable = */ 1,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScaling = */ 1,
- /* .uInterpolationTableName = */ 0,
- },
-
- /* BATT_THERM (BATT_THERM pin) */
- Package()
- {
- /* .sName = */ "BATT_THERM",
- /* .eChannel = */ 6,
- /* .eEnable = */ 1,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScaling = */ 3,
- /* .uInterpolationTableName = */ 0,
- },
-
- /* AUX_THERM (AUX_THERM pin) */
- Package()
- {
- /* .sName = */ "AUX_THERM",
- /* .eChannel = */ 7,
- /* .eEnable = */ 1,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScaling = */ 3,
- /* .uInterpolationTableName = */ 0,
- },
-
- /* SKIN_THERM (AUX_THERM pin) */
- Package()
- {
- /* .sName = */ "SKIN_THERM",
- /* .eChannel = */ 0,
- /* .eEnable = */ 1,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScaling = */ 3,
- /* .uInterpolationTableName = */ 0,
- },
-
- /* PMIC_TEMP2 (internal sensor) */
- Package()
- {
- /* .sName = */ "PMIC_TEMP2",
- /* .eChannel = */ 12,
- /* .eEnable = */ 1,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 3,
- /* .scalingFactor.den = */ 2,
- /* .eScaling = */ 2,
- /* .uInterpolationTableName = */ FGDT,
- },
-
- /* CHG_TEMP (internal sensor) */
- Package()
- {
- /* .sName = */ "CHG_TEMP",
- /* .eChannel = */ 13,
- /* .eEnable = */ 1,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 3,
- /* .scalingFactor.den = */ 2,
- /* .eScaling = */ 2,
- /* .uInterpolationTableName = */ FGCT,
- },
-
- /* USB_IN (USB_IN pin) */
- Package()
- {
- /* .sName = */ "USB_IN",
- /* .eChannel = */ 8,
- /* .eEnable = */ 1,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 8,
- /* .eScaling = */ 0,
- /* .uInterpolationTableName = */ 0,
- },
-
- /* USB_IN_I (USB_IN pin) */
- Package()
- {
- /* .sName = */ "USB_IN_I",
- /* .eChannel = */ 9,
- /* .eEnable = */ 1,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScaling = */ 4,
- /* .uInterpolationTableName = */ 0,
- },
-
- /* DC_IN (DC_IN pin) */
- Package()
- {
- /* .sName = */ "DC_IN",
- /* .eChannel = */ 10,
- /* .eEnable = */ 1,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 8,
- /* .eScaling = */ 0,
- /* .uInterpolationTableName = */ 0,
- },
-
- /* DC_IN_I (DC_IN pin) */
- Package()
- {
- /* .sName = */ "DC_IN_I",
- /* .eChannel = */ 11,
- /* .eEnable = */ 1,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScaling = */ 4,
- /* .uInterpolationTableName = */ 0,
- },
-
- /* FG_GPIO */
- Package()
- {
- /* .sName = */ "FG_GPIO",
- /* .eChannel = */ 14,
- /* .eEnable = */ 0,
- /* .ucTriggers = */ 0x0,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 2,
- /* .eScaling = */ 0,
- /* .uInterpolationTableName = */ 0,
- },
- })
- }
-
- /*
- * Die temperature sensor scaling table
- *
- * The first column in the table is sensor voltage in millivolts and the
- * second column is the temperature in milli degrees C.
- *
- * Scaling equation:
- *
- * milliDegC = (uV - 600000) / 2 + 25000
- *
- */
- Method (FGDT)
- {
- Return (Package()
- {
- Package(){ 450, 0xFFFF3CB0}, // -50000
- Package(){ 870, 160000}
- })
- }
-
- /*
- * NOTE: CHG_TEMP on PMI8998 uses fab-dependent scaling in the driver.
- * This is the default scaling if no fab-dependent scaling is found.
- * It corresponds to GF.
- */
- /*
- * Charger temperature sensor scaling table
- *
- * The first column in the table is sensor voltage in millivolts and the
- * second column is the temperature in milli degrees C.
- *
- * Scaling equation:
- *
- * milliDegC = (1303168 - uV) / 3.784 + 25000
- *
- */
- Method (FGCT)
- {
- Return (Package()
- {
- Package(){ 1587, 0xFFFF3CB0}, // -50000
- Package(){ 792, 160000}
- })
- }
-}
-
-Include("cust_adc.asl")
+++ /dev/null
-/*============================================================================
- FILE: cust_adc.asl
-
- OVERVIEW: This file contains the board-specific configuration info for
- ADC1 - qcadc analog-to-digital converter (ADC): channel
- configurations, scaling functions, look-up tables, etc.
-
- DEPENDENCIES: None
-
-============================================================================*/
-/*----------------------------------------------------------------------------
- * QCADC
- * -------------------------------------------------------------------------*/
-
-Scope(\_SB.ADC1)
-{
- /*----------------------------------------------------------------------------
- * Voltage ADC (VADC) Configuration
- * -------------------------------------------------------------------------*/
- /*
- * VADC Channel Configuration Table
- *
- * The following table is the list of channels the ADC can read. Channels may
- * be added or removed. Below is a description of each field:
- *
- * sName:
- * Appropriate string name for the channel from AdcInputs.h.
- *
- * uAdcHardwareChannel:
- * AMUX channel.
- *
- * eSettlingDelay:
- * Holdoff time to allow the voltage to settle before reading the channel.
- * 0 - VADC_SETTLING_DELAY_0_US
- * 1 - VADC_SETTLING_DELAY_100_US
- * 2 - VADC_SETTLING_DELAY_200_US
- * 3 - VADC_SETTLING_DELAY_300_US
- * 4 - VADC_SETTLING_DELAY_400_US
- * 5 - VADC_SETTLING_DELAY_500_US
- * 6 - VADC_SETTLING_DELAY_600_US
- * 7 - VADC_SETTLING_DELAY_700_US
- * 8 - VADC_SETTLING_DELAY_800_US
- * 9 - VADC_SETTLING_DELAY_900_US
- * 10 - VADC_SETTLING_DELAY_1_MS
- * 11 - VADC_SETTLING_DELAY_2_MS
- * 12 - VADC_SETTLING_DELAY_4_MS
- * 13 - VADC_SETTLING_DELAY_6_MS
- * 14 - VADC_SETTLING_DELAY_8_MS
- * 15 - VADC_SETTLING_DELAY_10_MS
- *
- * eAverageMode:
- * Obtains N ADC readings and averages them together.
- * 0 - VADC_AVERAGE_1_SAMPLE
- * 1 - VADC_AVERAGE_2_SAMPLES
- * 2 - VADC_AVERAGE_4_SAMPLES
- * 3 - VADC_AVERAGE_8_SAMPLES
- * 4 - VADC_AVERAGE_16_SAMPLES
- *
- * eDecimationRatio:
- * The decimation ratio.
- * 0 - VADC_DECIMATION_RATIO_256
- * 1 - VADC_DECIMATION_RATIO_512
- * 2 - VADC_DECIMATION_RATIO_1024
- *
- * eCalMethod:
- * Calibration method.
- * 0 - VADC_CAL_METHOD_NO_CAL
- * 1 - VADC_CAL_METHOD_RATIOMETRIC
- * 2 - VADC_CAL_METHOD_ABSOLUTE
- *
- * scalingFactor.num:
- * Numerator of the channel scaling
- *
- * scalingFactor.den:
- * Denominator of the channel scaling
- *
- * eScalingMethod:
- * The scaling method to use.
- * 0 - VADC_SCALE_TO_MILLIVOLTS
- * 1 - VADC_SCALE_INTERPOLATE_FROM_MILLIVOLTS (requires uInterpolationTableName)
- * 2 - VADC_SCALE_THERMISTOR (requires uPullUp and uInterpolationTableName)
- *
- * uPullUp:
- * The pull up resistor value. Use with eScalingMethod == VADC_SCALE_THERMISTOR,
- * otherwise, 0.
- *
- * uInterpolationTableName:
- * The name of the lookup table in ACPI that will be interpolated to obtain
- * a physical value. Note that the physical value (which has default units
- * of millivolts unless custom scaling function is used) is passed as the
- * input. This value corresponds to the first column of the table. The
- * scaled output appears in the physical adc result.
- * 0 - No interpolation table
- * WXYZ - Where 'WXYZ' is the interpolation table name
- *
- * uScalingFunctionName:
- * The name of the function to call in the ACPI table to perform custom
- * scaling. The input to the custom scaling function is defined by
- * eScalingFunctionInput. The output of the custom scaling function is
- * the physical value.
- * 0 - No scaling function
- * WXYZ - Where 'WXYZ' is the scaling function name
- *
- * Note: if both a custon scaling function & interpolation table are used
- * the custom scaling function is called first.
- *
- * eScalingFunctionInput:
- * Defines which ADC result is passed to the custom scaling function.
- * 0 - VADC_SCALING_FUNCTION_INPUT_PHYSICAL
- * 1 - VADC_SCALING_FUNCTION_INPUT_PERCENT
- * 2 - VADC_SCALING_FUNCTION_INPUT_MICROVOLTS
- * 3 - VADC_SCALING_FUNCTION_INPUT_CODE
- *
- */
- Method (CHAN)
- {
- Return (Package()
- {
- /* VPH_PWR (VPH_PWR_SNS pin) */
- Package()
- {
- /* .sName = */ "VPH_PWR",
- /* .uAdcHardwareChannel = */ 0x83,
- /* .eSettlingDelay = */ 0,
- /* .eAverageMode = */ 0,
- /* .eDecimationRatio = */ 2,
- /* .eCalMethod = */ 2,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 3,
- /* .eScalingMethod = */ 0,
- /* .uPullUp = */ 0,
- /* .uInterpolationTableName = */ 0,
- /* .uScalingFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- },
-
- /* VCOIN (VCOIN pin) */
- Package()
- {
- /* .sName = */ "VCOIN",
- /* .uAdcHardwareChannel = */ 0x85,
- /* .eSettlingDelay = */ 0,
- /* .eAverageMode = */ 0,
- /* .eDecimationRatio = */ 2,
- /* .eCalMethod = */ 2,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 3,
- /* .eScalingMethod = */ 0,
- /* .uPullUp = */ 0,
- /* .uInterpolationTableName = */ 0,
- /* .uScalingFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- },
-
- /* PMIC_TEMP1 (internal sensor) */
- Package()
- {
- /* .sName = */ "PMIC_THERM",
- /* .uAdcHardwareChannel = */ 0x6,
- /* .eSettlingDelay = */ 0,
- /* .eAverageMode = */ 0,
- /* .eDecimationRatio = */ 2,
- /* .eCalMethod = */ 2,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 0,
- /* .uPullUp = */ 0,
- /* .uInterpolationTableName = */ 0,
- /* .uScalingFunctionName = */ PTCF,
- /* .eScalingFunctionInput = */ 2,
- },
-
- /* XO_THERM (XO_THERM pin) */
- Package()
- {
- /* .sName = */ "XO_THERM",
- /* .uAdcHardwareChannel = */ 0x4c,
- /* .eSettlingDelay = */ 8,
- /* .eAverageMode = */ 0,
- /* .eDecimationRatio = */ 2,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ XTTB,
- /* .uScalingFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- },
-
- /* XO_THERM_GPS (XO_THERM pin) */
- Package()
- {
- /* .sName = */ "XO_THERM_GPS",
- /* .uAdcHardwareChannel = */ 0x4c,
- /* .eSettlingDelay = */ 8,
- /* .eAverageMode = */ 2,
- /* .eDecimationRatio = */ 2,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ XTTB,
- /* .uScalingFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- },
-
- /* SYS_THERM1 (AMUX_1 pin) */
- Package()
- {
- /* .sName = */ "SYS_THERM1",
- /* .uAdcHardwareChannel = */ 0x4d,
- /* .eSettlingDelay = */ 1,
- /* .eAverageMode = */ 0,
- /* .eDecimationRatio = */ 2,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ SYTB,
- /* .uScalingFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- },
-
- /* SYS_THERM2 (AMUX_2 pin) */
- Package()
- {
- /* .sName = */ "SYS_THERM2",
- /* .uAdcHardwareChannel = */ 0x4e,
- /* .eSettlingDelay = */ 1,
- /* .eAverageMode = */ 0,
- /* .eDecimationRatio = */ 2,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ SYTB,
- /* .uScalingFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- },
-
- /* PA_THERM (AMUX_3 pin) */
- Package()
- {
- /* .sName = */ "PA_THERM",
- /* .uAdcHardwareChannel = */ 0x4f,
- /* .eSettlingDelay = */ 1,
- /* .eAverageMode = */ 0,
- /* .eDecimationRatio = */ 2,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ SYTB,
- /* .uScalingFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- },
-
- /* PA_THERM1 (AMUX_4 pin) */
- Package()
- {
- /* .sName = */ "PA_THERM1",
- /* .uAdcHardwareChannel = */ 0x50,
- /* .eSettlingDelay = */ 1,
- /* .eAverageMode = */ 0,
- /* .eDecimationRatio = */ 2,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ SYTB,
- /* .uScalingFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- },
-
- /* SYS_THERM3 (AMUX_5 pin) */
- Package()
- {
- /* .sName = */ "SYS_THERM3",
- /* .uAdcHardwareChannel = */ 0x51,
- /* .eSettlingDelay = */ 1,
- /* .eAverageMode = */ 0,
- /* .eDecimationRatio = */ 2,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ SYTB,
- /* .uScalingFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- },
- })
- }
-
- /*
- * System Thermistor Table
- *
- * The first column in the table is thermistor resistance R_T in ohms
- * and the second column is the temperature in degrees C.
- *
- * VDD ___
- * |
- * >
- * P_PU <
- * >
- * |
- * |
- * |- - - V_T
- * |
- * >
- * R_T < 100 kOhms (NTCG104EF104FB)
- * >
- * |
- * |
- * Gnd
- *
- */
- Method (SYTB)
- {
- Return (Package()
- {
- Package(){4251000, 0xFFFFFFD8}, // -40
- Package(){3004900, 0xFFFFFFDD}, // -35
- Package(){2148900, 0xFFFFFFE2}, // -30
- Package(){1553800, 0xFFFFFFE7}, // -25
- Package(){1135300, 0xFFFFFFEC}, // -20
- Package(){ 837800, 0xFFFFFFF1}, // -15
- Package(){ 624100, 0xFFFFFFF6}, // -10
- Package(){ 469100, 0xFFFFFFFB}, // -5
- Package(){ 355600, 0},
- Package(){ 271800, 5},
- Package(){ 209400, 10},
- Package(){ 162500, 15},
- Package(){ 127000, 20},
- Package(){ 100000, 25},
- Package(){ 79200, 30},
- Package(){ 63200, 35},
- Package(){ 50700, 40},
- Package(){ 40900, 45},
- Package(){ 33200, 50},
- Package(){ 27100, 55},
- Package(){ 22200, 60},
- Package(){ 18300, 65},
- Package(){ 15200, 70},
- Package(){ 12600, 75},
- Package(){ 10600, 80},
- Package(){ 8890, 85},
- Package(){ 7500, 90},
- Package(){ 6360, 95},
- Package(){ 5410, 100},
- Package(){ 4620, 105},
- Package(){ 3970, 110},
- Package(){ 3420, 115},
- Package(){ 2950, 120},
- Package(){ 2560, 125}
- })
- }
-
- /*
- * XO Thermistor Table
- *
- * This lookup table is used to convert the XO thermistor reading to temperature
- * in degrees C multiplied by a factor of 1024.
- *
- * The first column in the table is thermistor resistance R_T in ohms
- *
- * The second column is the temperature in degrees Celsius multiplied by a factor
- * of 1024.
- *
- * VDD ___
- * |
- * >
- * P_PU < 100 kOhms
- * >
- * |
- * |
- * |- - - V_T
- * |
- * >
- * R_T < 100 kOhms (NTCG104EF104FB)
- * >
- * |
- * |
- * Gnd
- *
- */
- Method (XTTB)
- {
- Return (Package()
- {
- Package(){4250657, 0xFFFF6000}, // -40960
- Package(){3962085, 0xFFFF6400}, // -39936
- Package(){3694875, 0xFFFF6800}, // -38912
- Package(){3447322, 0xFFFF6C00}, // -37888
- Package(){3217867, 0xFFFF7000}, // -36864
- Package(){3005082, 0xFFFF7400}, // -35840
- Package(){2807660, 0xFFFF7800}, // -34816
- Package(){2624405, 0xFFFF7C00}, // -33792
- Package(){2454218, 0xFFFF8000}, // -32768
- Package(){2296094, 0xFFFF8400}, // -31744
- Package(){2149108, 0xFFFF8800}, // -30720
- Package(){2012414, 0xFFFF8C00}, // -29696
- Package(){1885232, 0xFFFF9000}, // -28672
- Package(){1766846, 0xFFFF9400}, // -27648
- Package(){1656598, 0xFFFF9800}, // -26624
- Package(){1553884, 0xFFFF9C00}, // -25600
- Package(){1458147, 0xFFFFA000}, // -24576
- Package(){1368873, 0xFFFFA400}, // -23552
- Package(){1285590, 0xFFFFA800}, // -22528
- Package(){1207863, 0xFFFFAC00}, // -21504
- Package(){1135290, 0xFFFFB000}, // -20480
- Package(){1067501, 0xFFFFB400}, // -19456
- Package(){1004155, 0xFFFFB800}, // -18432
- Package(){ 944935, 0xFFFFBC00}, // -17408
- Package(){ 889550, 0xFFFFC000}, // -16384
- Package(){ 837731, 0xFFFFC400}, // -15360
- Package(){ 789229, 0xFFFFC800}, // -14336
- Package(){ 743813, 0xFFFFCC00}, // -13312
- Package(){ 701271, 0xFFFFD000}, // -12288
- Package(){ 661405, 0xFFFFD400}, // -11264
- Package(){ 624032, 0xFFFFD800}, // -10240
- Package(){ 588982, 0xFFFFDC00}, // -9216
- Package(){ 556100, 0xFFFFE000}, // -8192
- Package(){ 525239, 0xFFFFE400}, // -7168
- Package(){ 496264, 0xFFFFE800}, // -6144
- Package(){ 469050, 0xFFFFEC00}, // -5120
- Package(){ 443480, 0xFFFFF000}, // -4096
- Package(){ 419448, 0xFFFFF400}, // -3072
- Package(){ 396851, 0xFFFFF800}, // -2048
- Package(){ 375597, 0xFFFFFC00}, // -1024
- Package(){ 355598, 0},
- Package(){ 336775, 1024},
- Package(){ 319052, 2048},
- Package(){ 302359, 3072},
- Package(){ 286630, 4096},
- Package(){ 271806, 5120},
- Package(){ 257829, 6144},
- Package(){ 244646, 7168},
- Package(){ 232209, 8192},
- Package(){ 220471, 9216},
- Package(){ 209390, 10240},
- Package(){ 198926, 11264},
- Package(){ 189040, 12288},
- Package(){ 179698, 13312},
- Package(){ 170868, 14336},
- Package(){ 162519, 15360},
- Package(){ 154622, 16384},
- Package(){ 147150, 17408},
- Package(){ 140079, 18432},
- Package(){ 133385, 19456},
- Package(){ 127046, 20480},
- Package(){ 121042, 21504},
- Package(){ 115352, 22528},
- Package(){ 109960, 23552},
- Package(){ 104848, 24576},
- Package(){ 100000, 25600},
- Package(){ 95402, 26624},
- Package(){ 91038, 27648},
- Package(){ 86897, 28672},
- Package(){ 82965, 29696},
- Package(){ 79232, 30720},
- Package(){ 75686, 31744},
- Package(){ 72316, 32768},
- Package(){ 69114, 33792},
- Package(){ 66070, 34816},
- Package(){ 63176, 35840},
- Package(){ 60423, 36864},
- Package(){ 57804, 37888},
- Package(){ 55312, 38912},
- Package(){ 52940, 39936},
- Package(){ 50681, 40960},
- Package(){ 48531, 41984},
- Package(){ 46482, 43008},
- Package(){ 44530, 44032},
- Package(){ 42670, 45056},
- Package(){ 40897, 46080},
- Package(){ 39207, 47104},
- Package(){ 37595, 48128},
- Package(){ 36057, 49152},
- Package(){ 34590, 50176},
- Package(){ 33190, 51200},
- Package(){ 31853, 52224},
- Package(){ 30577, 53248},
- Package(){ 29358, 54272},
- Package(){ 28194, 55296},
- Package(){ 27082, 56320},
- Package(){ 26020, 57344},
- Package(){ 25004, 58368},
- Package(){ 24033, 59392},
- Package(){ 23104, 60416},
- Package(){ 22216, 61440},
- Package(){ 21367, 62464},
- Package(){ 20554, 63488},
- Package(){ 19776, 64512},
- Package(){ 19031, 65536},
- Package(){ 18318, 66560},
- Package(){ 17636, 67584},
- Package(){ 16982, 68608},
- Package(){ 16355, 69632},
- Package(){ 15755, 70656},
- Package(){ 15180, 71680},
- Package(){ 14628, 72704},
- Package(){ 14099, 73728},
- Package(){ 13592, 74752},
- Package(){ 13106, 75776},
- Package(){ 12640, 76800},
- Package(){ 12192, 77824},
- Package(){ 11762, 78848},
- Package(){ 11350, 79872},
- Package(){ 10954, 80896},
- Package(){ 10574, 81920},
- Package(){ 10209, 82944},
- Package(){ 9858, 83968},
- Package(){ 9521, 84992},
- Package(){ 9197, 86016},
- Package(){ 8886, 87040},
- Package(){ 8587, 88064},
- Package(){ 8299, 89088},
- Package(){ 8023, 90112},
- Package(){ 7757, 91136},
- Package(){ 7501, 92160},
- Package(){ 7254, 93184},
- Package(){ 7017, 94208},
- Package(){ 6789, 95232},
- Package(){ 6570, 96256},
- Package(){ 6358, 97280},
- Package(){ 6155, 98304},
- Package(){ 5959, 99328},
- Package(){ 5770, 100352},
- Package(){ 5588, 101376},
- Package(){ 5412, 102400},
- Package(){ 5243, 103424},
- Package(){ 5080, 104448},
- Package(){ 4923, 105472},
- Package(){ 4771, 106496},
- Package(){ 4625, 107520},
- Package(){ 4484, 108544},
- Package(){ 4348, 109568},
- Package(){ 4217, 110592},
- Package(){ 4090, 111616},
- Package(){ 3968, 112640},
- Package(){ 3850, 113664},
- Package(){ 3736, 114688},
- Package(){ 3626, 115712},
- Package(){ 3519, 116736},
- Package(){ 3417, 117760},
- Package(){ 3317, 118784},
- Package(){ 3221, 119808},
- Package(){ 3129, 120832},
- Package(){ 3039, 121856},
- Package(){ 2952, 122880},
- Package(){ 2868, 123904},
- Package(){ 2787, 124928},
- Package(){ 2709, 125952},
- Package(){ 2633, 126976},
- Package(){ 2560, 128000},
- Package(){ 2489, 129024},
- Package(){ 2420, 130048}
- })
- }
-
- /*----------------------------------------------------------------------------
- * Voltage ADC Threshold Monitor (VADCTM) Configuration
- * -------------------------------------------------------------------------*/
- /*
- * VADCTM Measurement Configuration Table
- *
- * The following is a list of periodic measurements that the VADCTM
- * can periodically monitor. Thresholds for these measurements are set
- * in software.
- *
- * sName:
- * Appropriate string name for the channel from AdcInputs.h.
- *
- * uAdcHardwareChannel:
- * AMUX channel.
- *
- * eSettlingDelay:
- * Holdoff time to allow the voltage to settle before reading the channel.
- * 0 - VADCTM_SETTLING_DELAY_0_US
- * 1 - VADCTM_SETTLING_DELAY_100_US
- * 2 - VADCTM_SETTLING_DELAY_200_US
- * 3 - VADCTM_SETTLING_DELAY_300_US
- * 4 - VADCTM_SETTLING_DELAY_400_US
- * 5 - VADCTM_SETTLING_DELAY_500_US
- * 6 - VADCTM_SETTLING_DELAY_600_US
- * 7 - VADCTM_SETTLING_DELAY_700_US
- * 8 - VADCTM_SETTLING_DELAY_800_US
- * 9 - VADCTM_SETTLING_DELAY_900_US
- * 10 - VADCTM_SETTLING_DELAY_1_MS
- * 11 - VADCTM_SETTLING_DELAY_2_MS
- * 12 - VADCTM_SETTLING_DELAY_4_MS
- * 13 - VADCTM_SETTLING_DELAY_6_MS
- * 14 - VADCTM_SETTLING_DELAY_8_MS
- * 15 - VADCTM_SETTLING_DELAY_10_MS
- *
- * eMeasIntervalTimeSelect:
- * The interval timer to use for the measurement period.
- * 0 - VADCTM_MEAS_INTERVAL_TIME1
- * 1 - VADCTM_MEAS_INTERVAL_TIME2
- * 2 - VADCTM_MEAS_INTERVAL_TIME3
- *
- * bAlwaysOn:
- * Keep the measurement always sampling even if no thresholds are set.
- * 0 - FALSE
- * 1 - TRUE
- *
- * eCalMethod:
- * Calibration method.
- * 0 - VADC_CAL_METHOD_NO_CAL
- * 1 - VADC_CAL_METHOD_RATIOMETRIC
- * 2 - VADC_CAL_METHOD_ABSOLUTE
- *
- * scalingFactor.num:
- * Numerator of the channel scaling
- *
- * scalingFactor.den:
- * Denominator of the channel scaling
- *
- * eScalingMethod:
- * The scaling method to use.
- * 0 - VADC_SCALE_TO_MILLIVOLTS
- * 1 - VADC_SCALE_INTERPOLATE_FROM_MILLIVOLTS (requires uInterpolationTableName)
- * 2 - VADC_SCALE_THERMISTOR (requires uPullUp and uInterpolationTableName)
- *
- * uPullUp:
- * The pull up resistor value. Use with eScalingMethod == VADC_SCALE_THERMISTOR,
- * otherwise, 0.
- *
- * uInterpolationTableName:
- * The name of the lookup table in ACPI that will be interpolated to obtain
- * a physical value. Note that the physical value (which has default units
- * of millivolts unless custom scaling function is used) is passed as the
- * input. This value corresponds to the first column of the table. The
- * scaled output appears in the physical adc result.
- * 0 - No interpolation table
- * WXYZ - Where 'WXYZ' is the interpolation table name
- *
- * uScalingFunctionName:
- * The name of the function to call in the ACPI table to perform custom
- * scaling. The input to the custom scaling function is defined by
- * eScalingFunctionInput. The output of the custom scaling function is
- * the physical value.
- * 0 - No scaling function
- * WXYZ - Where 'WXYZ' is the scaling function name
- *
- * Note: if both a custon scaling function & interpolation table are used
- * the custom scaling function is called first.
- *
- * uInverseFunctionName:
- * The name of the inverse scaling for uScalingFunctionName.
- * 0 - No scaling function
- * WXYZ - Where 'WXYZ' is the scaling function name
- *
- * eScalingFunctionInput:
- * Defines which ADC result is passed to the custom scaling function.
- * 0 - VADC_SCALING_FUNCTION_INPUT_PHYSICAL
- * 1 - VADC_SCALING_FUNCTION_INPUT_PERCENT
- * 2 - VADC_SCALING_FUNCTION_INPUT_MICROVOLTS
- * 3 - VADC_SCALING_FUNCTION_INPUT_CODE
- *
- * nPhysicalMin:
- * Minimum threshold value in physical units.
- *
- * nPhysicalMax:
- * Maximum threshold value in physical units.
- *
- */
- Method (VTCH)
- {
- Return (Package()
- {
- /* VPH_PWR (VPH_PWR_SNS pin) */
- Package()
- {
- /* .sName = */ "VPH_PWR",
- /* .uAdcHardwareChannel = */ 0x83,
- /* .eSettlingDelay = */ 0,
- /* .eMeasIntervalTimeSelect = */ 1,
- /* .bAlwaysOn = */ 0,
- /* .eCalMethod = */ 2,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 3,
- /* .eScalingMethod = */ 0,
- /* .uPullUp = */ 0,
- /* .uInterpolationTableName = */ 0,
- /* .uScalingFunctionName = */ 0,
- /* .uInverseFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- /* .nPhysicalMin = */ 0,
- /* .nPhysicalMax = */ 5625,
- },
-
- /* PMIC_TEMP1 (internal sensor) */
- Package()
- {
- /* .sName = */ "PMIC_THERM",
- /* .uAdcHardwareChannel = */ 0x6,
- /* .eSettlingDelay = */ 0,
- /* .eMeasIntervalTimeSelect = */ 0,
- /* .bAlwaysOn = */ 0,
- /* .eCalMethod = */ 2,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 0,
- /* .uPullUp = */ 0,
- /* .uInterpolationTableName = */ 0,
- /* .uScalingFunctionName = */ PTCF,
- /* .uInverseFunctionName = */ PTCI,
- /* .eScalingFunctionInput = */ 2,
- /* .nPhysicalMin = */ 0xFFFF3CB0, // -50000
- /* .nPhysicalMax = */ 150000,
- },
-
- /* SYS_THERM1 (AMUX_1 pin) */
- Package()
- {
- /* .sName = */ "SYS_THERM1",
- /* .uAdcHardwareChannel = */ 0x4d,
- /* .eSettlingDelay = */ 1,
- /* .eMeasIntervalTimeSelect = */ 0,
- /* .bAlwaysOn = */ 0,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ SYTB,
- /* .uScalingFunctionName = */ 0,
- /* .uInverseFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- /* .nPhysicalMin = */ 0xFFFFFFD8, // -40
- /* .nPhysicalMax = */ 125,
- },
-
- /* SYS_THERM2 (AMUX_2 pin) */
- Package()
- {
- /* .sName = */ "SYS_THERM2",
- /* .uAdcHardwareChannel = */ 0x4e,
- /* .eSettlingDelay = */ 1,
- /* .eMeasIntervalTimeSelect = */ 0,
- /* .bAlwaysOn = */ 0,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ SYTB,
- /* .uScalingFunctionName = */ 0,
- /* .uInverseFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- /* .nPhysicalMin = */ 0xFFFFFFD8, // -40
- /* .nPhysicalMax = */ 125,
- },
-
- /* PA_THERM (AMUX_3 pin) */
- Package()
- {
- /* .sName = */ "PA_THERM",
- /* .uAdcHardwareChannel = */ 0x4f,
- /* .eSettlingDelay = */ 1,
- /* .eMeasIntervalTimeSelect = */ 0,
- /* .bAlwaysOn = */ 0,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ SYTB,
- /* .uScalingFunctionName = */ 0,
- /* .uInverseFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- /* .nPhysicalMin = */ 0xFFFFFFD8, // -40
- /* .nPhysicalMax = */ 125,
- },
-
- /* PA_THERM1 (AMUX_4 pin) */
- Package()
- {
- /* .sName = */ "PA_THERM1",
- /* .uAdcHardwareChannel = */ 0x50,
- /* .eSettlingDelay = */ 1,
- /* .eMeasIntervalTimeSelect = */ 0,
- /* .bAlwaysOn = */ 0,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ SYTB,
- /* .uScalingFunctionName = */ 0,
- /* .uInverseFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- /* .nPhysicalMin = */ 0xFFFFFFD8, // -40
- /* .nPhysicalMax = */ 125,
- },
-
- /* SYS_THERM3 (AMUX_5 pin) */
- Package()
- {
- /* .sName = */ "SYS_THERM3",
- /* .uAdcHardwareChannel = */ 0x51,
- /* .eSettlingDelay = */ 1,
- /* .eMeasIntervalTimeSelect = */ 0,
- /* .bAlwaysOn = */ 0,
- /* .eCalMethod = */ 1,
- /* .scalingFactor.num = */ 1,
- /* .scalingFactor.den = */ 1,
- /* .eScalingMethod = */ 2,
- /* .uPullUp = */ 100000,
- /* .uInterpolationTableName = */ SYTB,
- /* .uScalingFunctionName = */ 0,
- /* .uInverseFunctionName = */ 0,
- /* .eScalingFunctionInput = */ 0,
- /* .nPhysicalMin = */ 0xFFFFFFD8, // -40
- /* .nPhysicalMax = */ 125,
- },
- })
- }
-
- /*
- * General VADCTM measurement timer properties
- *
- * eMeasIntervalTime1:
- * Interval timer 1 periodic value.
- * 0 - VADCTM_MEAS_INTERVAL_TIME1_0_MS
- * 1 - VADCTM_MEAS_INTERVAL_TIME1_1P0_MS
- * 2 - VADCTM_MEAS_INTERVAL_TIME1_2P0_MS
- * 3 - VADCTM_MEAS_INTERVAL_TIME1_3P9_MS
- * 4 - VADCTM_MEAS_INTERVAL_TIME1_7P8_MS
- * 5 - VADCTM_MEAS_INTERVAL_TIME1_15P6_MS
- * 6 - VADCTM_MEAS_INTERVAL_TIME1_31P1_MS
- * 7 - VADCTM_MEAS_INTERVAL_TIME1_62P5_MS
- * 8 - VADCTM_MEAS_INTERVAL_TIME1_125_MS
- * 9 - VADCTM_MEAS_INTERVAL_TIME1_250_MS
- * 10 - VADCTM_MEAS_INTERVAL_TIME1_500_MS
- * 11 - VADCTM_MEAS_INTERVAL_TIME1_1000_MS
- * 12 - VADCTM_MEAS_INTERVAL_TIME1_2000_MS
- * 13 - VADCTM_MEAS_INTERVAL_TIME1_4000_MS
- * 14 - VADCTM_MEAS_INTERVAL_TIME1_8000_MS
- * 15 - VADCTM_MEAS_INTERVAL_TIME1_16000_MS
- *
- * eMeasIntervalTime2:
- * Interval timer 2 periodic value.
- * 0 - VADCTM_MEAS_INTERVAL_TIME2_0_MS
- * 1 - VADCTM_MEAS_INTERVAL_TIME2_100_MS
- * 2 - VADCTM_MEAS_INTERVAL_TIME2_200_MS
- * 3 - VADCTM_MEAS_INTERVAL_TIME2_300_MS
- * 4 - VADCTM_MEAS_INTERVAL_TIME2_400_MS
- * 5 - VADCTM_MEAS_INTERVAL_TIME2_500_MS
- * 6 - VADCTM_MEAS_INTERVAL_TIME2_600_MS
- * 7 - VADCTM_MEAS_INTERVAL_TIME2_700_MS
- * 8 - VADCTM_MEAS_INTERVAL_TIME2_800_MS
- * 9 - VADCTM_MEAS_INTERVAL_TIME2_900_MS
- * 10 - VADCTM_MEAS_INTERVAL_TIME2_1000_MS
- * 11 - VADCTM_MEAS_INTERVAL_TIME2_1100_MS
- * 12 - VADCTM_MEAS_INTERVAL_TIME2_1200_MS
- * 13 - VADCTM_MEAS_INTERVAL_TIME2_1300_MS
- * 14 - VADCTM_MEAS_INTERVAL_TIME2_1400_MS
- * 15 - VADCTM_MEAS_INTERVAL_TIME2_1500_MS
- *
- * eMeasIntervalTime3:
- * Interval timer 3 periodic value.
- * 0 - VADCTM_MEAS_INTERVAL_TIME3_0_S
- * 1 - VADCTM_MEAS_INTERVAL_TIME3_1_S
- * 2 - VADCTM_MEAS_INTERVAL_TIME3_2_S
- * 3 - VADCTM_MEAS_INTERVAL_TIME3_3_S
- * 4 - VADCTM_MEAS_INTERVAL_TIME3_4_S
- * 5 - VADCTM_MEAS_INTERVAL_TIME3_5_S
- * 6 - VADCTM_MEAS_INTERVAL_TIME3_6_S
- * 7 - VADCTM_MEAS_INTERVAL_TIME3_7_S
- * 8 - VADCTM_MEAS_INTERVAL_TIME3_8_S
- * 9 - VADCTM_MEAS_INTERVAL_TIME3_9_S
- * 10 - VADCTM_MEAS_INTERVAL_TIME3_10_S
- * 11 - VADCTM_MEAS_INTERVAL_TIME3_11_S
- * 12 - VADCTM_MEAS_INTERVAL_TIME3_12_S
- * 13 - VADCTM_MEAS_INTERVAL_TIME3_13_S
- * 14 - VADCTM_MEAS_INTERVAL_TIME3_14_S
- * 15 - VADCTM_MEAS_INTERVAL_TIME3_15_S
- *
- */
- Method (VTMT)
- {
- Return (Package()
- {
- /* .eMeasIntervalTime1 = */ 11, // 1000 ms
- /* .eMeasIntervalTime2 = */ 1, // 100 ms
- /* .eMeasIntervalTime3 = */ 5, // 5000 ms
- })
- }
-}
+++ /dev/null
-//
-// The Driver for Dynamically Changing Thresholds
-// of Thermal Zones
-//
-
-Method(THTZ, 0x4, NotSerialized)
-{
-
- // Switch based on thermal zone number
- Switch(toInteger(Arg0))
- {
- Case(1)
- {
- Switch(toInteger(Arg3))
- {
- Case(0) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ1.TPSV)
- Notify(\_SB.TZ1, 0x81)
- }
- Return(\_SB.TZ1._PSV)
- }
-
- Case(2) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ1.TTSP)
- Notify(\_SB.TZ1, 0x81)
- }
- Return(\_SB.TZ1._TSP)
- }
-
- Case(3) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ1.TTC1)
- Notify(\_SB.TZ1, 0x81)
- }
- Return(\_SB.TZ1._TC1)
- }
-
- Case(4) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ1.TTC2)
- Notify(\_SB.TZ1, 0x81)
- }
- Return(\_SB.TZ1._TC2)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Case(3)
- {
- Switch(toInteger(Arg3))
- {
- Case(0) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ3.TPSV)
- Notify(\_SB.TZ3, 0x81)
- }
- Return(\_SB.TZ3._PSV)
- }
-
- Case(2) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ3.TTSP)
- Notify(\_SB.TZ3, 0x81)
- }
- Return(\_SB.TZ3._TSP)
- }
-
- Case(3) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ3.TTC1)
- Notify(\_SB.TZ3, 0x81)
- }
- Return(\_SB.TZ3._TC1)
- }
-
- Case(4) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ3.TTC2)
- Notify(\_SB.TZ3, 0x81)
- }
- Return(\_SB.TZ3._TC2)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Case(20)
- {
- Switch(toInteger(Arg3))
- {
- Case(0) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ20.TPSV)
- Notify(\_SB.TZ20, 0x81)
- }
- Return(\_SB.TZ20._PSV)
- }
-
- Case(2) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ20.TTSP)
- Notify(\_SB.TZ20, 0x81)
- }
- Return(\_SB.TZ20._TSP)
- }
-
- Case(3) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ20.TTC1)
- Notify(\_SB.TZ20, 0x81)
- }
- Return(\_SB.TZ20._TC1)
- }
-
- Case(4) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ20.TTC2)
- Notify(\_SB.TZ20, 0x81)
- }
- Return(\_SB.TZ20._TC2)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Case(21)
- {
- Switch(toInteger(Arg3))
- {
- Case(0) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ21.TPSV)
- Notify(\_SB.TZ21, 0x81)
- }
- Return(\_SB.TZ21._PSV)
- }
-
- Case(2) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ21.TTSP)
- Notify(\_SB.TZ21, 0x81)
- }
- Return(\_SB.TZ21._TSP)
- }
-
- Case(3) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ21.TTC1)
- Notify(\_SB.TZ21, 0x81)
- }
- Return(\_SB.TZ21._TC1)
- }
-
- Case(4) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ21.TTC2)
- Notify(\_SB.TZ21, 0x81)
- }
- Return(\_SB.TZ21._TC2)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Case(33) {
- Switch(toInteger(Arg3))
- {
- Case(0) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ33.TPSV)
- Notify(\_SB.TZ33, 0x81)
- }
- Return(\_SB.TZ33._PSV)
- }
-
- Case(2) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ33.TTSP)
- Notify(\_SB.TZ33, 0x81)
- }
- Return(\_SB.TZ33._TSP)
- }
-
- Case(3) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ33.TTC1)
- Notify(\_SB.TZ33, 0x81)
- }
- Return(\_SB.TZ33._TC1)
- }
-
- Case(4) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ33.TTC2)
- Notify(\_SB.TZ33, 0x81)
- }
- Return(\_SB.TZ33._TC2)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Case(36) {
- Switch(toInteger(Arg3))
- {
- Case(0) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ36.TPSV)
- Notify(\_SB.TZ36, 0x81)
- }
- Return(\_SB.TZ36._PSV)
- }
-
- Case(2) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ36.TTSP)
- Notify(\_SB.TZ36, 0x81)
- }
- Return(\_SB.TZ36._TSP)
- }
-
- Case(3) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ36.TTC1)
- Notify(\_SB.TZ36, 0x81)
- }
- Return(\_SB.TZ36._TC1)
- }
-
- Case(4) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ36.TTC2)
- Notify(\_SB.TZ36, 0x81)
- }
- Return(\_SB.TZ36._TC2)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Case(37) {
- Switch(toInteger(Arg3))
- {
- Case(0) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ37.TPSV)
- Notify(\_SB.TZ37, 0x81)
- }
- Return(\_SB.TZ37._PSV)
- }
-
- Case(1)
- {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ37.TCRT)
- Notify(\_SB.TZ37, 0x81)
- }
- Return(\_SB.TZ37._CRT)
- }
-
- Case(2) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ37.TTSP)
- Notify(\_SB.TZ37, 0x81)
- }
- Return(\_SB.TZ37._TSP)
- }
-
- Case(3) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ37.TTC1)
- Notify(\_SB.TZ37, 0x81)
- }
- Return(\_SB.TZ37._TC1)
- }
-
- Case(4) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ37.TTC2)
- Notify(\_SB.TZ37, 0x81)
- }
- Return(\_SB.TZ37._TC2)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Case(38) {
- Switch(toInteger(Arg3))
- {
- Case(0) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ38.TPSV)
- Notify(\_SB.TZ38, 0x81)
- }
- Return(\_SB.TZ38._PSV)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Case(40) {
- Switch(toInteger(Arg3))
- {
- Case(0) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ40.TPSV)
- Notify(\_SB.TZ40, 0x81)
- }
- Return(\_SB.TZ40._PSV)
- }
-
- Case(2) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ40.TTSP)
- Notify(\_SB.TZ40, 0x81)
- }
- Return(\_SB.TZ40._TSP)
- }
-
- Case(3) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ40.TTC1)
- Notify(\_SB.TZ40, 0x81)
- }
- Return(\_SB.TZ40._TC1)
- }
-
- Case(4) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ40.TTC2)
- Notify(\_SB.TZ40, 0x81)
- }
- Return(\_SB.TZ40._TC2)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Case(44) {
- Switch(toInteger(Arg3))
- {
- Case(0) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ44.TPSV)
- Notify(\_SB.TZ44, 0x81)
- }
- Return(\_SB.TZ44._PSV)
- }
-
- Case(2) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ44.TTSP)
- Notify(\_SB.TZ44, 0x81)
- }
- Return(\_SB.TZ44._TSP)
- }
-
- Case(3) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ44.TTC1)
- Notify(\_SB.TZ44, 0x81)
- }
- Return(\_SB.TZ44._TC1)
- }
-
- Case(4) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ44.TTC2)
- Notify(\_SB.TZ44, 0x81)
- }
- Return(\_SB.TZ44._TC2)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Case(98)
- {
- Switch(toInteger(Arg3))
- {
- Case(0) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ98.TPSV)
- Notify(\_SB.TZ98, 0x81)
- }
- Return(\_SB.TZ98._PSV)
- }
-
- Case(2) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ98.TTSP)
- Notify(\_SB.TZ98, 0x81)
- }
- Return(\_SB.TZ98._TSP)
- }
-
- Case(3) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ98.TTC1)
- Notify(\_SB.TZ98, 0x81)
- }
- Return(\_SB.TZ98._TC1)
- }
-
- Case(4) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ98.TTC2)
- Notify(\_SB.TZ98, 0x81)
- }
- Return(\_SB.TZ98._TC2)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Case(99)
- {
- Switch(toInteger(Arg3))
- {
- Case(1) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ99.TCRT)
- Notify(\_SB.TZ99, 0x81)
- }
- Return(\_SB.TZ99._CRT)
- }
-
- Case(2) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ99.TTSP)
- Notify(\_SB.TZ99, 0x81)
- }
- Return(\_SB.TZ99._TSP)
- }
-
- Case(3) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ99.TTC1)
- Notify(\_SB.TZ99, 0x81)
- }
- Return(\_SB.TZ99._TC1)
- }
-
- Case(4) {
- If(Arg2)
- {
- Store(Arg1, \_SB.TZ99.TTC2)
- Notify(\_SB.TZ99, 0x81)
- }
- Return(\_SB.TZ99._TC2)
- }
-
- Default
- {
- Return(0xFFFF)
- }
- }
- }
-
- Default {
- Return(0xFFFF)
- }
- }
-}
é¡¹ç® / edk2-sdm845-acpi.git / commitdiff