-#
-# Copyright (c) 2018, Linaro Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-################################################################################
-#
-# FD Section
-# The [FD] Section is made up of the definition statements and a
-# description of what goes into the Flash Device Image. Each FD section
-# defines one flash "device" image. A flash device image may be one of
-# the following: Removable media bootable image (like a boot floppy
-# image,) an Option ROM image (that would be "flashed" into an add-in
-# card,) a System "Flash" image (that would be burned into a system's
-# flash) or an Update ("Capsule") image that will be used to update and
-# existing system flash.
-#
-################################################################################
-
-[FD.sdm845Pkg_UEFI]
-BaseAddress = 0xd0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
-Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
-ErasePolarity = 1
-
-# This one is tricky, it must be: BlockSize * NumBlocks = Size
-BlockSize = 0x00001000
-NumBlocks = 0x200
-
-################################################################################
-#
-# Following are lists of FD Region layout which correspond to the locations of different
-# images within the flash device.
-#
-# Regions must be defined in ascending order and may not overlap.
-#
-# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
-# the pipe "|" character, followed by the size of the region, also in hex with the leading
-# "0x" characters. Like:
-# Offset|Size
-# PcdOffsetCName|PcdSizeCName
-# RegionType <FV, DATA, or FILE>
-#
-################################################################################
-
-# from ArmVirtPkg/ArmVirtQemuKernel.fdf
-#
-# Implement the Linux kernel header layout so that the loader will identify
-# it as something bootable, and execute it with a FDT pointer in x0 or r2.
-#
-0x00000000|0x00008000
-DATA = {
- 0x01, 0x00, 0x00, 0x10, # code0: adr x1, .
- 0xff, 0x1f, 0x00, 0x14, # code1: b 0x8000
- 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, # text_offset: 512 KB
- 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, # image_size: 2 MB
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # flags
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res2
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res3
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res4
- 0x41, 0x52, 0x4d, 0x64, # magic: "ARM\x64"
- 0x00, 0x00, 0x00, 0x00 # res5
-}
-
-0x00008000|0x001f8000
-gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
-FV = FVMAIN_COMPACT
-
-
-################################################################################
-#
-# FV Section
-#
-# [FV] section is used to define what components or modules are placed within a flash
-# device file. This section also defines order the components and modules are positioned
-# within the image. The [FV] section consists of define statements, set statements and
-# module statements.
-#
-################################################################################
-
-[FV.FvMain]
-BlockSize = 0x40
-NumBlocks = 0 # This FV gets compressed so make it just big enough
-FvAlignment = 8 # FV alignment and FV attributes setting.
-ERASE_POLARITY = 1
-MEMORY_MAPPED = TRUE
-STICKY_WRITE = TRUE
-LOCK_CAP = TRUE
-LOCK_STATUS = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP = TRUE
-WRITE_STATUS = TRUE
-WRITE_LOCK_CAP = TRUE
-WRITE_LOCK_STATUS = TRUE
-READ_DISABLED_CAP = TRUE
-READ_ENABLED_CAP = TRUE
-READ_STATUS = TRUE
-READ_LOCK_CAP = TRUE
-READ_LOCK_STATUS = TRUE
-
- APRIORI DXE {
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- }
-
- INF MdeModulePkg/Core/Dxe/DxeMain.inf
-
- #
- # PI DXE Drivers producing Architectural Protocols (EFI Services)
- #
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
-
- #
- # Multiple Console IO support
- #
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
-
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-
- INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
-
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
-
-
- #
- # Virtual Keyboard
- #
- INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
-
- INF sdm845Pkg/Drivers/sdm845Dxe/sdm845Dxe.inf
- INF sdm845Pkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf
-
- FILE DRIVER = 0d35cd8e-97ea-4f9a-96af-0f0d89f76567 {
- SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/UFSDxe/UFSDxe.depex
- SECTION PE32 = sdm845Pkg/Binary/polaris/UFSDxe/UFSDxe.efi
- SECTION UI = "UFSDxe"
- }
-
- FILE DRIVER = f541d663-4a48-40aa-aabf-ff158ccae34c {
- SECTION DXE_DEPEX = sdm845Pkg/Binary/polaris/SmemDxe/SmemDxe.depex
- SECTION PE32 = sdm845Pkg/Binary/polaris/SmemDxe/SmemDxe.efi
- SECTION UI = "SmemDxe"
- }
-
- #
- # USB Host Support
- #
- INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
-
- #
- # USB Mass Storage Support
- #
- INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
-
- #
- # USB Peripheral Support
- #
- INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
-
- #
- # Fastboot
- #
- INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
-
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- INF FatPkg/EnhancedFatDxe/Fat.inf
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
-
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
-
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-
- #
- # ACPI Support
- #
- INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
- INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
- # INF RuleOverride = ACPITABLE sdm845Pkg/AcpiTables/AcpiTables.inf
-
- FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD {
- # SECTION RAW = sdm845Pkg/AcpiTables/testing/CSRT.aml
- SECTION RAW = sdm845Pkg/AcpiTables/testing/DBG2.aml
- SECTION RAW = sdm845Pkg/AcpiTables/polaris/DSDT.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/testing/FACS.aml
- SECTION RAW = sdm845Pkg/AcpiTables/testing/FADT.aml
- SECTION RAW = sdm845Pkg/AcpiTables/testing/GTDT.aml
- SECTION RAW = sdm845Pkg/AcpiTables/testing/IORT.aml
- SECTION RAW = sdm845Pkg/AcpiTables/testing/MADT.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/testing/MCFG.aml
- SECTION RAW = sdm845Pkg/AcpiTables/testing/PPTT.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/testing/TPM2.aml
-
- # SECTION RAW = sdm845Pkg/AcpiTables/test2/CSRT.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/test2/DBG2.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/test2/DSDT.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/test2/FACS.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/test2/FADT.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/test2/GTDT.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/test2/IORT.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/test2/MADT.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/test2/MCFG.aml
- # SECTION RAW = sdm845Pkg/AcpiTables/test2/PPTT.aml
-
- SECTION UI = "AcpiTables"
- }
-
- #
- # FDT support
- #
- INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
-
- FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
- SECTION RAW = sdm845Pkg/FdtBlob/sdm845-xiaomi-polaris.dtb
- }
-
- #
- # SMBIOS Support
- #
- INF sdm845Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
- INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
-
- #
- # UEFI applications
- #
- INF ShellPkg/Application/Shell/Shell.inf
-!ifdef $(INCLUDE_TFTP_COMMAND)
- INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
-!endif #$(INCLUDE_TFTP_COMMAND)
-
- #
- # Bds
- #
- INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
- INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
- INF MdeModulePkg/Application/UiApp/UiApp.inf
- INF sdm845Pkg/Drivers/LogoDxe/LogoDxe.inf
-
-[FV.FVMAIN_COMPACT]
-FvAlignment = 8
-ERASE_POLARITY = 1
-MEMORY_MAPPED = TRUE
-STICKY_WRITE = TRUE
-LOCK_CAP = TRUE
-LOCK_STATUS = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP = TRUE
-WRITE_STATUS = TRUE
-WRITE_LOCK_CAP = TRUE
-WRITE_LOCK_STATUS = TRUE
-READ_DISABLED_CAP = TRUE
-READ_ENABLED_CAP = TRUE
-READ_STATUS = TRUE
-READ_LOCK_CAP = TRUE
-READ_LOCK_STATUS = TRUE
-
- INF ArmPlatformPkg/PrePi/PeiUniCore.inf
-
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
- SECTION FV_IMAGE = FVMAIN
- }
- }
-
-!include sdm845Pkg/CommonFdf.fdf.inc
+#\r
+# Copyright (c) 2018, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into the Flash Device Image. Each FD section\r
+# defines one flash "device" image. A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash" image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+\r
+[FD.sdm845Pkg_UEFI]\r
+BaseAddress = 0xd0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.\r
+Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device\r
+ErasePolarity = 1\r
+\r
+# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
+BlockSize = 0x00001000\r
+NumBlocks = 0x200\r
+\r
+################################################################################\r
+#\r
+# Following are lists of FD Region layout which correspond to the locations of different\r
+# images within the flash device.\r
+#\r
+# Regions must be defined in ascending order and may not overlap.\r
+#\r
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
+# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
+# "0x" characters. Like:\r
+# Offset|Size\r
+# PcdOffsetCName|PcdSizeCName\r
+# RegionType <FV, DATA, or FILE>\r
+#\r
+################################################################################\r
+\r
+# from ArmVirtPkg/ArmVirtQemuKernel.fdf\r
+#\r
+# Implement the Linux kernel header layout so that the loader will identify\r
+# it as something bootable, and execute it with a FDT pointer in x0 or r2.\r
+#\r
+0x00000000|0x00008000\r
+DATA = {\r
+ 0x01, 0x00, 0x00, 0x10, # code0: adr x1, .\r
+ 0xff, 0x1f, 0x00, 0x14, # code1: b 0x8000\r
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, # text_offset: 512 KB\r
+ 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, # image_size: 2 MB\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # flags\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res2\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res3\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res4\r
+ 0x41, 0x52, 0x4d, 0x64, # magic: "ARM\x64"\r
+ 0x00, 0x00, 0x00, 0x00 # res5\r
+}\r
+\r
+0x00008000|0x001f8000\r
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
+FV = FVMAIN_COMPACT\r
+\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+\r
+[FV.FvMain]\r
+BlockSize = 0x40\r
+NumBlocks = 0 # This FV gets compressed so make it just big enough\r
+FvAlignment = 8 # FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+APRIORI DXE {\r
+\r
+ #\r
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
+ #\r
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf\r
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ INF FatPkg/EnhancedFatDxe/Fat.inf\r
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+\r
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf\r
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf\r
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+\r
+ FILE DRIVER = 9A5163E7-5C29-453F-825C-837A46A81E15 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/SerialDxe/SerialDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/SerialDxe/SerialDxe.efi\r
+ SECTION UI = "SerialDxe"\r
+ } \r
+\r
+ FILE DRIVER = f541d663-4a48-40aa-aabf-ff158ccae34c {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/SmemDxe/SmemDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/SmemDxe/SmemDxe.efi\r
+ SECTION UI = "SmemDxe"\r
+ } \r
+\r
+ FILE DRIVER = 8E9BD160-B184-11DF-94E2-0800200C9A66 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/DALSys/DALSys.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/DALSys/DALSys.efi\r
+ SECTION UI = "DALSys"\r
+ }\r
+\r
+ FILE DRIVER = 8681CC5A-0DF6-441E-B4B8-E915C538F067 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/HWIODxeDriver/HWIODxeDriver.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/HWIODxeDriver/HWIODxeDriver.efi\r
+ SECTION UI = "HWIODxeDriver"\r
+ }\r
+\r
+ FILE DRIVER = 10e193df-9966-44e7-b17c-59dd831e20fc {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/ChipInfo/ChipInfo.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/ChipInfo/ChipInfo.efi\r
+ SECTION UI = "ChipInfo"\r
+ }\r
+\r
+ FILE DRIVER = B105211B-BBBD-4ADD-A3B0-D1CF4A52154C {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/PlatformInfoDxeDriver/PlatformInfoDxeDriver.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/PlatformInfoDxeDriver/PlatformInfoDxeDriver.efi\r
+ SECTION UI = "PlatformInfoDxeDriver"\r
+ }\r
+\r
+ FILE DRIVER = 9A00771F-36D4-4DD5-8916-C48ED9B16B86 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/HALIOMMU/HALIOMMU.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/HALIOMMU/HALIOMMU.efi\r
+ SECTION UI = "HALIOMMU"\r
+ }\r
+\r
+ FILE DRIVER = E43128A8-8692-42B6-8AFA-676158578D18 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/ULogDxe/ULogDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/ULogDxe/ULogDxe.efi\r
+ SECTION UI = "ULogDxe"\r
+ }\r
+\r
+ FILE DRIVER = ABA01FF8-2CCB-4E12-8B2E-CD3F4A742993 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/CmdDbDxe/CmdDbDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/CmdDbDxe/CmdDbDxe.efi\r
+ SECTION UI = "CmdDbDxe"\r
+ }\r
+\r
+ FILE DRIVER = CB29F4D1-7F37-4692-A416-93E82E219711 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/NpaDxe/NpaDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/NpaDxe/NpaDxe.efi\r
+ SECTION UI = "NpaDxe"\r
+ }\r
+\r
+ FILE DRIVER = CB29F4D1-7F37-4692-A416-93E82E219766 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/RpmhDxe/RpmhDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/RpmhDxe/RpmhDxe.efi\r
+ SECTION UI = "RpmhDxe"\r
+ }\r
+\r
+ FILE DRIVER = B43C22DB-6333-490C-872D-0A73439059FD {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/PdcDxe/PdcDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/PdcDxe/PdcDxe.efi\r
+ SECTION UI = "PdcDxe"\r
+ }\r
+\r
+ FILE DRIVER = 4DB5DEA6-5302-4D1A-8A82-677A683B0D29 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/ClockDxe/ClockDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/ClockDxe/ClockDxe.efi\r
+ SECTION UI = "ClockDxe"\r
+ }\r
+\r
+ FILE DRIVER = 1B52138D-3FA3-4E50-B958-20887353F809 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/CPRDxe/CPRDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/CPRDxe/CPRDxe.efi\r
+ SECTION UI = "CPRDxe"\r
+ }\r
+\r
+ FILE DRIVER = AF9763A2-033B-4109-8E17-56A98D380C92 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/DALTLMM/DALTLMM.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/DALTLMM/DALTLMM.efi\r
+ SECTION UI = "DALTLMM"\r
+ }\r
+\r
+ FILE DRIVER = 04DE8591-D2B3-4077-BBBE-B12070094EB6 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/I2C/I2C.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/I2C/I2C.efi\r
+ SECTION UI = "I2C"\r
+ }\r
+\r
+ FILE DRIVER = 2a7b4bef-80cd-49e1-b473-374ba4d673fc {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/SPMI/SPMI.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/SPMI/SPMI.efi\r
+ SECTION UI = "SPMI"\r
+ }\r
+\r
+ FILE DRIVER = 5776232e-082d-4b75-9a0e-fe1d13f7a5d9 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/PmicDxe/PmicDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/PmicDxe/PmicDxe.efi\r
+ SECTION UI = "PmicDxe"\r
+ }\r
+\r
+ FILE DRIVER = 11faed4c-b21f-4d88-8e48-c4c28a1e50df {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi\r
+ SECTION UI = "UsbPwrCtrlDxe"\r
+ }\r
+\r
+ FILE DRIVER = 94f8a6a7-dc34-4101-88c1-99179cceae83 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UsbfnDwc3Dxe/UsbfnDwc3Dxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UsbfnDwc3Dxe/UsbfnDwc3Dxe.efi\r
+ SECTION UI = "UsbfnDwc3Dxe"\r
+ }\r
+\r
+ FILE DRIVER = cd823a4d-7dec-4531-ae5d-4134fa4127b8 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UsbConfigDxe/UsbConfigDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UsbConfigDxe/UsbConfigDxe.efi\r
+ SECTION UI = "UsbConfigDxe"\r
+ }\r
+\r
+ FILE DRIVER = 0A134F0E-075E-40B3-9C63-3B3906804663 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UsbInitDxe/UsbInitDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UsbInitDxe/UsbInitDxe.efi\r
+ SECTION UI = "UsbInitDxe"\r
+ }\r
+\r
+ FILE DRIVER = 3299a266-15f0-4346-8318-716336736d3e {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UsbDeviceDxe/UsbDeviceDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UsbDeviceDxe/UsbDeviceDxe.efi\r
+ SECTION UI = "UsbDeviceDxe"\r
+ }\r
+\r
+ FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/ButtonsDxe/ButtonsDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/ButtonsDxe/ButtonsDxe.efi\r
+ SECTION UI = "ButtonsDxe"\r
+ }\r
+\r
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf \r
+\r
+}\r
+\r
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
+\r
+ #\r
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
+ #\r
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf\r
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf\r
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ #\r
+ # Multiple Console IO support\r
+ #\r
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+\r
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+\r
+ FILE DRIVER = 9A5163E7-5C29-453F-825C-837A46A81E15 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/SerialDxe/SerialDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/SerialDxe/SerialDxe.efi\r
+ SECTION UI = "SerialDxe"\r
+ } \r
+\r
+ FILE DRIVER = f541d663-4a48-40aa-aabf-ff158ccae34c {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/SmemDxe/SmemDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/SmemDxe/SmemDxe.efi\r
+ SECTION UI = "SmemDxe"\r
+ } \r
+\r
+ FILE DRIVER = 8E9BD160-B184-11DF-94E2-0800200C9A66 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/DALSys/DALSys.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/DALSys/DALSys.efi\r
+ SECTION UI = "DALSys"\r
+ }\r
+\r
+ FILE DRIVER = 8681CC5A-0DF6-441E-B4B8-E915C538F067 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/HWIODxeDriver/HWIODxeDriver.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/HWIODxeDriver/HWIODxeDriver.efi\r
+ SECTION UI = "HWIODxeDriver"\r
+ }\r
+\r
+ FILE DRIVER = 10e193df-9966-44e7-b17c-59dd831e20fc {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/ChipInfo/ChipInfo.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/ChipInfo/ChipInfo.efi\r
+ SECTION UI = "ChipInfo"\r
+ }\r
+\r
+ FILE DRIVER = B105211B-BBBD-4ADD-A3B0-D1CF4A52154C {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/PlatformInfoDxeDriver/PlatformInfoDxeDriver.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/PlatformInfoDxeDriver/PlatformInfoDxeDriver.efi\r
+ SECTION UI = "PlatformInfoDxeDriver"\r
+ }\r
+\r
+ FILE DRIVER = 9A00771F-36D4-4DD5-8916-C48ED9B16B86 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/HALIOMMU/HALIOMMU.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/HALIOMMU/HALIOMMU.efi\r
+ SECTION UI = "HALIOMMU"\r
+ }\r
+\r
+ FILE DRIVER = E43128A8-8692-42B6-8AFA-676158578D18 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/ULogDxe/ULogDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/ULogDxe/ULogDxe.efi\r
+ SECTION UI = "ULogDxe"\r
+ }\r
+\r
+ FILE DRIVER = ABA01FF8-2CCB-4E12-8B2E-CD3F4A742993 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/CmdDbDxe/CmdDbDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/CmdDbDxe/CmdDbDxe.efi\r
+ SECTION UI = "CmdDbDxe"\r
+ }\r
+\r
+ FILE DRIVER = CB29F4D1-7F37-4692-A416-93E82E219711 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/NpaDxe/NpaDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/NpaDxe/NpaDxe.efi\r
+ SECTION UI = "NpaDxe"\r
+ }\r
+\r
+ FILE DRIVER = CB29F4D1-7F37-4692-A416-93E82E219766 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/RpmhDxe/RpmhDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/RpmhDxe/RpmhDxe.efi\r
+ SECTION UI = "RpmhDxe"\r
+ }\r
+\r
+ FILE DRIVER = B43C22DB-6333-490C-872D-0A73439059FD {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/PdcDxe/PdcDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/PdcDxe/PdcDxe.efi\r
+ SECTION UI = "PdcDxe"\r
+ }\r
+\r
+ FILE DRIVER = 4DB5DEA6-5302-4D1A-8A82-677A683B0D29 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/ClockDxe/ClockDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/ClockDxe/ClockDxe.efi\r
+ SECTION UI = "ClockDxe"\r
+ }\r
+\r
+ FILE DRIVER = 1B52138D-3FA3-4E50-B958-20887353F809 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/CPRDxe/CPRDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/CPRDxe/CPRDxe.efi\r
+ SECTION UI = "CPRDxe"\r
+ }\r
+\r
+ FILE DRIVER = AF9763A2-033B-4109-8E17-56A98D380C92 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/DALTLMM/DALTLMM.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/DALTLMM/DALTLMM.efi\r
+ SECTION UI = "DALTLMM"\r
+ }\r
+\r
+ FILE DRIVER = 04DE8591-D2B3-4077-BBBE-B12070094EB6 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/I2C/I2C.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/I2C/I2C.efi\r
+ SECTION UI = "I2C"\r
+ }\r
+\r
+ FILE DRIVER = 2a7b4bef-80cd-49e1-b473-374ba4d673fc {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/SPMI/SPMI.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/SPMI/SPMI.efi\r
+ SECTION UI = "SPMI"\r
+ }\r
+\r
+ FILE DRIVER = 5776232e-082d-4b75-9a0e-fe1d13f7a5d9 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/PmicDxe/PmicDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/PmicDxe/PmicDxe.efi\r
+ SECTION UI = "PmicDxe"\r
+ }\r
+\r
+ FILE DRIVER = 11faed4c-b21f-4d88-8e48-c4c28a1e50df {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi\r
+ SECTION UI = "UsbPwrCtrlDxe"\r
+ }\r
+\r
+ FILE DRIVER = 94f8a6a7-dc34-4101-88c1-99179cceae83 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UsbfnDwc3Dxe/UsbfnDwc3Dxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UsbfnDwc3Dxe/UsbfnDwc3Dxe.efi\r
+ SECTION UI = "UsbfnDwc3Dxe"\r
+ }\r
+\r
+ FILE DRIVER = cd823a4d-7dec-4531-ae5d-4134fa4127b8 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UsbConfigDxe/UsbConfigDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UsbConfigDxe/UsbConfigDxe.efi\r
+ SECTION UI = "UsbConfigDxe"\r
+ }\r
+\r
+ FILE DRIVER = 0A134F0E-075E-40B3-9C63-3B3906804663 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UsbInitDxe/UsbInitDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UsbInitDxe/UsbInitDxe.efi\r
+ SECTION UI = "UsbInitDxe"\r
+ }\r
+\r
+ FILE DRIVER = 3299a266-15f0-4346-8318-716336736d3e {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UsbDeviceDxe/UsbDeviceDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UsbDeviceDxe/UsbDeviceDxe.efi\r
+ SECTION UI = "UsbDeviceDxe"\r
+ }\r
+\r
+ FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/ButtonsDxe/ButtonsDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/ButtonsDxe/ButtonsDxe.efi\r
+ SECTION UI = "ButtonsDxe"\r
+ }\r
+\r
+ FILE DRIVER = 5af77f10-90df-4e7e-8325-a17ec09d5443 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UsbMsdDxe/UsbMsdDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UsbMsdDxe/UsbMsdDxe.efi\r
+ SECTION UI = "UsbMsdDxe"\r
+ }\r
+\r
+ FILE DRIVER = 0d35cd8e-97ea-4f9a-96af-0f0d89f76567 {\r
+ SECTION DXE_DEPEX = sdm845Pkg/Binary/845/UFSDxe/UFSDxe.depex\r
+ SECTION PE32 = sdm845Pkg/Binary/845/UFSDxe/UFSDxe.efi\r
+ SECTION UI = "UFSDxe"\r
+ }\r
+\r
+ #\r
+ # Virtual Keyboard\r
+ #\r
+ INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf\r
+\r
+ INF sdm845Pkg/Drivers/sdm845Dxe/sdm845Dxe.inf\r
+ INF sdm845Pkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf\r
+\r
+ #\r
+ # USB Host Support\r
+ #\r
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
+\r
+ #\r
+ # USB Mass Storage Support\r
+ #\r
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r
+\r
+ #\r
+ # USB Peripheral Support\r
+ #\r
+ INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf\r
+\r
+ #\r
+ # Fastboot\r
+ #\r
+ INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf\r
+\r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ INF FatPkg/EnhancedFatDxe/Fat.inf\r
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+\r
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ #\r
+ # ACPI Support\r
+ #\r
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf\r
+ INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf\r
+ # INF RuleOverride = ACPITABLE sdm845Pkg/AcpiTables/AcpiTables.inf\r
+\r
+ FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { \r
+ SECTION RAW = sdm845Pkg/AcpiTables/testing/DBG2.aml\r
+ SECTION RAW = sdm845Pkg/AcpiTables/845/DSDT.aml\r
+ SECTION RAW = sdm845Pkg/AcpiTables/testing/CSRT.aml\r
+ SECTION RAW = sdm845Pkg/AcpiTables/testing/FADT.aml\r
+ SECTION RAW = sdm845Pkg/AcpiTables/testing/FACS.aml\r
+ SECTION RAW = sdm845Pkg/AcpiTables/testing/GTDT.aml\r
+ SECTION RAW = sdm845Pkg/AcpiTables/testing/IORT.aml\r
+ SECTION RAW = sdm845Pkg/AcpiTables/testing/MCFG.aml\r
+ SECTION RAW = sdm845Pkg/AcpiTables/testing/MADT.aml\r
+ SECTION RAW = sdm845Pkg/AcpiTables/testing/PPTT.aml\r
+ SECTION RAW = sdm845Pkg/AcpiTables/testing/TPM2.aml\r
+ SECTION UI = "AcpiTables"\r
+ }\r
+\r
+ #\r
+ # FDT support\r
+ #\r
+ INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf\r
+\r
+ FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {\r
+ SECTION RAW = sdm845Pkg/FdtBlob/sdm845-xiaomi-polaris.dtb\r
+ }\r
+\r
+ #\r
+ # SMBIOS Support\r
+ #\r
+ INF sdm845Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf\r
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf\r
+\r
+ #\r
+ # UEFI applications\r
+ #\r
+ INF ShellPkg/Application/Shell/Shell.inf\r
+!ifdef $(INCLUDE_TFTP_COMMAND)\r
+ INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf\r
+!endif #$(INCLUDE_TFTP_COMMAND)\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf\r
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+ INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf\r
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+ INF MdeModulePkg/Application/UiApp/UiApp.inf\r
+ INF sdm845Pkg/Drivers/LogoDxe/LogoDxe.inf\r
+\r
+[FV.FVMAIN_COMPACT]\r
+FvAlignment = 8\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf\r
+\r
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
+ SECTION FV_IMAGE = FVMAIN\r
+ }\r
+ }\r
+\r
+!include sdm845Pkg/CommonFdf.fdf.inc\r
+\r
+\r
#include <dt-bindings/clock/qcom,lpass-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
no-map;
qcom,client-id = <1>;
- //qcom,vmid = <15>;
+ qcom,vmid = <15>;
};
qseecom_mem: memory@8ab00000 {
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_400>;
L2_400: l2-cache {
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_500>;
L2_500: l2-cache {
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_600>;
L2_600: l2-cache {
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_700>;
L2_700: l2-cache {
};
};
+ cpu0_opp_table: cpu0_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu0_opp1: opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <800000 4800000>;
+ };
+
+ cpu0_opp2: opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ opp-peak-kBps = <800000 4800000>;
+ };
+
+ cpu0_opp3: opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-peak-kBps = <800000 6451200>;
+ };
+
+ cpu0_opp4: opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-peak-kBps = <800000 6451200>;
+ };
+
+ cpu0_opp5: opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-peak-kBps = <800000 7680000>;
+ };
+
+ cpu0_opp6: opp-748800000 {
+ opp-hz = /bits/ 64 <748800000>;
+ opp-peak-kBps = <1804000 9216000>;
+ };
+
+ cpu0_opp7: opp-825600000 {
+ opp-hz = /bits/ 64 <825600000>;
+ opp-peak-kBps = <1804000 9216000>;
+ };
+
+ cpu0_opp8: opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <1804000 10444800>;
+ };
+
+ cpu0_opp9: opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-peak-kBps = <1804000 11980800>;
+ };
+
+ cpu0_opp10: opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-peak-kBps = <1804000 11980800>;
+ };
+
+ cpu0_opp11: opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-peak-kBps = <2188000 13516800>;
+ };
+
+ cpu0_opp12: opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-peak-kBps = <2188000 15052800>;
+ };
+
+ cpu0_opp13: opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <2188000 16588800>;
+ };
+
+ cpu0_opp14: opp-1420800000 {
+ opp-hz = /bits/ 64 <1420800000>;
+ opp-peak-kBps = <3072000 18124800>;
+ };
+
+ cpu0_opp15: opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <3072000 19353600>;
+ };
+
+ cpu0_opp16: opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <4068000 19353600>;
+ };
+
+ cpu0_opp17: opp-1689600000 {
+ opp-hz = /bits/ 64 <1689600000>;
+ opp-peak-kBps = <4068000 20889600>;
+ };
+
+ cpu0_opp18: opp-1766400000 {
+ opp-hz = /bits/ 64 <1766400000>;
+ opp-peak-kBps = <4068000 22425600>;
+ };
+ };
+
+ cpu4_opp_table: cpu4_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu4_opp1: opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <800000 4800000>;
+ };
+
+ cpu4_opp2: opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ opp-peak-kBps = <800000 4800000>;
+ };
+
+ cpu4_opp3: opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-peak-kBps = <1804000 4800000>;
+ };
+
+ cpu4_opp4: opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-peak-kBps = <1804000 4800000>;
+ };
+
+ cpu4_opp5: opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-peak-kBps = <1804000 4800000>;
+ };
+
+ cpu4_opp6: opp-748800000 {
+ opp-hz = /bits/ 64 <748800000>;
+ opp-peak-kBps = <1804000 4800000>;
+ };
+
+ cpu4_opp7: opp-825600000 {
+ opp-hz = /bits/ 64 <825600000>;
+ opp-peak-kBps = <2188000 9216000>;
+ };
+
+ cpu4_opp8: opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <2188000 9216000>;
+ };
+
+ cpu4_opp9: opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-peak-kBps = <2188000 9216000>;
+ };
+
+ cpu4_opp10: opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-peak-kBps = <3072000 9216000>;
+ };
+
+ cpu4_opp11: opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-peak-kBps = <3072000 11980800>;
+ };
+
+ cpu4_opp12: opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ opp-peak-kBps = <4068000 11980800>;
+ };
+
+ cpu4_opp13: opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ opp-peak-kBps = <4068000 11980800>;
+ };
+
+ cpu4_opp14: opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <4068000 15052800>;
+ };
+
+ cpu4_opp15: opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <4068000 15052800>;
+ };
+
+ cpu4_opp16: opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <5412000 15052800>;
+ };
+
+ cpu4_opp17: opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <5412000 15052800>;
+ };
+
+ cpu4_opp18: opp-1689600000 {
+ opp-hz = /bits/ 64 <1689600000>;
+ opp-peak-kBps = <5412000 19353600>;
+ };
+
+ cpu4_opp19: opp-1766400000 {
+ opp-hz = /bits/ 64 <1766400000>;
+ opp-peak-kBps = <6220000 19353600>;
+ };
+
+ cpu4_opp20: opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ opp-peak-kBps = <6220000 19353600>;
+ };
+
+ cpu4_opp21: opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-peak-kBps = <7216000 19353600>;
+ };
+
+ cpu4_opp22: opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-peak-kBps = <7216000 20889600>;
+ };
+
+ cpu4_opp23: opp-2092800000 {
+ opp-hz = /bits/ 64 <2092800000>;
+ opp-peak-kBps = <7216000 20889600>;
+ };
+
+ cpu4_opp24: opp-2169600000 {
+ opp-hz = /bits/ 64 <2169600000>;
+ opp-peak-kBps = <7216000 20889600>;
+ };
+
+ cpu4_opp25: opp-2246400000 {
+ opp-hz = /bits/ 64 <2246400000>;
+ opp-peak-kBps = <7216000 20889600>;
+ };
+
+ cpu4_opp26: opp-2323200000 {
+ opp-hz = /bits/ 64 <2323200000>;
+ opp-peak-kBps = <7216000 20889600>;
+ };
+
+ cpu4_opp27: opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-peak-kBps = <7216000 22425600>;
+ };
+
+ cpu4_opp28: opp-2476800000 {
+ opp-hz = /bits/ 64 <2476800000>;
+ opp-peak-kBps = <7216000 22425600>;
+ };
+
+ cpu4_opp29: opp-2553600000 {
+ opp-hz = /bits/ 64 <2553600000>;
+ opp-peak-kBps = <7216000 22425600>;
+ };
+
+ cpu4_opp30: opp-2649600000 {
+ opp-hz = /bits/ 64 <2649600000>;
+ opp-peak-kBps = <7216000 22425600>;
+ };
+
+ cpu4_opp31: opp-2745600000 {
+ opp-hz = /bits/ 64 <2745600000>;
+ opp-peak-kBps = <7216000 25497600>;
+ };
+
+ cpu4_opp32: opp-2803200000 {
+ opp-hz = /bits/ 64 <2803200000>;
+ opp-peak-kBps = <7216000 25497600>;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
};
+ qup_opp_table: qup-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
+ gpi_dma0: dma-controller@800000 {
+ #dma-cells = <3>;
+ compatible = "qcom,sdm845-gpi-dma";
+ reg = <0 0x00800000 0 0x60000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x0016 0x0>;
+ status = "disabled";
+ };
+
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x008c0000 0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x3 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core";
status = "disabled";
i2c0: i2c@880000 {
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
+ gpi_dma1: dma-controller@0xa00000 {
+ #dma-cells = <3>;
+ compatible = "qcom,sdm845-gpi-dma";
+ reg = <0 0x00a00000 0 0x60000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x06d6 0x0>;
+ status = "disabled";
+ };
+
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x00ac0000 0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x6c3 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core";
status = "disabled";
i2c8: i2c@a80000 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart8_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart10_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart11_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart13_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart14_default>;
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
status = "disabled";
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
};
spi15: spi@a9c000 {
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart15_default>;
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
mem_noc: interconnect@1380000 {
compatible = "qcom,sdm845-mem-noc";
reg = <0 0x01380000 0 0x27200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
dc_noc: interconnect@14e0000 {
compatible = "qcom,sdm845-dc-noc";
reg = <0 0x014e0000 0 0x400>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
config_noc: interconnect@1500000 {
compatible = "qcom,sdm845-config-noc";
reg = <0 0x01500000 0 0x5080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1620000 {
compatible = "qcom,sdm845-system-noc";
reg = <0 0x01620000 0 0x18080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sdm845-aggre1-noc";
reg = <0 0x016e0000 0 0x15080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,sdm845-aggre2-noc";
reg = <0 0x01700000 0 0x1f300>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
compatible = "qcom,sdm845-mmss-noc";
reg = <0 0x01740000 0 0x1c100>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x2500>;
+ reg = <0 0x01d84000 0 0x2500>,
+ <0 0x01d90000 0 0x8000>;
+ reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
+ "rx_lane1_sync_clk",
+ "ice_core_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
freq-table-hz =
<50000000 200000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>,
- <0 0>;
+ <0 0>,
+ <0 300000000>;
status = "disabled";
};
};
};
+ cryptobam: dma@1dc4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rpmhcc 15>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely = <1>;
+ iommus = <&apps_smmu 0x704 0x1>,
+ <&apps_smmu 0x706 0x1>,
+ <&apps_smmu 0x714 0x1>,
+ <&apps_smmu 0x716 0x1>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,crypto-v5.4";
+ reg = <0 0x01dfa000 0 0x6000>;
+ clocks = <&gcc GCC_CE1_AHB_CLK>,
+ <&gcc GCC_CE1_AHB_CLK>,
+ <&rpmhcc 15>;
+ clock-names = "iface", "bus", "core";
+ dmas = <&cryptobam 6>, <&cryptobam 7>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x704 0x1>,
+ <&apps_smmu 0x706 0x1>,
+ <&apps_smmu 0x714 0x1>,
+ <&apps_smmu 0x716 0x1>;
+ };
+
ipa: ipa@1e40000 {
compatible = "qcom,sdm845-ipa";
- iommus = <&apps_smmu 0x720 0x3>;
+ iommus = <&apps_smmu 0x720 0x0>,
+ <&apps_smmu 0x722 0x0>;
reg = <0 0x1e40000 0 0x7000>,
<0 0x1e47000 0 0x2000>,
<0 0x1e04000 0 0x2c000>;
reg-names = "ipa-reg",
"ipa-shared",
"gsi";
-
- memory-region = <&ipa_fw_mem>;
- interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
- <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
+ <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ipa",
clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
- interconnects = <&aggre2_noc MASTER_IPA &mem_noc SLAVE_EBI1>,
- <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>,
- <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
+ interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
+ <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
"imem",
"config";
qcom,smem-state-names = "ipa-clock-enabled-valid",
"ipa-clock-enabled";
- modem-remoteproc = <&mss_pil>;
-
status = "disabled";
};
"gpio2", "gpio3";
function = "qup0";
};
+
+ config {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ drive-strength = <6>;
+ bias-disable;
+ };
};
qup_spi1_default: qup-spi1-default {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
out-ports {
port {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
out-ports {
port {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
out-ports {
port {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
out-ports {
port {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
out-ports {
port {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
out-ports {
port {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
out-ports {
port {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
out-ports {
port {
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
iommus = <&apps_smmu 0xa0 0xf>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
status = "disabled";
+
+ sdhc2_opp_table: sdhc2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-9600000 {
+ opp-hz = /bits/ 64 <9600000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-201500000 {
+ opp-hz = /bits/ 64 <201500000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ qspi_opp_table: qspi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
};
qspi: spi@88df000 {
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core";
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&qspi_opp_table>;
status = "disabled";
};
resets = <&gcc GCC_USB30_PRIM_BCR>;
- interconnects = <&aggre2_noc MASTER_USB3_0 &mem_noc SLAVE_EBI1>,
- <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
+ interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
interconnect-names = "usb-ddr", "apps-usb";
usb_1_dwc3: dwc3@a600000 {
resets = <&gcc GCC_USB30_SEC_BCR>;
- interconnects = <&aggre2_noc MASTER_USB3_1 &mem_noc SLAVE_EBI1>,
- <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
+ interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
interconnect-names = "usb-ddr", "apps-usb";
usb_2_dwc3: dwc3@a800000 {
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&videocc VENUS_GDSC>,
<&videocc VCODEC0_GDSC>,
- <&videocc VCODEC1_GDSC>;
- power-domain-names = "venus", "vcodec0", "vcodec1";
+ <&videocc VCODEC1_GDSC>,
+ <&rpmhpd SDM845_CX>;
+ power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
+ operating-points-v2 = <&venus_opp_table>;
clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
<&videocc VIDEO_CC_VENUS_AHB_CLK>,
<&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
iommus = <&apps_smmu 0x10a0 0x8>,
<&apps_smmu 0x10b0 0x0>;
memory-region = <&venus_mem>;
+ interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
+ interconnect-names = "video-mem", "cpu-cfg";
video-core0 {
compatible = "venus-decoder";
video-core1 {
compatible = "venus-encoder";
};
+
+ venus_opp_table: venus-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-380000000 {
+ opp-hz = /bits/ 64 <380000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-533000097 {
+ opp-hz = /bits/ 64 <533000097>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+ };
};
videocc: clock-controller@ab00000 {
#power-domain-cells = <1>;
};
+ dsi_opp_table: dsi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-180000000 {
+ opp-hz = /bits/ 64 <180000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-328580000 {
+ opp-hz = /bits/ 64 <328580000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
mdss: mdss@ae00000 {
compatible = "qcom,sdm845-mdss";
reg = <0 0x0ae00000 0 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
iommus = <&apps_smmu 0x880 0x8>,
<&apps_smmu 0xc80 0x8>;
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <300000000>,
<19200000>;
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SDM845_CX>;
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
+
+ mdp_opp_table: mdp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-171428571 {
+ opp-hz = /bits/ 64 <171428571>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-344000000 {
+ opp-hz = /bits/ 64 <344000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-430000000 {
+ opp-hz = /bits/ 64 <430000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
dsi0: dsi@ae94000 {
"core",
"iface",
"bus";
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi0_phy>;
phy-names = "dsi";
"core",
"iface",
"bus";
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi1_phy>;
phy-names = "dsi";
qcom,gmu = <&gmu>;
+ interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "gfx-mem";
+
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-710000000 {
opp-hz = /bits/ 64 <710000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <7216000>;
};
opp-675000000 {
opp-hz = /bits/ 64 <675000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <7216000>;
};
opp-596000000 {
opp-hz = /bits/ 64 <596000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <6220000>;
};
opp-520000000 {
opp-hz = /bits/ 64 <520000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <6220000>;
};
opp-414000000 {
opp-hz = /bits/ 64 <414000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <4068000>;
};
opp-342000000 {
opp-hz = /bits/ 64 <342000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <2724000>;
};
opp-257000000 {
opp-hz = /bits/ 64 <257000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <1648000>;
};
};
};
adreno_smmu: iommu@5040000 {
- compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
+ compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
reg = <0 0x5040000 0 0x10000>;
#iommu-cells = <1>;
#global-interrupts = <2>;
cell-index = <0>;
};
+ imem@146bf000 {
+ compatible = "simple-mfd";
+ reg = <0 0x146bf000 0 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0x146bf000 0x1000>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x80000>;
gladiator_noc: interconnect@17900000 {
compatible = "qcom,sdm845-gladiator-noc";
reg = <0 0x17900000 0 0xd080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
reg = <0 0x17980000 0 0x1000>;
clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
apss_shared: mailbox@17990000 {
};
};
- slimbam: dma@17184000 {
+ slimbam: dma-controller@17184000 {
compatible = "qcom,bam-v1.7.0";
qcom,controlled-remotely;
reg = <0 0x17184000 0 0x2a000>;
é¡¹ç® / edk2-sdm845.git / commitdiff